Preparation method of drain-source voltage overshoot resistant silicon carbide VDMOS

Abstract

The invention provides a drain-source voltage overshoot resistant silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; performing ion implantation on the drift layer to form a conductive layer; forming a barrier layer, etching, carrying out ion implantation, and forming a masking layer and a P-type well region; re-forming a barrier layer, etching, and then depositing to form an insulating medium layer and an N-type source region; a barrier layer is formed again, etching and ion implantation are carried out, and a P-type source region is formed; a barrier layer is formed again, a gate dielectric layer is formed through etching and oxidation, and a groove is formed in the gate dielectric layer; and forming a barrier layer again, etching, depositing metal, forming a gate metal layer and a source metal layer, and removing the barrier layer to complete preparation. And the switching speed is improved while the drain voltage impact resistance of the device is improved.

Description

Technical Field

[0001] The invention relates to a method for preparing a silicon carbide VDMOS capable of withstanding drain-source voltage overshoot. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices, and is widely used in electric vehicles, aerospace, power conversion and other fields. The development of device structure and preparation process has promoted the reduction of device on-resistance and the improvement of reliability. For trench gate devices, they have the characteristics of low on-resistance, but they are easily damaged by occasional voltage shocks at the drain, so improving the voltage shock resistance of the drain source can effectively improve the reliability of the device, which is a technical problem that needs to be solved urgently. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a method for preparing a silicon carbide VDMOS that is resistant to drain-source voltage overshoot, thereby improving the device's ability to withstand drain voltage shocks while increasing the switching speed.

[0004] One of the present inventions is achieved as follows: a method for preparing a silicon carbide VDMOS with resistance to drain-source voltage overshoot comprises the following steps:

[0005] Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer;

[0006] Step 2: Form a conductive layer by ion implantation into the drift layer, with the ion implantation energy being 300-400kev;

[0007] Step 3, forming a barrier layer on the drift layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a masking layer, wherein the ion implantation energy is 200-230kev;

[0008] Step 4: remove the barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a P-type well region. The ion implantation energy is 10-170kev;

[0009] Step 5, remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the P-type well region, and then deposit to form an insulating dielectric layer, with an etching depth of 500nm;

[0010] Step 6: Deposition to form an N-type source region;

[0011] Step 7: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer and the P-type well region to form a P-type source region. The ion implantation energy is 10-100 keV.

[0012] Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the P-type well region and the drift layer until the upper side of the masking layer, and oxidizing to form a gate dielectric layer, wherein the gate dielectric layer is provided with a groove;

[0013] Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer;

[0014] Step 10: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

[0015] The second aspect of the present invention is achieved as follows: a silicon carbide VDMOS resistant to drain-source voltage overshoot, wherein the silicon carbide VDMOS is prepared by the preparation method described in one aspect of the present invention.

[0016] The advantages of the present invention are:

[0017] 1. The present invention adopts a trench gate structure, and the device has the characteristics of low on-resistance;

[0018] Second, the present invention constructs a layer of insulating medium under the N-type source region, which can shield the voltage overshoot from the drain of the device, prevent the drain voltage overshoot from impacting the source structure after inversion in the well region, and improve the ability to withstand drain-source voltage overshoot;

[0019] 3. The N-type source of the present invention is located directly above the insulating medium, and is 30nm away from the gate dielectric layer of the device. The portion of this distance is the P-type well region. When the drain voltage overshoots, the pn junction inversion is realized in this region. Since the thickness of this portion is greater than the thickness of the P-type well region under the insulating medium, this portion has a strong voltage bearing capacity and can increase the drain-source voltage resistance capability.

[0020] Fourth, the P-type well region of the present invention only wraps the N-type source region of the device and the insulating dielectric layer thereunder, but does not wrap the P-type source region, thereby achieving direct contact between the P-type source region and the N-type drift region, thereby reducing the on-resistance of the body diode;

[0021] 5. The P-type well region of the present invention is wider than the N-type source region and the insulating dielectric layer, in order to avoid the conductive channel from the N-type source region to the N-type drift layer that may be caused by process errors, thereby improving the device yield;

[0022] 6. The conductive layer of the present invention realizes current equalization inside the device and reduces the on-resistance of the device;

[0023] 7. The P-type shielding layer of the present invention is to protect the gate corner of the device from being broken down by the concentrated electric field, thereby improving the reliability of the device gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0025] Figure 1 The schematic diagram of the silicon carbide VDMOS with resistance to drain-source voltage overshoot of the present invention is shown.

[0026] Figure 2 A cross-sectional view of the process of a silicon carbide VDMOS with a drain-source voltage overshoot resistance according to the present invention Figure 1 .

[0027] Figure 3 A cross-sectional view of the process of a silicon carbide VDMOS with a drain-source voltage overshoot resistance according to the present invention Figure 2 .

[0028] Figure 4 A cross-sectional view of the process of a silicon carbide VDMOS with a drain-source voltage overshoot resistance according to the present invention Figure 3 .

[0029] Figure 5 A cross-sectional view of the process of a silicon carbide VDMOS with a drain-source voltage overshoot resistance according to the present invention Figure 4 .

[0030] Figure 6 A cross-sectional view of the process of a silicon carbide VDMOS with a drain-source voltage overshoot resistance according to the present invention Figure 5 .

[0031] Figure 7 A cross-sectional view of the process of a silicon carbide VDMOS with a drain-source voltage overshoot resistance according to the present invention Figure 6 .

[0032] Figure 8 A cross-sectional view of the process of a silicon carbide VDMOS with a drain-source voltage overshoot resistance according to the present invention Figure 7 .

[0033] Fig. 9 A cross-sectional view of the process of a silicon carbide VDMOS with a drain-source voltage overshoot resistance according to the present invention Figure 8 .

[0034] Fig.10 A cross-sectional view of the process of a silicon carbide VDMOS with a drain-source voltage overshoot resistance according to the present invention Figure 9 .

[0035] Fig.11 A cross-sectional view of the process of a silicon carbide VDMOS with a drain-source voltage overshoot resistance according to the present invention Figure 10 .

[0036] Fig.12 A cross-sectional view of the process of a silicon carbide VDMOS with a drain-source voltage overshoot resistance according to the present invention Figure 10 one.

[0037] Fig.13 A cross-sectional view of the process of a silicon carbide VDMOS with a drain-source voltage overshoot resistance according to the present invention Figure 10 two. DETAILED DESCRIPTION

[0038] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0040] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0041] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0042] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0043] like Figures 1 to 13 As shown, the embodiment of the present application provides a method for preparing a silicon carbide VDMOS with resistance to drain-source voltage overshoot, comprising the following steps:

[0044] Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 7; epitaxially growing on the side of the silicon carbide substrate 1 to form a drift layer 2;

[0045] Step 2: forming a conductive layer 21 by ion implantation into the drift layer 2, wherein the ion implantation energy is 300-400kev;

[0046] Step 3, forming a barrier layer a on the drift layer 2, etching the barrier layer a to form a through hole, and performing ion implantation into the drift layer 2 to form a masking layer 3, wherein the ion implantation energy is 200-230kev;

[0047] Step 4, removing the barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, and performing ion implantation into the drift layer 2 to form a P-type well region 25, wherein the ion implantation energy is 10-170kev;

[0048] Step 5, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and etch the P-type well region 25, and then deposit to form an insulating dielectric layer 24, the etching depth is 500nm;

[0049] Step 6: Deposition to form an N-type source region 23;

[0050] Step 7, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, perform ion implantation into the drift layer 2 and the P-type well region 25 to form a P-type source region 22, and the ion implantation energy is 10-100kev;

[0051] Step 8, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, etching the P-type well region 25 and the drift layer 2 until the upper side of the masking layer 3, and oxidizing to form a gate dielectric layer 4, wherein the gate dielectric layer 4 is provided with a groove 41;

[0052] Step 9, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, depositing metal, and forming a gate metal layer 5;

[0053] Step 10: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, deposit metal to form a source metal layer 6, remove the barrier layer a, and complete the preparation.

[0054] The doping concentration of the masking layer 3 is greater than that of the conductive layer 21 , the doping concentration of the conductive layer 21 is greater than that of the drift layer 2 , the masking layer 3 is P-type, and the silicon carbide substrate 1 , the conductive layer 21 and the drift layer 2 are all N-type.

[0055] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0056] Silicon carbide substrate 1;

[0057] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1, and a conductive layer 21 is provided in the drift layer 2; a P-type source region 22, an N-type source region 23, an insulating dielectric layer 24 and a P-type well region 25 are provided on the drift layer 2, the lower side of the P-type source region 22 is connected to the drift layer 2, the inner side of the P-type source region 22 is respectively connected to the outer side of the N-type source region 23 and the outer side of the insulating dielectric layer 24, the lower side of the N-type source region 23 is connected to the upper side of the insulating dielectric layer 24, the lower side of the insulating dielectric layer 24 is connected to the P-type well region 25, the inner side of the insulating dielectric layer 24 and the inner side of the N-type source region 23 are both connected to the P-type well region 25, and a groove 26 is provided on the drift layer 2;

[0058] A masking layer 3, wherein the masking layer 3 is disposed in the groove 26;

[0059] A gate dielectric layer 4, wherein the gate dielectric layer 4 is disposed in the groove 26, and the lower side of the gate dielectric layer 4 is connected to the upper side of the masking layer 3, and the outer side of the gate dielectric layer 4 is respectively connected to the drift layer 2 and the P-type well region 25, and a groove 41 is disposed in the gate dielectric layer;

[0060] A gate metal layer 5, wherein the gate metal layer 5 is disposed in the groove 41;

[0061] A source metal layer 6, wherein the source metal layer 6 is respectively connected to the P-type source region 22, the N-type source region 23 and the P-type well region 25;

[0062] and a drain metal layer 7 , wherein the drain metal layer 7 is connected to the lower side of the silicon carbide substrate 1 .

[0063] In a specific embodiment, the doping concentration of the silicon carbide substrate 1 is 2e18cm -3 , the doping concentration of N-type drift layer 2 is 6e16cm -3 , the doping concentration of the conductive layer 21 is 5e17cm -3 , the doping concentration of the P-type masking layer 3 is 1e18cm -3 , the doping concentration of the P-type well region 25 is 5e17 cm -3 The insulating dielectric layer 24 can be one or a combination of silicon dioxide, aluminum nitride, and hafnium dioxide. The doping concentration of the N-type source region 23 is 2e18cm -3 , the doping concentration of the P-type source region 22 is 1e19cm -3 ; The concentration of the N-type silicon carbide substrate 1 is to ensure the formation of a low-resistance ohmic contact with the drain metal layer 7, thereby reducing the overall on-resistance of the device; the doping concentration of the N-type drift layer 2 is a compromise between the reverse withstand voltage and on-resistance of the device; the conductive layer 21 and its doping concentration are to evenly distribute the current from the N-type source region 23 on both sides of the gate inside the device to avoid the burning phenomenon caused by excessive electric field density due to current concentration; the P-type masking layer 3 is to suppress the electric field concentration at the gate corner of the device and the influence of the drain voltage shock on the gate of the device; the doping concentrations of the N-type source region 23 and the P-type source region 22 are to form an ohmic contact with the source metal and reduce the contact resistance.

[0064] The thickness of the N-type silicon carbide substrate 1 is 1 μm, and the thickness of the N-type drift layer 2 is 15-25 μm, which can be adjusted within the above range according to different requirements for the withstand voltage characteristics of the device. The thickness of the conductive layer 21 is 300 nm, and the distance between the lower side of the conductive layer 21 and the upper side of the P-type shielding layer 3 is 200 nm. The conductive layer 21 can effectively shield the capacitance effect of the gate to the drain, reduce the gate-drain charge of the device, and increase the switching speed of the device. The thickness of the P-type shielding layer is 100 nm, which is to protect the gate of the device and suppress the breakdown problem caused by the electric field concentration at the corner of the gate; the thickness of the insulating dielectric layer 24 is 100 nm, the thickness of the P-type source region 22 is 300 nm, the thickness of the N-type source region 23 is 250 nm, and the P-type well region 25 is insulated. The thickness of the bottom portion of the gate dielectric layer 24 is 150nm, the thickness of the bottom portion of the P-type well region 25 at the P-type source region 22 is 200nm, the thickness of the P-type well region 25 below the source metal layer 6 is 500nm, and the distance from the inner side of the N-type source region 23 to the outer side of the gate dielectric layer 4 is 30nm, which is to ensure a compromise between the device's gate control capability and the device's conduction capability and withstand voltage capability. The device's P-type well region 25 only wraps the device's N-type source region 23 and the insulating dielectric layer 24 thereunder, and does not wrap the P-type source region 22, thereby achieving direct contact between the P-type source region 22 and the N-type drift region 2, reducing the on-resistance of the body diode, and the device's P-type well region 25 is wider than the N-type source region 23, which is to improve the device yield;

[0065] An insulating dielectric layer 24 is constructed below the N-type source region 23 of the device. The insulating dielectric layer 24 can shield the voltage overshoot from the drain of the device, prevent the drain voltage overshoot from impacting the source structure after inversion through the P-type well region 25, and improve the ability to withstand drain-source voltage overshoot; between the N-type source region 23 and the gate dielectric layer 4 is the P-type well region 25. When the drain voltage overshoots, the pn junction inversion continues upward in this region. Since the thickness of this part is greater than the thickness of the P-type well region below the insulating dielectric, this part has a strong voltage-bearing capacity and can increase the ability to withstand drain-source voltage overshoot.

[0066] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a silicon carbide VDMOS with resistance to drain-source voltage overshoot, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2, forming a conductive layer by ion implantation into the drift layer; Step 3, forming a barrier layer on the drift layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a masking layer; Step 4: remove the barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a P-type well region; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the P-type well region, and then depositing to form an insulating dielectric layer; Step 6: Deposition to form an N-type source region; Step 7: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer and the P-type well region to form a P-type source region; Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the P-type well region and the drift layer until the upper side of the masking layer, and oxidizing to form a gate dielectric layer, wherein the gate dielectric layer is provided with a groove; Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 10: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

2. The method for preparing a silicon carbide VDMOS with resistance to drain-source voltage overshoot according to claim 1, characterized in that: The doping concentration of the masking layer is greater than the doping concentration of the conductive layer, and the doping concentration of the conductive layer is greater than the doping concentration of the drift layer.

3. The method for preparing a silicon carbide VDMOS with resistance to drain-source voltage overshoot according to claim 1, characterized in that: The masking layer is of P type, and the silicon carbide substrate, the conductive layer and the drift layer are all of N type.

4. The method for preparing a silicon carbide VDMOS with resistance to drain-source voltage overshoot according to claim 1, characterized in that: The thickness of the conductive layer is 300 nm.

5. The method for preparing a silicon carbide VDMOS with resistance to drain-source voltage overshoot according to claim 1, characterized in that: The distance between the upper side of the conductive layer and the upper side of the drift layer is 200 nm.

6. The method for preparing a silicon carbide VDMOS with resistance to drain-source voltage overshoot according to claim 1, characterized in that: The thickness of the masking layer is 100 nm.

7. The method for preparing a silicon carbide VDMOS with resistance to drain-source voltage overshoot according to claim 1, characterized in that: The distance between the inner side surface of the N-type source region and the outer side surface of the gate dielectric layer is 30 nm.

8. A silicon carbide VDMOS with resistance to drain-source voltage overshoot, characterized in that: The silicon carbide VDMOS is prepared by the preparation method according to any one of claims 1 to 7.

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