Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing an SOI substrate which comprises a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top; a gate layer and a first conductive structure are formed, the gate layer is formed on the semiconductor layer, the first conductive structure penetrates through the semiconductor layer and the insulating buried layer to be electrically connected with the lower substrate, and the first conductive structure is insulated from the semiconductor layer; forming a source region and a drain region in the semiconductor layer at two sides of the gate layer; forming an interlayer dielectric layer on the semiconductor layer, wherein the interlayer dielectric layer covers the gate layer, the first conductive structure, the source region and the drain region; and forming a contact plug in the interlayer dielectric layer on the source electrode region and the drain electrode region, and simultaneously forming a second conductive structure in the interlayer dielectric layer on the first conductive structure. According to the technical scheme, the influence of the process for forming the conductive structure on the structure of the contact plug can be avoided, and the difficulty of the process for forming the conductive structure can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] In the RF-SOI process, a conductive structure penetrating the shallow trench isolation structure and the insulating buried layer is formed. The metal interconnect structure above the top semiconductor layer is electrically connected to the underlying substrate (trap-rich layer, such as a polysilicon layer) below the insulating buried layer through the conductive structure, so as to introduce free charges above the semiconductor layer into the underlying substrate, thereby reducing the interference of free charges on the device.

[0003] However, there are the following problems in the process of making conductive structures:

[0004] After etching to form the contact holes where the contact plugs are located on the source / drain regions, when performing the photolithography process of the through holes where the conductive structures are located, the photoresist will enter the contact holes, resulting in the possibility that byproducts of the ashing photoresist will remain in the contact holes when the photoresist is subsequently ashed to remove the photoresist, thereby affecting the size of the contact holes.

[0005] Therefore, it is necessary to improve the manufacturing process of the conductive structure to solve the above problems. Summary of the invention

[0006] The object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which can avoid the process of forming a conductive structure from affecting the structure of a contact plug and can reduce the difficulty of the process of forming the conductive structure.

[0007] To achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0008] Providing an SOI substrate, the SOI substrate comprising, from bottom to top, a lower substrate, an insulating buried layer and a semiconductor layer;

[0009] forming a gate layer and a first conductive structure, wherein the gate layer is formed on the semiconductor layer, the first conductive structure penetrates the semiconductor layer and the insulating buried layer to be electrically connected to the underlying substrate, and the first conductive structure is insulated from the semiconductor layer;

[0010] forming a source region and a drain region in the semiconductor layer on both sides of the gate layer;

[0011] forming an interlayer dielectric layer on the semiconductor layer, wherein the interlayer dielectric layer covers the gate layer, the first conductive structure, the source region and the drain region;

[0012] Contact plugs are formed in the interlayer dielectric layer on the source region and the drain region, and a second conductive structure is formed in the interlayer dielectric layer on the first conductive structure.

[0013] Optionally, a shallow trench isolation structure is formed in the semiconductor layer, the shallow trench isolation structure penetrates the semiconductor layer, and the first conductive structure penetrates the shallow trench isolation structure and the buried insulating layer.

[0014] Optionally, the gate layer and the first conductive structure are formed simultaneously.

[0015] Optionally, the gate layer and the first conductive structure are made of metal or polysilicon.

[0016] Optionally, the gate layer and the first conductive structure are made of polysilicon, and before forming the interlayer dielectric layer on the semiconductor layer, the method for manufacturing the semiconductor device further includes:

[0017] A metal silicide layer is formed on the upper surfaces of the gate layer, the source region, the drain region and the first conductive structure.

[0018] Optionally, the lower substrate includes a base and a trap-rich layer from bottom to top, and the first conductive structure is electrically connected to the trap-rich layer.

[0019] The present invention also provides a semiconductor device, comprising:

[0020] SOI substrate, including a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top;

[0021] A gate structure formed on the semiconductor layer;

[0022] a first conductive structure, penetrating the semiconductor layer and the buried insulating layer to be electrically connected to the underlying substrate, the first conductive structure being insulated from the semiconductor layer;

[0023] A source region and a drain region, formed in the semiconductor layer on both sides of the gate structure;

[0024] An interlayer dielectric layer, formed on the semiconductor layer, the interlayer dielectric layer covering the gate structure, the first conductive structure, the source region and the drain region;

[0025] Contact plugs formed in the interlayer dielectric layer on the source region and the drain region;

[0026] The second conductive structure is formed in the interlayer dielectric layer on the first conductive structure.

[0027] Optionally, a shallow trench isolation structure is formed in the semiconductor layer, the shallow trench isolation structure penetrates the semiconductor layer, and the first conductive structure penetrates the shallow trench isolation structure and the buried insulating layer.

[0028] Optionally, the gate structure includes a gate dielectric layer and a gate layer from bottom to top, and the gate layer is made of the same material as the first conductive structure.

[0029] Optionally, the gate layer and the first conductive structure are made of metal or polysilicon.

[0030] Optionally, the first conductive structure is made of polysilicon, a metal silicide layer is formed on an upper surface of the first conductive structure, and the second conductive structure is connected to the first conductive structure via the metal silicide layer.

[0031] Optionally, the lower substrate includes a base and a trap-rich layer from bottom to top, and the first conductive structure is electrically connected to the trap-rich layer.

[0032] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0033] 1. The method for manufacturing a semiconductor device of the present invention comprises forming a gate layer and a first conductive structure, wherein the gate layer is formed on the semiconductor layer, the first conductive structure penetrates the semiconductor layer and the insulating buried layer to be electrically connected to the lower substrate, and the first conductive structure is insulated from the semiconductor layer; forming a source region and a drain region in the semiconductor layer on both sides of the gate layer; forming an interlayer dielectric layer on the semiconductor layer, the interlayer dielectric layer covering the gate layer, the first conductive structure, the source region and the drain region; forming a contact plug in the interlayer dielectric layer on the source region and the drain region, and forming a second conductive structure in the interlayer dielectric layer on the first conductive structure. This can avoid the process of forming the conductive structure from affecting the structure of the contact plug, and can reduce the difficulty of forming the conductive structure.

[0034] 2. The semiconductor device of the present invention comprises: an SOI substrate, including a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top; a gate structure formed on the semiconductor layer; a first conductive structure penetrating the semiconductor layer and the insulating buried layer to be electrically connected to the lower substrate, the first conductive structure being insulated from the semiconductor layer; a source region and a drain region formed in the semiconductor layer on both sides of the gate structure; an interlayer dielectric layer formed on the semiconductor layer, the interlayer dielectric layer covering the gate structure, the first conductive structure, the source region and the drain region; a contact plug formed in the interlayer dielectric layer on the source region and the drain region; and a second conductive structure formed in the interlayer dielectric layer on the first conductive structure. This makes it possible to avoid the process of forming the conductive structure from affecting the structure of the contact plug, and to reduce the difficulty of forming the conductive structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0036] Figure 2a to Figure 2g yes Figure 1 A schematic diagram of a device in a method for manufacturing a semiconductor device is shown.

[0037] Among them, Figure 1 to Figure 2g The reference numerals are described as follows:

[0038] 101-lower substrate; 102-buried insulating layer; 103-semiconductor layer; 104-shallow trench isolation structure; 111-gate dielectric layer; 1111-gate dielectric material layer; 112-gate layer; 113-sidewall; 12-first conductive structure; 121-first through hole; 122-first conductive material layer; 131-source region; 132-drain region; 133-lightly doped source region; 134-lightly doped drain region; 14-metal silicide layer; 15-interlayer dielectric layer; 16-contact plug; 17-second conductive structure. DETAILED DESCRIPTION

[0039] In order to make the purpose, advantages and features of the present invention more clear, the semiconductor device and the manufacturing method thereof proposed by the present invention are further described in detail below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0040] An embodiment of the present invention provides a method for manufacturing a semiconductor device. Figure 1 , Figure 1 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein the method for manufacturing a semiconductor device comprises:

[0041] Step S1, providing an SOI substrate, wherein the SOI substrate comprises, from bottom to top, a lower substrate, an insulating buried layer and a semiconductor layer;

[0042] Step S2, forming a gate layer and a first conductive structure, wherein the gate layer is formed on the semiconductor layer, the first conductive structure penetrates the semiconductor layer and the insulating buried layer to be electrically connected to the underlying substrate, and the first conductive structure is insulated from the semiconductor layer;

[0043] Step S3, forming a source region and a drain region in the semiconductor layer on both sides of the gate layer;

[0044] Step S4, forming an interlayer dielectric layer on the semiconductor layer, wherein the interlayer dielectric layer covers the gate layer, the first conductive structure, the source region and the drain region;

[0045] Step S5: forming contact plugs in the interlayer dielectric layer on the source region and the drain region, and forming a second conductive structure in the interlayer dielectric layer on the first conductive structure.

[0046] See below Figure 2a to Figure 2g The manufacturing method of the semiconductor device provided in this embodiment is introduced in more detail.

[0047] Follow step S1, refer to Figure 2a , providing an SOI substrate, wherein the SOI substrate includes, from bottom to top, a lower substrate 101, an insulating buried layer 102 and a semiconductor layer 103.

[0048] A shallow trench isolation structure 104 is formed in the semiconductor layer 103 , and the shallow trench isolation structure 104 penetrates the semiconductor layer 103 .

[0049] The area surrounded by the shallow trench isolation structure 104 is the active area. The top surface of the shallow trench isolation structure 104 is flush with the top surface of the semiconductor layer 103 , or the top surface of the shallow trench isolation structure 104 is slightly lower or slightly higher than the top surface of the semiconductor layer 103 .

[0050] The lower substrate 101 includes a base, or the lower substrate 101 includes a base and a trap-rich layer from bottom to top. The trap-rich layer is taken as a polysilicon layer as an example below.

[0051] The substrate and the semiconductor layer 103 may be made of any suitable semiconductor material, including but not limited to: Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, other III / V or II / VI compound semiconductors and other semiconductor materials, and the insulating buried layer 102 is, for example, a silicon oxide layer.

[0052] According to step S2, refer to Figure 2d , forming a gate layer 112 and a first conductive structure 12, the gate layer 112 is formed on the semiconductor layer 103, the first conductive structure 12 penetrates the semiconductor layer 103 and the insulating buried layer 102 to be electrically connected to the underlying substrate 101, and the first conductive structure 12 is insulated from the semiconductor layer 103.

[0053] In one embodiment, the first conductive structure 12 may penetrate the shallow trench isolation structure 104 and the buried insulating layer 102, and the first conductive structure 12 is insulated and isolated from the semiconductor layer 103 by a portion of the shallow trench isolation structure 104, so that the first conductive structure 12 and the shallow trench isolation structure 104 share an area without occupying the area of ​​the active area. In other embodiments, the first conductive structure 12 may be located in the active area surrounded by the shallow trench isolation structure 104, and an insulating layer is sandwiched between the first conductive structure 12 and the semiconductor layer 103 in the active area.

[0054] When the lower substrate 101 includes only the base, the first conductive structure 12 is electrically connected to the base. When the lower substrate 101 includes a base and a polysilicon layer from bottom to top, it is preferred that the first conductive structure 12 only penetrates the shallow trench isolation structure 104 and the buried insulating layer 102 to be electrically connected to the polysilicon layer; or, the first conductive structure 12 may penetrate the shallow trench isolation structure 104, the buried insulating layer 102 and the polysilicon layer to be electrically connected to the polysilicon layer and the base.

[0055] The gate layer 112 is located on the active area surrounded by the shallow trench isolation structure 104 , and a gate dielectric layer 111 is formed below the gate layer 112 .

[0056] Preferably, the gate layer 112 and the first conductive structure 12 are formed simultaneously by using the same deposition process and etching process to simplify the process and save costs.

[0057] In one embodiment, the steps of forming the gate layer 112 and the first conductive structure 12 may include: first, Figure 2a As shown, a gate dielectric material layer 1111 is formed on the top surface of the semiconductor layer 103 by thermal oxidation or deposition process; then, as shown in FIG. Figure 2b As shown, a photolithography process is performed, and the shallow trench isolation structure 104 and the insulating buried layer 102 are etched to form a first through hole 121 penetrating the shallow trench isolation structure 104 and the insulating buried layer 102 and exposing the lower substrate 101; then, as shown Figure 2cAs shown, a first conductive material layer 122 is deposited on the gate dielectric material layer 1111 and the shallow trench isolation structure 104, and the first conductive material layer 122 fills the first through hole 121; then, as shown Figure 2d As shown, the first conductive material layer 122 and the gate dielectric material layer 1111 are etched to form a stacked gate dielectric layer 111 and a gate layer 112 on part of the active area. At the same time, a first conductive structure 12 is formed in the first through hole 121, and the first conductive structure 12 is electrically connected to the lower substrate 101.

[0058] like Figure 2e As shown, a sidewall spacer 113 is formed on the sidewalls of the gate dielectric layer 111 and the gate layer 112 .

[0059] The gate structure includes a gate dielectric layer 111 , a gate layer 112 and a spacer 113 .

[0060] When the gate layer 112 and the first conductive structure 12 are formed simultaneously by the same deposition process and etching process, the gate layer 112 and the first conductive structure 12 are made of the same material. In other embodiments, the gate layer 112 and the first conductive structure 12 can be formed in separate steps, in which case the gate layer 112 and the first conductive structure 12 can be made of the same or different materials.

[0061] The gate layer 112 and the first conductive structure 12 may be made of metal or polysilicon.

[0062] According to step S3, refer to Figure 2e , forming a source region 131 and a drain region 132 in the semiconductor layer 103 on both sides of the gate layer 112 .

[0063] Before forming the source region 131 and the drain region 132 in the semiconductor layer 103 on both sides of the gate layer 112, the method for manufacturing the semiconductor device further includes: forming a lightly doped source region 133 and a lightly doped drain region 134 in the semiconductor layer 103 on both sides of the gate structure, the depth of the lightly doped source region 133 and the lightly doped drain region 134 in the semiconductor layer 103 being less than the depth of the source region 131 and the drain region 132 in the semiconductor layer 103, and the source region 131, the drain region 132, the lightly doped source region 133 and the lightly doped drain region 134 all extend to below the gate structure, and the length of the source region 131 and the drain region 132 extending to below the gate structure is less than the length of the lightly doped source region 133 and the lightly doped drain region 134 extending to below the gate structure. For example, Figure 2eIn the illustrated embodiment, the source region 131 and the drain region 132 extend to below the spacer 113 , and the lightly doped source region 133 and the lightly doped drain region 134 extend to below the gate layer 112 .

[0064] The source region 131 , the drain region 132 , the lightly doped source region 133 and the lightly doped drain region 134 are formed by performing an ion implantation process.

[0065] When the material of the first conductive structure 12 is polysilicon, preferably, doping ions are formed in the first conductive structure 12 .

[0066] Further preferably, in the process of performing an ion implantation process to form the source region 131 and the drain region 132, and / or in the process of performing an ion implantation process to form the lightly doped source region 133 and the lightly doped drain region 134, doping ions are simultaneously implanted into the first conductive structure 12, so that doping ions are formed in the first conductive structure 12 and the process steps can be simplified.

[0067] When the gate layer 112 and the first conductive structure 12 are made of polysilicon, preferably, Figure 2f As shown, before subsequently forming the interlayer dielectric layer 15 on the semiconductor layer 103 , the method for manufacturing the semiconductor device also includes: forming a metal silicide layer 14 on the upper surfaces of the gate layer 112 , the source region 131 , the drain region 132 and the first conductive structure 12 .

[0068] According to step S4, refer to Figure 2g , an interlayer dielectric layer 15 is formed on the semiconductor layer 103 , and the interlayer dielectric layer 15 covers the gate structure, the first conductive structure 12 , the source region 131 and the drain region 132 .

[0069] Preferably, before forming the interlayer dielectric layer 15 on the semiconductor layer 103, the method for manufacturing the semiconductor device also includes: forming an etch stop layer (not shown) on the semiconductor layer 103, the etch stop layer covering the gate structure, the first conductive structure 12, the source region 131 and the drain region 132, and the interlayer dielectric layer 15 covers the etch stop layer.

[0070] When the metal silicide layer 14 is formed on the upper surfaces of the gate layer 112 , the source region 131 , the drain region 132 and the first conductive structure 12 , the etch stop layer covers the metal silicide layer 14 .

[0071] According to step S5, refer to Figure 2g, forming contact plugs 16 in the interlayer dielectric layer 15 on the source region 131 and the drain region 132 , and forming a second conductive structure 17 in the interlayer dielectric layer 15 on the first conductive structure 12 .

[0072] In one embodiment, the contact plug 16 may also be formed in the interlayer dielectric layer 15 on the gate layer 112 .

[0073] When the metal silicide layer 14 is formed on the upper surfaces of the gate layer 112, the source region 131, the drain region 132 and the first conductive structure 12, the contact resistance between the contact plug 16 and the gate layer 112, the source region 131 and the drain region 132 respectively can be reduced, and the contact resistance between the second conductive structure 17 and the first conductive structure 12 can be reduced.

[0074] In one embodiment, the step of forming the contact plug 16 and the second conductive structure 17 may include: etching the interlayer dielectric layer 15 and the etch stop layer to respectively form a second through hole exposing the source region 131, the drain region 132 and the metal silicide layer 14 on the gate layer 112, and simultaneously forming a third through hole exposing the metal silicide layer 14 on the first conductive structure 12; then, filling the second through hole and the third through hole with a second conductive material layer, the second conductive material layer also covering the interlayer dielectric layer 15; then, removing the second conductive material layer on the interlayer dielectric layer 15 by a chemical mechanical polishing process, the second conductive material layer in the second through hole serving as the contact plug 16, and the second conductive material layer in the third through hole serving as the second conductive structure 17.

[0075] The contact plug 16 and the second conductive structure 17 may be made of metal.

[0076] In addition, the manufacturing method of the semiconductor device also includes: forming a metal interconnection structure (not shown) on the contact plug 16 and the second conductive structure 17, the metal interconnection structure can be connected to the source region 131, the drain region 132 and the gate layer 112 respectively through the contact plug 16, and the metal interconnection structure can be connected to the underlying substrate 101 through the second conductive structure 17 and the first conductive structure 12.

[0077] The second conductive structure 17 and the first conductive structure 12 can introduce free charges generated above the semiconductor layer 103 during the device production process and the operation process into the lower substrate 101, thereby reducing the interference of the free charges on the device.

[0078] As can be seen from the above, when forming a conductive structure for introducing free charges above the semiconductor layer 103 into the lower substrate 101, the first conductive structure 12 is first formed to penetrate the semiconductor layer 103 and the buried insulating layer 102 to be electrically connected to the lower substrate 101, and then the second conductive structure 17 is formed to be electrically connected to the first conductive structure 12, and the second conductive structure 17 and the contact plug 16 on the source region 131, the drain region 132 and the gate layer 112 are formed simultaneously by the same photolithography process, etching process and deposition process, so that it is possible to avoid the need for performing the above process. During the photolithography process corresponding to the third through hole where the second conductive structure 17 is located, the photoresist enters the second through hole where the contact plug 16 is located, thereby avoiding the byproducts of the ashing photoresist remaining in the second through hole when the photoresist is ashed to be removed, thereby avoiding affecting the size of the second through hole and the structure of the contact plug 16; and, since the conductive structure is formed in two steps, in the process of forming the conductive structure, the etching depth is reduced each time the etching process is performed and the filling depth is reduced each time the deposition process is performed, thereby reducing the process difficulty of forming the conductive structure.

[0079] When the material of the first conductive structure 12 is polysilicon and doped ions are formed in the first conductive structure 12 , the conductivity of the first conductive structure 12 can be improved, thereby making the rate at which free charges are introduced into the lower substrate 101 faster.

[0080] When the material of the first conductive structure 12 is polysilicon and the metal silicide layer 14 is formed on the upper surface of the first conductive structure 12, the contact resistance between the second conductive structure 17 and the first conductive structure 12 can be reduced, so that free charges can be introduced from the second conductive structure 17 to the first conductive structure 12 more quickly, and then can be introduced into the lower substrate 101 more quickly.

[0081] Since the trap-rich layer has a better effect of absorbing free charges than the substrate, when the lower substrate 101 includes the substrate and the trap-rich layer from bottom to top, it can better absorb the free charges introduced from the first conductive structure 12; when the first conductive structure 12 only penetrates the shallow trench isolation structure 104 and the insulating buried layer 102 to be electrically connected to the trap-rich layer, the effect of charge extraction is better. In addition, if the materials of the trap-rich layer and the first conductive structure 12 are both polysilicon, after the free charges quickly pass through the metal silicide layer 14 from the second conductive structure 17 made of metal and enter the first conductive structure 12 made of polysilicon, since the trap-rich layer and the first conductive structure 12 are made of the same material, the free charges can enter the trap-rich layer from the first conductive structure 12 more quickly.

[0082] In summary, the manufacturing method of the semiconductor device provided by the present invention includes: providing an SOI substrate, the SOI substrate includes a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top; forming a gate layer and a first conductive structure, the gate layer is formed on the semiconductor layer, the first conductive structure penetrates the semiconductor layer and the insulating buried layer to be electrically connected to the lower substrate, and the first conductive structure is insulated from the semiconductor layer; forming a source region and a drain region in the semiconductor layer on both sides of the gate layer; forming an interlayer dielectric layer on the semiconductor layer, the interlayer dielectric layer covers the gate layer, the first conductive structure, the source region and the drain region; forming a contact plug in the interlayer dielectric layer on the source region and the drain region, and forming a second conductive structure in the interlayer dielectric layer on the first conductive structure. The manufacturing method of the semiconductor device of the present invention can avoid the process of forming the conductive structure from affecting the structure of the contact plug, and can reduce the difficulty of forming the conductive structure.

[0083] An embodiment of the present invention provides a semiconductor device, comprising: an SOI substrate, comprising a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top; a gate structure formed on the semiconductor layer; a first conductive structure, penetrating the semiconductor layer and the insulating buried layer to be electrically connected to the lower substrate, the first conductive structure being insulated from the semiconductor layer; a source region and a drain region, formed in the semiconductor layer on both sides of the gate structure; an interlayer dielectric layer, formed on the semiconductor layer, the interlayer dielectric layer covering the gate structure, the first conductive structure, the source region and the drain region; a contact plug, formed in the interlayer dielectric layer on the source region and the drain region; and a second conductive structure, formed in the interlayer dielectric layer on the first conductive structure.

[0084] See below Figure 2gThe semiconductor device provided by this embodiment is introduced in more detail.

[0085] The SOI substrate includes, from bottom to top, a lower substrate 101 , an insulating buried layer 102 and a semiconductor layer 103 .

[0086] A shallow trench isolation structure 104 is formed in the semiconductor layer 103 , and the shallow trench isolation structure 104 penetrates the semiconductor layer 103 .

[0087] The area surrounded by the shallow trench isolation structure 104 is the active area. The top surface of the shallow trench isolation structure 104 is flush with the top surface of the semiconductor layer 103 , or the top surface of the shallow trench isolation structure 104 is slightly lower or slightly higher than the top surface of the semiconductor layer 103 .

[0088] The lower substrate 101 includes a base, or the lower substrate 101 includes a base and a trap-rich layer from bottom to top. The trap-rich layer is taken as a polysilicon layer as an example below.

[0089] The substrate and the semiconductor layer 103 may be made of any suitable semiconductor material, including but not limited to: Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, other III / V or II / VI compound semiconductors and other semiconductor materials, and the insulating buried layer 102 is, for example, a silicon oxide layer.

[0090] The gate structure is formed on the semiconductor layer 103 .

[0091] The gate structure is located on the active area surrounded by the shallow trench isolation structure 104 , and the gate structure includes a gate dielectric layer 111 and a gate layer 112 from bottom to top.

[0092] The gate structure further includes a sidewall spacer 113 , and the sidewall spacer 113 is formed on the sidewalls of the gate dielectric layer 111 and the gate layer 112 .

[0093] The first conductive structure 12 penetrates the semiconductor layer 103 and the buried insulating layer 102 to be electrically connected to the underlying substrate 101 , and the first conductive structure 12 is insulated from the semiconductor layer 103 .

[0094] In one embodiment, the first conductive structure 12 may penetrate the shallow trench isolation structure 104 and the buried insulating layer 102, and the first conductive structure 12 is insulated and isolated from the semiconductor layer 103 by a portion of the shallow trench isolation structure 104, so that the first conductive structure 12 and the shallow trench isolation structure 104 share an area without occupying the area of ​​the active area. In other embodiments, the first conductive structure 12 may be located in the active area surrounded by the shallow trench isolation structure 104, and an insulating layer is sandwiched between the first conductive structure 12 and the semiconductor layer 103 in the active area.

[0095] When the lower substrate 101 includes only the base, the first conductive structure 12 is electrically connected to the base. When the lower substrate 101 includes a base and a polysilicon layer from bottom to top, it is preferred that the first conductive structure 12 only penetrates the shallow trench isolation structure 104 and the buried insulating layer 102 to be electrically connected to the polysilicon layer; or, the first conductive structure 12 may penetrate the shallow trench isolation structure 104, the buried insulating layer 102 and the polysilicon layer to be electrically connected to the polysilicon layer and the base.

[0096] Preferably, the gate layer 112 and the first conductive structure 12 are made of the same material, so that the gate layer 112 and the first conductive structure 12 can be formed simultaneously using the same deposition process and etching process to simplify the process and save costs. In other embodiments, the gate layer 112 and the first conductive structure 12 can be made of different materials.

[0097] The gate layer 112 and the first conductive structure 12 may be made of metal or polysilicon.

[0098] The source region 131 and the drain region 132 are formed in the semiconductor layer 103 at both sides of the gate structure.

[0099] The semiconductor device further includes: a lightly doped source region 133 and a lightly doped drain region 134, which are formed in the semiconductor layer 103 on both sides of the gate structure, the depth of the lightly doped source region 133 and the lightly doped drain region 134 in the semiconductor layer 103 is less than the depth of the source region 131 and the drain region 132 in the semiconductor layer 103, and the source region 131, the drain region 132, the lightly doped source region 133 and the lightly doped drain region 134 all extend to the bottom of the gate structure, and the length of the source region 131 and the drain region 132 extending to the bottom of the gate structure is less than the length of the lightly doped source region 133 and the lightly doped drain region 134 extending to the bottom of the gate structure. For example, in Figure 2eIn the illustrated embodiment, the source region 131 and the drain region 132 extend to below the sidewall spacer 113 , and the lightly doped source region 133 and the lightly doped drain region 134 extend to below the gate layer 112 .

[0100] When the material of the first conductive structure 12 is polysilicon, preferably, doped ions are formed in the first conductive structure 12 .

[0101] Further preferably, the concentration of the doping ions in the first conductive structure 12 is the same as the doping concentration of the source region 131 and the drain region 132, or the concentration of the doping ions in the first conductive structure 12 is the same as the doping concentration of the lightly doped source region 133 and the lightly doped drain region 134, or the concentration of the doping ions in the first conductive structure 12 is equal to the sum of the doping concentrations of the source region 131 and the lightly doped source region 133 or equal to the sum of the doping concentrations of the drain region 132 and the lightly doped drain region 134, so that the doping ions can be simultaneously implanted into the first conductive structure 12 during the process of performing an ion implantation process to form the source region 131 and the drain region 132, and / or during the process of performing an ion implantation process to form the lightly doped source region 133 and the lightly doped drain region 134, thereby forming the doping ions in the first conductive structure 12 and simplifying the process steps.

[0102] When the gate layer 112 and the first conductive structure 12 are made of polysilicon, preferably, the semiconductor device further includes: a metal silicide layer 14 formed on the upper surfaces of the gate layer 112 , the source region 131 , the drain region 132 and the first conductive structure 12 .

[0103] The interlayer dielectric layer 15 is formed on the semiconductor layer 103 , and the interlayer dielectric layer 15 covers the gate structure, the first conductive structure 12 , the source region 131 , and the drain region 132 .

[0104] The semiconductor device further includes: an etch stop layer (not shown) formed on the semiconductor layer 103 , the etch stop layer covers the gate structure, the first conductive structure 12 , the source region 131 and the drain region 132 , and the interlayer dielectric layer 15 covers the etch stop layer.

[0105] When the metal silicide layer 14 is formed on the upper surfaces of the gate layer 112 , the source region 131 , the drain region 132 and the first conductive structure 12 , the etch stop layer covers the metal silicide layer 14 .

[0106] The contact plug 16 is formed in the interlayer dielectric layer 15 on the source region 131 and the drain region 132 .

[0107] In one embodiment, the contact plug 16 may also be formed in the interlayer dielectric layer 15 on the gate layer 112 .

[0108] The second conductive structure 17 is formed in the interlayer dielectric layer 15 on the first conductive structure 12 .

[0109] When the metal silicide layer 14 is formed on the upper surfaces of the gate layer 112, the source region 131, the drain region 132 and the first conductive structure 12, the contact plug 16 is connected to the gate layer 112, the source region 131 and the drain region 132 through the metal silicide layer 14, which can reduce the contact resistance between the contact plug 16 and the gate layer 112, the source region 131 and the drain region 132 respectively, and the second conductive structure 17 is connected to the first conductive structure 12 through the metal silicide layer 14, which can reduce the contact resistance between the second conductive structure 17 and the first conductive structure 12.

[0110] The contact plug 16 and the second conductive structure 17 may be made of metal.

[0111] The semiconductor device also includes: a metal interconnection structure (not shown), formed on the contact plug 16 and the second conductive structure 17, the metal interconnection structure can be connected to the source region 131, the drain region 132 and the gate layer 112 respectively through the contact plug 16, and the metal interconnection structure can be connected to the underlying substrate 101 through the second conductive structure 17 and the first conductive structure 12.

[0112] The second conductive structure 17 and the first conductive structure 12 can introduce free charges generated above the semiconductor layer 103 during the device production process and the operation process into the lower substrate 101, thereby reducing the interference of the free charges on the device.

[0113] As can be seen from the above content, since the conductive structure for introducing the free charges above the semiconductor layer 103 into the lower substrate 101 includes: the first conductive structure 12 that penetrates the semiconductor layer 103 and the buried insulating layer 102 to be electrically connected to the lower substrate 101, and the second conductive structure 17 that is electrically connected to the first conductive structure 12, the second conductive structure 17 can be formed simultaneously with the contact plug 16 on the source region 131, the drain region 132 and the gate layer 112 using the same photolithography process, etching process and deposition process, thereby avoiding the occurrence of When executing the photolithography process corresponding to the third through hole where the second conductive structure 17 is located, the photoresist enters the second through hole where the contact plug 16 is located, thereby avoiding the byproducts of the ashing photoresist remaining in the second through hole when the photoresist is ashed to be removed, thereby avoiding affecting the size of the second through hole and the structure of the contact plug 16; and, since the conductive structure includes two parts, in the process of forming the conductive structure, the etching depth is reduced each time the etching process is performed and the filling depth is reduced each time the deposition process is performed, thereby reducing the process difficulty of forming the conductive structure.

[0114] When the material of the first conductive structure 12 is polysilicon and doped ions are formed in the first conductive structure 12 , the conductivity of the first conductive structure 12 can be improved, thereby making the rate at which free charges are introduced into the lower substrate 101 faster.

[0115] When the material of the first conductive structure 12 is polysilicon and the metal silicide layer 14 is formed on the upper surface of the first conductive structure 12, the contact resistance between the second conductive structure 17 and the first conductive structure 12 can be reduced, so that free charges can be introduced from the second conductive structure 17 to the first conductive structure 12 more quickly, and then can be introduced into the lower substrate 101 more quickly.

[0116] Since the trap-rich layer has a better effect of absorbing free charges than the substrate, when the lower substrate 101 includes the substrate and the trap-rich layer from bottom to top, it can better absorb the free charges introduced from the first conductive structure 12; when the first conductive structure 12 only penetrates the shallow trench isolation structure 104 and the insulating buried layer 102 to be electrically connected to the trap-rich layer, the effect of charge extraction is better. In addition, if the materials of the trap-rich layer and the first conductive structure 12 are both polysilicon, after the free charges quickly pass through the metal silicide layer 14 from the second conductive structure 17 made of metal and enter the first conductive structure 12 made of polysilicon, since the trap-rich layer and the first conductive structure 12 are made of the same material, the free charges can enter the trap-rich layer from the first conductive structure 12 more quickly.

[0117] In summary, the semiconductor device provided by the present invention includes: an SOI substrate, including a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top; a gate structure formed on the semiconductor layer; a first conductive structure, penetrating the semiconductor layer and the insulating buried layer to be electrically connected to the lower substrate, the first conductive structure being insulated from the semiconductor layer; a source region and a drain region, formed in the semiconductor layer on both sides of the gate structure; an interlayer dielectric layer, formed on the semiconductor layer, the interlayer dielectric layer covering the gate structure, the first conductive structure, the source region and the drain region; a contact plug, formed in the interlayer dielectric layer on the source region and the drain region; and a second conductive structure, formed in the interlayer dielectric layer on the first conductive structure. The semiconductor device of the present invention can avoid the process of forming the conductive structure from affecting the structure of the contact plug, and can reduce the difficulty of the process of forming the conductive structure.

[0118] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing an SOI substrate, the SOI substrate comprising, from bottom to top, a lower substrate, an insulating buried layer and a semiconductor layer; forming a gate layer and a first conductive structure, wherein the gate layer is formed on the semiconductor layer, the first conductive structure penetrates the semiconductor layer and the insulating buried layer to be electrically connected to the underlying substrate, and the first conductive structure is insulated from the semiconductor layer; forming a source region and a drain region in the semiconductor layer on both sides of the gate layer; forming an interlayer dielectric layer on the semiconductor layer, wherein the interlayer dielectric layer covers the gate layer, the first conductive structure, the source region and the drain region; Contact plugs are formed in the interlayer dielectric layer on the source region and the drain region, and a second conductive structure is formed in the interlayer dielectric layer on the first conductive structure.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: A shallow trench isolation structure is formed in the semiconductor layer, and the shallow trench isolation structure penetrates the semiconductor layer. The first conductive structure penetrates the shallow trench isolation structure and the buried insulating layer.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The gate layer and the first conductive structure are formed simultaneously.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The gate layer and the first conductive structure are made of metal or polysilicon.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The gate layer and the first conductive structure are made of polysilicon. Before forming the interlayer dielectric layer on the semiconductor layer, the method for manufacturing the semiconductor device further includes: A metal silicide layer is formed on the upper surfaces of the gate layer, the source region, the drain region and the first conductive structure.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, characterized in that: The lower substrate includes a base and a trap-rich layer from bottom to top, and the first conductive structure is electrically connected to the trap-rich layer.

7. A semiconductor device, characterized in that: include: SOI substrate, including a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top; A gate structure formed on the semiconductor layer; a first conductive structure, penetrating the semiconductor layer and the buried insulating layer to be electrically connected to the underlying substrate, the first conductive structure being insulated from the semiconductor layer; A source region and a drain region, formed in the semiconductor layer on both sides of the gate structure; An interlayer dielectric layer, formed on the semiconductor layer, the interlayer dielectric layer covering the gate structure, the first conductive structure, the source region and the drain region; Contact plugs formed in the interlayer dielectric layer on the source region and the drain region; The second conductive structure is formed in the interlayer dielectric layer on the first conductive structure.

8. The semiconductor device according to claim 7, wherein: A shallow trench isolation structure is formed in the semiconductor layer, and the shallow trench isolation structure penetrates the semiconductor layer. The first conductive structure penetrates the shallow trench isolation structure and the buried insulating layer.

9. The semiconductor device according to claim 7, wherein: The gate structure includes a gate dielectric layer and a gate layer from bottom to top, and the gate layer is made of the same material as the first conductive structure.

10. The semiconductor device according to claim 9, wherein: The gate layer and the first conductive structure are made of metal or polysilicon.

11. The semiconductor device according to claim 7, wherein: The material of the first conductive structure is polysilicon, a metal silicide layer is formed on the upper surface of the first conductive structure, and the second conductive structure is connected to the first conductive structure through the metal silicide layer.

12. The semiconductor device according to any one of claims 7 to 11, characterized in that: The lower substrate includes a base and a trap-rich layer from bottom to top, and the first conductive structure is electrically connected to the trap-rich layer.

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