Semiconductor device with auxiliary trench gate and manufacturing method thereof

Abstract

The invention provides a semiconductor device with an auxiliary trench gate and a manufacturing method thereof, and the semiconductor device comprises an epitaxial layer which is provided with a first surface and a second surface which are opposite to each other; a plurality of main trench gates located in the first surface, wherein the main trench gates are sequentially arranged at intervals in the first direction; a plurality of auxiliary trench gates which are arranged in sequence are arranged in the first surface between two adjacent main trench gates; and the depth of the auxiliary trench gate is smaller than that of the main trench gate. The auxiliary trench gates are arranged between the adjacent main trench gates, the channel density is improved, the distance between the two adjacent trench gates is reduced, control over the trench gates is enhanced, the equivalent carrier mobility and the inversion carrier concentration are improved, and then the channel resistance is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and more specifically, to a semiconductor device with an auxiliary trench gate and a manufacturing method thereof. Background Art

[0002] With the continuous development of the semiconductor industry, more and more semiconductor materials have been discovered. Among them, SiC (silicon carbide) materials have advantages in physical properties such as large bandgap, high breakdown electric field, fast electron mobility, and high thermal conductivity, which enables semiconductor devices based on SiC to work in high temperature, high pressure, high frequency and radiation-resistant environments. At the same time, compared with traditional semiconductor devices, it has higher operating voltage, lower loss and higher power density, and thus gradually becomes the mainstream of the market. However, semiconductor devices based on SiC have more SiC-SiO2 interface defects inside, which makes their internal carrier mobility low. Summary of the invention

[0003] In view of this, the present application provides a semiconductor device with an auxiliary trench gate and a method for manufacturing the same, the scheme is as follows: In a first aspect, the present application provides a semiconductor device having an auxiliary trench gate, comprising: an epitaxial layer having opposing first and second surfaces; A plurality of main trench gates are located in the first surface, and the main trench gates are sequentially spaced apart in a first direction; At least one auxiliary trench gate is provided in the first surface between two adjacent main trench gates; the depth of the auxiliary trench gate is smaller than the depth of the main trench gate.

[0004] Preferably, in the semiconductor device described above, in the first direction, a plurality of auxiliary trench gates are arranged in sequence in the first surface between two adjacent main trench gates.

[0005] Preferably, in the semiconductor device described above, between two adjacent main trench gates, the depths of the plurality of auxiliary trench gates are the same.

[0006] Preferably, in the semiconductor device described above, depths of the plurality of auxiliary trench gates between two adjacent main trench gates are not completely the same.

[0007] Preferably, in the semiconductor device described above, the distance between two adjacent main trench gates is 1 μm to 2 μm; The spacing between two adjacent main trench gates and between the auxiliary trench gates is less than 100 nm.

[0008] Preferably, in the semiconductor device described above, a trench bottom protection structure is provided in the epitaxial layer at the bottom of the main trench gate, and the doping type of the trench bottom protection structure is opposite to the doping type of the epitaxial layer.

[0009] Preferably, in the semiconductor device described above, the first surface between two adjacent trench gates has a source region; The first surface is covered with an insulating layer; the insulating layer has an opening that drains the source region; The surface of the insulating layer is covered with a metal source electrode, which is connected to the source region through an opening.

[0010] A second aspect of the present application provides a method for preparing any of the semiconductor devices described above, comprising: forming an epitaxial layer on a substrate, the epitaxial layer having a first surface and a second surface opposite to each other; the first surface faces away from the substrate; A main trench gate and an auxiliary trench gate are formed in the first surface; wherein the first surface has a plurality of main trench gates arranged in sequence in the first direction; the first surface between two adjacent main trench gates has at least one auxiliary trench gate; the depth of the auxiliary trench gate is less than the depth of the main trench gate.

[0011] Preferably, in the manufacturing method described above, forming the main trench gate and the auxiliary trench gate includes: forming a main groove and an auxiliary groove in the first surface; forming a gate dielectric layer on the surface of the main trench and the surface of the auxiliary trench; The gate semiconductor material is filled in the main trench having the gate dielectric layer and in the auxiliary trench.

[0012] Preferably, in the manufacturing method described above, before forming the gate dielectric layer, the method further comprises: Based on the main trench, ion implantation is performed on the epitaxial layer to form a trench bottom protection structure in the epitaxial layer at the bottom of the main trench; The doping type of the trench bottom protection structure is opposite to the doping type of the epitaxial layer.

[0013] Preferably, in the manufacturing method described above, the method of forming the main groove and the auxiliary groove includes: forming a sacrificial structure on the first surface; Depositing multiple layers of alternately stacked first and second sacrificial layers on the top and sidewalls of the sacrificial structure; the first sacrificial layer comprises: a first portion and a second portion, the first portion being located above the plane where the top is located; the second portion being located below the plane where the top is located and parallel to the plane where the sidewall is located; removing the first sacrificial layer and the second sacrificial layer above the plane where the top is located, and removing the second sacrificial layer and the sacrificial structure between the second portion; Based on the second part, a main trench and an auxiliary trench are formed in the first surface; Remove the second part; The main groove is located in the first surface corresponding to the sacrificial structure; and the auxiliary groove is located between two adjacent second parts.

[0014] Preferably, in the above-described manufacturing method, before removing the second part, the method further comprises: forming a third sacrificial layer, wherein the third sacrificial layer covers the sidewalls of the main trench and fills the auxiliary trench; Based on the bottom of the main trench exposed by the third sacrificial layer, ion implantation is performed to form a trench bottom protection structure in the epitaxial layer at the bottom of the main trench; After removing the third sacrificial layer and the second portion, the gate material is filled in the main trench and the auxiliary trench having the gate dielectric layer.

[0015] Based on the above introduction, the present application provides a semiconductor device with auxiliary trench gate and a manufacturing method thereof, the semiconductor device comprising: an epitaxial layer having a first surface and a second surface relative to each other; a plurality of main trench gates located in the first surface, the main trench gates being arranged in sequence and spaced in a first direction; at least one auxiliary trench gate is provided in the first surface between two adjacent main trench gates; the depth of the auxiliary trench gate is less than the depth of the main trench gate. The auxiliary trench gate is provided between adjacent main trench gates, which increases the density of the channel while reducing the distance between two adjacent trench gates, strengthens the control of the trench gate, increases the equivalent carrier mobility and the inversion carrier concentration, and thus reduces the channel resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments or descriptions of the prior art will be briefly introduced below. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0017] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.

[0018] Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application; Figure 2A schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application; Figure 3 A schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application; Figure 4 A schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application; Figure 5 A process signaling diagram of a semiconductor device manufacturing method provided in an embodiment of the present application; Figure 6-Figure 8 A product structure diagram of a semiconductor device manufacturing method in different process steps provided in an embodiment of the present application; Figure 9-10 A product structure diagram of a method for manufacturing a main trench gate and an auxiliary trench gate in different process steps provided in an embodiment of the present application; Figure 11-Figure 16 A product structure diagram of a method for manufacturing a main groove and an auxiliary groove in different process steps provided in an embodiment of the present application; Figure 17-Figure 19 A product structure diagram of a method for manufacturing a groove bottom protection structure provided in this application in different process steps; Fig. 20 A schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application; Fig.21 A schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0020] In order to solve the problem of low carrier mobility at the SiC-SiO2 interface inside semiconductor devices based on SiC, resulting in excessively high channel resistance. One solution is to use a planar channel structure and add multiple FinFET structures in a direction parallel to the channel to improve control over channel carriers and thereby improve carrier mobility. However, this method requires an additional high-precision lithography, and at the same time, it is necessary to ensure that the depth and doping of the formed FinFET structure are consistent, which increases the difficulty of the process.

[0021] Another solution is an improved structure based on trench gates, which reduces the spacing between trench gates to a size that produces a FinFET effect, thereby improving control over channel carriers and, in turn, improving equivalent mobility. However, with this structure, it is necessary to set trench gates in the same plane while achieving ohmic contact with the source, which limits the increase in the density of the trench gates. At the same time, due to the particularity of SiC semiconductor devices, the electric field at the bottom of the trench is high, and the gate dielectric layer at the bottom of the trench is easily broken down. Therefore, it is necessary to set an ion protection layer at the bottom of the trench gate to protect the gate dielectric layer. However, when the density of the trench gates increases, a significant JFET effect will occur, causing the total resistance to increase.

[0022] In order to solve the above problems, the present application provides a semiconductor device with auxiliary trench gates, the semiconductor device comprising: an epitaxial layer having a first surface and a second surface opposite to each other; a plurality of main trench gates located in the first surface, the main trench gates being arranged in sequence and spaced in a first direction; at least one auxiliary trench gate is provided in the first surface between two adjacent main trench gates; the depth of the auxiliary trench gate is less than the depth of the main trench gate. By providing an auxiliary trench gate between two adjacent main trenches, the distance between two adjacent trench gates at both ends is reduced, and the density of the channel between the trench gates is also improved, thereby improving the control of channel carriers and improving the carrier mobility. At the same time, due to the existence of the auxiliary trench gates, the trench gate density is improved.

[0023] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0024] refer to Figure 1 , Figure 1 A schematic structural diagram of a semiconductor device provided in an embodiment of the present application, the semiconductor device comprising: an epitaxial layer 11 having a first surface and a second surface relative to each other; a plurality of main trench gates 12 located in the first surface, the main trench gates 12 being arranged in sequence and spaced apart in a first direction X; at least one auxiliary trench gate 13 is provided in the first surface between two adjacent main trench gates 12; the depth of the auxiliary trench gate 13 is less than the depth of the main trench gate 12.

[0025] Among them, the first direction X is Figure 1 The first direction X and the second direction Y are parallel to the first surface, and the first direction X is perpendicular to the second direction Y.

[0026] In order to improve the cell density of the device, the width of the auxiliary trench gate 13 in the first direction X is set to be smaller than the width of the main trench gate 12 in the first direction X.

[0027] In the embodiment of the present application, the semiconductor device is a trench gate device, wherein the trench gate includes: a main trench gate 12 and an auxiliary trench gate 13 .

[0028] The main trench gate 12 includes: a main trench 121, the surface of the main trench 121 is covered with a gate dielectric layer 123; and a main gate material 122 filling the main trench. The auxiliary trench gate 13 includes: an auxiliary trench 131, the surface of the auxiliary trench 131 is covered with a gate dielectric layer 123; and an auxiliary gate material filling the auxiliary trench 131. In order to facilitate process preparation, the main gate material 122 and the auxiliary gate material can both be polysilicon.

[0029] The depth of the auxiliary trench gate 13 is smaller than that of the main trench gate 12, so that the electric field is mainly concentrated at the bottom of the main trench gate 12, while the electric field at the bottom of the auxiliary trench gate 13 is small, preventing the auxiliary trench gate 13 from being broken down by the electric field, and protecting the auxiliary trench gate 13. The semiconductor device arranges the auxiliary trench gate 13 between adjacent main trench gates 12, reduces the distance between two adjacent trench gates, increases the density of the channel, and forms a FinFET effect, thereby strengthening the control of channel carriers, thereby increasing carrier mobility, and reducing channel resistance.

[0030] Optionally, in the semiconductor device described above, in the first direction X, a plurality of sequentially arranged auxiliary trench gates 13 may be provided in the first surface between two adjacent main trench gates 12. In order to facilitate the process preparation of the auxiliary trench gates 13, the widths of the auxiliary trench gates 13 in the first direction X may be the same.

[0031] By arranging a plurality of auxiliary trench gates 13 in the first surface between two adjacent main trench gates 12, as the number of trench gates increases, the density of the trench gates is increased, and the performance of the semiconductor device prepared based on this structure is improved. At the same time, by arranging a plurality of auxiliary trench gates 13, the distance between two adjacent trench gates is reduced, thereby strengthening the control of channel carriers, and further improving the mobility of carriers.

[0032] In the embodiment of the present application, one or any number of auxiliary trench gates 13 may be disposed between two adjacent main trench gates 12 , and the number of the auxiliary trench gates 13 between two main trench gates 12 is not limited.

[0033] When a plurality of auxiliary trench gates 13 are arranged between two main trench gates 12, the layout of the auxiliary trench gates 13 can be as follows: Figure 2-Figure 4 shown.

[0034] refer to Figure 2 , Figure 2 A schematic diagram of another semiconductor device provided in an embodiment of the present application, combined with Figure 1 and Figure 2 As shown, between two adjacent main trench gates 12 , the depths of the plurality of auxiliary trench gates 13 are the same.

[0035] Since the depths of the auxiliary trench gates 13 are the same, all the auxiliary trench gates 13 can be formed simultaneously without adding additional process steps, thereby reducing the process cost.

[0036] If a plurality of auxiliary trench gates 13 are disposed between two adjacent main trench gates 12 , the depths of the plurality of auxiliary trench gates 13 may not be completely the same.

[0037] When multiple auxiliary trench gates 13 are arranged between two adjacent main trench gates 12, the depths of the multiple auxiliary trench gates 13 may not be exactly the same. By adjusting the depths of each auxiliary trench gate 13, the electric field at the bottom of the trench of the device can be optimized, and the resistance layout of the device can also be optimized, thereby optimizing the performance of the device.

[0038] refer to Figure 3 , Figure 3 A schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application is shown in FIG. Figure 3 In the semiconductor device shown, between two adjacent main trench gates 12, the depth of the auxiliary trench gate 13 gradually decreases from both sides to the middle, that is, the depth of the auxiliary trench gate 13 is inversely proportional to the distance between the two main trench gates 12. This method can optimize the distribution of the electric field at the bottom of the main trench gate 12 and the auxiliary trench gate 13, and protect the gate dielectric layer 123 at the bottom of the main trench gate 12.

[0039] refer to Figure 4 , Figure 4 A schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application, in which the depth of the auxiliary trench gate 13 between two adjacent main trench gates 12 gradually increases from both sides to the middle, that is, the depth of the auxiliary trench gate 13 is proportional to the distance between the two main trench gates 12. This structure can optimize the resistance layout, reduce the resistance of the device, and improve the efficiency of the semiconductor device while ensuring a strong control effect on the channel carriers.

[0040] Combination Figure 1-Figure 4 As shown, in the semiconductor device provided in the embodiment of the present application, the distance between two adjacent main trench gates 12 may be 1 μm to 2 μm; and the spacing between adjacent main trench gates 12 and auxiliary trench gates 13 is less than 100 nm.

[0041] In the embodiment of the present application, the distance between two adjacent trench gates is less than 100 nm, so that a FinFET structure can be formed between the two trench gates, thereby enhancing the control effect on channel carriers and improving carrier mobility.

[0042] If there is one auxiliary trench gate 13, the distance between two adjacent main trench gates 12 and the auxiliary trench gate 13 therebetween is less than 100 nm. If there are multiple auxiliary trench gates 13, the distance between the main trench gate 12 and the adjacent auxiliary trench gate 13 and between adjacent auxiliary trench gates 13 is less than 100 nm.

[0043] in, Figure 1 The semiconductor device shown has three auxiliary trench gates 13 between two adjacent main trench gates 12. At the same time, the spacing between each auxiliary trench gate 13 and between the main trench gate 12 and its adjacent auxiliary trench gate 13 is the same and is less than 100nm, forming a FinFET structure, thereby enhancing the control effect on channel carriers and improving carrier mobility.

[0044] In the semiconductor device described above, a trench bottom protection structure 14 is provided in the epitaxial layer 11 at the bottom of the main trench gate 12, and the doping type of the trench bottom protection structure 14 is opposite to the doping type of the epitaxial layer 11. In the direction perpendicular to the first surface, the trench bottom protection structure 14 has no overlapping area with the auxiliary trench gate 13, that is, the trench bottom protection structure 14 does not need to be provided at the bottom of the auxiliary trench gate 13.

[0045] The bottom protection structure 14 in the epitaxial layer 11 at the bottom of the main trench gate 12 is a P+ ion implantation region, while the epitaxial layer 11 is N- ion doped. A substrate 10 is also provided in the second surface of the epitaxial layer 11, and the doping type of the substrate 10 is N+ ion doping. By providing the bottom protection structure 14, the voltage at the bottom of the main trench gate 12 can be reduced, so that the voltage of this part is close to the voltage of the source 17, and the voltage difference at the position of the gate dielectric layer 123 at the bottom of the main trench gate 12 is reduced, thereby protecting the gate dielectric layer 123. At the same time, the bottom protection structure 14 in the epitaxial layer 11 at the bottom of two adjacent main trench gates 12 will form a JFET effect, which can protect the auxiliary trench gate 13 located between the two main trench gates 12 from being affected by the over-electric field.

[0046] In the semiconductor device described above, there is a source region 15 in the first surface between adjacent main trench gates 12 and auxiliary trench gates 13. If multiple auxiliary trench gates 13 are arranged between two adjacent main trench gates 12, there is a source region 15 in the first surface between adjacent auxiliary trench gates 13. The source region 15 includes a first source region 151 and a second source region 152 of different doping types. Among them, the first source region 151 is of the second doping type, and its sidewall forms a channel with the trench, which can play a channel role when the FinFET action occurs; the second source region 152 is of the first doping type; the first surface is covered with an insulating layer 16; the insulating layer 16 has an opening for leaking out of the source region 15, and the opening in the leaking source region 15 is not shown in the drawings of the embodiment of the present application; the surface of the insulating layer 16 is covered with a metal source electrode 17, and the metal source electrode 17 is connected to the source region 15 through the opening in the leaking source region 15.

[0047] By covering the first surface with an insulating layer 16, the metal source 17 located on the top of the insulating layer 16 is insulated from the main trench gate 12 and the auxiliary trench gate 13, and the opening of the insulating layer 16 corresponding to the source region 15 can ensure the contact between the metal source 17 and the source region 15. The opening penetrates the insulating layer, and the area corresponding to the opening is the area outside the auxiliary trench gate, which is not shown in the drawings.

[0048] The source region 15 includes a second source region 152 close to the first surface and a first source region 151 located under the second source region 152. The first source region 151 and the second source region 152 can be formed in the first surface through an ion implantation region. The second source region 152 is in contact with the metal source electrode 17 through an opening. The doping type of the second source region 152 and the substrate 10 are both N+ ion doping, and the first source region 151 is P- ion doping. The existence of the second source region 152 and the first source region 151 can improve the control of the main trench gate 12 and the auxiliary trench gate 13, thereby improving the mobility of carriers in the device, so that the performance of the semiconductor device is improved.

[0049] The present application also provides a method for manufacturing a semiconductor device, referring to Figure 5-Figure 8 As shown, Figure 5 A process signaling diagram of a semiconductor device manufacturing method provided in an embodiment of the present application. Figure 6-Figure 8 A product structure diagram of a semiconductor device manufacturing method in different process steps provided in an embodiment of the present application, combined with Figure 5-Figure 8 , the manufacturing method provided in this application includes: Step S11, as Figure 6 As shown, a substrate 10 is provided.

[0050] Step S12, as Figure 7 As shown, an epitaxial layer 11 is formed on a substrate 10 , and the epitaxial layer 11 has a first surface and a second surface opposite to each other; the first surface is away from the substrate.

[0051] Step S13, as Figure 8 As shown, a main trench gate 12 and an auxiliary trench gate 13 are formed in the first surface; wherein, the first surface has a plurality of main trench gates 12 arranged in sequence in the first direction X; the first surface between two adjacent main trench gates 12 has at least one auxiliary trench gate 13; the depth of the auxiliary trench gate 13 is less than the depth of the main trench gate 12.

[0052] refer to Figure 8-Figure 10 , Figure 9-10 A product structure diagram of a method for manufacturing a main trench gate and an auxiliary trench gate in different process steps provided in an embodiment of the present application, combined with Figure 8-Figure 10 As shown, in the above step S13, forming the main trench gate 12 and the auxiliary trench gate 13 includes: Step S21, as Fig. 9 As shown, a main trench 121 and an auxiliary trench 131 are formed in the first surface.

[0053] Step S22, as Fig.10 As shown, a gate dielectric layer 123 is formed on the surface of the main trench 121 and the surface of the auxiliary trench 131 .

[0054] Step S23, as Figure 8 As shown, gate semiconductor material is filled in the main trench 121 having the gate dielectric layer 123 and in the auxiliary trench 131 .

[0055] Before forming the gate dielectric layer in the above step S22, the method further includes: Based on the main trench 121 , ion implantation is performed on the epitaxial layer 11 to form a trench bottom protection structure 14 in the epitaxial layer 11 at the bottom of the main trench 121 ; wherein the doping type of the trench bottom protection structure 14 is opposite to that of the epitaxial layer 11 .

[0056] In the above step S21, the method of forming the main trench 121 and the auxiliary trench 131 includes: One method for forming the main groove 121 and the auxiliary groove 131 is: first, multiple mask structures are deposited on the first surface, a mask layer is deposited on the surface of the mask structure, and then the mask layer and the mask structure are parallel to the first surface, and the epitaxial layer 11 is etched based on the remaining mask layer to form the main groove 121 and the auxiliary groove 131.

[0057] Another way to form the main trench 121 and the auxiliary trench 131 is: deposit a mask layer on the first surface, then etch the mask layer to expose a portion of the first surface, and etch the epitaxial layer 11 based on the remaining mask layer to form the main trench 121 and the auxiliary trench 131.

[0058] In the first method described above, the spacing between the remaining mask layers is large due to the limitation of the mask structure. In the second method, the remaining mask layer is large due to the limitation of the etching equipment accuracy, and the spacing between two adjacent remaining mask layers is large. In addition, in the above two methods, the auxiliary trench gate 13 formed is deep and wide, and the spacing between two adjacent auxiliary trenches 131 is large. Due to the limitation of the equipment and the manufacturing method, it is difficult to form an auxiliary trench 131 with a smaller width and a shallower depth, and it is difficult to reduce the spacing between two adjacent auxiliary trenches 131.

[0059] In order to solve the above problems, in the embodiment of the present application, a method for forming the main groove 121 and the auxiliary groove 131 is provided. Figure 11-Figure 16 , Figure 11-Figure 16 A product structure diagram of a method for manufacturing a main groove and an auxiliary groove in different process steps provided in an embodiment of the present application, forming a main groove 121 and an auxiliary groove 131 in the first surface includes: Step S211, as Fig.11 As shown, a sacrificial structure 21 is formed on the first surface.

[0060] Step S212, as Fig.12 As shown, multiple layers of alternating first sacrificial layers 22 and second sacrificial layers 24 are deposited on the top and side walls of the sacrificial structure 21; the first sacrificial layer 22 includes: a first part 222 and a second part 221, the first part 222 is located above the plane where the top of the sacrificial structure 21 is located; the second part 221 is located below the plane where the top of the sacrificial structure 21 is located, and parallel to the plane where the side walls of the sacrificial structure 21 are located.

[0061] Step S213, as Figure 13-14 As shown, the first sacrificial layer 22 and the second sacrificial layer 24 above the plane where the top of the sacrificial structure 21 is located are removed, and the second sacrificial layer 24 and the sacrificial structure 21 between the second portion 221 are removed.

[0062] Among them, the first part 222 of the first sacrificial layer 22 and part of the second sacrificial layer 24 above the plane where the top of the sacrificial structure 21 is located can be removed by using a CMP process, and then the remaining structure can be selectively etched to retain the second part 221 of the first sacrificial layer 22 and remove the remaining second sacrificial layer 24. The spacing between two adjacent second parts 221 is the thickness of the second sacrificial layer 24, and the thickness of the second part 221 is the same as the deposition thickness of the first sacrificial layer 22. Since the deposition process is relatively mature, the thickness of the first sacrificial layer and the thickness of the second sacrificial layer are relatively small. This makes the thickness of the formed second part 221 and the spacing between two adjacent second parts 221 smaller.

[0063] Step S214, as Fig.15As shown, based on the second portion 221 , a main trench 121 and an auxiliary trench 131 are formed in the first surface; wherein the main trench 121 is located in the first surface corresponding to the sacrificial structure 21 ; and the auxiliary trench 131 is located between two adjacent second portions 221 .

[0064] In this step, dry etching is used to form the main groove 121 and the auxiliary groove 131. Due to the characteristic of dry etching that different etching depths are formed according to different etching widths, the spacing between the second parts 221 formed corresponding to the auxiliary grooves is smaller, and the sacrificial structure 21 is formed at the position corresponding to the main groove 121, and the spacing between the second parts 221 on both sides of the sacrificial structure is larger. Therefore, based on the second part, a dry etching is performed on the epitaxial layer once to form a deeper main groove 121 and a shallower auxiliary groove 131.

[0065] A larger width gap formed based on the sacrificial structure 21 is used to form the main groove 121, and a smaller width gap formed based on the second part 221 is used to form the auxiliary groove 131. The groove depths formed by gaps of different widths are different. The larger the gap width, the greater the groove depth. Therefore, self-aligned etching of the main groove 121 and the auxiliary groove 131 can be achieved in the embodiment of the present application. The main groove 121 and the auxiliary groove 131 of different depths can be formed by one etching, and the depth of the main groove 121 is greater than the depth of the auxiliary groove 131.

[0066] Step S215, as Fig.16 As shown, the second portion 221 is removed.

[0067] In the manufacturing method provided in the present application, since the width of the formed second part 221 can be changed by the thickness of the deposited first sacrificial layer 22, and the spacing between two adjacent second parts 221 can be changed by the thickness of the deposited second sacrificial layer 24, since the deposition process is more mature, the first sacrificial layer 22 and the second sacrificial layer 24 with smaller thickness can be deposited, so that the width of the second part is smaller, and the spacing between two adjacent second parts is smaller, and then the depth of the auxiliary groove 131 formed by dry etching based on the second part is shallower, and the spacing between two adjacent auxiliary grooves 131 is smaller. In addition, more auxiliary grooves 131 can be formed between two adjacent main grooves 121, which improves the density of the trench gate of the semiconductor device formed based on this structure.

[0068] Before removing the second portion 221 described in S215, ions can be implanted into the epitaxial layer 11 at the bottom of the main trench 121 by high-precision ion implantation to form a trench bottom protection structure 14. However, this method has high requirements on the precision of ion implantation, so expensive ion implantation equipment is required, which increases the process cost. Therefore, the present application provides a method for forming a trench bottom protection structure 14. Figure 17-Figure 19 As shown, Figure 17-Figure 19 This is a product structure diagram of a manufacturing method of a groove bottom protection structure provided by this application in different process steps. Figure 17-Figure 19 As shown, before removing the second part, it also includes: First, if Fig.17 As shown, a third sacrificial layer 23 is formed, and the third sacrificial layer 23 covers the sidewalls of the main trench and fills the auxiliary trench. In this step, the third sacrificial layer 23 can be formed only above the first surface, or only in the main trench gate 12. It is only necessary to ensure that ions are implanted based on the third sacrificial layer 23, and the bottom protection structure 14 formed is as shown in FIG. Fig.16 As shown, the present application does not limit the specific shape and position of the third sacrificial layer 23.

[0069] Then, if Fig.18 As shown, ion implantation is performed based on the bottom of the main trench exposed by the third sacrificial layer 23 to form a trench bottom protection structure 14 in the epitaxial layer 11 at the bottom of the main trench 121. This method can achieve a second self-alignment based on the first sacrificial layer 22 and the third sacrificial layer 23, and can distinguish the area of ​​the main trench 121 that needs ion implantation to form the trench bottom protection structure 14 and the non-ion implantation area.

[0070] Finally, if Fig.19 As shown, the third sacrificial layer 23 is removed. After removing the second portion 221, the following is formed Fig.16 In the structure shown, after removing the third sacrificial layer 23 and the second portion 221, a gate material is filled in the main trench and the auxiliary trench having a gate dielectric layer.

[0071] When ion implantation is performed based on the method provided in the present application, since the auxiliary trench 131 and the sidewall of the main trench both have the third sacrificial layer 23, the ion implantation can be performed directly to form the bottom trench protection structure 14 in the epitaxial layer at the bottom of the main trench, thereby reducing the process difficulty. The third sacrificial layer 23 located on the sidewall of the main trench 121 can not only ensure that the ions are implanted into the epitaxial layer 11 located at the bottom of the main trench 121. The position of the third sacrificial layer 23 can also be adjusted to adjust the boundary position of the bottom trench protection structure 14, thereby improving the process accuracy.

[0072] In an implementation of the embodiment of the present application, along the second direction Y, the depths of the main trench gate 12 and the auxiliary trench gate 13 may be uniform and unchanged.

[0073] refer to Fig. 20 , Fig. 20 A schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application is shown. Fig. 20 It is a cross-sectional view of the semiconductor device parallel to the second direction.

[0074] Based on any of the above implementations, Fig. 20 As shown, the depth of the main trench gate 12 can be set to be uniform along the second direction Y, and the depth of the main trench 121 can be set to be uniform along the second direction Y. If a trench bottom protection structure 14 is provided, the implantation depth of the trench bottom protection structure 14 at the bottom of the main trench 1221 is uniform.

[0075] refer to Fig.21 , Fig.21 A schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application is shown. Fig.21 It is a cross-sectional view of the semiconductor device parallel to the second direction.

[0076] Based on any of the above implementations, Fig.21 As shown, the depth of the main trench gate 12 can be set to change periodically along the second direction Y, and the depth of the main trench 121 can change periodically along the second direction Y. The main trench gate 121 includes a first region 12a and a second region 12b alternately distributed along the second direction Y, wherein the depth of the first region 12a is greater than the depth of the second region 12b.

[0077] The depth of the main trench gate 12 is set to change periodically along the second direction Y, which can prevent the electric field from gathering at the bottom of the main trench gate 12, thereby preventing the gate dielectric layer 123 from being broken down due to the electric field gathering.

[0078] At this time, if a groove bottom protection structure 14 is provided, the groove bottom protection structure 14 can be provided in the bottom surface of the main groove 121 in the first region 12a, and the groove bottom protection structure 14 and the bottom surface of the main groove 121 in the second region 12b have no overlapping area. Since the depth of the first region 12a is large, the breakdown problem is more likely to occur in the first region 12a, and it is not necessary to provide the groove bottom protection structure 14 below the second region 12b. In this way, the area of ​​the ion implantation region used to form the groove bottom protection structure 14 can be reduced.

[0079] Further, such as Fig.21 As shown, along the second direction Y, the depth of the first region 12a can be set to gradually decrease from the central area of ​​the first region 12a to both sides, and the depth of the second region 12b can be set to gradually increase from the central area of ​​the second region 12b to both sides, so as to achieve a periodic and continuous gradient of the depth of the main trench gate 12 along the second direction Y, so as to better optimize the electric field and resistance distribution at the bottom of the trench, and better improve the device performance.

[0080] Furthermore, for two adjacent main trench gates 12 in the first direction X, a first region 12a of one main trench gate 12 may be arranged to be opposite to a second region 12b of another main trench gate 12. In this way, the current flow inside the device can be converted into a three-dimensional grid structure, which can better reduce the intensity of the electric field at the bottom of the first region 12a of the device and improve the withstand voltage performance of the device.

[0081] In this specification, each embodiment is described in a progressive, parallel, or progressive and parallel manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the device part description.

[0082] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same reference numerals throughout the embodiments of the specification identify the same structure. In addition, for the sake of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. It is also understood that when an element such as a layer, film, region, or substrate is referred to as "on" another element, the element may be directly on the other element or there may be an intermediate element. In addition, "on" refers to positioning an element on or below another element, but does not essentially refer to positioning on the upper side of another element according to the direction of gravity.

[0083] The terms "upper", "lower", "top", "bottom", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0084] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0085] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor device having an auxiliary trench gate, characterized in that: include: an epitaxial layer having opposing first and second surfaces; A plurality of main trench gates located in the first surface, the main trench gates being sequentially spaced apart in a first direction; A plurality of auxiliary trench gates are arranged in sequence in the first surface between two adjacent main trench gates; The depth of the auxiliary trench gate is smaller than the depth of the main trench gate.

2. The semiconductor device according to claim 1, wherein: Between two adjacent main trench gates, the depths of the plurality of auxiliary trench gates are the same.

3. The semiconductor device according to claim 1, wherein: Between two adjacent main trench gates, the depths of the plurality of auxiliary trench gates are not completely the same.

4. The semiconductor device according to claim 1, wherein: The distance between two adjacent main trench gates is 1 μm to 2 μm; The spacing between two adjacent main trench gates and between the auxiliary trench gates is less than 100 nm.

5. The semiconductor device according to claim 1, wherein: A trench bottom protection structure is provided in the epitaxial layer at the bottom of the main trench gate, and the doping type of the trench bottom protection structure is opposite to the doping type of the epitaxial layer.

6. The semiconductor device according to any one of claims 1 to 6, characterized in that: The first surface between two adjacent trench gates has a source region; The first surface is covered with an insulating layer; the insulating layer has an opening leaking out of the source region; A metal source electrode is covered on the surface of the insulating layer, and the metal source electrode is connected to the source region through the opening.

7. A method for manufacturing a semiconductor device according to any one of claims 1 to 6, characterized in that: include: forming an epitaxial layer on a substrate, the epitaxial layer having a first surface and a second surface opposite to each other; The first surface faces away from the substrate; A main trench gate and an auxiliary trench gate are formed in the first surface; wherein the first surface has a plurality of main trench gates arranged in sequence in a first direction; the first surface between two adjacent main trench gates has a plurality of auxiliary trench gates arranged in sequence; the depth of the auxiliary trench gate is less than the depth of the main trench gate.

8. The method according to claim 7, characterized in that: Forming the main trench gate and the auxiliary trench gate includes: forming a main groove and an auxiliary groove in the first surface; forming a gate dielectric layer on the surface of the main trench and the surface of the auxiliary trench; The gate material is filled in the main trench and the auxiliary trench having the gate dielectric layer.

9. The manufacturing method according to claim 8, characterized in that: Before forming the gate dielectric layer, the method further includes: Based on the main trench, ion implantation is performed on the epitaxial layer to form a trench bottom protection structure in the epitaxial layer at the bottom of the main trench; Wherein, the doping type of the trench bottom protection structure is opposite to the doping type of the epitaxial layer.

10. The manufacturing method according to claim 8, characterized in that: The method of forming the main groove and the auxiliary groove comprises: forming a sacrificial structure on the first surface; Depositing multiple layers of alternately stacked first and second sacrificial layers on the top and sidewalls of the sacrificial structure; the first sacrificial layer comprises: a first portion and a second portion, the first portion being located above the plane where the top is located; the second portion being located below the plane where the top is located and parallel to the plane where the sidewall is located; removing the first sacrificial layer and the second sacrificial layer above the plane where the top is located, and removing the second sacrificial layer and the sacrificial structure between the second parts; Based on the second portion, forming the main groove and the auxiliary groove in the first surface; Remove the second part; Wherein, the main groove is located in the first surface corresponding to the sacrificial structure; and the auxiliary groove is located between two adjacent second parts.

11. The manufacturing method according to claim 10, characterized in that: Before removing the second part, the method further comprises: forming a third sacrificial layer, wherein the third sacrificial layer covers the sidewalls of the main trench and fills the auxiliary trench; Based on the bottom of the main trench exposed by the third sacrificial layer, ion implantation is performed to form a trench bottom protection structure in the epitaxial layer at the bottom of the main trench; After removing the third sacrificial layer and the second portion, gate material is filled in the main trench and the auxiliary trench having the gate dielectric layer.

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