Asymmetric hybrid multi-gate semiconductor device, manufacturing method thereof and chip

Abstract

The invention discloses an asymmetric hybrid multi-gate semiconductor device, a manufacturing method thereof and a chip, and belongs to the technical field of semiconductors. The asymmetric hybrid multi-gate semiconductor device comprises a substrate which comprises a first high-voltage well region, a drain region, a first drift region and a second drift region which are sequentially connected in the target direction are arranged in the first high-voltage well region, and the doping concentration of the second drift region is larger than that of the first drift region; a first source region and a second source region which are spaced in the target direction are arranged in the well region in the second drift region, the well region, close to one side of the first drift region, of the first source region forms a first channel region, and the well region at the bottom of the second source region forms a second channel region; a first gate structure covering the first channel region; the second gate structure is located in the first high-voltage well region and covers the second channel region. According to the invention, the overcurrent capability of the device can be improved, a small device area is maintained, and the integration level of the device is ensured.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to an asymmetric hybrid multi-gate semiconductor device and a manufacturing method and chip thereof. Background Art

[0002] Modern power electronics technology requires chip systems to develop in the direction of high frequency, integration and intelligence, and the BCD (Bipolar-CMOS-DMOS) process is the key to achieving this trend. As the core device of power chips, DMOS (double-diffused MOSFET) devices have outstanding advantages such as high voltage resistance, large current, and easy driving, and are widely used in power management, motor control, automotive electronics and other industrial fields.

[0003] To achieve process platform compatibility, DMOS devices usually adopt a lateral design, with voltage-bearing units distributed in parallel on the chip surface, forming the LDMOS (Lateral DMOS) device type. The overcurrent capability of LDMOS devices is positively correlated with the voltage-bearing unit. Although a larger voltage-bearing unit brings excellent overcurrent characteristics, it greatly increases the surface area of ​​the device, and the integration level of the chip is greatly reduced. Summary of the invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes an asymmetric hybrid multi-gate semiconductor device and a manufacturing method and chip thereof, which can improve the overcurrent capability of the device while maintaining a small device area and ensuring the device integration.

[0005] In a first aspect, the present application provides an asymmetric hybrid multi-gate semiconductor device, comprising:

[0006] A substrate, comprising a first high-voltage well region, wherein the first high-voltage well region is provided with a drain region, a first drift region, and a second drift region sequentially connected along a target direction, wherein the doping concentration of the second drift region is greater than the doping concentration of the first drift region; wherein the second drift region is provided with a well region, wherein the well region is provided with a first source region and a second source region spaced apart along the target direction, wherein the well region of the first source region close to one side of the first drift region constitutes a first channel region, and the well region at the bottom of the second source region constitutes a second channel region;

[0007] A first gate structure, located on one side of the substrate and covering the first channel region;

[0008] The second gate structure is located in the first high-voltage well region and on a side of the second drift region away from the first drift region, and covers the second channel region.

[0009] According to the asymmetric hybrid multi-gate semiconductor device of the present application, by setting a first drift region and a second drift region, and the doping concentration of the second drift region is greater than the doping concentration of the first drift region, the current can be diverted to two conduction paths, the first conduction path is from the drain region through the first drift region and the first channel region to the first source region, the second conduction path is from the drain region through the first drift region, the second drift region and the second channel region to the second source region, and the second channel region is arranged along the thickness direction of the substrate, which effectively reduces the on-resistance of the device, increases the overcurrent capacity of the device, and makes the heat inside the device more uniform, while maintaining a smaller device area, thereby ensuring the device integration.

[0010] According to one embodiment of the present application, the drain region, the first drift region, the first channel region and the first source region constitute a first conduction path, the drain region, the first drift region, the second drift region, the second channel region and the second source region constitute a second conduction path, and the first conduction path and the second conduction path are arranged in parallel.

[0011] According to an embodiment of the present application, the on-resistance of the first conducting path is symmetrical to the on-resistance of the second conducting path.

[0012] According to one embodiment of the present application, a length of the second channel region along a thickness direction of the substrate is smaller than a length of the first channel region along a target direction, and the target direction is perpendicular to the thickness direction.

[0013] According to an embodiment of the present application, the first source region and the second source region are arranged asymmetrically.

[0014] According to one embodiment of the present application, the ion concentration of the second source region is greater than the ion concentration of the first source region.

[0015] According to one embodiment of the present application, a depth of the second source region along a thickness direction of the substrate is greater than a depth of the first source region along the thickness direction.

[0016] According to one embodiment of the present application, a body electrode contact region is also provided in the well region, and the body electrode contact region is located between the first source region and the second source region, and the distance between the body electrode contact region and the first source region is greater than the distance between the body electrode contact region and the second source region.

[0017] According to an embodiment of the present application, a cross section of the second drift region coincides with a cross section of the well region along the target direction.

[0018] According to an embodiment of the present application, the semiconductor device further includes an isolation structure, wherein the isolation structure is located between the first drift region and the first gate structure.

[0019] According to an embodiment of the present application, the isolation structure includes a field oxide structure or a shallow trench isolation structure.

[0020] According to an embodiment of the present application, the first gate structure covers the first channel region, a portion of the isolation structure, and a first drift region between the isolation structure and the first channel region.

[0021] According to an embodiment of the present application, the first gate structure includes a first gate and a first gate insulating layer;

[0022] The first gate insulating layer covers the first channel region, a portion of the isolation structure, and a first drift region between the isolation structure and the first channel region, and the first gate covers the first gate insulating layer.

[0023] According to one embodiment of the present application, the second gate structure extends from the upper surface of the second drift region along the thickness direction of the substrate into the second drift region, and the height of the second gate structure along the thickness direction is greater than or equal to the depth of the well region along the thickness direction.

[0024] According to an embodiment of the present application, the second gate structure includes a second gate and a second gate insulating layer;

[0025] The second gate extends from the upper surface of the second drift region along the thickness direction into the second drift region, and the second gate oxide layer is arranged around the second gate.

[0026] According to an embodiment of the present application, a lightly doped source region is further provided in the well region, and the lightly doped source region is located between the first source region and the first channel region.

[0027] According to one embodiment of the present application, the substrate further includes a second high-voltage well region;

[0028] The second high-voltage well region is spaced apart from the first high-voltage well region along the target direction, and a substrate electrode contact region is provided in the second high-voltage well region.

[0029] According to one embodiment of the present application, the semiconductor device further includes a drain contact, a first source contact, a second source contact, a first gate contact, and a second gate contact;

[0030] The drain contact is located on the drain region and connected to the drain region, the first source contact is located on the first source region and connected to the first source region, the second source contact is located on the second source region and connected to the second source region, the first source contact is connected to the second source contact, the first gate contact is located on the first gate structure and connected to the first gate structure, and the second gate contact is located on the second gate structure and connected to the second gate structure.

[0031] In a second aspect, the present application provides a chip, comprising the asymmetric hybrid multi-gate semiconductor device as described in the first aspect above.

[0032] In a third aspect, the present application provides a method for manufacturing an asymmetric hybrid multi-gate semiconductor device, comprising:

[0033] forming a first high-voltage well region in a substrate;

[0034] forming a first drift region and a second drift region connected along a target direction in the first high-voltage well region, wherein the doping concentration of the second drift region is greater than the doping concentration of the first drift region;

[0035] forming a well region in the second drift region;

[0036] forming a first gate structure on one side of the substrate, and forming a second gate structure in the first high-voltage well region on a side of the second drift region away from the first drift region;

[0037] A drain region is formed in the first high-voltage well region on the side of the first drift region away from the second drift region, and a first source region and a second source region spaced apart along the target direction are formed in the well region, the well region of the first source region close to the side of the first drift region constitutes a first channel region, the well region at the bottom of the second source region constitutes a second channel region, the first gate structure covers the first channel region, and the second gate structure covers the second channel region.

[0038] According to one embodiment of the present application, the drain region, the first drift region, the first channel region and the first source region constitute a first conduction path, the drain region, the first drift region, the second drift region, the second channel region and the second source region constitute a second conduction path, the first conduction path and the second conduction path are arranged in parallel, and the on-resistance of the first conduction path is the same as the on-resistance of the second conduction path.

[0039] According to an embodiment of the present application, the first source region and the second source region are arranged asymmetrically.

[0040] According to one embodiment of the present application, the method further includes:

[0041] A body electrode contact region is formed in the well region between the first source region and the second source region, and a distance between the body electrode contact region and the first source region is greater than a distance between the body electrode contact region and the second source region.

[0042] According to an embodiment of the present application, the cross-section of the second drift region coincides with that of the well region along the target direction, and the second drift region and the well region are formed using the same mask.

[0043] According to an embodiment of the present application, before forming the first drift region and the second drift region connected along the target direction in the first high-voltage well region, the method further includes:

[0044] forming an isolation structure in the first high-voltage well region;

[0045] Wherein, the isolation structure is located between the first drift region and the first gate structure.

[0046] According to an embodiment of the present application, forming a first gate structure on one side of the substrate, and forming a second gate structure in the first high-voltage well region on a side of the second drift region away from the first drift region, includes:

[0047] forming a gate trench in the first high-voltage well region on a side of the second drift region away from the first drift region, wherein the gate trench extends from an upper surface of the second drift region along a thickness direction of the substrate into the second drift region, and a height of the gate trench along the thickness direction is greater than or equal to a depth of the well region along the thickness direction;

[0048] A first gate structure is formed on one side of the substrate, and a second gate structure is formed in the gate trench, wherein the first gate structure covers the first channel region, a portion of the isolation structure, and a first drift region between the isolation structure and the first channel region.

[0049] According to an embodiment of the present application, the first gate structure includes a first gate and a first gate insulating layer, and the second gate structure includes a second gate and a second gate insulating layer;

[0050] The first gate structure is formed on one side of the substrate, and the second gate structure is formed in the gate trench, comprising:

[0051] forming the first gate insulating layer on one side of the substrate, and forming the second gate insulating layer on the inner surface of the gate trench, wherein the first gate insulating layer covers the first channel region, a portion of the isolation structure, and a first drift region between the isolation structure and the first channel region;

[0052] The first gate is formed on a side of the first gate insulating layer facing away from the substrate, and the second gate is filled in the gate trench.

[0053] According to one embodiment of the present application, the method further includes:

[0054] A lightly doped source region is formed in the well region on a side of the first source region close to the first drift region, and the well region between the lightly doped source region and the first drift region constitutes the first channel region.

[0055] According to one embodiment of the present application, the method further includes:

[0056] forming a second high-voltage well region in the substrate, wherein the second high-voltage well region and the first high-voltage well region are spaced apart from each other along the target direction;

[0057] A substrate electrode contact region is formed in the second high-voltage well region.

[0058] According to one embodiment of the present application, the method further includes:

[0059] A drain contact connected to the drain region is formed on the drain region, a first source contact connected to the first source region is formed on the first source region, a second source contact connected to the second source region is formed on the second source region, the first source contact is connected to the second source contact, a first gate contact connected to the first gate structure is formed on the first gate structure, and a second gate contact connected to the second gate structure is formed on the second gate structure.

[0060] The above one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0061] By setting a first drift region and a second drift region, and the doping concentration of the second drift region is greater than the doping concentration of the first drift region, the current can be diverted to two conduction paths. The first conduction path is from the drain region through the first drift region and the first channel region to the first source region, and the second conduction path is from the drain region through the first drift region, the second drift region and the second channel region to the second source region. The second channel region is arranged along the thickness direction of the substrate, which effectively reduces the on-resistance of the device, increases the overcurrent capacity of the device, and makes the heat inside the device more uniform. At the same time, a smaller device area is maintained, thereby ensuring the device integration.

[0062] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0064] Figure 1 It is a schematic diagram of the structure of a standard LDMOS device in the related art;

[0065] Figure 2 It is a schematic diagram of the structure of a dual-gate LDMOS device in the related art;

[0066] Figure 3 is a schematic structural diagram of an asymmetric hybrid multi-gate semiconductor device provided in an embodiment of the present application;

[0067] Figure 4 It is a schematic flow chart of a method for manufacturing an asymmetric hybrid multi-gate semiconductor device provided in an embodiment of the present application;

[0068] Figure 5 This is one of the structural schematic diagrams of the method for manufacturing an asymmetric hybrid multi-gate semiconductor device provided in an embodiment of the present application;

[0069] Figure 6 This is the second structural schematic diagram of the method for manufacturing an asymmetric hybrid multi-gate semiconductor device provided in an embodiment of the present application;

[0070] Figure 7 This is the third structural schematic diagram of the method for manufacturing an asymmetric hybrid multi-gate semiconductor device provided in an embodiment of the present application;

[0071] Figure 8 This is the fourth structural schematic diagram of the method for manufacturing an asymmetric hybrid multi-gate semiconductor device provided in an embodiment of the present application;

[0072] Fig. 9 This is the fifth structural schematic diagram of the method for manufacturing an asymmetric hybrid multi-gate semiconductor device provided in an embodiment of the present application;

[0073] Fig.10 This is the sixth structural schematic diagram of the method for manufacturing an asymmetric hybrid multi-gate semiconductor device provided in an embodiment of the present application;

[0074] Fig.11 This is the seventh structural schematic diagram of the method for manufacturing an asymmetric hybrid multi-gate semiconductor device provided in an embodiment of the present application;

[0075] Fig.12This is the eighth structural schematic diagram of the method for manufacturing an asymmetric hybrid multi-gate semiconductor device provided in an embodiment of the present application;

[0076] Fig.13 This is the ninth structural schematic diagram of the method for manufacturing an asymmetric hybrid multi-gate semiconductor device provided in an embodiment of the present application;

[0077] Fig.14 This is the tenth structural schematic diagram of the method for manufacturing an asymmetric hybrid multi-gate semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0078] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0079] The related art has two types of LDMOS devices, namely, a standard LDMOS device and a dual-gate LDMOS device. Figure 1 As shown, the standard LDMOS device includes a substrate 100, the substrate 100 includes a high-voltage well region 101, the high-voltage well region 101 is provided with a drain region 106, a drift region 102 and a well region 103 sequentially connected along a target direction X, a source region 104 is provided in the well region 103, and the well region on one side of the source region 104 close to the drift region 102 forms a channel C. The standard LDMOS device also includes a field oxide structure 105 located on the drift region 102 and a gate structure 107 covering the field oxide structure 105, a portion of the drift region 102 and the C-side of the channel region.

[0080] The pressure-bearing capacity of a standard LDMOS device is determined by the current conduction path under the field oxide structure 105. Under the regulation of the gate field plate, the electric field distribution inside the device is smooth. When turned on, the current flows from the drain region 106 along the dotted line through the drift region 102 to the source region 104. Since the conduction path is much longer than the length of the channel C, the on-resistance of the device is increased compared to ordinary CMOS devices (only the channel region), and the overcurrent capability of the device is reduced.

[0081] like Figure 2As shown, the drift region 102, drain region 106, source region 104, channel C, field oxide structure 105 and gate structure 107 in the dual-gate LDMOS device are all symmetrically arranged, that is, the dual-gate LDMOS device adopts a dual-gate structure to enhance the overcurrent capability of the LDMOS device. The pressure-bearing part of the dual-gate LDMOS device is symmetrically distributed on both sides of the device. By connecting the electrode structures in parallel, the overall resistance of the device becomes 1 / 2 of the on-resistance of the standard LDMOS device without changing the voltage bearing, and the overcurrent capability is greatly improved. However, the dual-gate LDMOS device greatly increases the device area. Generally, the integration of the BCD process chip is determined by the power device. The increase in the area of ​​the dual-gate LDMOS device greatly affects the integration of the chip, and the chip performance is therefore limited.

[0082] The asymmetric hybrid multi-gate semiconductor device and its manufacturing method and chip provided by the embodiments of the present application are described below with reference to the accompanying drawings.

[0083] Figure 3 The schematic diagram of the structure of an asymmetric hybrid multi-gate semiconductor device provided in an embodiment of the present application is shown in FIG.

[0084] like Figure 3 As shown, the asymmetric hybrid multi-gate semiconductor device provided in the embodiment of the present application includes a substrate 1, the substrate 1 includes a first high-voltage well region 21, the first high-voltage well region 21 is provided with a drain region 3, a first drift region 41 and a second drift region 42 sequentially connected along a target direction X, and the doping concentration of the second drift region 42 is greater than the doping concentration of the first drift region 41. A well region 5 is provided in the second drift region 42, and a first source region 61 and a second source region 62 spaced apart along the target direction X are provided in the well region 5, the well region of the first source region 61 close to one side of the first drift region 41 constitutes a first channel region C1, and the well region at the bottom of the second source region 62 constitutes a second channel region C2.

[0085] The substrate 1 may be a silicon substrate or a germanium substrate, or a semiconductor substrate including other elements. The substrate 1 may be a first doping type substrate, and the first doping type may be P-type or N-type. For example, a trace amount of trivalent elements, such as boron, indium, gallium, aluminum, etc., may be doped into the substrate 1 to form a P-type semiconductor substrate; a trace amount of pentavalent elements, such as phosphorus, antimony, arsenic, etc., may also be doped into the substrate 1 to form an N-type semiconductor substrate.

[0086] The first high-voltage well region 21 is located in the substrate 1, and the first high-voltage well region 21 is arranged close to the upper surface of the substrate 1. The first high-voltage well region 21 constitutes an active region. The first high-voltage well region 21 has a second doping type, and the second doping type may be P-type or N-type, and the second doping type is different from the first doping type, that is, the first high-voltage well region 21 is different from the doping type of the substrate 1. For example, the substrate 1 is a P-type semiconductor substrate, and the first high-voltage well region 21 is a high-voltage N-type well region.

[0087] The first drift region 41 and the second drift region 42 are both located in the first high-voltage well region 21, and the first drift region 41 and the second drift region 42 are arranged close to the upper surface of the first high-voltage well region 21. The first drift region 41 and the second drift region 42 are adjacent to each other along the target direction X, and the target direction X is parallel to the upper surface of the substrate 1. The first drift region 41 and the second drift region 42 both have a second doping type, that is, the first drift region 41 and the second drift region 42 have the same doping type as the first high-voltage well region 21. For example, the first high-voltage well region 21 is a high-voltage N-type well region, and the first drift region 41 and the second drift region 42 are both N-type drift regions. Among them, the setting of the first drift region 41 can reduce the overall on-resistance of the device. The second drift region 42 has a high doping concentration, which can make the second drift region 42 have a sufficiently low resistance characteristic to ensure that the current can flow to the second drift region 42 during the device start-up phase.

[0088] The drain region 3 is located in the first high-voltage well region 21, and the drain region 3 is arranged close to the upper surface of the first high-voltage well region 21. The drain region 3 is located on the side of the first drift region 41 away from the second drift region 42, and the drain region 3 is adjacent to the first drift region 41. The drain region 3 has the second doping type, that is, the drain region 3 has the same doping type as the first high-voltage well region 21. For example, the first high-voltage well region 21 is a high-voltage N-type well region, and the drain region 3 is an N-type heavily doped region.

[0089] The well region 5 is located in the second drift region 42, the well region 5 is disposed close to the upper surface of the second drift region 42, and the width of the well region 5 along the target direction X is the same as the width of the second drift region 42 along the target direction X. The well region 5 has a first doping type, that is, the well region 5 has a different doping type from the second drift region 42. For example, the second drift region 42 is an N-type drift region, and the well region 5 is a P-type well region.

[0090] The first source region 61 and the second source region 62 are located in the well region 5, the first source region 61 and the second source region 62 are arranged close to the upper surface of the well region 5, and the first source region 61 and the second source region 62 are arranged at intervals along the target direction X. The first source region 61 and the second source region 62 both have the second doping type, that is, the first source region 61 and the second source region 62 are different from the doping type of the well region 5. For example, the well region 5 is a P-type well region, and the first source region 61 and the second source region 62 are both N-type heavily doped regions.

[0091] The first channel region C1 is located on one side of the first source region 61 close to the first drift region 41, and the second channel region C2 is located at the bottom of the second source region 62. The first channel region C1 is a planar channel, and the second channel region C2 is a vertical channel, so that the present embodiment has the excellent characteristics of both LDMOS (with a planar channel) and VDMOS (with a vertical channel), and can support a larger overcurrent capability of the device.

[0092] The asymmetric hybrid multi-gate semiconductor device further includes a first gate structure 8 . The first gate structure 8 is located on one side of the substrate 1 and covers the first channel region C1 .

[0093] The asymmetric hybrid multi-gate semiconductor device further includes a second gate structure 9, which is located in the first high-voltage well region 21. The second gate structure 9 is located on the side of the second drift region 42 away from the first drift region 41, and the second gate structure 9 is adjacent to the second drift region 42, that is, the second gate structure 9 is adjacent to the well region 5. The second gate structure 9 extends along the thickness direction Y of the substrate 1, and the second gate structure 9 covers the second channel region C2. The target direction X is perpendicular to the thickness direction Y of the substrate 1.

[0094] In this embodiment, by providing the first drift region 41 and the second drift region 42, and the doping concentration of the second drift region 42 is greater than the doping concentration of the first drift region 41, the current in the device can be divided into two paths, that is, a part of the current flows from the drain region 3 through the first drift region 41 and the first channel region C1 to the first source region 61, and the other part of the current flows from the drain region 3 through the first drift region 41, the second drift region 42 and the second channel region C2 to the second source region 62, and the second channel region C2 draws the current along the thickness direction Y of the substrate 1. Compared with the standard LDMOS device, this embodiment reduces the on-resistance of the device, increases the overcurrent capability of the device, and makes the internal heating of the device more uniform. Compared with the dual-gate LDMOS device, this embodiment does not increase the device area by multiples, but still maintains a small device area, thereby ensuring the device integration.

[0095] In some embodiments, the drain region 3, the first drift region 41, the first channel region C1 and the first source region 61 constitute a first conduction path L1, the drain region 3, the first drift region 41, the second drift region 42, the second channel region C2 and the second source region 62 constitute a second conduction path L2, and the first conduction path L1 and the second conduction path L2 are arranged in parallel. The first source region 61 and the second source region 62 may be electrically connected.

[0096] This embodiment sets two parallel conduction paths, the conduction resistance of the first conduction path L1 is jointly determined by the first drift region 41 and the first channel region C1, and the conduction resistance of the second conduction path L2 is jointly determined by the first drift region 41, the second drift region 42 and the second channel region C2. Compared with the standard LDMOS device, this embodiment adds a parallel conduction path (i.e., the second conduction path L2), effectively reduces the conduction resistance of the device, increases the overcurrent capability of the device, and makes the internal heating of the device more uniform. Compared with the dual-gate LDMOS device, the second channel region C2 in the second conduction path L2 in this embodiment is set along the thickness direction Y, does not double the device area, and still maintains a small device area, thereby ensuring the device integration.

[0097] In some embodiments, the on-resistance of the first conducting path L1 is symmetrical to the on-resistance of the second conducting path L2 .

[0098] For example, by adjusting the first channel region C1 and the second channel region C2, the on-resistance of the first conduction path L1 and the on-resistance of the second conduction path L2 can be adjusted so that the on-resistance of the first conduction path L1 and the on-resistance of the second conduction path L2 are equal or similar, reaching a balance state, and further reducing the overall on-resistance of the device.

[0099] In some embodiments, a length of the second channel region C2 along a thickness direction Y of the substrate 1 is smaller than a length of the first channel region C1 along a target direction X, and the target direction X is perpendicular to the thickness direction Y.

[0100] In order to ensure the relative resistance symmetry between the first conduction path and the second conduction path, the length of the second channel region C2 along the thickness direction Y of the substrate 1 is smaller than the length of the first channel region C1 along the target direction X. The second channel region C2 is controlled by the second gate structure 9, which has a lower operating voltage and a stronger field control capability.

[0101] In some embodiments, the first source region 61 and the second source region 62 are arranged asymmetrically.

[0102] For example, the first source region 61 and the second source region 62 have different ion concentrations, and the first source region 61 and the second source region 62 have different doping depths (i.e., depths along the thickness direction Y). The first source region 61 and the second source region 62 are designed asymmetrically, which can make the device have more dimensional optimization potential.

[0103] In some embodiments, the ion concentration of the second source region 62 is greater than the ion concentration of the first source region 61 .

[0104] In some embodiments, the depth of the second source region 62 along the thickness direction Y is greater than the depth of the first source region along the thickness direction Y.

[0105] In this embodiment, the length of the second channel region C2 along the thickness direction Y of the substrate 1 is determined by the doping depth of the second drift region 42 (i.e., the depth along the thickness direction Y), the doping depth of the well region 5, and the doping depth of the second source region 62. Compared with the double-gate LCMOS device, this embodiment weakens the layout design correlation. By optimizing the parameters of the second drift region 42, the well region 5, and the second source region 62, excellent conduction characteristics can be achieved.

[0106] In some embodiments, a body electrode contact region 63 is further provided in the well region 5, and the body electrode contact region 63 is arranged near the upper surface of the well region 5. The body electrode contact region 63 is located between the first source region 61 and the second source region 62, and the body electrode contact region 63 is spaced apart from the first source region 61 and the second source region 62, respectively. The distance between the body electrode contact region 63 and the first source region 61 is greater than the distance between the body electrode contact region 63 and the second source region 62. The body electrode contact region 63 has a first doping type, that is, the body electrode contact region 63 has a different doping type from the first source region 61 and the second source region 62. For example, the first source region 61 and the second source region 62 are N-type heavily doped regions, and the body electrode contact region 63 is a P-type heavily doped region.

[0107] When the standard LDMOS device in the related art is working, the body electrode is usually connected to 0 potential and is not regulated. In this embodiment, the device adjusts the position and bias of the body electrode to perform different regulation on the two channel regions. By changing the relative position between the body electrode contact region 63 and the two source regions, the body electrode contact region 63 is closer to the second source region 62, that is, the distance between the body electrode contact region 63 and the first source region 61 is greater than the distance between the body electrode contact region 63 and the second source region 62, so as to adjust the body electrode bias to perform different degrees of field control on the two channels, thereby achieving effective coordination of the electric field strength of the two channels by the same body electrode, and increasing the flexibility of the device's electrical performance.

[0108] In some embodiments, a lightly doped source region 64 is further provided in the well region 5, and the lightly doped source region 64 is provided near the upper surface of the well region 5. The lightly doped source region 64 is located between the first source region 61 and the first channel region C2, that is, the lightly doped source region 64 is located on the side of the first source region 61 away from the second source region 62, and the lightly doped source region 64 is adjacent to the first source region 61, and the first channel region C2 is located on the side of the lightly doped source region 64 away from the first source region 61.

[0109] In this embodiment, a lightly doped source region 64 is disposed between the first source region 61 and the first channel region C2, which can alleviate electric field breakdown. Moreover, the provision of the lightly doped source region 64 can increase the on-resistance of the second conduction path L2, making the on-resistance of the first conduction path L1 symmetrical with the on-resistance of the second conduction path L2.

[0110] In some embodiments, the second drift region 42 coincides with a cross section of the well region 5 along the target direction X.

[0111] During the manufacturing process, the second drift region 42 and the well region 5 can be formed using the same mask plate, that is, the second drift region 42 is first formed in the first high-voltage well region 21 using a mask plate, and then the well region 5 is formed in the second drift region 42 using the same mask plate, so as to simplify the manufacturing process, reduce production costs, and reduce wafer production losses.

[0112] In some embodiments, the asymmetric hybrid multi-gate semiconductor device further includes an isolation structure 7 , and the isolation structure 7 is located between the first drift region 41 and the first gate structure 8 .

[0113] In some embodiments, the isolation structure 7 includes a field oxide structure or a shallow trench isolation structure. The isolation structure 7 may include silicon oxide, etc. The isolation structure 7 may also include other types of isolation structures, which are not specifically limited here.

[0114] In the case where the isolation structure 7 includes a field oxide structure, part of the structure of the isolation structure 7 may be located in the first drift region 41, and another part of the structure may be located on the first drift region 41. The edge of the isolation structure 7 may be in a bird's beak shape, that is, the cross section of the isolation structure 7 along the thickness direction Y may be in a hexagonal shape. The provision of the field oxide structure 7 can increase the device conduction path, improve the pressure resistance, and at the same time, as a key part of the field plate, regulate the device electric field distribution.

[0115] When the isolation structure 7 includes a shallow trench isolation (STI), the isolation structure 7 may be located in the first drift region 41, and the upper surface of the isolation structure 7 may be flush with the upper surface of the first drift region 41. The cross section of the isolation structure 7 along the thickness direction Y may be in an inverted trapezoidal shape.

[0116] In some embodiments, the first gate structure 8 covers the first channel region C1, a portion of the isolation structure 7, and the first drift region 41 between the isolation structure 7 and the first channel region C1. The first gate structure 8 is located on the isolation structure 7, the first drift region 41, and the well region 5, and the first gate structure 8 only covers a portion of the isolation structure 7, a portion of the first drift region 41, and the first channel region C1 in the well region 5.

[0117] When the well region 5 has a lightly doped source region 64 , the first gate structure 8 does not overlap with the lightly doped source region 64 , that is, the surface of the first gate structure 8 close to the first source region 61 is flush with the surface of the lightly doped source region 64 away from the first source region 61 .

[0118] In some embodiments, the first gate structure 8 includes a first gate 81 and a first gate insulating layer 82. The first gate insulating layer 82 covers the first channel region C1, a portion of the isolation structure 7, and the first drift region 41 between the isolation structure 7 and the first channel region C1, and the first gate 81 covers the first gate insulating layer 82. The first gate insulating layer 82 is used to isolate the first gate 81 from the first drift region 41 and the first channel region C1. The first gate insulating layer 82 may include at least one of silicon nitride, silicon oxide, etc. The first gate 81 may include polysilicon (poly), etc.

[0119] In some embodiments, the second gate structure 9 extends from the upper surface of the second drift region 42 along the thickness direction Y of the substrate 1 into the second drift region 42. The second gate structure 9 is located in the first high-voltage well region 21, and the upper surface of the second gate structure 9 is flush with the upper surface of the first high-voltage well region 21. The height of the second gate structure 9 along the thickness direction Y is greater than or equal to the depth of the well region 5 along the thickness direction Y, so that the second gate structure 9 covers the second channel region C2.

[0120] In some embodiments, the second gate structure 9 includes a second gate 91 and a second gate insulating layer 92. The second gate 92 extends from the upper surface of the second drift region 42 along the thickness direction Y into the second drift region 42, and the second gate oxide layer 92 is arranged around the second gate 91. The second gate oxide layer 92 is used to isolate the first gate 91 from the first high-voltage well region 21. The second gate insulating layer 92 may include at least one of silicon nitride, silicon oxide, etc. The second gate 91 may include polysilicon, etc.

[0121] In some embodiments, the substrate 1 further includes a second high-voltage well region 22, which is disposed near the upper surface of the substrate 1, and the second high-voltage well region 22 and the first high-voltage well region 21 are spaced apart along the target direction X. The second high-voltage well region 22 has a first doping type, that is, the second high-voltage well region 22 and the first high-voltage well region 21 have different doping types. For example, the first high-voltage well region 21 is an N-type high-voltage well region, and the second high-voltage well region 22 is a P-type high-voltage well region.

[0122] In this embodiment, the second high-voltage well region 22 is provided to enhance the conductivity and field control capabilities of the substrate structure.

[0123] A substrate electrode contact region 23 is provided in the second high-voltage well region 22, and the substrate electrode contact region 23 is provided close to the upper surface of the second high-voltage well region 22. The substrate electrode contact region 23 has a first doping type, that is, the substrate electrode contact region 23 has the same doping type as the second high-voltage well region. For example, the second high-voltage well region 22 is a P-type high-voltage well region, and the substrate electrode contact region 23 is a P-type heavily doped region.

[0124] In some embodiments, the asymmetric hybrid multi-gate semiconductor device further includes a drain contact 11, a first source contact 12, a second source contact 13, a first gate contact 14, and a second gate contact 15. The drain contact 11 is located on the drain region 3 and connected to the drain region 3, and the drain contact 11 is electrically connected to the drain region 3 to lead out the drain. The first source contact 12 is located on the first source region 61 and connected to the first source region 61, and the first source contact 12 is electrically connected to the first source region 61 to lead out the first source. The second source contact 13 is located on the second source region 62 and connected to the second source region 62, and the second source contact 13 is electrically connected to the second source region 62 to lead out the second source. The first source contact 12 is connected to the second source contact 13, so that the two conduction paths are connected in parallel. The first gate contact 14 is located on the first gate structure 8 and connected to the first gate structure 8. The first gate contact 14 is electrically connected to the first gate 81 in the first gate structure 8 to lead out the first gate 81. The second gate contact 15 is located on the second gate structure 9 and connected to the second gate structure 9. The second gate contact 15 is electrically connected to the second gate 91 in the second gate structure 9 to lead out the second gate 91.

[0125] The asymmetric hybrid multi-gate semiconductor device further includes a body electrode 16 . The body electrode 16 is located on the body electrode contact region 63 and connected to the body electrode contact region 63 , that is, the body electrode 16 is electrically connected to the body electrode contact region 63 .

[0126] The asymmetric hybrid multi-gate semiconductor device further includes a substrate electrode 17 . The substrate electrode 17 is located on the substrate electrode contact region 23 and connected to the substrate electrode contact region 23 , that is, the substrate electrode 17 is electrically connected to the substrate electrode contact region 23 .

[0127] The drain contact 11, the first source contact 12, the second source contact 13, the first gate contact 14, the second gate contact 15, the body electrode 16 and the substrate electrode 17 are located on the same side of the substrate 1 and are located on the top of the substrate 1. The drain contact 11, the first source contact 12, the second source contact 13, the first gate contact 14, the second gate contact 15, the body electrode 16 and the substrate electrode 17 may all include metal materials such as tungsten.

[0128] In this embodiment, all electrodes of the asymmetric hybrid multi-gate semiconductor device are electrically connected through the device surface, which is different from the VDMOS device where electrodes are drawn from the bottom. This embodiment combines the characteristics of VDMOS while considering process compatibility, that is, this embodiment is more compatible with the BCD process than the VDMOS device.

[0129] The asymmetric hybrid multi-gate semiconductor device provided in the embodiment of the present application has a dual channel region, namely a first channel region C1 and a second channel region C2, and has the excellent characteristics of LDMOS (with a planar channel) and VDMOS (with a vertical channel), and can support a larger overcurrent capability of the device; compared with the standard LDMOS, the internal region of the present embodiment has a large and uniform overcurrent, a stronger heat dissipation capability, and improved device reliability; the on-resistance of the second channel region C2 can be adjusted by adjusting the doping concentration of the second drift region 42, and the length of the second channel region C2 can be adjusted by the doping depth of the second drift region 42, the well region 5, and the second source region 62, thereby weakening the layout design correlation; by adjusting the distance between the body electrode region 64 and the first source region 61 and the second source region 62, the bias control of a single channel can be achieved, and the performance design is more flexible.

[0130] Correspondingly, an embodiment of the present application further provides a chip, comprising the asymmetric hybrid multi-gate semiconductor device in the above embodiment.

[0131] According to the chip provided in the embodiment of the present application, by setting a first drift region and a second drift region, and the doping concentration of the second drift region is greater than the doping concentration of the first drift region, the current can be diverted to two conduction paths, the first conduction path is from the drain region through the first drift region and the first channel region to the first source region, the second conduction path is from the drain region through the first drift region, the second drift region and the second channel region to the second source region, and the second channel region is arranged along the thickness direction of the substrate, thereby reducing the on-resistance of the device, increasing the overcurrent capacity of the device, and making the heat inside the device more uniform, while maintaining a smaller device area, thereby ensuring the chip integration.

[0132] Correspondingly, an embodiment of the present application further provides a method for manufacturing an asymmetric hybrid multi-gate semiconductor device, which can manufacture the asymmetric hybrid multi-gate semiconductor device in the above embodiment.

[0133] like Figure 4 As shown, the method for manufacturing an asymmetric hybrid multi-gate semiconductor device provided in the embodiment of the present application includes steps 110 to 160.

[0134] Step 110: forming a first high-voltage well region in the substrate.

[0135] Combination Figure 5 As shown, a substrate 1 is first provided, and the substrate 1 may be a silicon substrate or a germanium substrate, or a semiconductor substrate including other elements. The substrate 1 may be a first doping type substrate, and the first doping type may be P type or N type.

[0136] By ion implantation (IMP), a specific area in the substrate 1 is doped to form a first high-voltage well region 21 in the substrate 1 to constitute an active area. The first high-voltage well region 21 is arranged close to the upper surface of the substrate 1. The first high-voltage well region 21 has a second doping type, which may be a P-type or an N-type, and the second doping type is different from the first doping type, that is, the first high-voltage well region 21 is different from the doping type of the substrate 1. For example, the substrate 1 is a P-type semiconductor substrate, and the first high-voltage well region 21 is a high-voltage N-type well region.

[0137] In some embodiments, the method for manufacturing an asymmetric hybrid multi-gate semiconductor device further includes:

[0138] A second high-voltage well region is formed in the substrate, and the second high-voltage well region is spaced apart from the first high-voltage well region along a target direction.

[0139] Combination Figure 5 As shown, before forming the first high-voltage well region 21 in the substrate 1, a second high-voltage well region 22 can be formed in the substrate 1 by ion implantation. The second high-voltage well region 22 has a first doping type, that is, the second high-voltage well region 22 has the same doping type as the substrate 1. For example, the substrate 1 is a P-type semiconductor substrate, and the second high-voltage well region 22 is a P-type high-voltage well region. The second high-voltage well region 22 is arranged close to the upper surface of the substrate 1, and the second high-voltage well region 22 and the first high-voltage well region 21 are arranged at intervals along the target direction X, and the target direction X is parallel to the upper surface of the substrate 1.

[0140] In this embodiment, the second high-voltage well region 22 is provided to enhance the conductivity and field control capabilities of the substrate structure.

[0141] In some embodiments, the method for manufacturing an asymmetric hybrid multi-gate semiconductor device further includes:

[0142] An isolation structure is formed in the first high-voltage well region.

[0143] In some embodiments, the isolation structure may include a field oxide structure or a shallow trench isolation structure, etc. The field oxide structure or the shallow trench isolation structure may be selected as the isolation structure according to the complexity of the process. The isolation structure may also include other types of isolation structures, which are not specifically limited here.

[0144] For example, the isolation structure includes a field oxide structure. Figure 6 As shown, a LOCOS (Local Oxidation of Silicon) process is used to form an isolation structure 7 on the first high-voltage well region 21. The edge of the isolation structure 7 may be in a bird's beak shape. The isolation structure 7 may include silicon oxide or the like.

[0145] The isolation structure 7 in this embodiment includes a field oxide structure, which can increase the conduction path of the device and improve the pressure resistance, and at the same time, serves as a key part of the field plate to regulate the electric field distribution of the device.

[0146] Step 120 , forming a first drift region and a second drift region connected along a target direction in the first high-voltage well region, wherein the doping concentration of the second drift region is greater than the doping concentration of the first drift region.

[0147] Combination Figure 7 As shown, a first drift region 41 is formed in the first high-voltage well region 21 by ion implantation, and the isolation structure 7 is located on the first drift region 41. The first drift region 41 is arranged close to the upper surface of the first high-voltage well region 21, and has the second doping type.

[0148] Combination Figure 8 As shown, by ion implantation, a second drift region 42 is formed in the first high-voltage well region 21, and the first drift region 41 and the second drift region 42 are adjacent to each other along the target direction X. The second drift region 42 is arranged close to the upper surface of the first high-voltage well region 21, and the second drift region 42 has a second doping type. The first drift region 41, the second drift region 42 and the first high-voltage well region 21 have the same doping type. For example, the first high-voltage well region 21 is a high-voltage N-type well region, and the first drift region 41 and the second drift region 42 are both N-type drift regions.

[0149] The doping concentration of the second drift region 42 is greater than the doping concentration of the first drift region 41. The provision of the first drift region 41 can reduce the overall on-resistance of the device. The second drift region 42 has a high doping concentration, which can make the second drift region 42 have a sufficiently low resistance characteristic to ensure that the current can flow to the second drift region 42 during the device start-up phase.

[0150] Step 130 : forming a well region in the second drift region.

[0151] Combination Fig. 9 As shown, a well region 5 is formed in the second drift region 42 by ion implantation. The well region 5 is arranged close to the upper surface of the second drift region 42, and the width of the well region 5 along the target direction X is the same as the width of the second drift region 42 along the target direction X. The well region 5 has a first doping type, that is, the well region 5 has a different doping type from the second drift region 42. For example, the second drift region 42 is an N-type drift region, and the well region 5 is a P-type well region.

[0152] Step 140 , forming a first gate structure on one side of the substrate, and forming a second gate structure in the first high-voltage well region on a side of the second drift region away from the first drift region.

[0153] Combination Fig.10 and Fig.11As shown, a first gate structure 8 and a second gate structure 9 are formed simultaneously. The first gate structure 8 covers a portion of the isolation structure 7, and covers a portion of the first drift region 41 and a portion of the well region 5. The second gate structure 9 is located in the first high-voltage well region 21, and the second gate structure 9 is located on the side of the second drift region 42 away from the first drift region 41, and is adjacent to the second drift region 42, that is, the second gate structure 9 is adjacent to the well region 5. The second gate structure 9 extends along the thickness direction Y of the substrate 1, and the target direction X is perpendicular to the thickness direction Y of the substrate 1.

[0154] In some embodiments, forming a first gate structure on one side of the substrate and forming a second gate structure in the first high-voltage well region on a side of the second drift region away from the first drift region in step 140 includes:

[0155] A gate trench is formed in the first high-voltage well region on a side of the second drift region away from the first drift region, the gate trench extends from the upper surface of the second drift region along the thickness direction of the substrate into the second drift region, and the height of the gate trench along the thickness direction is greater than or equal to the depth of the well region along the thickness direction;

[0156] A first gate structure is formed on one side of the substrate, and a second gate structure is formed in the gate trench.

[0157] like Fig.10 As shown, an etching process is first used to etch a gate line groove 90 in the first high-voltage well region 21, and the gate line groove 90 extends along the thickness direction Y of the substrate 1. The gate line groove 90 is located on the side of the second drift region 42 away from the first drift region 41, and is adjacent to the second drift region 42, that is, the gate line groove 90 is adjacent to the well region 5. The height of the gate line groove 90 along the thickness direction Y is greater than or equal to the depth of the well region 5 along the thickness direction Y.

[0158] Then, if Fig.11 As shown, a thin film deposition process is used to simultaneously form a first gate structure 8 on a side of the field oxide structure 7 facing away from the substrate 1 and a second gate structure 9 in the gate trench 90 .

[0159] In some embodiments, the first gate structure 8 includes a first gate 81 and a first gate insulating layer 82, and the second gate structure 9 includes a second gate 91 and a second gate insulating layer 92. The steps of forming the first gate structure on one side of the substrate and forming the second gate structure in the gate trench include:

[0160] forming a first gate insulating layer on one side of the substrate, and forming a second gate insulating layer on the inner surface of the gate trench;

[0161] A first gate is formed on a side of the first gate insulating layer facing away from the substrate, and a second gate is filled in the gate trench.

[0162] Combination Fig.11 As shown, a thin film deposition process is first used to simultaneously form a first gate insulating layer 82 on the side of the isolation structure 7 facing away from the substrate 1 and a second gate insulating layer 92 is formed in the gate trench 90. The first gate insulating layer 82 covers a portion of the isolation structure 7, a portion of the first drift region 41 and a portion of the well region 5, and the second gate insulating layer 92 covers the inner surface of the gate trench 90.

[0163] Then, a thin film deposition process is used to simultaneously form a first gate 81 on the side of the first gate insulating layer 82 facing away from the substrate 1 and fill a second gate 91 in the gate trench 90 .

[0164] The first gate insulating layer 82 and the second gate insulating layer 92 may each include at least one of silicon nitride, silicon oxide, etc. The first gate 81 and the second gate 91 may each include polysilicon, etc.

[0165] Step 150, forming a drain region in the first high-voltage well region on the side of the first drift region away from the second drift region, and forming a first source region and a second source region spaced apart along a target direction in the well region, the well region of the first source region close to the side of the first drift region constitutes a first channel region, the well region at the bottom of the second source region constitutes a second channel region, the first gate structure covers the first channel region, and the second gate structure covers the second channel region.

[0166] Combination Fig.12 As shown, by ion implantation, a drain region 3 is formed in the first high-voltage well region 21, and a first source region 61 is formed in the well region 5. The drain region 3 is arranged close to the upper surface of the first high-voltage well region 21, and the drain region 3 is located on the side of the first drift region 41 away from the second drift region 42, and the drain region 3 is adjacent to the first drift region 41. The first source region 61 is arranged close to the upper surface of the well region 5. The drain region 3 and the first source region 61 both have the second doping type, that is, the drain region 3, the first source region 61 and the first high-voltage well region 21 have the same doping type. For example, the first high-voltage well region 21 is a high-voltage N-type well region, and the drain region 3 and the first source region 61 are both N-type heavily doped regions.

[0167] The well region of the first source region 61 near the first drift region 41 constitutes the first channel region C1, and the first gate structure 8 covers the first channel region C1. In some embodiments, the first gate structure 8 covers a portion of the isolation structure 7, the first channel region C1, and the first drift region 41 between the isolation structure 7 and the first channel region C1. In the case where the first gate structure 8 includes a first gate 81 and a first gate insulating layer 82, the first gate insulating layer 82 covers a portion of the isolation structure 7, the first channel region C1, and the first drift region 41 between the isolation structure 7 and the first channel region C1, and the first gate 81 covers the first gate insulating layer 82.

[0168] In some embodiments, the method for manufacturing an asymmetric hybrid multi-gate semiconductor device further includes:

[0169] A lightly doped source region is formed in the well region on one side of the first source region close to the first drift region.

[0170] Combination Fig.12 As shown, when forming the drain region 3 and the first source region 61, a lightly doped source region 64 can be formed in the well region 5 by ion implantation. The lightly doped source region 64 is arranged close to the upper surface of the well region 5, and the lightly doped source region 64 is located on the side of the first source region 61 close to the first drift region 41, and the lightly doped source region 64 is adjacent to the first source region 61. In the case where the asymmetric hybrid multi-gate semiconductor device includes the lightly doped source region 64, the well region on the side of the lightly doped source region 64 away from the first source region 61 constitutes the first channel region C1, that is, the lightly doped source region 64 is located between the first source region 61 and the first channel region C1.

[0171] Then, combine Fig.13 As shown, by ion implantation, a second source region 62 is formed in the well region 5. The second source region 62 is arranged close to the upper surface of the well region 5, the second source region 62 is located in the first source region 61 away from the first drift region 41, and the second source region 62 is spaced apart from the first source region 61. The second source region 62 has a second doping type, and the second source region 62 and the first source region 61 have the same doping type.

[0172] The well region at the bottom of the second source region 62 forms a second channel region C2. The second gate structure 9 extends along the thickness direction Y and covers the second channel region C2.

[0173] The first channel region C1 is a planar channel, and the second channel region C2 is a vertical channel, so that this embodiment has the excellent characteristics of both LDMOS (with a planar channel) and VDMOS (with a vertical channel), and can support a larger overcurrent capability of the device.

[0174] In this embodiment, the length of the second channel region C2 along the thickness direction Y of the substrate 1 is determined by the doping depth of the second drift region 42 (i.e., the depth along the thickness direction Y), the doping depth of the well region 5, and the doping depth of the second source region 62. Compared with the double-gate LCMOS device, this embodiment weakens the layout design correlation. By optimizing the parameters of the second drift region 42, the well region 5, and the second source region 62, excellent conduction characteristics can be achieved.

[0175] In some embodiments, the drain region 3, the first drift region 41, the first channel region C1 and the first source region 61 constitute a first conduction path L1, the drain region 3, the first drift region 41, the second drift region 42, the second channel region C2 and the second source region 62 constitute a second conduction path L2, and the first conduction path L1 and the second conduction path L2 are arranged in parallel to effectively reduce the on-resistance of the device.

[0176] In some embodiments, the on-resistance of the first conduction path L1 is symmetrical to the on-resistance of the second conduction path L2 , further reducing the on-resistance of the device.

[0177] In some embodiments, the length of the second channel region C2 along the thickness direction Y of the substrate 1 is less than the length of the first channel region C1 along the target direction X. The second channel region C2 is controlled by the second gate structure 9 , which has a lower operating voltage and a stronger field control capability.

[0178] In some embodiments, the first source region 61 and the second source region 62 are arranged asymmetrically. The asymmetrical source design enables the device to have optimization potential in more dimensions.

[0179] In some embodiments, the ion concentration of the second source region 62 is greater than the ion concentration of the first source region 61 .

[0180] In some embodiments, the depth of the second source region 62 along the thickness direction Y is greater than the depth of the first source region along the thickness direction Y.

[0181] In some embodiments, the method for manufacturing an asymmetric hybrid multi-gate semiconductor device further includes:

[0182] A body electrode contact region is formed in the well region between the first source region and the second source region, and a distance between the body electrode contact region and the first source region is greater than a distance between the body electrode contact region and the second source region.

[0183] Combination Fig.14 As shown, after the second source region 62 is formed in the well region 5, a body electrode contact region 63 can be formed in the well region 5 by ion implantation, and the body electrode contact region 63 is arranged close to the upper surface of the well region 5. The body electrode contact region 63 is located between the first source region 61 and the second source region 62, and the body electrode contact region 63 is spaced apart from the first source region 61 and the second source region 62, respectively. The body electrode contact region 63 has a first doping type, that is, the body electrode contact region 63 has a different doping type from the first source region 61 and the second source region 62. For example, the first source region 61 and the second source region 62 are N-type heavily doped regions, and the body electrode contact region 63 is a P-type heavily doped region.

[0184] The distance between the body electrode contact region 63 and the first source region 61 is greater than the distance between the body electrode contact region 63 and the second source region 62, so as to adjust the body electrode bias to perform different degrees of field control on the two channels, thereby achieving effective coordination of the electric field strength of the two channels by the same body electrode and increasing the flexibility of the device's electrical performance.

[0185] In some embodiments, the second drift region 41 and the well region 5 overlap in cross section along the target direction X, and the second drift region 41 and the well region 5 are formed using the same mask, which can simplify the manufacturing process, reduce production costs, and reduce wafer loss.

[0186] In some embodiments, the method for manufacturing an asymmetric hybrid multi-gate semiconductor device further includes:

[0187] A substrate electrode contact region is formed in the second high-voltage well region.

[0188] Combination Fig.14 As shown, when the body electrode contact region 63 is formed in the well region 5, a substrate electrode contact region 23 can be formed in the second high-voltage well region 22 by ion implantation, and the substrate electrode contact region 23 is arranged close to the upper surface of the second high-voltage well region 22. The substrate electrode contact region 23 has a first doping type, that is, the substrate electrode contact region 23 has the same doping type as the second high-voltage well region. For example, the second high-voltage well region 22 is a P-type high-voltage well region, and the substrate electrode contact region 23 is a P-type heavily doped region.

[0189] In some embodiments, the method for manufacturing an asymmetric hybrid multi-gate semiconductor device further includes:

[0190] A drain contact connected to the drain region is formed on the drain region, a first source contact connected to the first source region is formed on the first source region, a second source contact connected to the second source region is formed on the second source region, the first source contact is connected to the second source contact, a first gate contact connected to the first gate structure is formed on the first gate structure, and a second gate contact connected to the second gate structure is formed on the second gate structure.

[0191] Combination Figure 3As shown, through the thin film deposition process, a first drain contact 11 can be formed on the drain region 3, a first source contact 13 can be formed on the first source region 61, a second source contact 12 can be formed on the second source region 62, a first gate contact 14 can be formed on the first gate structure 8, and a second gate contact 15 can be formed on the second gate structure 9. Among them, the drain contact 11 is electrically connected to the drain region 3 to lead out the drain. The first source contact 13 is electrically connected to the first source region 61 to lead out the first source. The second source contact 12 is electrically connected to the second source region 62 to lead out the second source. Moreover, the first source contact 13 is connected to the second source contact 12, so that the two conduction paths are connected in parallel. The first gate contact 14 is electrically connected to the first gate 81 in the first gate structure 8 to lead out the first gate 81. The second gate contact 15 is electrically connected to the second gate 91 in the second gate structure 9 to lead out the second gate 91.

[0192] In some embodiments, the method for manufacturing an asymmetric hybrid multi-gate semiconductor device further includes:

[0193] forming a body electrode connected to the body electrode contact region on the body electrode contact region;

[0194] A substrate electrode connected to the substrate electrode contact region is formed on the substrate electrode contact region.

[0195] Combination Figure 3 As shown, when forming the drain contact 11, the first source contact 13, the second source contact 12, the first gate contact 14 and the second gate contact 15, a body electrode 16 may be formed on the body electrode contact region 63, and a substrate electrode 17 may be formed on the substrate electrode contact region 23. The body electrode 16 is electrically connected to the body electrode contact region 63, and the substrate electrode 17 is electrically connected to the substrate electrode contact region 23.

[0196] The drain contact 11, the first source contact 12, the second source contact 13, the first gate contact 14, the second gate contact 15, the body electrode 16 and the substrate electrode 17 are located on the same side of the substrate 1 and are located on the top of the substrate 1. The drain contact 11, the first source contact 12, the second source contact 13, the first gate contact 14, the second gate contact 15, the body electrode 16 and the substrate electrode 17 may all include metal materials such as tungsten.

[0197] In this embodiment, all electrodes of the asymmetric hybrid multi-gate semiconductor device are electrically connected through the device surface, which has stronger compatibility with the BCD process.

[0198] According to the manufacturing method of the asymmetric hybrid multi-gate semiconductor device provided in the embodiment of the present application, it has a dual channel region, namely the first channel region C1 and the second channel region C2, and has the excellent characteristics of LDMOS (with a planar channel) and VDMOS (with a vertical channel), which can support a larger overcurrent capability of the device; compared with the standard LDMOS, the internal area of ​​the present embodiment has a large and uniform overcurrent, a stronger heat dissipation capability, and improved device reliability; the on-resistance of the second channel region C2 can be adjusted by adjusting the doping concentration of the second drift region 42, and the length of the second channel region C2 can be adjusted by the doping depth of the second drift region 42, the well region 5, and the second source region 62, thereby weakening the layout design correlation; by adjusting the distance between the body electrode region 64 and the first source region 61 and the second source region 62, the bias control of a single channel can be achieved, which has more flexibility in performance design.

[0199] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0200] In the description of the present application, “plurality” means two or more.

[0201] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0202] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. An asymmetric hybrid multi-gate semiconductor device, characterized in that: include: A substrate, comprising a first high-voltage well region, wherein the first high-voltage well region is provided with a drain region, a first drift region, and a second drift region sequentially connected along a target direction, wherein the doping concentration of the second drift region is greater than the doping concentration of the first drift region; wherein the second drift region is provided with a well region, wherein the well region is provided with a first source region and a second source region spaced apart along the target direction, wherein the well region of the first source region close to one side of the first drift region constitutes a first channel region, and the well region at the bottom of the second source region constitutes a second channel region; A first gate structure, located on one side of the substrate and covering the first channel region; The second gate structure is located in the first high-voltage well region and on a side of the second drift region away from the first drift region, and covers the second channel region.

2. The asymmetric hybrid multi-gate semiconductor device according to claim 1, characterized in that: The drain region, the first drift region, the first channel region and the first source region constitute a first conduction path, the drain region, the first drift region, the second drift region, the second channel region and the second source region constitute a second conduction path, and the first conduction path and the second conduction path are arranged in parallel.

3. The asymmetric hybrid multi-gate semiconductor device according to claim 2, characterized in that: The on-resistance of the first conductive path is symmetrical to the on-resistance of the second conductive path.

4. The asymmetric hybrid multi-gate semiconductor device according to claim 3, characterized in that: A length of the second channel region along a thickness direction of the substrate is smaller than a length of the first channel region along a target direction, and the target direction is perpendicular to the thickness direction.

5. The asymmetric hybrid multi-gate semiconductor device according to claim 1, characterized in that: The first source region and the second source region are arranged asymmetrically.

6. The asymmetric hybrid multi-gate semiconductor device according to claim 5, characterized in that: The ion concentration of the second source region is greater than the ion concentration of the first source region.

7. The asymmetric hybrid multi-gate semiconductor device according to claim 5, characterized in that: A depth of the second source region along a thickness direction of the substrate is greater than a depth of the first source region along the thickness direction.

8. The asymmetric hybrid multi-gate semiconductor device according to claim 1, characterized in that: A body electrode contact region is also provided in the well region. The body electrode contact region is located between the first source region and the second source region, and the distance between the body electrode contact region and the first source region is greater than the distance between the body electrode contact region and the second source region.

9. The asymmetric hybrid multi-gate semiconductor device according to claim 1, characterized in that: A cross section of the second drift region coincides with a cross section of the well region along the target direction.

10. The asymmetric hybrid multi-gate semiconductor device according to claim 1, characterized in that: The semiconductor device further includes an isolation structure located between the first drift region and the first gate structure.

11. The asymmetric hybrid multi-gate semiconductor device according to claim 10, characterized in that: The isolation structure includes a field oxide structure or a shallow trench isolation structure.

12. The asymmetric hybrid multi-gate semiconductor device according to claim 10, characterized in that: The first gate structure covers the first channel region, a portion of the isolation structure, and a first drift region between the isolation structure and the first channel region.

13. The asymmetric hybrid multi-gate semiconductor device according to claim 12, characterized in that: The first gate structure includes a first gate and a first gate insulating layer; The first gate insulating layer covers the first channel region, a portion of the isolation structure, and a first drift region between the isolation structure and the first channel region, and the first gate covers the first gate insulating layer.

14. The asymmetric hybrid multi-gate semiconductor device according to claim 1, characterized in that: The second gate structure extends from an upper surface of the second drift region into the second drift region along a thickness direction of the substrate, and a height of the second gate structure along the thickness direction is greater than or equal to a depth of the well region along the thickness direction.

15. The asymmetric hybrid multi-gate semiconductor device according to claim 14, characterized in that: The second gate structure includes a second gate and a second gate insulating layer; The second gate extends from the upper surface of the second drift region along the thickness direction into the second drift region, and the second gate oxide layer is arranged around the second gate.

16. The asymmetric hybrid multi-gate semiconductor device according to claim 1, characterized in that: A lightly doped source region is also provided in the well region, and the lightly doped source region is located between the first source region and the first channel region.

17. The asymmetric hybrid multi-gate semiconductor device according to claim 1, characterized in that: The substrate further includes a second high-voltage well region; The second high-voltage well region is spaced apart from the first high-voltage well region along the target direction, and a substrate electrode contact region is provided in the second high-voltage well region.

18. The asymmetric hybrid multi-gate semiconductor device according to any one of claims 1 to 17, characterized in that: The semiconductor device further comprises a drain contact, a first source contact, a second source contact, a first gate contact and a second gate contact; The drain contact is located on the drain region and connected to the drain region, the first source contact is located on the first source region and connected to the first source region, the second source contact is located on the second source region and connected to the second source region, the first source contact is connected to the second source contact, the first gate contact is located on the first gate structure and connected to the first gate structure, and the second gate contact is located on the second gate structure and connected to the second gate structure.

19. A chip, characterized in that: It comprises the asymmetric hybrid multi-gate semiconductor device as claimed in any one of claims 1 to 18.

20. A method for manufacturing an asymmetric hybrid multi-gate semiconductor device, characterized in that: include: forming a first high-voltage well region in a substrate; forming a first drift region and a second drift region connected along a target direction in the first high-voltage well region, wherein the doping concentration of the second drift region is greater than the doping concentration of the first drift region; forming a well region in the second drift region; forming a first gate structure on one side of the substrate, and forming a second gate structure in the first high-voltage well region on a side of the second drift region away from the first drift region; A drain region is formed in the first high-voltage well region on the side of the first drift region away from the second drift region, and a first source region and a second source region spaced apart along the target direction are formed in the well region, the well region of the first source region close to the side of the first drift region constitutes a first channel region, the well region at the bottom of the second source region constitutes a second channel region, the first gate structure covers the first channel region, and the second gate structure covers the second channel region.

21. The method for manufacturing an asymmetric hybrid multi-gate semiconductor device according to claim 20, characterized in that: The drain region, the first drift region, the first channel region and the first source region constitute a first conduction path, the drain region, the first drift region, the second drift region, the second channel region and the second source region constitute a second conduction path, the first conduction path and the second conduction path are arranged in parallel, and the on-resistance of the first conduction path is the same as the on-resistance of the second conduction path.

22. The method for manufacturing an asymmetric hybrid multi-gate semiconductor device according to claim 20, characterized in that: The first source region and the second source region are arranged asymmetrically.

23. The method for manufacturing an asymmetric hybrid multi-gate semiconductor device according to claim 20, characterized in that: The method further comprises: A body electrode contact region is formed in the well region between the first source region and the second source region, and a distance between the body electrode contact region and the first source region is greater than a distance between the body electrode contact region and the second source region.

24. The method for manufacturing an asymmetric hybrid multi-gate semiconductor device according to claim 20, characterized in that: The second drift region and the well region have cross sections overlapped along the target direction, and the second drift region and the well region are formed using the same mask.

25. The method for manufacturing an asymmetric hybrid multi-gate semiconductor device according to claim 20, characterized in that: Before forming the first drift region and the second drift region connected along the target direction in the first high-voltage well region, the method further includes: forming an isolation structure in the first high-voltage well region; Wherein, the isolation structure is located between the first drift region and the first gate structure.

26. The method for manufacturing an asymmetric hybrid multi-gate semiconductor device according to claim 25, characterized in that: The step of forming a first gate structure on one side of the substrate and forming a second gate structure in the first high-voltage well region on a side of the second drift region away from the first drift region comprises: forming a gate trench in the first high-voltage well region on a side of the second drift region away from the first drift region, wherein the gate trench extends from an upper surface of the second drift region along a thickness direction of the substrate into the second drift region, and a height of the gate trench along the thickness direction is greater than or equal to a depth of the well region along the thickness direction; A first gate structure is formed on one side of the substrate, and a second gate structure is formed in the gate trench, wherein the first gate structure covers the first channel region, a portion of the isolation structure, and a first drift region between the isolation structure and the first channel region.

27. The method for manufacturing an asymmetric hybrid multi-gate semiconductor device according to claim 26, characterized in that: The first gate structure includes a first gate and a first gate insulating layer, and the second gate structure includes a second gate and a second gate insulating layer; The first gate structure is formed on one side of the substrate, and the second gate structure is formed in the gate trench, comprising: forming the first gate insulating layer on one side of the substrate, and forming the second gate insulating layer on the inner surface of the gate trench, wherein the first gate insulating layer covers the first channel region, a portion of the isolation structure, and a first drift region between the isolation structure and the first channel region; The first gate is formed on a side of the first gate insulating layer facing away from the substrate, and the second gate is filled in the gate trench.

28. The method for manufacturing an asymmetric hybrid multi-gate semiconductor device according to claim 20, characterized in that: The method further comprises: A lightly doped source region is formed in the well region on a side of the first source region close to the first drift region, and the well region between the lightly doped source region and the first drift region constitutes the first channel region.

29. The method for manufacturing an asymmetric hybrid multi-gate semiconductor device according to claim 20, characterized in that: The method further comprises: forming a second high-voltage well region in the substrate, wherein the second high-voltage well region and the first high-voltage well region are spaced apart from each other along the target direction; A substrate electrode contact region is formed in the second high-voltage well region.

30. The method for manufacturing an asymmetric hybrid multi-gate semiconductor device according to any one of claims 20 to 29, characterized in that: The method further comprises: A drain contact connected to the drain region is formed on the drain region, a first source contact connected to the first source region is formed on the first source region, a second source contact connected to the second source region is formed on the second source region, the first source contact is connected to the second source contact, a first gate contact connected to the first gate structure is formed on the first gate structure, and a second gate contact connected to the second gate structure is formed on the second gate structure.

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