SiC wafer and method for producing same

Abstract

The invention relates to a SiC wafer and a method for manufacturing the same. [Problem] When a SiC wafer provided with an epitaxial layer on a SiC substrate is divided into a plurality of chips by forming a gate electrode on a main surface via a gate insulating film. [Solution] Provided is a SiC wafer (1) that includes a SiC substrate (2) and an epitaxial layer (3) that is formed on the SiC substrate (2) and contains SiC, the C-Si composition ratio of the top surface of the epitaxial layer (3) being 50 atm% or less.

Description

[0001] This application is a divisional application of Chinese patent application No. 202110239887.X with the same invention name, and the original application date is February 25, 2021. Technical Field

[0002] The present invention relates to a SiC wafer, and more particularly to a SiC wafer having an epitaxial layer formed on an upper portion thereof, and a method for manufacturing the same. Background Art

[0003] In addition to high withstand voltage, semiconductor power elements also require low on-state resistance and low switching loss, but the current mainstream silicon (Si) power elements are close to the theoretical performance limit. Compared with Si, the insulation breakdown electric field strength of silicon carbide (SiC) is about one order of magnitude greater, so by making the drift layer that maintains the withstand voltage thinner to about 1 / 10 and increasing the impurity concentration by about 100 times, the element resistance can theoretically be reduced by more than three orders of magnitude. In addition, the band gap is about three times larger than that of Si, so it can also operate at high temperatures. SiC semiconductor elements are expected to surpass the performance of Si semiconductor elements, and the development of SiC power devices is being promoted.

[0004] Patent Document 1 (Japanese Patent Application Laid-Open No. 2012-142597) describes preventing step bunching on a substrate surface.

[0005] Patent Document 2 (Japanese Patent Application Laid-Open No. 2010-258294) describes evaporating silicon atoms from the surface of a silicon carbide epitaxial layer so that the silicon carbide surface contains 95 at % or more of carbon atoms.

[0006] Patent documents 3 to 7 describe adjusting the conditions during epitaxial growth to control the flow ratio (raw material supply ratio) or the composition ratio of the epitaxial growth layer. However, the techniques described in Patent documents 3 to 7 do not make the surface of the epitaxial growth layer carbon-rich, and the flow ratio is not related to the composition ratio of the surface of the SiC wafer.

[0007] Prior art literature

[0008] Patent Literature

[0009] Patent Document 1: Japanese Patent Application Publication No. 2012-142597

[0010] Patent Document 2: Japanese Patent Application Publication No. 2010-258294

[0011] Patent Document 3: Japanese Patent Application Publication No. 2003-282451

[0012] Patent Document 4: Japanese Patent Application Publication No. 2015-143168

[0013] Patent Document 5: Japanese Patent Application Publication No. 2009-239103

[0014] Patent Document 6: Japanese Patent Application Publication No. 2007-137689

[0015] Patent Document 7: International Publication No. 2015 / 159949

[0016] Non-patent literature

[0017] Non-patent literature 1: Senzaki, Junji, et al. "Challenges of High-Performance and High-Reliablity in SiC MOS Structures." Materials Science Forum.Vol.717.TransTech Publications, 2012. Summary of the invention

[0018] Problems to be solved by the invention

[0019] In the mass production process of SiC devices, multiple chip formation areas are made on the wafer at the same time, and the wafer is divided into multiple chips in the cutting process. If the characteristics of each chip are all the same, there is no problem, but there are a certain number of defective chips, and the deviation of device characteristics between chips becomes larger. Especially in power devices that require a large area, it is important to reduce the deviation of device characteristics to improve the yield. For example, Non-Patent Document 1 describes improving the reliability of the gate insulating film by preventing the occurrence of step aggregation on the substrate surface.

[0020] An object of the present invention is to provide a SiC wafer with an epitaxial growth layer, which can reduce the variation in the lifetime of a gate insulating film by controlling the composition of the wafer surface.

[0021] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0022] Means for solving problems

[0023] Among the embodiments disclosed in the present application, the outline of representative embodiments will be briefly described as follows.

[0024] A SiC wafer according to one embodiment includes a SiC substrate and an epitaxial layer formed on the SiC substrate and containing SiC, wherein a composition ratio of C—Si on a top surface (upper surface) of the epitaxial layer is 50 atm % or less.

[0025] Effects of the Invention

[0026] According to the representative embodiment, the reliability of the SiC wafer can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a plan view showing the manufacturing process of the SiC wafer according to the first embodiment.

[0028] Figure 2 It is a cross-sectional view showing the manufacturing process of the SiC wafer according to the first embodiment.

[0029] Figure 3 It shows that Figure 2 A cross-sectional view of the manufacturing process.

[0030] Figure 4 It shows that Figure 3 A cross-sectional view of the manufacturing process.

[0031] Figure 5 This is a schematic diagram for explaining a surface composition analysis method using XPS.

[0032] Figure 6 This is a schematic diagram for explaining a surface composition analysis method using XPS.

[0033] Figure 7 It is a graph showing the details of the peak separation of the C1s spectrum obtained by the surface composition analysis using XPS.

[0034] Figure 8 It is a graph showing the details of the peak separation of the C1s spectrum obtained by the surface composition analysis using XPS.

[0035] Fig. 9 It is a graph showing the details of the peak separation of the C1s spectrum obtained by the surface composition analysis using XPS.

[0036] Fig.10 It is a graph showing the details of the peak separation of the C1s spectrum obtained by the surface composition analysis using XPS.

[0037] Fig.11 This is a table showing the relationship between the composition ratios of various bonds containing carbon on the surface of the SiC wafer before the carbon enrichment treatment and the take-off angle of the XPS analysis.

[0038] Fig.12 It is a graph showing the relationship between the composition ratio of various bonds containing carbon on the surface of the SiC wafer before the carbon enrichment treatment and the take-off angle of the XPS analysis.

[0039] Fig.13 This is a graph showing the relationship between the composition ratio of various bonds containing carbon on the surface of the SiC wafer after the carbon enrichment treatment and the take-off angle of the XPS analysis.

[0040] Fig.14 This is a graph showing the relationship between the composition ratio of various bonds containing carbon on the surface of the SiC wafer after the carbon enrichment treatment and the take-off angle of the XPS analysis.

[0041] Fig.15 It is a graph showing the total of the composition ratio of C—Si bonds and the composition ratio of bonds containing carbon other than C—Si before and after the carbon enrichment treatment.

[0042] Fig.16 is a formula showing the cumulative failure rate.

[0043] Fig.17 Graph showing the relationship between the amount of injection charge for dielectric breakdown and the cumulative failure rate of SiC devices of the comparative example and the present embodiment.

[0044] Fig.18 1 is a cross-sectional view showing a manufacturing process of a DMOSFET on a SiC wafer according to a modification of the first embodiment.

[0045] Fig.19 It shows that Fig.18 A cross-sectional view of the manufacturing process.

[0046] Fig. 20 It shows that Fig.19 A cross-sectional view of the manufacturing process.

[0047] Fig.21 It shows that Fig. 20 A cross-sectional view of the manufacturing process.

[0048] Fig. 22 It shows that Fig.21 A cross-sectional view of the manufacturing process.

[0049] Fig.23 It shows that Fig. 22 A cross-sectional view of the manufacturing process.

[0050] Fig.24 It shows that Fig.23 A cross-sectional view of the manufacturing process.

[0051] Fig.25 It shows that Fig.24 A cross-sectional view of the manufacturing process.

[0052] Fig.26 It shows that Fig.25 A cross-sectional view of the manufacturing process.

[0053] Fig. 27 It is a plan view showing the manufacturing process of the DMOSFET on the SiC wafer according to the modification of the first embodiment.

[0054] Fig.28 It is a graph showing the composition ratios of C—Si bonds and bonds containing carbon other than C—Si bonds on the top surface of an oxidation-treated SiC wafer.

[0055] Fig.29 Graph showing the relationship between the amount of injection charge for dielectric breakdown and the cumulative failure rate of a SiC device of a comparative example.

[0056] Description of Reference Numerals

[0057] 1SiC Wafer

[0058] 2SiC substrate

[0059] 3 Epitaxial layer

[0060] 4 Carbon-rich layer DETAILED DESCRIPTION

[0061] Hereinafter, the embodiments of the present invention will be described in detail based on the accompanying drawings. It should be noted that in all the drawings used to illustrate the embodiments, the same reference numerals are given to components having the same functions, and their repeated descriptions are omitted. In addition, in the embodiments, the description of the same or similar parts is not repeated as a principle unless it is particularly necessary.

[0062] In the present application, a wafer consisting only of a SiC substrate and a wafer including a SiC substrate and an epitaxial layer on the SiC substrate are respectively referred to as SiC wafers. The SiC substrate referred to here is a bulk substrate that does not include an epitaxial layer.

[0063] (Implementation Method 1)

[0064] <Details of room for improvement>

[0065] SiC (silicon carbide) has a wider band gap than Si (silicon), and the insulating film formed on the SiC substrate has a high dielectric breakdown strength. Although it is considered to utilize such characteristics and apply a high voltage to the element formed on the SiC substrate, in this case, the electric field applied to the insulating film becomes a problem. Therefore, in the design of a device using a SiC substrate, it is necessary to fully consider the electric field applied to the insulating film. In particular, in a device structure having a gate insulating film such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor), if the electric field strength applied to the gate insulating film becomes stronger, a leakage current is generated in the gate insulating film. The generation of such leakage current becomes the cause of device malfunctions such as a reduction in the life of the gate insulating film and dielectric breakdown of the gate insulating film.

[0066] Such defects do not occur in the same way in each chip cut from a wafer, but the gate insulation film life has deviations in each chip (device). That is, when the device is mass-produced, multiple chip formation areas are made on the wafer at the same time, and a cutting process is performed to separate multiple chips from the wafer. If the characteristics of each chip are all the same, there will be no problem, but there will be a certain number of defective chips. As the cause of the defective chips, in addition to the presence of foreign matter in the manufacturing process, defects on the surface of the SiC substrate can also be cited.

[0067] One of the defects is step clustering caused by the step flow growth method. Step clustering is mostly formed locally within the wafer surface, and its concave and convex shapes are various. When a device is manufactured on a wafer with step clustering, the characteristic deviation of the device becomes larger. Therefore, in order to reduce the deviation, it is important to reduce defects such as concave and convex. In particular, in power devices that require a large area, it is important to reduce the deviation of the power device to improve the yield.

[0068] Fig.29 , a Weibulplot of the results of evaluating CCS-TDDB (Constant Current Stress Time Dependent Dielectric Breakdown) characteristics of a plurality of MOSFETs existing within the same wafer surface is shown as a comparative example. MOSFETs (SiC devices) are fabricated on a wafer mainly composed of silicon carbide. Fig.29The horizontal axis (number of wafer pairs) of the coordinate diagram shown shows the amount of charge injected into the insulating film formed on the SiC substrate before dielectric breakdown occurs in the insulating film, that is, the dielectric breakdown injection charge amount Qbd. In addition, the vertical axis of this coordinate diagram shows the cumulative failure rate. That is, Fig.29 It is a coordinate diagram showing the relationship between the dielectric breakdown injection charge amount and the cumulative failure rate in the SiC device of the comparative example.

[0069] This Weibull diagram is a coordinate diagram that plots the dielectric breakdown injection charge amount Qbd of multiple devices when a constant current stress (CCS) is applied to the gate in a MOS structure such as a MOS capacitor or MOSFET. When a constant current stress (CCS) is applied to the gate, the stress time before the gate insulating film breaks down is measured, and thus the dielectric breakdown injection charge amount Qbd can be calculated from this stress time and the stress current.

[0070] In the case where the deviation of the time (life) until dielectric breakdown in the Weibull diagram is zero, the distribution of the diagram becomes a straight line parallel to the vertical axis. However, in Fig.29 the comparative example shown, the Weibull diagram has a slope. Such a slope of the Weibull diagram indicates the presence of deviation, meaning that there are defects that reduce the dielectric breakdown injection charge amount Qbd.

[0071] Thus, in the SiC wafer, there is room for improvement such as suppressing characteristic deviations such as the life of the insulating film between the devices formed thereon.

[0072] <Configuration of SiC Wafer>

[0073] In the first embodiment, efforts were made to solve the above-mentioned room for improvement. Hereinafter, the technical concept in this embodiment in which such efforts were made will be described.

[0074] As a result of the research by the present inventors, it was found that the composition of the wafer surface affects the reliability of the gate insulating film, and by controlling the composition of the surface of the SiC wafer, the deviation of the life of the gate insulating film can be reduced. Hereinafter, a SiC wafer with an epitaxial layer that can reduce the deviation of the life of the gate insulating film by controlling the composition of the surface of the SiC wafer will be described.

[0075] Here, Figure 1 to Figure 4 the manufacturing process of the SiC wafer of this embodiment will be described. Figure 1 It is a top view showing the manufacturing process of the SiC wafer of this embodiment, Figure 2 to Figure 4 It is a cross-sectional view showing the manufacturing process of the SiC wafer of this embodiment.

[0076] When manufacturing the SiC wafer of this embodiment, first, as Figure 1 and Figure 2As shown, a SiC wafer 1 consisting only of a SiC substrate (SiC bulk substrate) 2 is prepared. The crystal form of the SiC substrate 2 is, for example, 4H-SiC, or 6H-SiC or 3C-SiC. The off angle of the main surface of the SiC substrate 2 is, for example, preferably greater than 0.5 degrees and less than 8 degrees. Here, the off angle of the main surface of the SiC substrate 2 is, for example, 4 degrees. The plane direction of the main surface of the SiC substrate 2 can be any of the Si plane, the C plane, or other plane directions. Here, the plane direction of the main surface of the SiC substrate 2 is the Si plane.

[0077] The SiC substrate 2 may be a substrate produced by a sublimation method, a substrate produced by a solution method, or a substrate produced by a vapor phase growth method. The concentration of n-type impurities in the SiC substrate 2 is, for example, 1×10 18 ~1×10 21 / cm -3 , for example, 1×10 18 / cm -3 .

[0078] Then, if Figure 3 As shown, an epitaxial growth method is used to form an epitaxial layer (epitaxial growth layer, semiconductor layer) 3 on the main surface of the SiC substrate 2. Specifically, at a temperature above 1500°C, H2 (hydrogen) is used as a carrier gas to supply SiH4 (monosilane) and C3H8 (propane) to the SiC substrate 2. It should be noted that trichlorosilane and methane can also be used as gases for epitaxial growth. In addition, hydrogen chloride can also be introduced to increase the growth rate. Thus, epitaxial growth is performed to form an epitaxial layer 3. At this time, the epitaxial layer 3 is mainly composed of SiC.

[0079] The n-type impurity concentration of the epitaxial layer 3 varies depending on the device being fabricated, and is, for example, 1×10 14 ~1×10 18 / cm -3 The film thickness of the epitaxial layer 3 varies depending on the device to be manufactured, and is, for example, several μm to several tens of μm.

[0080] In addition, it is believed that there are basal plane dislocations (BPDs) that are defects that cause power-on degradation in the SiC substrate 2. The BPDs that extend from the SiC substrate 2 side to the epitaxial layer 3 during epitaxial growth have the property of hindering power-on and expanding when power is applied. In contrast, a portion of the BPDs in the SiC substrate 2 is transformed into threading edge dislocations (TEDs) at the interface between the SiC substrate 2 and the epitaxial layer 3 and extends into the epitaxial layer 3. TEDs do not hinder power-on in the substrate and do not expand even when power is applied.

[0081] Therefore, before forming the epitaxial layer 3, a high-concentration buffer layer (semiconductor layer) composed of SiC can be formed on the SiC substrate 2. The n-type impurity concentration of the buffer layer is, for example, 1×10 18 / cm -3 By providing a buffer layer between the SiC substrate 2 and the epitaxial layer 3, the probability of BPD expanding in the epitaxial layer 3 can be reduced. That is, during epitaxial growth, the BPD in the SiC substrate 2 is easily converted into TED at the interface between the SiC substrate 2 and the buffer layer. Furthermore, due to the presence of the buffer layer, the probability of holes reaching the BPD of the SiC substrate 2 can be reduced. As a result, in a device formed on a stacked substrate including the SiC substrate 2 and the epitaxial layer 3, the probability of power-on degradation can be reduced.

[0082] Furthermore, before forming the epitaxial layer 3 , CMP (Chemical Mechanical Polishing) may be performed on the top surface of the SiC substrate 2 or the top surface of the buffer layer.

[0083] In addition, although the epitaxial layer 3 is formed on the SiC substrate 2, a laminated substrate (SiC wafer 1) in which the epitaxial layer 3 is laminated on the SiC substrate 2 may be prepared instead of using Figure 1 to Figure 3 The process described.

[0084] Then, if Figure 4 As shown, a carbon-enrichment treatment is performed. That is, the surface composition of the epitaxial layer 3 is treated to be carbon-rich. Specifically, on the top surface of the epitaxial layer 3, the surface composition is changed so that the proportion of bonds other than C-Si such as CC or CO (atomic percent, atm%) is greater than the proportion of C-Si bonds. In other words, the carbon-rich mentioned in the present application refers to a state in which the proportion of bonds other than C-Si containing C is greater than the proportion of C-Si bonds. In other words, the carbon-rich mentioned in the present application refers to a state in which the composition ratio of C-Si on the top surface of the epitaxial layer is less than 50atm%.

[0085] There are several methods for carbon enrichment treatment, but here, for example, CMP is used to change the surface composition. Thus, a carbon-rich layer 4 is formed on the top surface of the epitaxial layer 3. The change in the surface composition of the SiC wafer can be achieved by, for example, CMP.

[0086] The ratio of the surface composition of the epitaxial layer 3 (the composition of the carbon-rich layer 4) is investigated, for example, by surface composition analysis using XPS (X-ray Photoelectron Spectroscopy). Here, in the surface composition analysis using XPS, when performing peak separation of the C1s spectrum, the conditions of the carbon-enrichment treatment are adjusted so that the ratio of bonds other than C-Si such as CC or CO is greater than the ratio of C-Si bonds.

[0087] Figure 5 and Figure 6 A schematic diagram illustrating a surface composition analysis method using XPS is shown in FIG. Figure 5 and Figure 6 In the figure, the carbon-rich layer formed on the top surface of the epitaxial layer is omitted. Here, XPS having a detector (detector) 35 with an angle resolution function is used. When XPS is used for surface composition analysis, the detector 35 has an angle resolution function, and information at a depth of several nm (for example, 1 to 3 nm) from the wafer surface can be decomposed from information at a position deeper from the wafer surface (for example, about 7 nm). In other words, when the detector 35 does not have an angle resolution function, the surface composition of the shallower area of ​​the wafer surface and the surface composition of the deeper area of ​​the wafer surface cannot be distinguished and detected.

[0088] In XPS measurement, the SiC wafer 1 is irradiated with X-rays 25 with strong transmission power, and the photoelectrons (secondary electrons) generated thereby are detected. Therefore, the detection depth is determined by the mean free path of the photoelectrons. In XPS where the detector has an angle resolution function, the depth information can be known based on the position within the detector surface where the photoelectrons are detected. In other words, the photoelectrons generated in the shallow area of ​​the wafer surface can be detected as Figure 5 As shown in FIG. 1 , the photoelectrons generated in the deep region of the wafer surface have a short mean free path in the SiC wafer 1. Therefore, as shown in FIG. Figure 6 As shown in the figure, it can only escape at a low angle, and cannot escape from the SiC wafer 1 at a high angle. Therefore, it is possible to perform composition analysis at a shallow region (e.g., a region 1 to 3 nm from the wafer surface) on the wafer surface based on the photoelectrons that escape from the wafer at a low angle toward the detector 35. In this way, if XPS with an angle resolution function is used, it is possible to resolve and obtain the composition at a depth of several nm from the wafer surface.

[0089] The high angle, low angle, etc. angles (extraction angle, escape angle of secondary electrons) mentioned here are the angles θ between a line perpendicular to the surface (primary surface) of the SiC wafer 1 and the traveling direction of photoelectrons released from the surface of the SiC wafer 1 due to irradiation of the X-ray 25.

[0090] In this embodiment, when XPS is used to perform composition analysis near the extreme surface of the SiC wafer (e.g., a region 1 to 3 nm from the wafer surface), the surface composition of the SiC wafer is adjusted by carbon enrichment treatment so that the surface composition ratio of C-Si becomes 43 atm%. However, without decomposing and detecting the composition near the extreme surface of the SiC wafer (e.g., a region 1 to 3 nm from the wafer surface), the results of the XPS analysis also include information on the bond state of a portion several nm (e.g., 7 nm) deep from the wafer surface. In this case, the surface composition ratio of C-Si as a result of the XPS analysis becomes 83 atm%. The following uses Figures 7 to 13 This is explained.

[0091] Figure 7 to Figure 10 The graphs are graphs showing details of the peak separation of the C1s spectrum obtained by surface composition analysis using XPS. In these graphs, the horizontal axis represents the binding energy of the composition on the wafer surface, and the vertical axis represents the energy of the photoelectrons (intensity of emitted photoelectrons). Figure 7 to Figure 9 , which shows the results of XPS analysis of a SiC wafer subjected to carbon enrichment treatment according to the present embodiment. Fig.10 The results of XPS analysis of a SiC wafer of a comparative example which was not subjected to the carbon enrichment treatment of the present embodiment are shown.

[0092] Figure 7 and Fig.10 This is a graph showing the analysis results when the detection angle of the detector 35 is 81.125 degrees, i.e., a high angle. Figure 7 and Fig.10 Indicates the composition of the shallower areas of the wafer surface. Fig. 9 This is a graph showing the analysis results when the detection angle of the detector 35 is 24.875 degrees, i.e., a low angle. Fig. 9 Indicates the composition of the deeper areas of the wafer surface. Figure 8 35 is a coordinate diagram showing the analysis result when the detection angle of the detector 35 is 51.125 degrees. That is, Figure 8 Indicates the composition of the shallow area Figure 7 The composition of the deep area is shown Fig. 9 The composition of the deeper region of the wafer surface of the comparative example is Fig.10 Since the composition of the shallower region on the wafer surface of the comparative example shown is substantially the same, illustration thereof is omitted here.

[0093] Figure 7 to Figure 10 A coordinate diagram showing the analysis results of each of the bond between carbon and silicon, namely C-Si, the bond between carbon and carbon, namely CC, the bond between carbon and oxygen, namely CO, the double bond between carbon and oxygen, namely C=O, and the ether bond between oxygen and carbon, namely OCO. Figure 7 to Figure 10In the figure, the coordinate diagram of C-Si is represented by a solid line, the coordinate diagram of CC is represented by a dotted line, the coordinate diagram of CO is represented by a single-dot chain line, the coordinate diagram of C=O is represented by a double-dot chain line, and the coordinate diagram of OCO is represented by a triple-dot chain line.

[0094] like Figure 7 to Figure 9 As shown, the composition ratio of each of the various bonds containing carbon has depth dependence. Figure 11 to Figure 15 Provide explanation. Fig.11 and Fig.12 It is a table and a graph showing the relationship between the composition ratio of various bonds containing carbon in the surface of the SiC wafer before the carbon enrichment treatment and the take-off angle of the XPS analysis. Fig.13 and Fig.14 This is a table and a coordinate graph showing the relationship between the composition ratio of various bonds containing carbon on the surface of the SiC wafer after carbon enrichment treatment and the extraction angle of XPS analysis. Fig.12 and Fig.14 In the graph, the horizontal axis represents the take-off angle of XPS analysis, and the vertical axis represents the composition ratio. The larger the horizontal axis of these graphs, that is, the take-off angle of XPS analysis, the closer the XPS analysis site is to the wafer surface.

[0095] Fig.15 This is a graph showing the total composition ratio of C-Si bonds before and after carbon enrichment treatment and the composition ratio of bonds containing carbon other than C-Si. Fig.15 In the figure, the right side shows the coordinate graph before the carbon enrichment treatment, and the left side shows the coordinate graph after the carbon enrichment treatment. Fig.15 In FIG. 1 , the composition ratio of C—Si bonds is indicated by white bars, and the bars indicating the total composition ratio of bonds other than C—Si and including carbon are hatched.

[0096] exist Fig.12 and Fig.14 In the figure, the coordinate diagram of C-Si is represented by a solid line, the coordinate diagram of CC is represented by a dotted line, the coordinate diagram of CO is represented by a single-dot chain line, the coordinate diagram of C=O is represented by a double-dot chain line, and the coordinate diagram of OCO is represented by a triple-dot chain line.

[0097] like Figure 11-12 and Fig.15 As shown in FIG. 1 , before the carbon enrichment treatment, C-Si bonds account for the majority of the composition ratio near the wafer surface, and the total composition ratio of bonds containing carbon other than C-Si bonds is less than the composition ratio of C-Si bonds. Figure 13 to Figure 15 As shown in FIG. 1 , after the carbon enrichment treatment, the composition ratio of C-Si bonds in the particularly shallow region near the wafer surface is about 43%, which is the largest. Figure 13 to Figure 15As shown, the total ratio of the composition ratio of bonds containing carbon other than C-Si bonds is about 57%, which is larger than the composition ratio of C-Si bonds. In particular, the composition ratio of CC bonds in the shallower region of the wafer surface is close to the composition ratio of C-Si bonds.

[0098] In this way, on the surface of the wafer, the total ratio of the composition ratio of each bond containing carbon other than the C-Si bond is larger than the composition ratio of the C-Si bond. That is, it becomes a carbon-rich state. In addition, when the surface composition of the SiC wafer is adjusted by carbon-rich treatment, the surface composition ratio of C-Si near the extreme surface of the SiC wafer (for example, the area 1 to 3 nm from the wafer surface) becomes 43atm% by XPS. Therefore, it is considered that when the XPS with angle resolution function is used for measurement, if the composition ratio of C-Si near the extreme surface of the epitaxial layer is 50atm% or less, it is a carbon-rich state. And by using this carbon-rich treatment, the surface composition ratio of C-Si at a depth of about a few nm (for example, 7nm) from the wafer surface becomes 83atm%. Therefore, it is considered that if the surface composition ratio of C-Si at a depth of about a few nm (for example, 7nm) from the wafer surface is 83atm% or less, it is a carbon-rich state. That is to say, when XPS without angle resolution function is used for measurement, even if the composition ratio of the wafer surface is measured, the shallow and deep areas of the wafer surface cannot be distinguished. Therefore, when such XPS is used for measurement, it is considered that when the composition ratio of C—Si on the top surface of the epitaxial layer, which is the wafer surface, is 83 atm % or less, it is in a carbon-rich state.

[0099] Here, the inventors confirmed that when the XPS extraction angle was 24.875 degrees, the composition ratio of CC was 8.79 atm%, and the composition ratio of CO was 3.6 atm% on the top surface of the epitaxial layer. That is, it can be considered that when the XPS extraction angle is small and the deeper region of the epitaxial layer is analyzed, the carbon-rich state is achieved when the composition ratio of CC is 8.7 atm% or more and the composition ratio of CO is 3.6 atm% or more.

[0100] In addition, the inventors confirmed that when the XPS extraction angle was 81.125 degrees, the composition ratio of CC was 36.01 atm%, and the composition ratio of CO was 10.55 atm% on the top surface of the epitaxial layer. That is, it can be considered that when the XPS extraction angle is large and a shallow region of the epitaxial layer is analyzed, when the composition ratio of CC is 35 atm% or more and the composition ratio of CO is 10 atm% or more, a carbon-rich state is achieved.

[0101] <Effects of the present embodiment>

[0102] The inventors evaluated the TDDB characteristics of 68 DMOSFETs (Double-Diffused MOSFETs) made on each of the SiC wafers of the present embodiment that were subjected to carbon enrichment treatment and SiC wafers that were not subjected to carbon enrichment treatment. Here, the potential of each of the source and drain was set to 0V, and a voltage was given to the gate to control the flow of a constant current, and the time until the gate insulating film broke through was measured. The temperature during the measurement was set to about 150°C, and the voltage was adjusted so that the current density became constant.

[0103] Fig.17 2 shows a Weibull plot of the results of evaluating the above TDDB characteristics. Fig.17 The horizontal and vertical axes of the coordinate graph shown are Fig.29 The horizontal and vertical axes represent the insulation breakdown injection charge Qbd and the cumulative failure rate respectively. Fig.17 Graph showing the relationship between the amount of injection charge for dielectric breakdown and the cumulative failure rate in the SiC devices of the comparative example and the present embodiment. Fig.17 In the graph, the evaluation results of the apparatus of the comparative example which did not perform the carbon enrichment treatment are represented by diamonds, and the evaluation results of the apparatus which used the wafer of this embodiment which performed the carbon enrichment treatment are represented by triangles.

[0104] In this evaluation, the shape parameter m is calculated during analysis. In addition, the size parameter is set to η. Generally, when the cumulative failure rate F(t) follows the Weibull distribution, the cumulative failure rate F(t) is expressed as Fig.16 The formula (1) shown is described.

[0105] In addition, the formula (1) can be rewritten as the following formula (2).

[0106] ln(-ln(1-F(t))=mln(t)-mlnη) (2)

[0107] In the Weibull plot, the slope is m when y = ln(-ln(1-F(t)) and x = ln(t), and the intercept is -mlnη. That is, as m increases, the distribution becomes neater and the characteristic deviation decreases, and as η increases, the maximum value of the main distribution increases. In other words, Fig.17 As shown, the Weibull plot of the comparative example has a slope with respect to the vertical axis, whereas the Weibull plot of the present embodiment has a uniform distribution parallel to the vertical axis.

[0108] In each method of the present embodiment in which the carbon enrichment treatment was performed and the comparative example in which the carbon enrichment treatment was not performed, if the shape parameter m is calculated, then in the method in which the carbon enrichment treatment was performed, m=11.3, and in the method in which the carbon enrichment treatment was not performed, m=2.1. That is, the value of m increases due to the carbon enrichment treatment. In addition, the inventors confirmed that the value of η also increases. This means that the slope of the main distribution becomes steeper and the maximum value of Qbd becomes higher. From the perspective of improving the yield, the increase in m and η due to the carbon enrichment treatment is effective.

[0109] As described above, in the present embodiment, a SiC wafer having an epitaxial layer on a SiC substrate and a main surface in a carbon-rich state is provided. That is, the composition ratio of C-Si on the top surface of the epitaxial layer is less than 50 atm%. Since the surface of the SiC wafer is carbon-rich, the time (lifetime) until insulation breakdown can be extended for components such as MOSFET with a gate insulating film formed on such a SiC wafer. In addition, the characteristics such as the life of each gate insulating film of the components formed in each chip area arranged in a matrix on the circular SiC wafer can be made consistent, thereby preventing the occurrence of characteristic deviations. Therefore, the above-mentioned room for improvement can be eliminated. The reliability of the SiC wafer can be improved. In addition, since the generation of defective chips is prevented, the yield of the product can be improved by using the SiC wafer that has been subjected to carbon-enrichment treatment according to the present embodiment.

[0110] However, attention should be paid to the composition ratio within the wafer surface after carbon enrichment treatment. When the SiC surface is completely carbonized by carbon enrichment treatment, that is, when the composition ratio of bonds other than C-Si on the wafer surface becomes 90-100 atm%, graphene will exist at the interface between the layer (epitaxial layer) composed of SiC and the gate insulating film when making devices such as MOSFET or IGBT. If graphene exists at the interface of SiC / SiO2, there is a concern that it will be turned on between the source and drain independently of the gate voltage, and the element will not be able to operate normally. Therefore, it is expected that the C-Si composition ratio on the wafer surface is greater than 10 atm%.

[0111] In this way, in order to obtain the effect of the present embodiment, it is necessary to adjust the composition ratio of the C—Si bond to be greater than 10 atm %.

[0112] <Modification 1>

[0113] The carbon enrichment treatment may be a short-time heat treatment of the SiC wafer in an inert gas (eg, Ar (argon)) atmosphere at a temperature of, for example, about 1300° C. The carbon enrichment treatment can be performed by carbonizing the surface of the SiC wafer by such a heat treatment.

[0114] However, even in this case, attention should be paid to the composition ratio within the wafer surface after carbon enrichment treatment. That is, when the SiC surface is completely carbonized by high-temperature annealing in an Ar atmosphere, graphene is formed at the interface of SiC / SiO2, so there is a concern that the source and drain will be turned on independently of the gate voltage, and the device will not be able to operate normally. Therefore, it is desirable that the C-Si composition ratio on the wafer surface is greater than 10 atm%.

[0115] <Modification 2>

[0116] As a second variation of this embodiment, Figure 18 to Figure 27 The process of forming a DMOSFET on a SiC wafer will be described. Figures 18 to 26 1 is a cross-sectional view showing the manufacturing process of the DMOSFET on the SiC wafer according to the present modification. Fig. 27 It is a top view showing the manufacturing process of the DMOSFET on the SiC wafer according to the present modification.

[0117] Here, first use Figure 1 to Figure 4 As described above, a SiC wafer 1 including an epitaxial layer 3 subjected to carbon enrichment treatment is formed. Figures 18 to 26 In FIG. 1 , the carbon-rich layer on the top surface of the epitaxial layer 3 is omitted from illustration.

[0118] Then, if Fig.18 As shown in FIG. 1 , Al (aluminum) ions are implanted into the surface of the epitaxial layer 3 using a mask (not shown) provided on the epitaxial layer 3. Thus, a p-body region 5 as a p-type semiconductor region is formed on the top surface of the epitaxial layer 3. It should be noted that the implantation depth of the impurity is, for example, about 1 μm. In addition, the p-type impurity concentration of the p-body region 5 is, for example, 5×10 16 ~1×10 19 cm -3 In addition, the ions implanted to form the p-body region 5 may be B (boron) ions. In addition, a p-type epitaxial layer composed of SiC may be further formed on the epitaxial layer 3, and the epitaxial layer may be used as the p-body region. In this case, Figure 4 The carbon enrichment treatment described above is not performed before the formation of the epitaxial layer, but is performed after the formation of the epitaxial layer and before the formation of the gate insulating film described below. Thereafter, the mask is removed.

[0119] Then, if Fig.19 As shown, a mask (not shown) provided on the epitaxial layer 3 is used to implant N (nitrogen) ions into the top surface of the epitaxial layer 3. As a result, a source region 6 as an n-type semiconductor region having a shallower depth than the p-body region 5 is formed on the top surface of the p-body region 5. The implantation depth of the impurity is, for example, in the range of 0.1 to 0.5 μm. In addition, the n-type impurity concentration of the source region 6 is, for example, 1×1018 ~1×10 21 cm -3 In addition, the ions implanted to form the source region 6 may be P (phosphorus). Thereafter, the mask is removed.

[0120] Then, if Fig. 20 As shown, Al ions are implanted into the top surface of the epitaxial layer 3 using a mask (not shown) provided on the epitaxial layer 3. As a result, a potential fixed region 7 as a p-type semiconductor region is formed on the top surface of the p-body region 5, which is shallower than the p-body region 5 and adjacent to the source region 6. The implantation depth of the impurity is, for example, in the range of 0.1 to 0.5 μm. In addition, the p-type impurity concentration of the potential fixed region 7 is set to, for example, 1×10 18 ~1×10 21 cm -3 In addition, the ions implanted to form the potential fixed region 7 may be B ions. Thereafter, the mask is removed.

[0121] Then, if Fig.21 As shown in FIG. 1 , N ions are implanted into the back surface of the SiC substrate 2 to form a drain region 8 as an n-type semiconductor region. The n-type impurity concentration of the drain region 8 is, for example, 1×10 16 ~1×10 19 cm -3 In addition, the ions implanted to form the drain region 8 may be P ions.

[0122] In addition, in this modification example, the formation process of the minimum structure for MOSFET operation is described, but a structure with additional functions such as a termination region may be formed.

[0123] Next, although not shown, after a carbon film is deposited as a coating material covering the periphery of the SiC wafer 1 composed of the SiC substrate 2 and the epitaxial layer 3, impurity activation annealing is performed at a temperature of, for example, 1600 to 1800° C. Thereafter, the carbon film is removed by oxygen plasma ashing. Thereafter, in order to obtain a cleaner surface, a thermal oxide film may be formed and removed using a dilute fluoric acid solution.

[0124] Then, if Fig. 22 As shown, a gate insulating film 9 is formed on the epitaxial layer 3. In this embodiment, a deposited oxide film having a thickness of about 10 to 100 nm is formed by, for example, using a CVD (Chemical Vapor Deposition) method.

[0125] Then, if Fig.23As shown in FIG. 1 , a gate electrode 10 composed of an n-type polysilicon film having a thickness of about 100 to 300 nm is deposited on the epitaxial layer 3. The gate electrode 10 can be formed by forming the silicon film by, for example, a CVD method, and then patterning the silicon film. The top surfaces of the source region 6 and the potential fixed region 7 are exposed from the gate electrode 10. Thus, a MOSFET having the gate electrode 10, the source region 6, and the drain region 8 is formed.

[0126] Then, if Fig.24 As shown, an interlayer film (interlayer insulating film) 11 covering the gate electrode is formed. The interlayer film 11 can be formed by patterning a silicon oxide film after forming a silicon oxide film on the gate electrode 10 by, for example, a CVD method. By this patterning, contact holes are formed to expose the top surfaces of the source region 6 and the potential fixed region 7.

[0127] Then, if Fig.25 As shown, in order to achieve n + Type source region 6 and p + In order to ensure electrical conduction of the potential fixed region 7 of the source region 6 and the potential fixed region 7, a silicide layer 12 is formed on each of the source region 6 and the potential fixed region 7. That is, a metal film for silicide is deposited on the epitaxial layer 3, and silicide is performed by annealing treatment at, for example, 700° C. to 1000° C. Thus, a silicide layer 12 serving as a source-base common connection portion is formed. Subsequently, in an area not shown in the figure, in order to ensure electrical conduction with the gate electrode, the interlayer film is etched to form a gate contact hole.

[0128] Next, the source electrode 13 covering the interlayer film 11 and the silicide layer 12 is formed on the epitaxial layer 3. The source electrode 13 is electrically connected to the source region 6 and the potential fixed region 7 via the silicide layer 12.

[0129] Then, if Fig.26 As shown, the bottom surface of the drain region 8 is silicided to form a silicide layer 14. Thereafter, a drain contact electrode 15 is formed under the silicide layer 14. The silicide metal film, the source electrode 13, and the drain contact electrode 15 are each made of a metal material such as Ni (nickel) or Al. Thereafter, in order to protect the device, a surface protection film composed of an insulator is formed on the top surface of the SiC wafer 1 and a wiring process is performed for each electrode, and the semiconductor device is completed. Thus, the semiconductor device 10 is obtained. Fig. 27 The SiC wafer shown in FIG. The SiC wafer is formed with chip regions arranged in a matrix shape when viewed from above. The chip regions are cut into pieces by a dicing process, thereby obtaining a plurality of semiconductor chips from the SiC wafer.

[0130] In the MOSFET formed in this modification, a carbon-rich layer is formed on the top surface of the epitaxial layer 3 connected to the gate insulating film 9. As a result, the time (lifetime) until the insulation breakdown of the gate insulating film 9 between the gate electrode 10 and the epitaxial layer 3 can be extended. In addition, the characteristics such as the life of the gate insulating film of each element formed in each chip area arranged in a matrix on the circular SiC wafer can be made consistent, preventing the occurrence of characteristic deviation. Therefore, the reliability of the SiC wafer can be improved, and the yield rate of the product can be improved.

[0131] Here, the carbon-rich layer is formed after the epitaxial layer is formed and before the p-body region is formed (see Figure 3 However, the carbon enrichment treatment is not limited to this time, and can be performed at any time as long as it is after the epitaxial layer constituting the outermost surface of the SiC wafer is formed and before the film forming step of the gate insulating film.

[0132] In the case of forming a trench gate MOSFET, a trench is formed on the top surface of the epitaxial layer, and then a gate electrode is buried in the trench via a gate insulating film. In this case, carbon enrichment treatment is performed after the trench is formed and before the gate insulating film is formed.

[0133] (Implementation Method 2)

[0134] The carbon enrichment treatment can also be achieved by oxidizing the surface of the SiC wafer having the epitaxial layer and removing the oxide film formed by the oxidation using a chemical liquid (chemical liquid) such as fluoric acid.

[0135] Fig.28 The graph is a graph showing the composition ratios of C-Si bonds and bonds containing carbon other than C-Si bonds on the top surfaces of SiC wafers before carbon enrichment treatment, SiC wafers after oxidation treatment at 1300°C and oxide film removal, and SiC wafers after oxidation treatment at 1150°C and oxide film removal. Fig.28 In FIG. 1 , the graphs of the case before the carbon enrichment treatment, the case after the oxidation treatment at 1300° C., and the case after the oxidation treatment at 1150° C. are arranged from right to left. That is, Fig.28 The surface composition ratios of SiC wafers obtained by oxidation treatment at 1150°C and 1300°C in a dry oxygen atmosphere to form an oxide film of about 50 nm and then removing the oxide film with fluoric acid were compared. Fig.28 In FIG. 1 , the composition ratio of C—Si bonds is indicated by white bars, and the bars indicating the total composition ratio of bonds other than C—Si and including carbon are hatched.

[0136] like Fig.28As shown in the figure, compared with the case before the carbon enrichment treatment, when the oxidation treatment was performed at 1300°C, the composition ratio of C-Si bonds became smaller, and the composition ratio of bonds containing carbon other than C-Si bonds became larger. In addition, compared with the case of the oxidation treatment at 1300°C, when the oxidation treatment was performed at 1150°C, the composition ratio of C-Si bonds became smaller, and the composition ratio of bonds containing carbon other than C-Si bonds became larger.

[0137] That is, in order to reduce the composition ratio of C—Si bonds, it is important to perform oxidation at a lower temperature.

[0138] As mentioned above, the invention completed by the present inventors has been specifically described based on the embodiments thereof, but the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the gist thereof.

Claims

1. A SiC wafer comprising a SiC substrate and an epitaxial layer formed on the SiC substrate and containing SiC, The composition ratio of C—Si on the surface of the epitaxial layer is 50 atm % or less and greater than 10 atm %.

2. The SiC wafer according to claim 1, wherein: A buffer layer is provided between the SiC substrate and the epitaxial layer.

3. The SiC wafer according to claim 1, wherein: The SiC substrate is a 4H-SiC single crystal substrate.

4. The SiC wafer according to claim 1, wherein: The epitaxial layer is a 4H-SiC single crystal epitaxial layer.

Images