Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and the semiconductor device comprises a semiconductor layer which comprises a first region and a second region; the first device structure is located in the first region and on the surface of the first region; the second device structure is located in the second region and on the surface of the second region; wherein the first device structure is a structure of a device manufactured by a BCD process technology, and the second device structure is a structure of a trench power device with a T-shaped gate. According to the invention, the semiconductor device with low-specific on-resistance and various advantages of devices manufactured by a BCD process technology can be manufactured through a relatively simple process flow and relatively low cost.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] BCD (Bipolar CMOS DMOS) process technology refers to a process technology that integrates bipolar devices, CMOS devices and DMOS devices on the same chip. The devices manufactured by this process technology combine the advantages of high transconductance and strong load driving capability of bipolar devices and high integration and low power consumption of CMOS devices. It also combines the advantages of high voltage and large current drive of DMOS devices, but performs poorly in terms of low specific on-resistance. Summary of the invention

[0003] In view of the above problems, the purpose of this application is to provide a semiconductor device with a new structure and a method for manufacturing the same, so as to manufacture a semiconductor device having low specific on-resistance and various advantages of devices manufactured by BCD process technology through a relatively simple process flow and lower cost.

[0004] According to a first aspect of the present application, there is provided a semiconductor device, comprising:

[0005] a semiconductor layer, the semiconductor layer comprising a first region and a second region;

[0006] a first device structure located within the first region and on a surface of the first region;

[0007] a second device structure located within the second region and on a surface of the second region;

[0008] The first device structure is a structure of a device manufactured using a BCD process technology, and the second device structure is a structure of a trench power device with a T-type gate.

[0009] According to a second aspect of the present application, a method for manufacturing a semiconductor device is provided, comprising:

[0010] Providing a semiconductor layer, the semiconductor layer comprising a first region and a second region;

[0011] forming a first device structure in the first region and on a surface of the first region;

[0012] forming a second device structure in the second region and on a surface of the second region;

[0013] The first device structure is a structure of a device manufactured using a BCD process technology, and the second device structure is a structure of a trench power device with a T-type gate.

[0014] The semiconductor device provided by the present application includes a semiconductor layer, a first device structure located in a first region of the semiconductor layer, and a second device structure located in a second region of the semiconductor layer, wherein the first device structure is a structure of a device manufactured by the BCD process technology, and the second device structure is a structure of a trench power device with a T-type gate, so the semiconductor device is a device after the device manufactured by the BCD process technology and the trench power device with a T-type gate are integrated. Since the manufacturing process of the trench power device with a T-type gate is relatively simple and has fewer mask levels, and the trench power device with a T-type gate has a lower specific on-resistance, the semiconductor device of the present application can be manufactured through a relatively simple process flow and at a lower cost, and the semiconductor device of the present application has both low specific on-resistance and various advantages of the device manufactured by the BCD process technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings:

[0016] Figure 1 Shown is a cross-sectional schematic diagram of a semiconductor device in the related art;

[0017] Figure 2 FIG. 1 is a cross-sectional schematic diagram of a semiconductor device provided in one embodiment of the present application;

[0018] Figure 3 FIG. 1 is a cross-sectional schematic diagram of another semiconductor device provided by an embodiment of the present application;

[0019] Figure 4 Shown is a flow chart of a method for manufacturing a semiconductor device provided by another embodiment of the present application;

[0020] Figure 5a FIG. 1 is a cross-sectional schematic diagram of a manufacturing method provided in another embodiment of the present application after etching a first groove and a second groove on the surface of a semiconductor layer;

[0021] Figure 5b It is a cross-sectional schematic diagram after a dielectric layer is formed in both the first trench and the second trench in a manufacturing method provided by another embodiment of the present application;

[0022] Figure 5c It is a cross-sectional schematic diagram of a manufacturing method provided by another embodiment of the present application after a first sacrificial structure is formed in a first trench and a second sacrificial structure is formed in a second trench;

[0023] Figure 5d It is a cross-sectional schematic diagram of a manufacturing method provided by another embodiment of the present application after the materials filled in the first trench and the second trench are flush with the surface of the epitaxial layer;

[0024] Figure 5e It is a cross-sectional schematic diagram after forming a second dielectric layer in the second region in a manufacturing method provided by another embodiment of the present application;

[0025] Figure 5f Shown is a cross-sectional schematic diagram after a third dielectric layer is formed in the second region in a manufacturing method provided by another embodiment of the present application.

[0026] Description of reference numerals: 100-semiconductor device; 110-semiconductor layer; 111-substrate; 112-epitaxial layer; 121-deep trench; 122-shielding gate; 123-control gate; 124-dielectric layer; 125-protective layer; 126-conductive plug; 127-wiring layer; 200-semiconductor device; 210-semiconductor layer; 211-substrate; 212-epitaxial layer; 221-second trench; 222a-second dielectric layer; 222b-third dielectric layer; 223-gate electrode; 224-protective layer; 225-conductive plug; 226-wiring layer; 241-drift region; 242-body region; 243-source region; 244-body contact region; 245-drain region; 2 46-gate structure; 300-semiconductor device; 310-semiconductor layer; 311-substrate; 312-epitaxial layer; 321-second trench; 322-gate dielectric layer; 322a-second dielectric layer; 322b-third dielectric layer; 322c-target dielectric layer; 322d-second sacrificial structure; 323-gate electrode; 324-protective layer; 325-conductive plug; 326-wiring layer; 331-first trench; 332-insulating structure; 332a-first dielectric layer; 332b-core structure; 332c-first sacrificial structure; 341-drift region; 342-body region; 343-source region; 344-body contact region; 345-drain region; 346-gate structure. DETAILED DESCRIPTION

[0027] In the following drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0028] Figure 1 FIG. 1 is a cross-sectional schematic diagram of a semiconductor device in the related art. Figure 1As shown, the semiconductor device 100 includes a semiconductor layer 110, and the semiconductor layer 110 is divided into a first region I and a second region II in the horizontal direction. In some examples, the semiconductor layer 110 includes a substrate 111 and an epitaxial layer 112 located on the surface of the substrate 111 in the vertical direction. The semiconductor device 100 also includes a device structure manufactured by the BCD process technology located in the first region I and on the surface of the first region I in the epitaxial layer 112 ( Figure 1 ), and the structure of the SGT device located in the second region II and on the surface of the second region II in the epitaxial layer 112. The devices manufactured by the BCD process technology are bipolar devices, CMOS devices and DMOS devices, which are different from SGT devices and their respective manufacturing processes do not require trenching.

[0029] Figure 1 The structure of the device manufactured by the BCD process technology is not shown in the figure, but the structure of the SGT device is shown. Figure 1 As shown, the structure of the SGT device includes a deep trench 121 located in the second region II, and a shielding gate 122, a control gate 123 and a dielectric layer 124 located in the deep trench 121. In the deep trench 121, the control gate 123 is located above the shielding gate 122 and does not contact each other, and the dielectric layer 124 fills the area outside the shielding gate 122 and the control gate 123. The structure of the SGT device also includes a protective layer 125 located on the surface of the second region II, a conductive plug 126 penetrating the protective layer 125, and a wiring layer 127 located on the surface of the protective layer 125, wherein one end of the conductive plug 126 is connected to the surface of the second region II between adjacent SGT devices, and the other end of the conductive plug 126 is connected to the wiring in the wiring layer 127.

[0030] Since SGT devices have the advantage of low specific on-resistance in the medium and low voltage fields, Figure 1 The semiconductor device 100 shown has various advantages of low specific on-resistance and devices manufactured by BCD process technology, and can reduce the device packaging cost. However, when integrating SGT devices with devices manufactured by BCD process technology in the traditional process, there are technical problems such as relatively complex process, more mask levels and high cost, and the process capability requirements are also relatively high.

[0031] In view of this, one embodiment of the present application provides a semiconductor device with a novel structure. Figure 2 Shown is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of the present application.

[0032] like Figure 2As shown, the semiconductor device 200 includes a semiconductor layer 210, the semiconductor layer 210 is divided into a first region I and a second region II, the semiconductor device 200 also includes a first device structure located in the first region I and on the surface of the first region I, and a second device structure located in the second region II and on the surface of the second region II, wherein the first device structure is a structure of a device manufactured by the BCD process technology; the second device structure is different from Figure 1 The device structure in the second region II and on the surface of the second region II of the semiconductor device 100 is specifically a structure of a trench power device with a T-type gate.

[0033] In some examples, the semiconductor layer 210 is Figure 2 The substrate 211 and the epitaxial layer 212 located on the surface of the substrate 211 are shown, and the substrate 211 and the epitaxial layer 212 are also divided into a first region I and a second region II accordingly. In this example, the first device structure is located in the first region I and on the surface of the first region I in the epitaxial layer 212, and the second device structure is located in the second region II and on the surface of the second region II in the epitaxial layer 212. Specifically, the substrate 211 can be a silicon substrate, a strained silicon substrate, a germanium substrate, a germanium silicon substrate, a silicon carbide substrate, a III-V compound substrate, etc., and is not limited to the examples listed above.

[0034] In the embodiment of the present application, since the manufacturing process of the trench power device with a T-type gate is simpler than that of the SGT device and has fewer mask levels, the semiconductor device 200 can be manufactured through a relatively simple process flow and at a lower cost; in addition, the trench power device with a T-type gate has a lower specific on-resistance than the SGT device, so the semiconductor device 200 has various advantages of low specific on-resistance and devices manufactured by BCD process technology.

[0035] Figure 2 The structure of a device manufactured by the BCD process technology is exemplarily shown. The device is a DMOS device, including a drift region 241. One end of the upper part of the drift region 241 has a body region 242. The upper part of the body region 242 is provided with a source region 243 and a body contact region 244 with a flush bottom in order from the inside to the outside. The other end of the upper part of the drift region 241 has a drain region 245, wherein the drift region 241, the source region 243 and the drain region 245 have the same doping type, the body region 242 and the body contact region 244 have the same doping type but are different from the doping type of the drift region 241, and these doping regions can be formed by an ion implantation process; in addition, the upper surface of the body region 242 and at least a portion of the upper surface of the drift region 241 are connected to the gate structure 246. It should be understood that the structure of the device manufactured by the BCD process technology includes the respective structures of bipolar devices, CMOS devices and DMOS devices. Figure 2 The examples shown are bipolar devices, CMOS devices, and DMOS devices perpendicular to Figure 2 The cross-sectional distribution shown is Figure 2 The cross section shown shows the structure of only one DMOS device.

[0036] Figure 2 An exemplary second device structure is also shown, which includes two trench power devices with T-type gates, each of which includes a gate structure. It should be understood that in other examples, the second region II may be provided with one or more trench power devices with T-type gates. Figure 2 The gate structure includes a second trench 221 formed in the second region II, and a gate dielectric layer 222 and a gate electrode 223 located in the second trench 221. The gate dielectric layer 222 includes a second dielectric layer 222a and a third dielectric layer 222b. The second dielectric layer 222a covers the lower end and bottom surface of the sidewall of the second trench 221, and the third dielectric layer 222b covers the sidewall at the notch of the second trench 221. The third dielectric layer 222b is above the second dielectric layer 222a and the two are in contact. The thickness of the third dielectric layer 222b is less than that of the second dielectric layer 222a, so the second trench 221 formed with the second dielectric layer 222a and the third dielectric layer 222b is filled to form a gate electrode as shown in FIG. Figure 2 The gate electrode 223 is shown to be T-shaped.

[0037] Furthermore, the second device structure can also be Figure 2 The device shown includes a protective layer 224 located on the surface of the second region II, a conductive plug 225 penetrating the protective layer 224, and a wiring layer 226 located on the surface of the protective layer 224, wherein one end of the conductive plug 225 is connected to the surface of the second region II between adjacent trench power devices with T-type gates, and the other end of the conductive plug 125 is connected to the wiring in the wiring layer 226. The conductive plug 225 and the wiring in the wiring layer 226 can be made of metal.

[0038] Figure 3 FIG. 2 is a cross-sectional schematic diagram of another semiconductor device provided in an embodiment of the present application. Figure 3 As shown, the semiconductor device 300 is Figure 2 The difference between the semiconductor device 200 shown in FIG. 2 is that it also includes an isolation structure located between the first region I and the second region II and an isolation structure located in the first region I. The other structures of the semiconductor device 300 refer to FIG. Figure 2 Specifically, the first device structure is a structure of multiple devices manufactured by BCD process technology. The isolation structure located in the first region I is located between two adjacent devices in the multiple devices to play an isolation role. Figure 3 The cross-sectional distribution shown is Figure 3Only the isolation structure between the first region I and the second region II is shown, and the isolation structure in the first region I is not shown. Each of these isolation structures includes the following: Figure 3 The first trench 331 and the insulating structure 332 located in the first trench 331 are shown. The existing BCD process technology uses a deep well to isolate two adjacent devices. The deep well is formed by implanting N-type ions or P-type ions into a substrate and performing a junction push-up process. The junction push-up process causes the ions injected into the substrate to diffuse laterally, thereby making the cross-sectional area of ​​the deep well parallel to the substrate surface relatively large. The isolation structure used in the semiconductor device 300 provided in the embodiment of the present application can effectively control the cross-sectional area parallel to the substrate surface, thereby facilitating improving the integration density of the semiconductor device 300 and realizing the miniaturization of the semiconductor device 300.

[0039] Furthermore, the insulating structure 332 may be Figure 3 The first dielectric layer 332a shown includes a first dielectric layer 332a covering the sidewall and bottom surface of the first trench 331; a second dielectric layer 322a located in the second region II covers the lower end of the sidewall and the bottom surface of the second trench 321; a third dielectric layer 322b covers the upper end of the sidewall of the second trench 321 so as to be close to the notch of the second trench 321; and the second dielectric layer 322a and the third dielectric layer 322b are connected. The first trench 331 and the second trench 321 have the same depth, and the first dielectric layer 332a and the second dielectric layer 322a are made of the same material and have the same thickness, so that the first trench 331 and the second trench 321 can be formed simultaneously by etching, and the first dielectric layer 332a and the target dielectric layer can be formed simultaneously by deposition or thermal growth, and the second dielectric layer 322a is formed by removing part of the target dielectric layer at the notch of the trench, which is conducive to simplifying the manufacturing process of the semiconductor device 300.

[0040] Furthermore, the insulating structure 332 may also include Figure 3 The core structure 332b shown is located in the first trench 331 and isolated from the first trench 331 by the first dielectric layer 332a; the gate structure located in the second region II includes the second trench 321 and the gate dielectric layer 322 and the gate electrode 323 located in the second trench 321, and the gate electrode 323 and the core structure 332b are made of the same material, so the first trench 331 forming the first dielectric layer 332a and the second trench 321 forming the gate dielectric layer 322 can be filled at the same time to form the core structure 332b and the gate electrode 323, which is conducive to simplifying the manufacturing process of the semiconductor device 300.

[0041] Corresponding to the semiconductor device provided in the above embodiments, another embodiment of the present application provides a method for manufacturing a semiconductor device, which realizes the integration of a device manufactured by the BCD process technology and a trench power device with a T-type gate, and manufactures a semiconductor device that has low specific on-resistance and various advantages of devices manufactured by the BCD process technology.

[0042] Figure 4 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application. Figure 4 As shown, the production method includes:

[0043] Step S110, providing a semiconductor layer, the semiconductor layer comprising a first region and a second region;

[0044] Step S120, forming a first device structure in the first region and on the surface of the first region, the first device structure being a structure of a device manufactured by a BCD process technology;

[0045] Step S130 , forming a second device structure in the second region and on the surface of the second region, wherein the second device structure is a structure of a trench power device with a T-type gate.

[0046] In an optional embodiment, the first device structure is a structure of multiple devices manufactured by BCD process technology. The method for manufacturing a semiconductor device provided in the embodiment of the present application also includes: forming a first trench between the first region and the second region and forming a first trench between two adjacent devices among the multiple devices in the first region, and filling the first trench to form an insulating structure located in the first trench. The first trench and the insulating structure located in the first trench form an isolation structure, so that the cross-sectional area of ​​the isolation structure parallel to the substrate surface can be controlled to a smaller value, and the manufactured semiconductor device can have a higher integration density.

[0047] Figure 5a to Figure 5f FIG. 1 is a schematic diagram showing the execution results of each step in a method for manufacturing a semiconductor device provided in an embodiment of the present application. Figures 5a to 5f This method for manufacturing a semiconductor device is introduced in detail.

[0048] like Figure 5a As shown, the semiconductor layer 310 is divided into a first region I and a second region II, and the first region I and the second region II are etched using the same mask to obtain a first trench 331 located between the first region I and the second region II and in the first region I and a second trench 321 located in the second region II. Figure 5aA photoresist layer is formed on the surface of the epitaxial layer 312 shown. The photoresist layer is exposed using the same mask to obtain a patterned photoresist layer. The patterned photoresist layer is then used as a mask to etch the epitaxial layer 312 to obtain a first trench 331 and a second trench 321 of the same depth.

[0049] It should be understood that, for positive photoresist, the light-transmitting area of ​​the mask corresponds to the opening area of ​​the photoresist layer, thereby corresponding to the formation of the first groove 331 and the second groove 321; for negative photoresist, the light-shielding area of ​​the mask corresponds to the opening area of ​​the photoresist layer, thereby corresponding to the formation of the first groove 331 and the second groove 321.

[0050] like Figure 5b As shown, a dielectric layer is simultaneously formed on the sidewalls and bottom surfaces of the first trench 331 and the second trench 321 by deposition or thermal growth, wherein the dielectric layer formed on the sidewalls and bottom surface of the first trench 331 is the first dielectric layer 332a, and the dielectric layer formed on the sidewalls and bottom surface of the second trench 321 is the target dielectric layer 322c, and the first dielectric layer 332a and the target dielectric layer 322c have the same thickness.

[0051] Specifically, the dielectric layer formed on the sidewalls and bottom surfaces of the first trench 331 and the second trench 321 by thermal growth is an oxide layer, and the oxide layer is a silicon dioxide film when the epitaxial layer 312 is made of doped silicon material. The dielectric layer formed on the sidewalls and bottom surfaces of the first trench 331 and the second trench 321 by deposition can also be an oxide layer.

[0052] The process of forming the first groove 331 and the process of forming the second groove 321 are performed simultaneously, and the process of forming the first dielectric layer 332a and the process of forming the target dielectric layer 322c are performed simultaneously, thereby simplifying the process flow. In addition, the first groove 331 and the second groove 321 are formed by a single mask, so the number of mask layers is small, which is conducive to reducing the manufacturing cost.

[0053] It should be noted that the target dielectric layer 322c is used in the formation process of a trench power device with a T-type gate, and therefore it is necessary to control the execution time of the deposition process or the amount of oxygen filled in the thermal growth process so that the second trench 321 forming the target dielectric layer 322c still has a gap to subsequently form a second sacrificial structure that occupies the T-type gate electrode.

[0054] In some examples, after the target dielectric layer 322c is formed, the surface of the second region II can be covered by a mask to continue the deposition process or thermal growth process until the first trench 331 is filled to obtain an insulating structure; in other examples, Figure 5cAs shown in the figure, while forming the second sacrificial structure 322d in the second trench 321 where the target dielectric layer 322c is formed, forming the first sacrificial structure 332c in the first trench 331 where the first dielectric layer 332a is formed to fill the first trench 331, so that the first dielectric layer 332a and the first sacrificial structure 332c constitute an insulating structure; in some other examples, the insulating structure may be formed by including Figure 5c to Figure 5f The steps shown in the figure are used to form the insulating structure and the gate structure. This example will be formed by combining the following Figure 5c to Figure 5f Among the above three examples, the latter two examples are beneficial to reducing the mask level, thereby helping to reduce the device manufacturing cost. Figure 5c In the embodiment, the first sacrificial structure 332c and the second sacrificial structure 322d are made of the same material, such as silicon nitride or photoresist.

[0055] It should be noted that filling the entire first trench 331 with the first sacrificial structure 332c and filling the entire second trench 321 with the second sacrificial structure 322d can help control the height of the sacrificial structure on the entire wafer and the subsequent etching depth of the target dielectric layer 322c, thereby improving the consistency of the shape and size of the T-type gate electrode and improving the production quality and yield of semiconductor devices.

[0056] In the process of forming the dielectric layer, the surface of the epitaxial layer 312 will also Figure 5b As shown in FIG. 1 , the first sacrificial structure 322c and the second sacrificial structure 322d are covered by the dielectric layer. Thus, after the first sacrificial structure 322c and the second sacrificial structure 322d are formed, Figure 5d As shown, the dielectric layer on the surface of the epitaxial layer 312 is removed, and the materials filled in the first trench 331 and the second trench 321 are made flush with the surface of the epitaxial layer 312 . This process can be achieved by chemical mechanical polishing or the like.

[0057] Next, the surface of the first region I and the surface of the region between the first region I and the second region II can be covered with a mask and then operated, including: Figure 5e As shown in FIG. 1 , the portion of the target dielectric layer 322c located at the notch of the second groove 321 is removed, and the steps include: Figure 5f As shown, a third dielectric layer 322b is formed on the sidewall of the notch of the second trench 321 from which the target dielectric layer 322c is removed. The thickness of the third dielectric layer 322b is less than that of the second dielectric layer 322a, so that the second trench 321 from which the third dielectric layer 322b is formed and the second sacrificial structure 322d is removed has Figure 5f The T-shaped gap is shown, and then a conductive material is filled in the T-shaped gap to form a T-shaped gate electrode. The conductive material is, for example, polysilicon.

[0058] Specifically, when the epitaxial layer 312, the target dielectric layer 322c and the second sacrificial structure 322d are made of different materials, a first selective etching process can be used to remove the portion of the target dielectric layer 322c located at the notch of the second groove 321, thereby avoiding the problem of multiple mask layers and high production cost caused by etching using a mask.

[0059] The first selective etching process uses a first etchant. Compared with the material used in the epitaxial layer 312 and the material used in the second sacrificial structure 322d, the first etchant has a higher etching rate for the material used in the target dielectric layer 322c, so that the epitaxial layer 312 will not be damaged while the portion of the target dielectric layer 322c at the notch of the second trench 321 is removed, and the second sacrificial structure 322d will not be damaged. The second sacrificial structure 322d is not damaged, which is conducive to etching the target dielectric layer 322c into a Figure 5e The target dielectric layer 322c is etched from top to bottom so that only the portion of the target dielectric layer 322c at the notch of the second trench 321 is removed, and the rest of the target dielectric layer 322c (i.e. Figure 5e The portion of the target dielectric layer 322c whose distance from the bottom surface of the second groove 321 is not greater than the threshold value h) will not be etched by the first etchant due to the removal of the second sacrificial structure 322d and the gap left after the removal of the second sacrificial structure 322d. It can be seen that the second sacrificial structure 322d plays an important role in the process of removing the portion of the target dielectric layer 322c located at the notch of the second groove 321.

[0060] After the portion of the target dielectric layer 322c located at the notch of the second trench 321 is removed, the second sacrificial structure 322d can be removed as follows: Figure 5f As shown, the first sacrificial structure 332c is removed while the second sacrificial structure 322d is removed; then, a conductive material is used to simultaneously fill the first trench 331 where the first sacrificial structure 332c is removed and the second trench 321 where the third dielectric layer 322b is formed and the second sacrificial structure 322d is removed, so as to form a conductive material in the first trench 331 where the first dielectric layer 332a is formed. Figure 3 The core structure 332b shown in the figure and the second trench 321 formed with the second dielectric layer 322a and the third dielectric layer 322b are formed. Figure 3 The T-shaped gate electrode 323 shown in the figure does not need to be covered with a mask to remove the second sacrificial structure 322d and form the T-shaped gate electrode 323. It should be understood that although the core structure 332b is made of a conductive material, the first dielectric layer 332a exists around the core structure 332b, and thus the insulation of the insulating structure 332 formed by the core structure 332b and the first dielectric layer 332a is not affected.

[0061] In addition, when the epitaxial layer 312, the second dielectric layer 322a, and the first sacrificial structure 332c and the second sacrificial structure 322d are made of different materials, a second selective etching process can be used to etch the first sacrificial structure 332c and the second sacrificial structure 322d, thereby avoiding the problem of multiple mask layers and high production cost caused by etching using a mask.

[0062] Specifically, the second selective etching process uses a second etchant different from the first etchant. Compared with the material used in the epitaxial layer 312 and the material used in the second dielectric layer 322a, the second etchant has a higher etching rate for the material used in the first sacrificial structure 332c and the second sacrificial structure 322d, so that the epitaxial layer 312 will not be damaged while the first sacrificial structure 332c and the second sacrificial structure 322d are removed, and the formed second dielectric layer 322a will not be damaged, so the manufactured T-type gate has a higher yield.

[0063] It should be understood that Figure 5f After the T-shaped gap shown is filled with conductive material, a second device structure is formed in the second region II and on the surface of the second region II in the above step S130, which also includes the formation of source and drain, the formation of a protective layer, and the formation of a conductive plug and a wiring layer. These common processes of the trench power device with a T-type gate are not described here one by one.

[0064] In addition, the first device structure is formed in the first region and on the surface of the first region in step S120, that is, the BCD process technology is used to form the first device structure in the first region and on the surface of the first region, including forming the first device structure in the first region and on the surface of the first region. Figure 3 The drift region 341, body region 342, source region 343, body contact region 344, drain region 345, gate structure 346 and the structures forming the bipolar device and the CMOS device respectively are shown. The process of manufacturing the bipolar device, CMOS device and DMOS device by the BCD process technology will not be described in detail here.

[0065] The embodiments of the present application are described above, and these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A semiconductor device, comprising: a semiconductor layer, the semiconductor layer comprising a first region and a second region; a first device structure located within the first region and on a surface of the first region; a second device structure located within the second region and on a surface of the second region; The first device structure is a structure of a device manufactured by a BCD process technology, and the second device structure is a structure of a trench power device with a T-type gate.

2. The semiconductor device according to claim 1, wherein The first device structure is a structure of multiple devices manufactured by BCD process technology; The semiconductor device further includes an isolation structure located between the first region and the second region and between two adjacent devices among the plurality of devices, wherein the isolation structure includes a first trench and an insulating structure located in the first trench.

3. The semiconductor device according to claim 2, wherein: The insulating structure includes a first dielectric layer covering the sidewalls and bottom surface of the first trench; The second device structure includes a gate structure, wherein the gate structure includes a second trench formed in the second region, and a second dielectric layer covering the lower end of the sidewall and the bottom surface of the second trench; The first trench and the second trench have the same depth, and the first dielectric layer and the second dielectric layer are made of the same material and have the same thickness.

4. The semiconductor device according to claim 3, wherein: The insulating structure further includes a core structure, wherein the core structure is located in the first trench and isolated from the first trench by the first dielectric layer; The gate structure further includes a third dielectric layer covering the sidewalls of the second trench and having a thickness less than that of the second dielectric layer, and a T-shaped gate electrode located in the second trench and isolated from the second trench by the second dielectric layer and the third dielectric layer; The core structure and the T-shaped gate electrode are made of the same material.

5. The semiconductor device according to claim 4, wherein: The second device structure further includes: a protective layer, located on the surface of the second region; a conductive plug penetrating through the protective layer and connected to a corresponding area on the surface of the second area; The wiring layer is located on the surface of the protection layer and includes wiring connected to the conductive plug.

6. A method for manufacturing a semiconductor device, comprising: Providing a semiconductor layer, the semiconductor layer comprising a first region and a second region; forming a first device structure in the first region and on a surface of the first region; forming a second device structure in the second region and on a surface of the second region; The first device structure is a structure of a device manufactured using a BCD process technology, and the second device structure is a structure of a trench power device with a T-type gate.

7. The method according to claim 6, wherein: The first device structure is a structure of multiple devices manufactured by BCD process technology. The manufacturing method also includes: forming a first trench located between the first region and the second region and forming a first trench located between two adjacent devices among the multiple devices in the first region, and filling the first trench to form an insulating structure located in the first trench.

8. The method according to claim 7, wherein: The second device structure includes a gate structure, the gate structure includes a second trench, and the formation process of the first trench and the second trench includes: etching the first region and the second region using the same mask; The insulating structure includes a first dielectric layer covering the sidewalls and bottom surface of the first trench, and the gate structure also includes a second dielectric layer. The formation process of the first dielectric layer and the second dielectric layer includes: forming dielectric layers on the sidewalls and bottom surfaces of the first trench and the second trench at the same time; The forming process of the second dielectric layer further includes: removing a portion of the dielectric layer at the opening of the second groove to obtain the second dielectric layer.

9. The method according to claim 8, wherein: Removing a portion of the dielectric layer at the opening of the second trench includes: Simultaneously filling the first trench and the second trench in which the dielectric layer is formed, so as to form a first sacrificial structure in the first trench and a second sacrificial structure in the second trench; The portion of the dielectric layer at the opening of the second trench is removed.

10. The manufacturing method according to claim 9, further comprising: The first sacrificial structure and the second sacrificial structure are removed simultaneously, and a third dielectric layer is formed on the sidewall of the second groove notch after the dielectric layer is removed, wherein the thickness of the third dielectric layer is smaller than that of the second dielectric layer; as well as The first trench and the second trench are simultaneously filled with a conductive material to form a core structure in the first trench where the first dielectric layer is formed, and a T-shaped gate electrode is formed in the second trench where the second dielectric layer and the third dielectric layer are formed.

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