Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel. The array substrate comprises a substrate; the driving circuit layer is arranged on the substrate, and the driving circuit layer comprises at least two signal layers; insulating layers are arranged among different signal layers; the insulating layer is provided with via holes, and different signal layers are electrically connected through the via holes. The protection layer is arranged on the side, away from the substrate, of the driving circuit layer, and the protection layer at least covers part of the signal layer in the via hole. According to the array substrate, the protection layer at least covers part of the signal layer in the via hole, in the subsequent process of the array substrate, the signal layer on the side, away from the substrate, of the insulating layer is prevented from being affected by the manufacturing process, and therefore the reliability of the signal line of the signal layer can be improved, and the reliability of the array substrate is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of display, and in particular to an array substrate and a display panel. Background Art

[0002] Micro Light Emitting Diode (Micro-LED / Mini-LED) display technology has become one of the hot spots in the development of future display technology because of its characteristics such as independent control of the picture, independent light control, high brightness, low power consumption, ultra-high resolution and high color.

[0003] Current Micro-LED / Mini-LED display panels are provided with a thick copper layer for forming a solder pad. The Micro-LED / Mini-LED is connected to a driving circuit via the solder pad to realize display of the display panel. Summary of the invention

[0004] The invention provides an array substrate and a display panel to improve the reliability of the array substrate.

[0005] In a first aspect, an embodiment of the present invention provides an array substrate, including:

[0006] substrate;

[0007] A driving circuit layer is arranged on the substrate, the driving circuit layer includes at least two signal layers; an insulating layer is arranged between different signal layers; a via hole is arranged on the insulating layer, and different signal layers are electrically connected through the via hole;

[0008] A protection layer is provided on a side of the driving circuit layer away from the substrate, and the protection layer at least covers a portion of the signal layer in the via hole.

[0009] Optionally, the protection layer includes a first inorganic layer, and the first inorganic layer at least covers a portion of the signal layer in the via hole.

[0010] Optionally, the protective layer further includes a first organic layer; the first organic layer and the first inorganic layer are stacked;

[0011] Preferably, the first organic layer is arranged on a side of the first inorganic layer away from the substrate; in the via hole, the first organic layer at least covers a portion of the first inorganic layer.

[0012] Optionally, the protection layer includes a metal layer, and the metal layer at least covers a portion of the signal layer in the via hole.

[0013] Optionally, the array substrate further includes a pad layer, which is disposed on a side of the driving circuit layer away from the substrate, the pad layer includes a protection portion and at least one pad, the pad is electrically connected to the signal layer, and the protection portion is multiplexed as the protection layer.

[0014] Optionally, the driving circuit layer further includes a second organic layer, which is disposed between the signal layer and the protection portion, and covers at least a portion of the signal layer in the via hole; in the via hole, the protection portion covers at least a portion of the second organic layer.

[0015] Optionally, the array substrate further includes a display area and a non-display area, the non-display area is at least arranged on one side of the display area; the signal layer and the insulating layer extend from the display area to the non-display area; the via hole and the protective layer are arranged in the non-display area;

[0016] Preferably, the insulating layer is a second inorganic layer.

[0017] Optionally, the array substrate also includes side routing and a circuit layer; the side routing is arranged on the side of the substrate, the circuit layer is arranged on the side of the substrate away from the driving circuit layer, one end of the side routing is connected to the signal layer; and the other end is connected to the circuit layer.

[0018] Optionally, the width of the side routing is greater than the diameter of the via hole.

[0019] In a second aspect, an embodiment of the present invention further provides a display panel, comprising the array substrate described in the first aspect.

[0020] According to the technical solution of the embodiment of the present invention, at least two signal layers in the driving circuit layer of the array substrate are electrically connected through vias on the insulating layer, and a protective layer is provided to cover at least a portion of the signal layer in the vias. In the subsequent process of the array substrate, the manufacturing process is prevented from affecting the signal layer on the side of the insulating layer away from the substrate, thereby improving the reliability of the signal line of the signal layer, thereby improving the reliability of the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic structural diagram of an array substrate provided by an embodiment of the present invention;

[0022] Figure 2 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0023] Figure 3 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0024] Figure 4A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0025] Figure 5 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0026] Figure 6 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0027] Figure 7 A schematic structural diagram of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0029] In the related art, the Micro-LED / Mini-LED display panel includes a thick copper layer and a driving circuit layer. The thick copper layer is used to form a pad, and the driving circuit layer is used to form a pixel circuit. The pixel circuit is connected to the electrode of the Micro-LED / Mini-LED through the pad to provide a driving signal for the Micro-LED / Mini-LED. The driving circuit layer includes multiple conductive layers. In the process of manufacturing the Micro-LED / Mini-LED display panel, different conductive layers are electrically connected through vias on the insulating layer. After the different conductive layers are electrically connected, the thick copper layer can be patterned by an etching process to form a pad. At this time, it is easy to cause the insulating layer between the thick copper layer and the driving circuit layer to explode at the via, which can easily cause the conductive layer to be etched and the circuit to break.

[0030] In view of the above technical problems, an embodiment of the present invention provides an array substrate. Figure 1 FIG. 1 is a schematic diagram of the structure of an array substrate provided by an embodiment of the present invention. Figure 1 As shown, the array substrate includes:

[0031] Substrate 110;

[0032] The driving circuit layer 120 is disposed on the substrate 110. The driving circuit layer 120 includes at least two signal layers 121. An insulating layer 122 is disposed between different signal layers 121. A via A is disposed on the insulating layer 122. Different signal layers 121 are electrically connected through the via A.

[0033] The protection layer 130 is disposed on a side of the driving circuit layer 120 away from the substrate 110 . The protection layer 130 at least covers a portion of the signal layer 121 in the via A.

[0034] Specifically, the substrate 110 is used to carry the driving circuit layer 120. Exemplarily, the material of the substrate 110 can be glass or polyimide (PI). The driving circuit layer 120 includes at least two signal layers 121 and an insulating layer 122 between the signal layers 121, and can also include an active layer, a conductive layer and an interlayer insulating layer. The active layer, the conductive layer and the interlayer insulating layer can be used to form transistors, capacitors and connecting lines in the pixel driving circuit. The signal layer 121 can be used to form a signal line, and the signal line can provide a driving signal for the pixel driving circuit. Exemplarily, the signal line on the signal layer 121 extends from the display area 101 to the non-display area 102, and is connected to the driving chip to receive the driving signal provided by the driving chip. The signal line of the signal layer 121 can include a first power signal line, a second power signal line and a data signal line, etc.

[0035] A via A is provided on the insulating layer 122 between the signal layers 121, and the signal layers 121 on both sides of the insulating layer 122 are electrically connected through the via A. At this time, the signal layer 121 on the side of the insulating layer 122 away from the substrate 110 covers the via A and contacts the signal layer 121 on the side of the insulating layer 122 close to the substrate 110 to achieve electrical connection. At the same time, the protective layer 130 at least covers a portion of the signal layer 121 in the via A. Figure 1 exemplarily shows that the protection layer 130 covers the entire signal layer 121 in the via A. In the subsequent processes of the array substrate, the manufacturing process is prevented from affecting the signal layer 121 on the side of the insulating layer 122 away from the substrate 110, thereby improving the reliability of the signal line of the signal layer 121, thereby improving the reliability of the array substrate.

[0036] For example, Figure 2 FIG. 1 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present invention. Figure 2As shown, the array substrate includes a display area 101 and a non-display area 102, and the non-display area 102 is arranged on one side of the display area 101. The array substrate also includes a pad layer 140, and the pad layer 140 is arranged on the side away from the driving circuit layer 120. In the display area 101, the pad layer 140 includes a pad 141. The signal layer 121 includes two layers, the signal layer 121 on the side of the insulating layer 122 close to the substrate 110 is used as the first signal layer 1211, and the signal layer 121 on the side of the insulating layer 122 away from the substrate 110 is used as the second signal layer 1212. In the non-display area 102, the first signal layer 1211 and the second signal layer 1212 are electrically connected through the via A on the insulating layer 122. At the same time, the protective layer 130 at least covers part of the second signal layer 1212 in the via A. In addition, there is an interlayer insulating layer between the second signal layer 1212 and the pad layer 140, and the interlayer insulating layer can be an organic insulating layer. In the display area 101, a through hole ( Figure 2 (not shown in the figure), the pad 141 is electrically connected to the signal layer 121 through a through hole to realize the electrical connection between the pixel driving circuit and the pad 141. When the pad layer 140 is patterned to form the pad 141, the patterning process includes an etching process, such as a wet etching process and a dry etching process. During the etching process, the protective layer 130 can protect the second signal layer 1212 from being affected by the etching process, thereby reducing the risk of the signal line of the second signal layer 1212 breaking at the via A, improving the reliability of the signal line of the second signal layer 1212, and further improving the reliability of the array substrate. For example, during the etching process, the etching liquid can easily blow up the interlayer insulating layer between the second signal layer 1212 and the pad layer 140. By providing the protective layer 130, the second signal layer 1212 can be protected from being affected by the etching liquid when the interlayer insulating layer between the second signal layer 1212 and the pad layer 140 blows up, thereby reducing the risk of the signal line of the second signal layer 1212 breaking at the via A.

[0037] According to the technical solution of the present embodiment, at least two signal layers in the driving circuit layer of the array substrate are electrically connected through vias on the insulating layer, and a protective layer is provided to cover at least a portion of the signal layer in the vias. In the subsequent processes of the array substrate, the manufacturing process is prevented from affecting the signal layer on the side of the insulating layer away from the substrate, thereby improving the reliability of the signal line of the signal layer, and further improving the reliability of the array substrate.

[0038] Continue to refer Figure 1 and Figure 2 The protection layer 130 includes a first inorganic layer 131 , and the first inorganic layer 131 at least covers a portion of the signal layer 121 in the via hole A.

[0039] Specifically, the protective layer 130 may include a first inorganic layer 131, and the first inorganic layer 131 has good bonding with the signal layer 121 on the side of the insulating layer 122 away from the substrate 110. When the first inorganic layer 131 covers at least a portion of the signal layer 121 in the via A, the probability of the first inorganic layer 131 exploding can be reduced in the etching process after the first inorganic layer 131 is formed, thereby reducing the probability of the signal layer 121 on the side of the insulating layer 122 away from the substrate 110 being affected by the etching process, improving the reliability of the signal line of the signal layer 121, and further improving the reliability of the array substrate.

[0040] It should be noted that when the protective layer 130 includes only the first inorganic layer 131, the thickness of the first inorganic layer 131 is relatively thick to ensure the protection reliability of the protective layer 130. For example, in the etching process, when the etching rate is constant, the thickness of the first inorganic layer 130 can be set to be greater than or equal to 450 nanometers.

[0041] Figure 3 FIG. 1 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present invention. Figure 3 As shown, the protection layer 130 further includes a first organic layer 132 ; the first organic layer 132 and the first inorganic layer 131 are stacked.

[0042] Specifically, the first organic layer 132 may be a film layer additionally provided in a conventional array substrate. Alternatively, when the array substrate further includes a pad layer for forming a pad, the first organic layer 132 may be an insulating layer between the pad layer and the signal layer 121. When the first organic layer 132 and the first inorganic layer 131 are stacked, the first inorganic layer 131 and the first organic layer 132 may simultaneously protect the signal layer 121 on the side of the insulating layer 122 away from the substrate 110 from being affected by the manufacturing process, thereby reducing the risk of breaking of the signal line of the signal layer 121 on the side of the insulating layer 122 away from the substrate 110, and improving the reliability of the array substrate.

[0043] For example, Figure 3 exemplarily shows that the first organic layer 132 is disposed on the side of the first inorganic layer 131 away from the substrate 110; in the via A, the first organic layer 132 at least covers a portion of the first inorganic layer 131. Figure 3 It is exemplarily shown that the first organic layer 132 can completely cover the first inorganic layer 131. At this time, the first inorganic layer 131 has good bonding with the signal layer 121 on the side of the insulating layer 122 away from the substrate 110. When the first organic layer 132 is blown up, the signal layer 121 on the side of the insulating layer 122 away from the substrate 110 can be protected from being affected by the manufacturing process, thereby reducing the risk of breaking the signal line of the signal layer 121 on the side of the insulating layer 122 away from the substrate 110 and improving the reliability of the array substrate.

[0044] In other embodiments, the first inorganic layer 131 may be arranged on the side of the first organic layer 132 away from the substrate 110. In the via A, the first inorganic layer 131 at least covers a portion of the first organic layer 132. Optionally, the first inorganic layer 131 may completely cover the first organic layer 132. In this case, the first inorganic layer 131 may reduce the probability of the first organic layer 132 being blown up, thereby reducing the probability of the signal layer 121 on the side of the insulating layer 122 away from the substrate 110 being affected by the manufacturing process, reducing the risk of breaking the signal line of the signal layer 121 on the side of the insulating layer 122 away from the substrate 110, and improving the reliability of the array substrate.

[0045] Figure 4 FIG. 1 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present invention. Figure 4 As shown, the protection layer 130 includes a metal layer 133 , and the metal layer 133 at least covers a portion of the signal layer 121 in the via A.

[0046] Specifically, Figure 4 exemplarily shows that the metal layer 133 completely covers the signal layer 121 in the via A. By setting the metal layer 133 to cover the signal layer 121, the probability that the signal layer 121 on the side of the insulating layer 122 away from the substrate 110 is affected by the manufacturing process can be reduced in the subsequent manufacturing process, the risk of breaking the signal line of the signal layer 121 on the side of the insulating layer 122 away from the substrate 110 is reduced, and the reliability of the array substrate is improved.

[0047] Figure 5 FIG. 1 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present invention. Figure 5 As shown, the array substrate also includes a pad layer 140, which is arranged on the side of the driving circuit layer 120 away from the substrate 110. The pad layer 140 includes a protection portion 142 and at least one pad 141, the pad 141 is electrically connected to the signal layer 121, and the protection portion 142 is reused as the protection layer 130.

[0048] Specifically, when the display panel is a Micro-LED / Mini-LED display panel, the array substrate further includes a pad layer 140. The array substrate includes a display area 101 and a non-display area 102, and the non-display area 102 is arranged on one side of the display area 101. At least one pad 141 is arranged in the display area 101, and is electrically connected to the driving circuit layer 120, and is electrically connected to the pin of the Micro-LED / Mini-LED in the display panel to provide a driving signal for the Micro-LED / Mini-LED. The protection portion 142 is arranged in the non-display area 102, and is reused as a protection layer 130, covering the signal layer 121 in the via A, which can reduce the risk of fracture of the signal layer 121 on the side of the insulating layer 122 away from the substrate 110, and avoid the additional provision of the protection layer 130, which is conducive to simplifying the manufacturing process of the array substrate. Among them, the material of the pad layer 140 can be copper, and the protection layer 130 is a metal layer at this time, that is, the pad layer 140 can be reused as a metal layer 133.

[0049] Exemplarily, when the pad layer 140 is patterned to form the pad 141 and the protection portion 142, a photoresist may be firstly coated on the side of the pad layer 140 away from the substrate 110, and then the photoresist is patterned by an exposure process, and the photoresist at the corresponding positions of the pad 141 and the protection portion 142 is retained. Then, the pad layer 140 is patterned by an etching process, so that the pad layer 140 at the corresponding positions of the pad 141 and the protection portion 142 is retained to form the pad 141 and the protection portion 142, and finally the photoresist is removed.

[0050] Continue to refer Figure 5 The driving circuit layer also includes a second organic layer 123, which is arranged between the signal layer 121 and the protection portion 142, and the second organic layer 123 at least covers a portion of the signal layer 121 in the via A; in the via A, the protection portion 142 at least covers a portion of the second organic layer 123.

[0051] Specifically, the second organic layer 123 serves as an insulating layer between the pad layer 140 and the signal layer 121, and is used to achieve insulation between the pad layer 140 and the signal layer 121. On the basis of ensuring insulation between the pad layer 140 and the signal layer 121, the thickness of the second organic layer 123 can be set relatively large to ensure that the vertical distance between the pad layer 140 and the signal layer 121 is relatively large. Therefore, Micro-LED / Mini-LED can be set on the pad layer 140 to avoid short circuit between the pad layer 140 and the signal layer 121 when the pad 141 is electrically connected to the pin of the Micro-LED / Mini-LED. At the same time, compared with the use of an inorganic layer as an insulating layer between the pad layer 140 and the signal layer 121, the influence of the pad layer 140 on the insulating layer when the pad 141 is formed by an etching process is reduced, thereby avoiding the etching process of the pad layer 140 from affecting the signal layer 121, and ensuring the reliability of the array substrate. The second organic layer 123 may extend from the display area 101 to the non-display area 102, and cover the signal layer 121 on the side of the insulating layer 122 away from the substrate 110 at the via hole A, so as to protect the signal layer 121 on the side of the insulating layer 122 away from the substrate 110 in the subsequent process, and reduce the influence of the manufacturing process on the signal layer 121 on the side of the insulating layer 122 away from the substrate 110. When the second organic layer 123 covers the signal layer 121 in the via hole A, the thickness of the second organic layer 123 in the via hole A is relatively small. When the subsequent process includes an etching process, the second organic layer 123 is prone to explosion. By providing the protection portion 142 to at least partially cover the second organic layer 123, the protection portion 142 can further protect the signal layer 121 on the side of the insulating layer 122 away from the substrate 110 when the second organic layer 123 explodes, thereby reducing the probability that the signal layer 121 on the side of the insulating layer 122 away from the substrate 110 is affected by the manufacturing process, reducing the risk of breaking the signal line of the signal layer 121 on the side of the insulating layer 122 away from the substrate 110, and improving the reliability of the array substrate.

[0052] On the basis of the above technical solutions, the array substrate further includes a display area and a non-display area, the non-display area is arranged at least on one side of the display area; the signal layer and the insulating layer extend from the display area to the non-display area; the vias and the protective layer are arranged in the non-display area;

[0053] Specifically, the driving circuit layer includes an active layer, a conductive layer and an interlayer insulating layer, which are used to form a pixel driving circuit. Exemplarily, the pixel driving circuit includes a transistor and a capacitor; the driving circuit layer may include three conductive layers and an interlayer insulating layer between different conductive layers. The first conductive layer can be used to form the gate of the transistor and the first plate of the capacitor, the second conductive layer can be used to form the second plate of the capacitor, and the third conductive layer can be used to form the source, drain and connecting line of the transistor. At least two signal layers may include a fourth conductive layer and a fifth conductive layer, which are arranged on the side of the third conductive layer away from the substrate, respectively serving as the first signal layer and the second signal layer. The first signal layer and the second signal layer may include a plurality of signal lines for transmitting different driving signals. Exemplarily, the signal line may include a first power signal line, a second power signal line and a data signal line. Different signal lines may be respectively arranged in the first signal layer and the second signal layer, which is conducive to simplifying the arrangement of the signal lines when the number of signal lines is relatively large. Alternatively, different signal lines may be arranged in the same signal layer, and another signal layer is used to set jumpers of signal lines of different directions at overlapping positions to avoid short circuits of signal lines of different directions. Exemplarily, the first signal layer is used to set signal lines with different directions, and the second signal layer is used to set jumpers at overlapping positions of signal lines with different directions. The signal layer and the insulating layer extend from the display area to the non-display area, and in the non-display area, vias are provided on the insulating layer, and at least two layers of signal layers are electrically connected through the vias, so that the signal lines of different signal layers can be electrically connected and the arrangement of different signal lines can be realized. When the vias are provided in the non-display area, the protective layer is provided in the non-display area to at least cover part of the vias to protect the signal layer in the vias. Thereby, in the subsequent processes of the array substrate, the influence of the manufacturing process on the signal layer in the vias can be reduced, the reliability of the signal lines of the signal layer can be improved, and the reliability of the array substrate can be improved.

[0054] Optionally, the insulating layer is a second inorganic layer.

[0055] Specifically, when the insulating layer is the second inorganic layer, the adhesion between the insulating layer and the signal layer can be improved while ensuring the insulation between the signal layers.

[0056] Figure 6 FIG. 1 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present invention. Figure 6 As shown, the array substrate also includes a side routing 150 and a circuit layer 160; the side routing 150 is arranged on the side of the substrate 110, and the circuit layer 160 is arranged on the side of the substrate 110 away from the driving circuit layer 120, and one end of the side routing 150 is connected to the signal layer 121; and the other end is connected to the circuit layer 160.

[0057] Specifically, the side wiring 150 can be arranged corresponding to the signal line of the signal layer 121, and one end is connected to the signal line of the signal layer 121, and the other end is connected to the circuit layer 160, so that the circuit layer 160 is electrically connected to the signal line of the signal layer 121 through the side wiring 150. When the driving circuit layer 120 is arranged on the front side of the substrate 110, the circuit layer 160 is arranged on the back side of the substrate 110. And the other end of the circuit layer 160 can be connected to the driving chip to provide a driving signal for the signal line of the signal layer 121. By setting the side wiring 150 and the circuit layer 160, the driving chip can be arranged on the back side of the substrate 110, which is conducive to reducing the frame of the array substrate. The side wiring 150 can be formed by a laser cutting process. After the pad 141 is formed on the pad layer 140, a side wiring layer can be formed in the non-display area 102 and connected to the signal line of the signal layer 121, and then the side wiring layer is cut by a laser cutting process to form the side wiring 150.

[0058] Based on the above technical solution, the width of the side trace 150 is greater than the diameter of the via A.

[0059] Specifically, the signal layer 121 on the side of the insulating layer 122 away from the substrate 110 can extend to the side of the substrate 110 as a side wiring 150. At this time, the via A can be set at a position close to the side of the non-display area 102 to realize the electrical connection of the signal lines in different signal layers 121, and then realize the electrical connection of the side wiring 150 with the signal layer 121 on the side of the insulating layer 122 close to the substrate 110. At the same time, the width of the side wiring 150 can be set to be greater than the diameter of the via A to ensure the reliability of the electrical connection between the side wiring 150 and the signal layer 121 on the side of the insulating layer 122 close to the substrate 110. At this time, since the line width of the signal layer 121 on the side of the insulating layer 122 away from the substrate 110 is relatively small, the film layer covering the via A is easy to explode due to the poor flatness. By setting the protective layer 130, the subsequent manufacturing process can reduce the impact of the signal layer 121 in the via A. Exemplarily, when the array substrate includes a pad layer 140, the driving circuit layer 120 may include an organic insulating layer arranged between the signal layer 121 and the pad layer 140. Since the flatness at the via A is relatively poor, the organic insulating layer between the signal layer 121 and the pad layer 140 is easily blown up during the etching process of the pad layer 140. At this time, the protective layer 130 at least covers a portion of the insulating organic layer, reducing the probability of the insulating organic layer being blown up, thereby reducing the influence of the etching process of the pad layer 140 on the signal layer 121 in the via A, reducing the risk of the signal line of the signal layer 121 being short-circuited at the via A, and improving the reliability of the array substrate.

[0060] An embodiment of the present invention further provides a display panel. Figure 7 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention. Figure 7 As shown, the display panel 20 includes an array substrate 21 provided by any embodiment of the present invention.

[0061] Specifically, the array substrate 21 is an array substrate provided by any embodiment of the present invention. When the display panel 20 includes the array substrate provided by any embodiment of the present invention, it has the same beneficial effects as the array substrate provided by any embodiment of the present invention, which will not be described in detail here. The display panel 20 can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, etc.

[0062] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. An array substrate, characterized in that: include: substrate; A driving circuit layer is arranged on the substrate, and the driving circuit layer includes at least two signal layers; an insulating layer is arranged between different signal layers; The insulating layer is provided with vias, and different signal layers are electrically connected through the vias; A protection layer is provided on a side of the driving circuit layer away from the substrate, and the protection layer at least covers a portion of the signal layer in the via hole.

2. The array substrate according to claim 1, characterized in that: The protection layer includes a first inorganic layer, and the first inorganic layer at least covers a portion of the signal layer in the via hole.

3. The array substrate according to claim 2, characterized in that: The protective layer further comprises a first organic layer; the first organic layer and the first inorganic layer are stacked; Preferably, the first organic layer is arranged on a side of the first inorganic layer away from the substrate; in the via hole, the first organic layer at least covers a portion of the first inorganic layer.

4. The array substrate according to claim 1, characterized in that: The protection layer includes a metal layer, and the metal layer at least covers a portion of the signal layer in the via hole.

5. The array substrate according to claim 1, characterized in that: It also includes a pad layer, which is arranged on a side of the driving circuit layer away from the substrate. The pad layer includes a protection portion and at least one pad, the pad is electrically connected to the signal layer, and the protection portion is multiplexed as the protection layer.

6. The array substrate according to claim 5, characterized in that: The driving circuit layer also includes a second organic layer, which is arranged between the signal layer and the protection part, and the second organic layer at least partially covers the signal layer in the via hole; in the via hole, the protection part at least partially covers the second organic layer.

7. The array substrate according to any one of claims 1 to 6, characterized in that: It also includes a display area and a non-display area, wherein the non-display area is at least arranged on one side of the display area; the signal layer and the insulating layer extend from the display area to the non-display area; the via hole and the protective layer are arranged in the non-display area; Preferably, the insulating layer is a second inorganic layer.

8. The array substrate according to claim 1, characterized in that: It also includes side routing and a circuit layer; the side routing is arranged on the side of the substrate, the circuit layer is arranged on the side of the substrate away from the driving circuit layer, one end of the side routing is connected to the signal layer; and the other end is connected to the circuit layer.

9. The array substrate according to claim 8, characterized in that: The width of the side routing is greater than the diameter of the via hole.

10. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 9.

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