Semiconductor package

Abstract

A semiconductor package according to an embodiment includes a photosensitive insulating layer, a first circuit pattern layer embedded in the photosensitive insulating layer, and a lower oxide layer disposed at an interface between the photosensitive insulating layer and the first circuit pattern layer.

Description

Technical Field

[0001] Embodiments relate to a circuit board, and more particularly, to a circuit board including a cavity and a semiconductor package including the circuit board. Background Art

[0002] High-performance electric / electronic products are being developed, and therefore, technologies for attaching a greater number of packages to a substrate of limited size are being proposed and studied.

[0003] A typical semiconductor package has a structure in which multiple chips are arranged. In addition, the size of semiconductor packages is increasing due to the high specifications of products to which semiconductor packages are applied and the adoption of multiple chips such as HBM (High Bandwidth Memory). Therefore, the semiconductor package includes an interposer for connecting multiple chips.

[0004] In addition, semiconductor packages applied to products providing the Internet of Things (IoT), autonomous vehicles, and high-performance servers, etc., require high performance and high reliability in line with the trend of high integration. Here, high performance may include multiple conditions such as high-speed transmission of signals, high integration of semiconductor packages, and high allowable current of transmittable signals.

[0005] At this time, the semiconductor package uses a substrate including a cavity to achieve miniaturization and integration, thereby reducing the thickness of the substrate and thus reducing the thickness of the semiconductor package.

[0006] (Patent Document 1) KR 10-2021-0024840A Summary of the invention

[0007] [Technical issues]

[0008] Embodiments provide a circuit board having a novel structure and a semiconductor package including the same.

[0009] In addition, embodiments provide a circuit board including a cavity and a semiconductor package including the circuit board.

[0010] In addition, the embodiment provides a circuit board capable of improving circuit integration and a semiconductor package including the same.

[0011] In addition, embodiments provide a circuit board having improved adhesion between insulating layers including different insulating materials and a semiconductor package including the same.

[0012] In addition, embodiments provide a circuit board having improved adhesion between a plurality of adjacent layers and a semiconductor package including the same.

[0013] In addition, the embodiment provides a circuit board capable of solving a reliability problem occurring due to exposure of glass fibers of a prepreg and a semiconductor package including the same.

[0014] The technical problems to be solved by the proposed embodiments are not limited to the above-mentioned technical problems, and those skilled in the art to which the proposed embodiments belong can clearly understand other technical problems not mentioned from the following description.

[0015] [Technical solution]

[0016] A semiconductor package according to an embodiment includes a photosensitive insulating layer, a first circuit pattern layer embedded in the photosensitive insulating layer, and a lower oxide layer disposed at an interface between the photosensitive insulating layer and the first circuit pattern layer.

[0017] In addition, the lower oxide layer is also disposed on the lower surface of the photosensitive insulating layer that does not vertically overlap with the first circuit pattern layer.

[0018] In addition, the semiconductor package further includes an additional insulating layer disposed on the lower surface of the photosensitive insulating layer, wherein the lower oxide layer disposed on the lower surface of the photosensitive insulating layer contacts the upper surface of the additional insulating layer.

[0019] In addition, the additional insulating layer includes an insulating material different from the insulating material of the photosensitive insulating layer.

[0020] Furthermore, the additional insulating layer comprises reinforcing fibers.

[0021] Additionally, the additional insulating layer is a thermosetting insulating layer.

[0022] In addition, the semiconductor package further includes a through electrode passing through the photosensitive insulating layer, and a second circuit pattern layer disposed on the photosensitive insulating layer, wherein the lower oxide layer includes an opening region vertically overlapping with a lower surface of the through electrode.

[0023] In addition, the semiconductor package further includes an upper oxide layer disposed on the photosensitive insulating layer.

[0024] Additionally, at least one of the upper oxide layer and the lower oxide layer includes aluminum oxide.

[0025] In addition, the semiconductor package further includes a protection layer disposed on the upper oxide layer, wherein the upper oxide layer includes a first portion disposed at an interface between the photosensitive insulating layer and the protection layer, and a second portion disposed at an interface between the second circuit pattern layer and the protection layer.

[0026] In addition, the protection layer includes an opening vertically overlapping the second circuit pattern layer, and the second portion of the upper oxide layer includes an opening region vertically overlapping the opening of the protection layer.

[0027] In addition, the semiconductor package further includes a protection layer disposed on the upper oxide layer, the oxide layer including a first portion disposed at an interface between the photosensitive insulating layer and the protection layer, and a second portion disposed between the photosensitive insulating layer and the second circuit pattern layer.

[0028] In addition, the upper oxide layer further includes a third portion disposed between an inner wall of the through hole passing through the photosensitive insulating layer and the through electrode.

[0029] In addition, the photosensitive insulating layer includes at least one cavity passing through the upper surface and the lower surface of the photosensitive insulating layer, and the upper oxide layer further includes a fourth portion disposed on an inner wall of the cavity of the photosensitive insulating layer.

[0030] In addition, the upper oxide layer or the lower oxide layer further includes a fifth portion disposed on the upper surface of the additional insulating layer corresponding to the lower surface of the cavity.

[0031] In addition, the first circuit pattern layer includes a pad vertically overlapping the cavity, and a fifth portion of the upper oxide layer or the lower oxide layer includes an opening area vertically overlapping an upper surface of the pad.

[0032] In addition, the first circuit pattern layer includes a circuit pattern that does not vertically overlap with the cavity and is covered by the photosensitive insulating layer, and a trace directly connecting the circuit pattern and the pad, the trace includes a first portion that is in direct contact with the pad and vertically overlaps with the cavity, and a second portion that is covered by the photosensitive insulating layer and in direct contact with the circuit pattern, and the upper oxide layer or the lower oxide layer also includes a sixth portion arranged on the upper surface and side surface of the second portion of the trace.

[0033] In addition, the semiconductor package further includes a connection member disposed on the pad.

[0034] In addition, the semiconductor package further includes a semiconductor device disposed on the connection member.

[0035] In addition, the semiconductor package further includes a molding layer which is disposed in the cavity and molds the semiconductor device.

[0036] In addition, the upper oxide layer includes a portion disposed on an inner wall of the cavity and in contact with the mold layer.

[0037] [Beneficial Effects]

[0038] The circuit board of the embodiment can improve adhesion between a plurality of layers.

[0039] Specifically, the circuit board of the embodiment includes a first insulating layer and a second insulating layer, the first insulating layer includes a first insulating material, and the second insulating layer is disposed on the first insulating layer and includes a second insulating material different from the first insulating material.

[0040] At this time, the embodiment includes a buffer layer disposed between the first insulating layer and the second insulating layer. The buffer layer can be used as an adhesive layer to improve the adhesion between the first insulating layer and the second insulating layer. The buffer layer can be an oxide layer. For example, the buffer layer can include aluminum oxide.

[0041] Thus, embodiments may improve adhesion between the first insulating layer and the second insulating layer, thereby improving physical reliability and / or electrical reliability of a circuit board and a semiconductor package including the circuit board.

[0042] In addition, the first insulating layer may include a thermosetting resin, and the second insulating layer may include a photocurable resin. The embodiment may improve the physical reliability and electrical reliability of the circuit pattern layer and the through electrode disposed on the second insulating layer by the second insulating layer including the photocurable resin. In addition, the circuit pattern layer and the through electrode disposed on the second insulating layer may be miniaturized by the second insulating layer including the photocurable resin.

[0043] At this time, the photocurable resin has a relatively high content of ceramic particles and a relatively high curing shrinkage, and therefore, there may be a problem in that the adhesion between the photocurable resin and other layers is reduced.

[0044] In contrast, the embodiment includes a buffer layer disposed on the surface of the photocurable resin. Therefore, even if the second insulating layer includes the photocurable resin, the embodiment can miniaturize the circuit pattern layer and the through-electrode without affecting the adhesiveness.

[0045] Therefore, embodiments may improve the circuit integration of a circuit board and further improve the physical reliability and / or electrical reliability of the circuit board.

[0046] At the same time, the buffer layer of the embodiment is also disposed between the second insulating layer and the circuit pattern layer. Therefore, the embodiment can improve the adhesion between the second insulating layer and the circuit pattern layer.

[0047] In addition, the buffer layer of the embodiment is also disposed between the second insulating layer and the through electrode. Therefore, the embodiment can improve the adhesion between the second insulating layer and the through electrode.

[0048] In addition, the buffer layer of the embodiment is also disposed between the second insulating layer and the first protective layer. Therefore, the embodiment can improve the adhesion between the second insulating layer and the first protective layer.

[0049] In addition, the buffer layer of the embodiment is also disposed between the circuit pattern layer and the first protective layer. Therefore, the embodiment can improve the adhesion between the circuit pattern layer and the first protective layer.

[0050] The embodiment may improve adhesion between a plurality of layers constituting a circuit board by forming a buffer layer having a structure as described above, and may accordingly improve product reliability.

[0051] At the same time, the second insulating layer includes a cavity. At this time, the buffer layer may also be disposed on the inner wall of the cavity of the second insulating layer. Therefore, the embodiment may omit a de-smear process for removing smear remaining on the inner wall of the cavity. Therefore, the embodiment may simplify the manufacturing process of the circuit board. In addition, the embodiment may prevent the size of the cavity from being enlarged due to the de-smear process by omitting the de-smear process, thereby forming a cavity with an optimal size. Therefore, the embodiment may reduce the volume of the circuit board.

[0052] In addition, the buffer layer may also be disposed on the lower surface of the cavity. In addition, if a desmear process is performed after the cavity is formed, the buffer layer disposed on the lower surface of the cavity may be used as a barrier layer. In addition, the embodiment may prevent the reinforcing fibers included in the first insulating layer from being exposed during the desmear process by the barrier layer. Therefore, the embodiment may further improve product reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1a 2 is a view showing a semiconductor package according to a first embodiment.

[0054] Figure 1b is a view showing a semiconductor package according to a second embodiment.

[0055] Figure 1c is a view showing a semiconductor package according to a third embodiment.

[0056] Figure 1d is a view showing a semiconductor package according to a fourth embodiment.

[0057] Figure 1e 2 is a view showing a semiconductor package according to a fifth embodiment.

[0058] Figure 1f 2 is a view showing a semiconductor package according to a sixth embodiment.

[0059] Figure 2 is a cross-sectional view showing a circuit board according to the first embodiment.

[0060] Figure 3 is a cross-sectional view explaining an arrangement structure of a first buffer layer according to an embodiment.

[0061] Figure 4 is a cross-sectional view explaining an arrangement structure of a second buffer layer according to the first embodiment.

[0062] Figure 5 is a cross-sectional view explaining an arrangement structure of a second buffer layer according to a second embodiment.

[0063] Figure 6 is a view showing a circuit board according to a second embodiment.

[0064] Figure 7a is a sectional view showing a circuit board according to a third embodiment.

[0065] Figure 7b yes Figure 7a A plan view of a circuit board.

[0066] Figure 8 2 is a view showing a semiconductor package of a seventh embodiment.

[0067] Fig. 9 2 is a view showing a semiconductor package of an eighth embodiment.

[0068] Figures 10 to 17 are cross-sectional views for explaining the method of manufacturing the circuit board of the embodiment in order of processes. DETAILED DESCRIPTION

[0069] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0070] However, the spirit and scope of the present disclosure are not limited to a part of the described embodiments, but may be implemented in various other forms, and one or more elements of the embodiments may be selectively combined and rearranged within the spirit and scope of the present disclosure.

[0071] In addition, unless otherwise clearly defined and described, the terms (including technical terms and scientific terms) used in the embodiments of the present disclosure may be interpreted as having the same meaning as that generally understood by a person of ordinary skill in the art to which the present disclosure belongs, and such terms as those defined in commonly used dictionaries may be interpreted as having a meaning consistent with their meaning in the context of the relevant art. In addition, the terms used in the embodiments of the present disclosure are used to describe the embodiments and are not intended to limit the present disclosure.

[0072] In the present specification, a singular form may also include a plural form, and unless otherwise specifically stated in a phrase, when described as "at least one (or more) of A (and), B, and C", at least one of all combinations of A, B, and C may be included. In addition, when describing elements of an embodiment of the present disclosure, terms such as first, second, A, B, (a), and (b) may be used.

[0073] These terms are only used to distinguish an element from other elements, and these terms do not limit the nature, order or sequence of the elements. In addition, when an element is described as being "connected", "coupled" or "in contact with" another element, it may include not only that the element is directly "connected", "coupled" or "in contact with" another element, but also that the element is "connected", "coupled" or "in contact with" another element through other elements between the element and another element.

[0074] In addition, when described as being formed or disposed “on (above)” or “under (below)” each element, “on (above)” or “under (below)” may include not only two elements being directly connected to each other but also one or more other elements being formed or disposed between the two elements. In addition, when expressed as “on (above)” or “under (below)”, not only an upper direction based on one element but also a lower direction may be included.

[0075] [Electronic equipment]

[0076] Before describing the embodiment, an electronic device to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device includes a mainboard (not shown). The mainboard can be physically and / or electrically connected to various components. For example, the mainboard can be connected to the semiconductor package of the embodiment. In addition, various semiconductor devices can be installed in the semiconductor package.

[0077] Semiconductor devices may include active devices and / or passive devices and have various functions. Active devices may be semiconductor devices in the form of integrated circuits (ICs) in which hundreds to millions of devices are integrated into a single chip. Semiconductor devices may be logic chips, memory chips, and the like. Logic chips may be central processing units (CPUs), graphics processing units (GPUs), and the like. For example, a logic chip may be an application processor (AP) semiconductor device including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, or an analog-to-digital converter, an application specific IC (ASIC), and the like, or a chipset including a specific combination of the above-listed items.

[0078] The memory chip may be a stacked memory such as HBM. In addition, the memory chip may include a memory chip such as a volatile memory (eg, DRAM), a nonvolatile memory (eg, ROM), or a flash memory.

[0079] Product groups of semiconductor packages to which the embodiments are applied include CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package on Package), and SIP (System in Package), but are not limited thereto.

[0080] In addition, the electronic device may include a smart phone, a personal digital assistant, a digital camera, a digital still camera, a network system, a computer, a monitor, a tablet computer, a laptop computer, a netbook, a television, a video game console, a smart watch, a car, etc. However, the embodiment is not limited thereto, and may be any other electronic device that processes data in addition to these.

[0081] Hereinafter, a semiconductor package including a circuit board according to an embodiment will be described. The semiconductor package of the embodiment may have various package structures including a circuit board which will be described later.

[0082] Figure 1a 2 is a view showing a semiconductor package according to a first embodiment.

[0083] refer to Figure 1a , the semiconductor package of the first embodiment includes a first substrate 100 .

[0084] The first substrate 100 may represent a package substrate.

[0085] For example, the first substrate 100 may provide a space coupled with at least one external substrate. For example, the first substrate 100 may provide a space coupled with a main board included in an electronic device.

[0086] As described below, the first substrate 100 may include at least one insulating layer, a circuit pattern layer disposed on the at least one insulating layer, a through electrode penetrating the at least one insulating layer, and a protection layer protecting the insulating layer and the circuit pattern layer.

[0087] The first substrate 100 may include a plurality of pads. Here, the plurality of pads may represent a portion of a circuit pattern layer disposed at the outermost layer of the first substrate 100. For example, the pad may represent a portion of a circuit pattern layer disposed at the uppermost side of the first substrate 100. For example, the pad may represent a portion of a circuit pattern layer disposed at the lowermost side of the first substrate 100. In addition, the protective layer may include an opening that exposes a surface (e.g., an upper surface or a lower surface) of the pad.

[0088] Meanwhile, the semiconductor package may include a plurality of connection members.

[0089] For example, the first substrate 100 may include a plurality of pads, and a plurality of connection members may be disposed on the plurality of pads, respectively.

[0090] Specifically, the first substrate 100 may include a plurality of first pads. In addition, the semiconductor package may include a first connection member 110 disposed on the plurality of first pads.

[0091] In addition, the first substrate 100 may include a plurality of second pads. In addition, the semiconductor package may include a second connection member 140 disposed on the plurality of second pads.

[0092] In addition, the first substrate 100 may include a plurality of third pads. In addition, the semiconductor package may include a third connection member 160 disposed on the plurality of third pads.

[0093] At this time, the first pad may be disposed on the upper surface of the first substrate 100. In addition, the second pad and the third pad may be disposed on the lower surface of the first substrate 100.

[0094] Meanwhile, a semiconductor package may include a plurality of semiconductor devices.

[0095] For example, the semiconductor package may include a first semiconductor device 120 disposed on a first connection member 110. At this time, the first pads of the first substrate 100 may be divided into a plurality of groups. In addition, the first connection member 110 may be arranged on each of the first pads in the plurality of groups. In addition, the first semiconductor device 120 may be mounted on each of the first pads in the plurality of groups. Therefore, the first semiconductor devices 120 may be mounted on the upper side of the first substrate 100 at a predetermined interval from each other. At this time, the first semiconductor device 120 may refer to a semiconductor device mounted on the upper side of the first substrate 100. In addition, a plurality of first semiconductor devices may be disposed on the upper side of the first substrate 100 at a predetermined interval from each other.

[0096] In addition, the semiconductor package may include a second semiconductor device 140 disposed under the second connection member 140. Among the semiconductor devices included in the semiconductor package, the second semiconductor device 140 may refer to a semiconductor device mounted on the lower side of the first substrate 100. In addition, a plurality of second semiconductor devices may be disposed on the lower side of the first substrate 100 at predetermined intervals from each other.

[0097] At this time, at least one of the first semiconductor device 120 and the second semiconductor device 140 may include a logic chip. For example, at least one of the first semiconductor device 120 and the second semiconductor device 140 may include an application processor chip. For example, at least one of the first semiconductor device 120 and the second semiconductor device 140 may include an analog-to-digital converter or an ASIC (Application Specific IC). For example, at least one of the first semiconductor device 120 and the second semiconductor device 140 may include a memory chip. The memory chip may be a stacked memory such as HBM. For example, the memory chip may include a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, etc.

[0098] In addition, at least one of the first semiconductor device 120 and the second semiconductor device 140 may include at least one of a driver IC chip, a diode chip, a power IC chip, a touch sensor IC chip, an MLCC (Multilayer Ceramic Capacitor) chip, a BGA (Ball Grid Array) chip, and a chip capacitor.

[0099] In addition, the semiconductor package may include a third connection member 160. The third connection member 160 may be located below the third pad of the first substrate 100. The third connection member 160 may be connected between the first substrate 100 and the main board of the electronic device. The third connection member 160 may have a larger diameter than the first connection member 110 and the second connection member 140. For example, the diameter of the third connection member 160 may be in the range of 10 to 200 times the diameter of at least one of the first connection member 110 and the second connection member 140. For example, the diameter of the third connection member 160 may be in the range of 20 to 180 times the diameter of at least one of the first connection member 110 and the second connection member 140. For example, the diameter of the third connection member 160 may be in the range of 40 to 150 times the diameter of at least one of the first connection member 110 and the second connection member 140. That is, the third connection member 160 is connected to the main board of the electronic device and may have a larger diameter than the other connection members to correspond to the width of the pad portion of the main board. In addition, the first and second connection members 110 and 140 are connected to the semiconductor device and may have a smaller diameter than the third connection member 160 to correspond to terminals of the semiconductor device.

[0100] The semiconductor package may include a molding layer.

[0101] For example, the semiconductor package may include a first mold layer 130 disposed on the first substrate 100. The first mold layer 130 may mold a component disposed on the outermost layer of the first substrate 100. For example, the first mold layer 130 may mold a surface of a protective layer disposed on the uppermost side of the first substrate 100, a surface of a circuit pattern layer, and a surface of an insulating layer. In addition, the first mold layer 130 may mold a first connection member 110 and a first semiconductor device 120 disposed on the first substrate 100. At this time, the semiconductor package may further include an underfill (not shown) surrounding the first connection member 110 and the first semiconductor device 120. In addition, when the semiconductor package includes an underfill, the first mold layer 130 may mold the periphery of the underfill.

[0102] In addition, the semiconductor package may include a second mold layer 170 disposed under the first substrate 100. The second mold layer 170 may mold a surface of a protection layer, a surface of a circuit pattern layer, and a surface of an insulating layer disposed at the lowermost side of the first substrate 100. In addition, the second mold layer 170 may mold a second connection member 140 and a second semiconductor device 140 disposed under the first substrate 100. In addition, the second mold layer 170 may mold a third connection member 160.

[0103] At this time, the second mold layer 170 may expose at least a portion of the lower surface of the second semiconductor device 140. For example, the lower surface of the second mold layer 170 may be positioned not lower than the lower surface of the second semiconductor device 140. For example, the lower surface of the second mold layer 170 may be positioned on the same plane as the lower surface of the second semiconductor device 140.

[0104] In addition, the second mold layer 170 may be positioned not lower than the lower surface of the third connection member 160. For example, the lower surface of the second mold layer 170 may be positioned on the same plane as the lower surface of the third connection member 160 or may be positioned higher than the lower surface of the third connection member 160. Therefore, the lower surface of the third connection member 160 may not be covered by the second mold layer 170. In addition, at least a portion of the third connection member 160 may protrude downward from the second mold layer 170.

[0105] The first mold layer 130 and the second mold layer 170 may be EMC (epoxy mold compound), but are not limited thereto. The first mold layer 130 and the second mold layer 170 may have a low dielectric constant. For example, the dielectric constant (Dk) of the first mold layer 130 and the second mold layer 170 may be 0.2 to 10. For example, the dielectric constant (Dk) of the first mold layer 130 and the second mold layer 170 may be 0.5 to 8. For example, the dielectric constant (Dk) of the first mold layer 130 and the second mold layer 170 may be 0.8 to 5. Therefore, in an embodiment, by making the first mold layer 130 and the second mold layer 170 have a low dielectric constant, the heat dissipation characteristics of the heat generated from the first semiconductor device 120 and the second semiconductor device 140 may be improved. The semiconductor package of the first embodiment may have a double-sided molding structure as described above.

[0106] That is, the semiconductor package of the first embodiment may have a structure in which at least one first semiconductor device 120 and a second semiconductor device 140 are mounted on the upper and lower sides of the first substrate 100 , respectively.

[0107] Figure 1b is a view showing a semiconductor package according to a second embodiment.

[0108] refer to Figure 1b , according to the second embodiment of the semiconductor package and Figure 1a The semiconductor package of the first embodiment is different in that the semiconductor package has a single-sided molding structure.

[0109] For example, the semiconductor package of the second embodiment may include a first substrate 100 , a first connection member 110 , a first semiconductor device 120 , a first mold layer 130 , and a third connection member 160 .

[0110] In addition, the semiconductor package of the second embodiment may have a structure in which a semiconductor device is mounted only on the upper side of the first substrate 100. Therefore, the molding layer of the semiconductor package of the second embodiment may be disposed only on the upper side of the first substrate 100.

[0111] Figure 1c is a view showing a semiconductor package according to a third embodiment.

[0112] refer to Figure 1c , according to the third embodiment of the semiconductor package and Figure 1b The semiconductor package of the second embodiment is different in that the semiconductor package further includes an additional package.

[0113] The semiconductor package of the third embodiment may further include a fourth pad disposed on the upper side of the first substrate 100. That is, the circuit pattern layer is disposed on the upper surface of the first substrate 100. In addition, a portion of the circuit pattern layer may be used as the first pad on which the first semiconductor device 120 is mounted, and another portion may be used as the fourth pad.

[0114] The semiconductor package of the third embodiment may further include a fourth connection member 180 disposed on the fourth pad.

[0115] The upper surface of the fourth connection member 180 may not be covered by the first mold layer 130 .

[0116] The semiconductor package of the third embodiment may include a second substrate 200 disposed on a fourth connection member 180. The second substrate 200 may be a memory substrate, but is not limited thereto.

[0117] The semiconductor package of the third embodiment may include a third semiconductor device 210 mounted on a second substrate 200. The third semiconductor device 210 may be a memory chip, but is not limited thereto.

[0118] In addition, the semiconductor package of the third embodiment may further include a connection member 220 connecting the second substrate 200 and the third semiconductor device 210. That is, Figure 1c The semiconductor package of the third embodiment may have a stacked package structure.

[0119] Figure 1d is a view showing a semiconductor package according to a fourth embodiment.

[0120] refer to Figure 1d , according to the fourth embodiment of the semiconductor package and Figure 1c The semiconductor package of the third embodiment is different in that the first semiconductor device 120 includes a plurality of logic chips, and an additional third substrate 190 is disposed on the first substrate 100 .

[0121] For example, a plurality of logic chips may be disposed on the first substrate 100. For example, a plurality of logic chips of the same type may be disposed on the first substrate 100, or differently, a plurality of logic chips of different types may be disposed.

[0122] At this time, a connection member may be provided on the first substrate 100 to connect the plurality of first semiconductor devices 120. The connection member may represent a third substrate 190.

[0123] The third substrate 190 may be a bridge substrate. The third substrate 190 may include a redistribution layer. The third substrate 190 is disposed on the first substrate 100. In addition, the third substrate 190 may electrically connect a plurality of first semiconductor devices 120 corresponding to a plurality of logic chips. At this time, although the drawings show that the third substrate 190 is embedded in the first substrate 100, the embodiment is not limited thereto. For example, the third substrate 190 may be disposed on the first substrate 100.

[0124] The third substrate 190 may be a silicon bridge substrate. Alternatively, the third substrate 190 may be an organic bridge member including an organic material.

[0125] Figure 1e 2 is a view showing a semiconductor package according to a fifth embodiment.

[0126] refer to Figure 1e , the semiconductor package according to the fifth embodiment is different from the semiconductor packages of the previous embodiments in that a fourth substrate 300 is disposed between the first substrate and the semiconductor device.

[0127] The semiconductor package according to the fifth embodiment may include a fourth substrate 300 disposed on the first substrate 100 .

[0128] To this end, a first connection member 110 connecting the first substrate 100 and the fourth substrate 300 may be disposed on the first substrate 100 .

[0129] In addition, the semiconductor package according to the fifth embodiment may include a fifth connection member 320 disposed on the fourth substrate 300. In addition, the semiconductor package according to the fifth embodiment may include a semiconductor device 320 disposed on the fifth connection member 320. The semiconductor device 320 may be provided in one, or the semiconductor device 320 may be provided in plural.

[0130] Meanwhile, the fourth substrate 300 may be disposed between the first substrate 100 and the semiconductor device 320. The fourth substrate 300 may perform a function of connecting the first substrate 100 and the semiconductor device 320. In addition, the fourth substrate 300 may perform a function of connecting a plurality of semiconductor devices 320.

[0131] At this time, the fourth substrate 300 may also be referred to as an interposer connecting the first substrate 100 and the semiconductor device 320 .

[0132] In one embodiment, the fourth substrate 300 may be an active interposer used as a semiconductor device. When the fourth substrate 300 is used as a semiconductor device, the package of the fifth embodiment may have a structure in which a plurality of logic chips of a vertical stacking structure are mounted on the first substrate 100. In addition, the first logic chip corresponding to the active interposer among the logic chips may perform the function of the corresponding logic chip while performing a signal transmission function between the second logic chip disposed on the upper side thereof and the first substrate 100.

[0133] According to another embodiment, the fourth substrate 300 may be a passive interposer. For example, the fourth substrate 300 may perform a signal relay function between the semiconductor device 320 and the first substrate 100. For example, due to 5G, Internet of Things (IOT), improved image quality, increased communication speed, etc., the number of terminals in the semiconductor device 320 is gradually increasing. That is, the number of terminals provided in the semiconductor device 320 increases, so the width of the terminal or the interval between the plurality of terminals decreases. At this time, the first substrate 100 is connected to the mainboard of the electronic device. Therefore, in order to make the pads provided on the first substrate 100 have a certain width and interval so as to be connected to the semiconductor device 320 and the mainboard respectively, there is a problem that the thickness of the first substrate 100 increases or the layer structure of the first substrate 100 becomes complicated. Therefore, the fourth substrate 300 may be provided between the first substrate 100 and the semiconductor device 320. The fourth substrate 300 may include pads having a micro width and interval corresponding to the terminals of the semiconductor device 320.

[0134] Figure 1f 2 is a view showing a semiconductor package according to a sixth embodiment.

[0135] refer to Figure 1f The semiconductor package according to the sixth embodiment is different from the semiconductor package of the fifth embodiment in that a fifth substrate 330 is additionally provided on the fourth substrate 300 .

[0136] A plurality of semiconductor devices 320 horizontally spaced apart from each other may be disposed on the fourth substrate 300. In addition, the plurality of semiconductor devices 320 may be active devices of different types or the same type. For example, the plurality of semiconductor devices 320 may represent AP chips of different types. In addition, one of the plurality of semiconductor devices 320 may be an AP chip, and another chip may be a memory chip.

[0137] In addition, the semiconductor package of the sixth embodiment further includes a fifth substrate 330. The fifth substrate 330 may be embedded in the fourth substrate 300, but is not limited thereto. For example, the fifth substrate 330 may be disposed on the fourth substrate 300 and may perform a function of connecting the plurality of semiconductor devices 320.

[0138] The fifth substrate 330 may include a redistribution layer. For example, the fifth substrate 330 may be a bridge. The fifth substrate 330 may include a silicon bridge. Alternatively, the fifth substrate 330 may be an organic bridge including an organic material.

[0139] Meanwhile, each of the semiconductor packages of the first to sixth embodiments includes the connection member as described above.

[0140] At this time, the connection member may be a member that electrically connects a plurality of components using at least one bonding method of wire bonding, solder bonding, and direct metal bonding.

[0141] That is, since the connection member has a function of electrically connecting a plurality of components, when direct metal bonding is used, the connection member may be understood as a portion of electrical connection, rather than solder or a wire.

[0142] The wire bonding method may refer to electrically connecting multiple components using a conductor such as gold (Au). In addition, the solder bonding method may electrically connect multiple components using at least one material including Sn, Ag, and Cu. In addition, the direct metal bonding method may refer to directly bonding multiple components by applying heat and pressure between multiple components to recrystallize the multiple components without the need for components such as solder, wires, or conductive adhesives. In addition, the direct bonding method between metals may refer to a connecting member connecting a substrate and a semiconductor device. At this time, the connecting member of the direct bonding method may refer to a metal layer formed between multiple components by recrystallization.

[0143] In addition, you can Figures 1a to 1f A cavity is provided in at least one of a plurality of substrates included in the semiconductor package.

[0144] Depending on the function of the substrate, the cavity can be used for different purposes.

[0145] For example, the cavity may be used for the purpose of arranging a semiconductor device.

[0146] For example, if a cavity is provided in the first substrate 100 , the cavity may be used for the purpose of embedding at least one semiconductor device among the plurality of semiconductor devices 120 and 140 .

[0147] Different from this, if a cavity is provided in the second substrate 200, the cavity may be used for the purpose of arranging the semiconductor device 210. In addition, if a cavity is provided in the second substrate 200, the cavity may be used for the purpose of accommodating at least a portion of the semiconductor device 120 provided on the first substrate 100. Here, providing the semiconductor device 210 may mean that the semiconductor device 210 is electrically connected to the corresponding substrate in the cavity. In addition, accommodating the semiconductor device 120 may mean that the semiconductor device 120 is not electrically connected to the substrate in the cavity, and at least a portion of the semiconductor device 120 is located in the cavity in a floating state.

[0148] Furthermore, the cavity may be used for the purpose of arranging a bridging substrate.

[0149] For example, if a cavity is provided in the first substrate 100 , the cavity may be used for the purpose of arranging the third substrate 190 connected between a plurality of semiconductor devices.

[0150] For example, if a cavity is provided in the fourth substrate 300 , the cavity may be used for the purpose of arranging the fifth substrate 330 connected between a plurality of semiconductor devices.

[0151] The circuit board of the embodiment is described below.

[0152] Before describing a circuit board of an embodiment, a circuit board described below may represent any one of a plurality of substrates included in a previous semiconductor package.

[0153] Preferably, a circuit board of one embodiment described below may be any one of first substrate 100, second substrate 200, third substrate 190, fourth substrate 300 and fifth substrate 330 included in a semiconductor package. Here, a circuit board of one embodiment may mean an embodiment not including a cavity.

[0154] As another example, the circuit board of another embodiment described below may be any one of the first substrate 100, the second substrate 200, and the fourth substrate 300 included in the semiconductor package. Here, the circuit board of another embodiment may represent an embodiment including a cavity. In addition, a semiconductor device may be mounted or accommodated in the cavity, or a bridge substrate may be coupled in the cavity.

[0155] Figure 2 is a cross-sectional view showing a circuit board according to the first embodiment.

[0156] refer to Figure 2 , the circuit board 400 includes an insulating layer 410 .

[0157] The insulating layer 410 may include a plurality of layers. The insulating layer 410 preferably has a multi-layer structure.

[0158] The insulating layer 410 may include a first insulating layer 411 , a second insulating layer 412 , and a third insulating layer 413 .

[0159] The first insulating layer 411 may refer to an insulating layer disposed at the center of a layer structure in a vertical direction of the circuit board 400 , but is not limited thereto.

[0160] The first insulating layer 411 includes a first insulating material. For example, the first insulating layer 411 may include a prepreg in which a reinforcing fiber is impregnated into a resin.

[0161] For example, the prepreg of the first insulating layer 411 may include epoxy resin impregnated in a fiber layer in the form of a fabric sheet, such as a glass fabric woven with glass fiber yarns.

[0162] At this time, although the first insulating layer 411 including the first insulating material is shown in the drawings as having a single-layer structure, it is not limited thereto. For example, the first insulating layer 411 may have a multi-layer structure of two or more layers.

[0163] The second insulating layer 412 is disposed on the first insulating layer 411. In addition, the third insulating layer 413 is disposed under the first insulating layer 411.

[0164] The second insulating layer 412 includes a second insulating material different from the first insulating material of the first insulating layer 411. Preferably, the second insulating layer 412 may not include the reinforcing fiber provided in the first insulating layer 411.

[0165] For example, the second insulating layer 412 may include at least one of ABF (Ajinomoto built-up film), FR-4, BT (bismaleimide triazine), PID (photo imaging dielectric resin), BT, and RCC (resin coated copper).

[0166] The third insulating layer 413 is disposed below the first insulating layer 411. The third insulating layer 413 may include the same second insulating material as the second insulating layer 412. For example, the third insulating layer 413 may not include reinforcing fibers. For example, the third insulating layer 413 may include at least one of ABF (Ajinomoto stacked film), FR-4, BT (bismaleimide triazine), PID (photo imaging dielectric resin), BT, and RCC (copper clad resin).

[0167] Meanwhile, although the second insulating layer 412 and the third insulating layer 413 are illustrated as having a single-layer structure in the drawings, they are not limited thereto. For example, at least one of the second insulating layer 412 and the third insulating layer 413 may have a multi-layer structure of two or more layers.

[0168] The second insulating layer 412 and the third insulating layer 413 may have a thickness in the range of 10 μm to 60 μm. The second insulating layer 412 and the third insulating layer 413 may have a thickness in the range of 15 μm to 55 μm. More preferably, the second insulating layer 412 and the third insulating layer 413 may have a thickness in the range of 18 μm to 52 μm.

[0169] The thickness of each of the second insulating layer 412 and the third insulating layer 413 may represent a vertical distance between a plurality of circuit pattern layers disposed vertically adjacent to each other.

[0170] If the thickness of the second insulating layer 412 and the third insulating layer 413 is less than 10 μm, the warpage characteristics of the circuit board 400 may be deteriorated. For example, if the thickness of the second insulating layer 412 and the third insulating layer 413 is less than 10 μm, the circuit pattern layer disposed on the surface of the second insulating layer 412 and the third insulating layer 413 may not be stably protected, and thus electrical reliability and / or physical reliability problems may occur. In addition, if the thickness of the second insulating layer 412 and the third insulating layer 413 is less than 10 μm, the processability in the process of forming the circuit pattern layer on the second insulating layer 412 and the third insulating layer 413 may be deteriorated.

[0171] In addition, if the thickness of the second insulating layer 412 and the third insulating layer 413 exceeds 60 μm, the total thickness of the circuit board 400 may increase, and thus the thickness of the semiconductor package may increase. In addition, if the thickness of the second insulating layer 412 and the third insulating layer 413 exceeds 60 μm, it may be difficult to miniaturize the circuit pattern layer. For example, if the thickness of the second insulating layer 412 and the third insulating layer 413 exceeds 60 μm, it may be difficult to form the width of the circuit pattern layer and the interval between adjacent patterns to be less than 12 μm, less than 10 μm, less than 8 μm, or less than 6 μm. In addition, if it is difficult to miniaturize the circuit pattern layer, the circuit integration may be reduced, and therefore, the signal transmission distance may increase, which may increase the signal transmission loss.

[0172] The circuit board 400 includes a circuit pattern layer disposed on an insulating layer 410 .

[0173] For example, the circuit board 400 may include a first circuit pattern layer 421 disposed on the first insulating layer 411. In addition, the circuit board 400 may include a second circuit pattern layer 422 disposed on the upper surface of the second insulating layer 412. In addition, the circuit board 400 may include a third circuit pattern layer 423 disposed on the lower surface of the first insulating layer 411. In addition, the circuit board 400 may include a fourth circuit pattern layer 424 disposed on the lower surface of the third insulating layer 413.

[0174] Each of the first circuit pattern layer 421 , the second circuit pattern layer 422 , the third circuit pattern layer 423 , and the fourth circuit pattern layer 424 may include a plurality of metal layers.

[0175] For example, the first circuit pattern layer 421 may include a plurality of metal layers. For example, the first circuit pattern layer 421 may include a first metal layer disposed on the upper surface of the first insulating layer 411 and a second metal layer disposed on the first metal layer. The first metal layer of the first circuit pattern layer 421 may be a seed layer for electroplating the second metal layer of the first circuit pattern layer 421. The thickness of the first metal layer of the first circuit pattern layer 421 may be in the range of 0.2 μm to 3.0 μm. Preferably, the thickness of the first metal layer of the first circuit pattern layer 421 may be in the range of 0.3 μm to 2.8 μm. More preferably, the thickness of the first metal layer of the first circuit pattern layer 421 may be in the range of 0.5 μm to 2.5 μm.

[0176] If the thickness of the first metal layer of the first circuit pattern layer 421 is less than 0.2 μm, the first metal layer of the first circuit pattern layer 421 may not be used as a seed layer. If the thickness of the first metal layer of the first circuit pattern layer 421 is less than 0.2 μm, it may be difficult to form a first metal layer having a uniform thickness on the upper surface of the first insulating layer 411. In addition, if the thickness of the first metal layer of the first circuit pattern layer 421 exceeds 3.0 μm, the process time for forming the first metal layer of the first circuit pattern layer 421 may increase, and thus the yield may decrease. In addition, if the thickness of the first metal layer of the first circuit pattern layer 421 exceeds 3.0 μm, the etching time of the first metal layer during the formation of the first circuit pattern layer 421 may increase. In addition, if the thickness of the first metal layer of the first circuit pattern layer 421 exceeds 3.0 μm, when the first metal layer of the first circuit pattern layer 421 is etched, deformation of the second metal layer of the first circuit pattern layer 421 may occur. Here, the deformation of the second metal layer of the first circuit pattern layer 421 may mean that when the first metal layer is etched, the difference between the width of the upper surface and the width of the lower surface of the second metal layer increases because the side of the second metal layer is also etched. For example, the deformation of the second metal layer of the first circuit pattern layer 421 may mean that the shape of the vertical cross section of the second metal layer changes from a square to a trapezoidal shape.

[0177] In addition, if the thickness of the first metal layer of the first circuit pattern layer 421 exceeds 3.0 μm, the etching amount during the etching process of the first metal layer increases, and therefore, the depth of the indentation (e.g., undercut) formed on the side of the first metal layer and the side of the second metal layer may increase. For example, if the etching amount during the etching process of the first metal layer increases, the difference between the width of the first metal layer and the width of the second metal layer may increase. In addition, if the difference between the width of the first metal layer and the width of the second metal layer increases, the electrical characteristics may deteriorate due to the increase in signal transmission loss. In addition, if the difference between the width of the first metal layer and the width of the second metal layer increases, dendrites may be formed due to electromigration, and thus the electrical characteristics and / or physical characteristics of the first circuit pattern layer 421 may deteriorate.

[0178] The second metal layer of the first circuit pattern layer 421 may be an electroplated layer electroplated with the first metal layer as a seed layer. The second metal layer of the first circuit pattern layer 421 may be formed on the first metal layer with a predetermined thickness. The second metal layer of the first circuit pattern layer 421 may include the same metal as the first metal layer of the first circuit pattern layer 421, but is not limited thereto. For example, the first metal layer and the second metal layer of the first circuit pattern layer 421 may each include copper.

[0179] The thickness of the second metal layer of the first circuit pattern layer 421 may be greater than the thickness of the first metal layer of the first circuit pattern layer 421 .

[0180] The thickness of the second metal layer of the first circuit pattern layer 421 may be in the range of 3.5 μm to 25 μm. Preferably, the thickness of the second metal layer of the first circuit pattern layer 421 may be in the range of 4.0 μm to 23 μm. More preferably, the thickness of the second metal layer of the first circuit pattern layer 421 may be in the range of 4.5 μm to 22 μm.

[0181] If the thickness of the second metal layer of the first circuit pattern layer 421 is less than 3.5 μm, etching of the second metal layer may also be performed during the etching process of the first metal layer. If the thickness of the second metal layer of the first circuit pattern layer 421 is less than 3.5 μm, the allowed current of the signal transmitted through the first circuit pattern layer may be reduced, and thus the electrical characteristics may be deteriorated. If the thickness of the second metal layer of the first circuit pattern layer 421 exceeds 25 μm, it may be difficult to miniaturize the first circuit pattern layer 421. For example, if the thickness of the second metal layer of the first circuit pattern layer 421 exceeds 25 μm, the width and spacing of the pattern constituting the first circuit pattern layer 421 may not meet the required conditions. As a result, the circuit integration may be reduced, or the volume of the circuit board and the semiconductor package may increase.

[0182] In addition, each of the second circuit pattern layer 422 , the third circuit pattern layer 423 , and the fourth circuit pattern layer 424 may include a first metal layer and a second metal layer corresponding to the first circuit pattern layer 421 .

[0183] Meanwhile, each of the first circuit pattern layer 421, the second circuit pattern layer 422, the third circuit pattern layer 423, and the fourth circuit pattern layer 424 is described as including a first metal layer and a second metal layer, but is not limited thereto. For example, each of the first circuit pattern layer 421 and the third circuit pattern layer 423 may further include a third metal layer disposed between the insulating layer and the first metal layer. In addition, the third metal layer may represent a copper layer, but is not limited thereto.

[0184] The first circuit pattern layer 421, the second circuit pattern layer 422, the third circuit pattern layer 423, and the fourth circuit pattern layer 424 may include a conductive material. For example, the first circuit pattern layer 421, the second circuit pattern layer 422, the third circuit pattern layer 423, and the fourth circuit pattern layer 424 may include at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the first circuit pattern layer 421, the second circuit pattern layer 422, the third circuit pattern layer 423, and the fourth circuit pattern layer 424 may be formed of copper (Cu) having high conductivity and being relatively inexpensive.

[0185] Meanwhile, the first circuit pattern layer 421, the second circuit pattern layer 422, the third circuit pattern layer 423 and the fourth circuit pattern layer 424 may be manufactured using conventional circuit board manufacturing processes, such as an additive process, a subtractive process, a modified semi-additive process (MSAP) and a semi-additive process (SAP), and a detailed description thereof is omitted herein.

[0186] The circuit board 400 of the embodiment may include a through electrode, and the through electrode may penetrate the insulating layer 410 .

[0187] For example, the through electrodes may include a through electrode 431 penetrating the first insulating layer 411 , a through electrode 432 penetrating the second insulating layer 412 , and a through electrode 433 penetrating the third insulating layer 413 .

[0188] The through electrode 431 may be electrically connected between the first circuit pattern layer 421 and the third circuit pattern layer 423 .

[0189] In addition, the through electrode 432 may electrically connect between the first circuit pattern layer 421 and the second circuit pattern layer 422 .

[0190] In addition, the through electrode 433 may be electrically connected between the third circuit pattern layer 423 and the fourth circuit pattern layer 424 .

[0191] The through electrodes 431 , 432 , and 433 may be formed by filling a conductive material inside a through hole penetrating the insulating layer 410 .

[0192] The through hole can be formed by any of mechanical, laser and chemical processing methods. When the through hole is formed by mechanical processing, methods such as milling, drilling and routing can be used. In addition, when the through hole is formed by laser processing, a UV or CO2 laser method can be used. In addition, when the through hole is formed by chemical processing, chemical agents including aminosilane, ketone, etc. can be used.

[0193] At this time, at least one through-electrode may be formed by a process different from that of at least one other through-electrode.

[0194] For example, the first insulating layer 411 includes an insulating material different from that of the second insulating layer 412 and the third insulating layer 413 .

[0195] That is, the first insulating layer 411 includes a thermosetting resin. Therefore, a through hole may be formed in the first insulating layer 411 by a laser processing method.

[0196] Differently, the second insulating layer 412 and the third insulating layer 413 include a photocurable resin. Therefore, a through hole may be formed in the second insulating layer 412 and the third insulating layer 413 by a chemical processing method through an exposure and development process.

[0197] Therefore, the through electrodes 432 and 433 penetrating the second and third insulating layers 412 and 413 may have a smaller width than the through electrode 431 penetrating the first insulating layer 411. In addition, a difference between an upper width and a lower width of the through electrodes 432 and 433 penetrating the second and third insulating layers 412 and 413 may be smaller than a difference between an upper width and a lower width of the through electrode 431 penetrating the first insulating layer 411.

[0198] Meanwhile, the circuit board 400 of the embodiment may include a protection layer.

[0199] For example, the circuit board 400 may include a first protection layer 450 disposed on the second insulating layer 412. For example, the circuit board 400 may include a second protection layer 460 disposed under the third insulating layer 413.

[0200] The first protective layer 450 and the second protective layer 460 may be resist layers. Preferably, the first protective layer 450 and the second protective layer 460 may be solder resist layers containing organic polymer materials. For example, the first protective layer 450 and the second protective layer 460 may contain epoxy acrylate resin. In detail, the first protective layer 450 and the second protective layer 460 may contain resin, curing agent, pigment, solvent, filler, additive, acrylic monomer, etc.

[0201] The total thickness of each of the first and second protective layers 450 and 460 may be greater than the thickness of each of the second and fourth circuit pattern layers 422 and 424. The total thickness may represent a vertical distance between the lower and upper surfaces of the first and second protective layers 450 and 460.

[0202] The total thickness of the first protective layer 450 may be in the range of 6.7 μm to 35.0 μm. Preferably, the total thickness of the first protective layer 450 may be in the range of 7.3 μm to 32 μm. More preferably, the total thickness of the first protective layer 450 may be in the range of 8.0 μm to 30 μm.

[0203] If the total thickness of the first protective layer 450 exceeds 30 μm, the thickness of the circuit board and the thickness of the semiconductor package may increase. In addition, if the total thickness of the first protective layer 450 is less than 6.7 μm, the second circuit pattern layer 422 may not be stably protected, and thus electrical reliability or physical reliability may be reduced.

[0204] In addition, the second protective layer 460 may have a thickness corresponding to that of the first protective layer 450 , but is not limited thereto.

[0205] The first protective layer 450 and the second protective layer 460 may each include an opening.

[0206] For example, the first protective layer 450 may include a first opening. The first opening may vertically overlap at least a portion of the second circuit pattern layer 422. As a result, the first opening of the first protective layer 450 may expose at least a portion of the upper surface of the second circuit pattern layer 422.

[0207] In addition, the second protection layer 460 may include a second opening. The second opening may vertically overlap at least a portion of the lower surface of the fourth circuit pattern layer 424. For example, the second opening may expose at least a portion of the lower surface of the fourth circuit pattern layer 424.

[0208] Meanwhile, the circuit board of the embodiment may include a buffer layer. The buffer layer may be referred to as an oxide layer. The buffer layer may be disposed in at least one of the following: between different insulating layers, between an insulating layer and a circuit pattern layer, between an insulating layer and a through electrode, between an insulating layer and a protective layer, and between a circuit pattern layer and a protective layer.

[0209] Specifically, the first insulating layer 411 and the second insulating layer 412 of the embodiment include different insulating materials. In addition, the first insulating layer 411 and the third insulating layer 413 of the embodiment include different insulating materials.

[0210] Therefore, adhesion between the first insulating layer 411 and the second insulating layer 412 may be reduced in laminating the second insulating layer 412 on the first insulating layer 411. In addition, adhesion between the first circuit pattern layer 421 disposed on the first insulating layer 411 and the second insulating layer 412 may be reduced.

[0211] In addition, adhesion between the first insulating layer 411 and the third insulating layer 413 may be reduced in the process of stacking the third insulating layer 413 under the first insulating layer 411. In addition, adhesion between the third circuit pattern layer 423 disposed under the first insulating layer 411 and the third insulating layer 413 may be reduced.

[0212] Specifically, the first insulating layer 411 may include a thermosetting resin. In addition, the second insulating layer 412 and the third insulating layer 413 may include a photocurable resin. For example, the second insulating layer 412 and the third insulating layer 413 may include a PID. That is, the second insulating layer 412 may be referred to as a photosensitive insulating layer, and the first insulating layer 411 may be referred to as an additional insulating layer disposed below the second insulating layer 412. In addition, the third insulating layer 413 may be referred to as another photosensitive insulating layer disposed below the first insulating layer 411.

[0213] Photocurable resin has a higher curing shrinkage than thermosetting resin. In addition, the content of ceramic particles such as SiO2 in the photocurable resin is higher than the content of ceramic particles in the thermosetting resin.

[0214] At this time, when the photocurable resin is analyzed by XPS (X-ray Photoelectron Spectroscopy), relatively high power peaks can be detected in both acrylic and epoxy resins. In addition, when the thermosetting resin not including the reinforcing fiber is analyzed by XPS, a high power peak can be detected only in the epoxy resin. Therefore, the photocurable resin not including the reinforcing fiber and the thermosetting resin can be distinguished.

[0215] Meanwhile, when the second insulating layer 412 is composed of a photocurable resin, adhesion between the first insulating layer 411 and the second insulating layer 412 may be reduced. In addition, adhesion between the first circuit pattern layer 421 and the second insulating layer 412 may be reduced.

[0216] In addition, in order to minimize the signal transmission loss in the high frequency band, the circuit pattern layer applied to the latest circuit boards has a low surface roughness. For example, as the frequency band increases, the signal has the characteristic of flowing along the surface of the circuit pattern layer. In addition, when the surface roughness of the circuit pattern layer is high, the signal transmission loss also increases.

[0217] In addition, as the surface roughness of the circuit pattern layer decreases, the adhesion of the circuit pattern layer to the second insulating layer 412 decreases.

[0218] Accordingly, adhesion between the first insulating layer 411 and the third insulating layer 413 may be reduced, and adhesion between the third circuit pattern layer 423 and the third insulating layer 413 may be reduced.

[0219] Therefore, in an embodiment, the first buffer layer 441 may be disposed on the first insulating layer 411. The first buffer layer 441 may be disposed between the first insulating layer 411 and the second insulating layer 412. Thus, the embodiment may improve adhesion between the first insulating layer 411 and the second insulating layer 412. The first buffer layer 441 may be referred to as a lower oxide layer.

[0220] In addition, the first buffer layer 441 may be disposed between the first circuit pattern layer 421 and the second insulating layer 412. Thus, the first buffer layer 441 may improve adhesion between the first circuit pattern layer 421 and the second insulating layer 412.

[0221] In addition, at least a portion of the first buffer layer 441 may be in contact with the through electrode 432 penetrating the second insulating layer 412. Thus, the first buffer layer 441 may improve adhesion of the through electrode 432.

[0222] Meanwhile, the first buffer layer 441 may include at least one opening region. Preferably, the first buffer layer 441 may open a region of the upper surface of the first circuit pattern layer 421 that vertically overlaps with the through electrode 432. That is, when the first buffer layer 441 is disposed between the first circuit pattern layer 421 and the through electrode 432, the electrical characteristics between the first circuit pattern layer 421 and the through electrode 432 may deteriorate. Therefore, the first buffer layer 441 includes an opening region on the upper surface of the first circuit pattern layer 421, which opens a region that vertically overlaps with the through electrode 432. Therefore, the through electrode 432 is disposed in the opening region of the first buffer layer 441, and thus may directly contact the upper surface of the first circuit pattern layer 421. Therefore, the through electrode 432 may have a structure that penetrates the first buffer layer 441 and the second insulating layer 412.

[0223] Meanwhile, the second buffer layer 442 may be disposed on the second insulating layer 412. The second buffer layer 442 may be referred to as an upper oxide layer.

[0224] The second buffer layer 442 may be disposed between the second insulating layer 412 and the first protective layer 450. Thus, the embodiment may improve adhesion between the second insulating layer 412 and the first protective layer 450.

[0225] In addition, the second buffer layer 442 may be disposed between the second circuit pattern layer 422 and the first protective layer 450. Thus, the embodiment may improve adhesion between the second circuit pattern layer 422 and the first protective layer 450.

[0226] In addition, the second buffer layer 442 may be disposed on the inner wall of the through hole penetrating the second insulating layer 412. For example, the second buffer layer 442 may be disposed between the through hole of the second insulating layer 412 and the through electrode 432. Thus, the second buffer layer 442 may improve the adhesion between the second insulating layer 412 and the through electrode 432.

[0227] At the same time, the second buffer layer 442 may include at least one opening area. For example, the second buffer layer 442 may include an opening area that vertically overlaps with the first opening of the first protective layer 450. For example, the second buffer layer 442 may include an opening area that opens at least a portion of the upper surface of the second circuit pattern layer 422. For example, the second buffer layer 442 may include an opening area on the upper surface of the second circuit pattern layer 422, which exposes a pad area coupled to a semiconductor device or an external substrate. At this time, although the second buffer layer 442 is described as including an opening area, it is not limited thereto. For example, a connecting member may be provided in the pad area, and a reflow process of the connecting member may be performed. In addition, the second buffer layer 442 provided on the pad area may be removed in the reflow process. Therefore, the embodiment may not form a separate opening area in the second buffer layer 442.

[0228] In addition, the third buffer layer 443 may be disposed under the first insulating layer 411 .

[0229] The third buffer layer 443 may be disposed between the first insulating layer 411 and the third insulating layer 413. Thus, the embodiment may improve adhesion between the first insulating layer 411 and the third insulating layer 413.

[0230] In addition, the third buffer layer 443 may be disposed between the third circuit pattern layer 423 and the third insulating layer 413. Thus, the third buffer layer 443 may improve adhesion between the third circuit pattern layer 423 and the third insulating layer 413.

[0231] In addition, at least a portion of the third buffer layer 443 may be in contact with the through electrode 433 penetrating the third insulating layer 413. Thus, the third buffer layer 443 may improve adhesion of the through electrode 433.

[0232] Meanwhile, the third buffer layer 443 may include at least one opening region. Preferably, the third buffer layer 443 may open the region of the lower surface of the third circuit pattern layer 423 vertically overlapping with the through electrode 433. That is, when the third buffer layer 443 is disposed between the third circuit pattern layer 423 and the through electrode 433, the electrical characteristics between the third circuit pattern layer 423 and the through electrode 433 may deteriorate. Therefore, the third buffer layer 443 includes an opening region on the lower surface of the third circuit pattern layer 423, which opens the region vertically overlapping with the through electrode 433. Therefore, the through electrode 433 is disposed in the opening region of the third buffer layer 443, and thus may directly contact the lower surface of the third circuit pattern layer 423. Therefore, the through electrode 433 may have a structure that penetrates the third buffer layer 443 and the third insulating layer 413.

[0233] Meanwhile, a fourth buffer layer 444 may be disposed under the third insulating layer 413 .

[0234] The fourth buffer layer 444 may be disposed between the third insulating layer 413 and the second protective layer 460. Thus, the embodiment may improve adhesion between the third insulating layer 413 and the second protective layer 460.

[0235] In addition, the fourth buffer layer 444 may be disposed between the fourth circuit pattern layer 424 and the second protective layer 460. Thus, the embodiment may improve adhesion between the fourth circuit pattern layer 424 and the second protective layer 460.

[0236] In addition, the fourth buffer layer 444 may be disposed on the inner wall of the through hole penetrating the third insulating layer 413. For example, the fourth buffer layer 444 may be disposed between the through hole of the third insulating layer 413 and the through electrode 433. Thus, the fourth buffer layer 444 may improve the adhesion between the third insulating layer 413 and the through electrode 433.

[0237] At the same time, the fourth buffer layer 444 may include at least one opening area. For example, the fourth buffer layer 444 may include an opening area vertically overlapping the second opening of the second protective layer 460. For example, the fourth buffer layer 444 may include an opening area that opens at least a portion of the lower surface of the fourth circuit pattern layer 424. For example, the fourth buffer layer 444 may include an opening area on the lower surface of the fourth circuit pattern layer 424, which exposes a pad area coupled to a semiconductor device or an external substrate. At this time, although the fourth buffer layer 444 is described as including an opening area, it is not limited thereto. For example, a connecting member may be provided in the pad area, and a reflow process of the connecting member may be performed. In addition, the fourth buffer layer 444 provided on the pad area may be removed in the reflow process. Therefore, the embodiment may not form a separate opening area in the fourth buffer layer 444.

[0238] Meanwhile, each of the first to fourth buffer layers 441, 442, 443, and 444 may include an oxide. For example, each of the first to fourth buffer layers 441, 442, 443, and 444 may be an oxide layer including an oxide. Preferably, the first to fourth buffer layers 441, 442, 443, and 444 may include aluminum oxide (Al2O3). However, the embodiment is not limited thereto, and the first to fourth buffer layers 441, 442, 443, and 444 may include a material containing at least one reactive group or functional group that reacts with the insulating layer or the protective layer.

[0239] Each of the first to fourth buffer layers 441, 442, 443, and 444 may have a thickness in the range of 5 nm to 100 nm. Preferably, each of the first to fourth buffer layers 441, 442, 443, and 444 may have a thickness in the range of 7 nm to 90 nm. More preferably, each of the first to fourth buffer layers 441, 442, 443, and 444 may have a thickness in the range of 10 nm to 50 nm.

[0240] If the thickness of each of the first to fourth buffer layers 441, 442, 443, and 444 is less than 5 nm, a buffer layer of uniform thickness may not be formed on the insulating layer or the circuit pattern layer. In addition, if the buffer layer does not have a uniform thickness, adhesion in a specific area may be reduced. In addition, if the thickness of each of the first to fourth buffer layers 441, 442, 443, and 444 is less than 5 nm, the effect of improving adhesion achieved according to the embodiment may not be significant.

[0241] In addition, if the thickness of the first to fourth buffer layers 441 , 442 , 443 , and 444 exceeds 100 nm, the time for forming the first to fourth buffer layers 441 , 442 , 443 , and 444 may increase, and product yield may decrease accordingly.

[0242] Meanwhile, each of the first to fourth buffer layers 441 , 442 , 443 , and 444 may be formed by a deposition method applying ALD (Atomic Layer Deposition) or CVD (Chemical Vapor Deposition), but is not limited thereto.

[0243] As described above, the embodiment includes a buffer layer disposed between a plurality of insulating layers including different insulating materials.

[0244] At this time, if the plurality of insulating layers are formed of the same insulating material, the buffer layer may be omitted. However, even if the plurality of insulating layers include the same insulating material, the buffer layer is preferably provided due to the characteristics of the circuit board applied to a high frequency band having a low surface roughness.

[0245] In addition, if all of the plurality of insulating layers are applied as prepreg, there is a problem that the total thickness of the circuit board increases. That is, the prepreg includes reinforcing fibers, so there is a limit to reducing the thickness of the insulating layer. As a result, there is a problem that the total thickness of the circuit board and the semiconductor package increases.

[0246] In addition, if all of the plurality of insulating layers are applied as insulating layers not including reinforcing fibers, there is a problem that the bending characteristics of the circuit board are deteriorated. That is, if reinforcing fibers are not included in the insulating layer, the warping characteristics of the insulating layer are deteriorated, and thus the processing characteristics in the process of manufacturing the circuit board may be deteriorated.

[0247] In addition, only applying thermosetting resin has a limitation in reducing the shape and size of the through-electrode. As a result, the circuit board may include a photocurable resin. In addition, due to the characteristics of the photocurable resin, the adhesion with the thermosetting resin or the circuit pattern layer may be reduced.

[0248] Therefore, the embodiment applies the first to fourth buffer layers 441 , 442 , 443 , and 444 as described above in order to improve adhesion between layers constituting the circuit board as a whole.

[0249] Hereinafter, the arrangement structure of the first to fourth buffer layers 441 , 442 , 443 , and 444 will be described in more detail.

[0250] However, the following description will focus on the first buffer layer 441 and the second buffer layer 442. In addition, the third buffer layer 443 and the fourth buffer layer 444 may have an arrangement structure corresponding to the first buffer layer 441 and the second buffer layer 442 described below.

[0251] Figure 3 is a cross-sectional view explaining an arrangement structure of a first buffer layer according to an embodiment.

[0252] refer to Figure 3 , the first buffer layer 441 is disposed on the first insulating layer 411. At this time, the first buffer layer 441 may include a plurality of parts.

[0253] The first buffer layer 441 may be formed after the first circuit pattern layer 421 is disposed on the first insulating layer 411. Therefore, the first buffer layer 441 may not be disposed between the first insulating layer 411 and the first circuit pattern layer 421.

[0254] The first buffer layer 441 may include a first portion 441 - 1 . The first portion 441 - 1 of the first buffer layer 441 may mean a region disposed on the upper surface of the first insulating layer 411 among the entire region of the first buffer layer 441 .

[0255] The first portion 441 - 1 of the first buffer layer 441 may be disposed between an upper surface of the first insulating layer 411 and a lower surface of the second insulating layer 412 . Thus, the first portion 441 - 1 of the first buffer layer 441 may improve adhesion between the first insulating layer 411 and the second insulating layer 412 .

[0256] In addition, the first buffer layer 441 may include a second portion 441 - 2 and a third portion 441 - 3 .

[0257] The second portion 441 - 2 and the third portion 441 - 3 of the first buffer layer 441 may mean a region disposed on the surface of the first circuit pattern layer 421 among the entire region of the first buffer layer 441 .

[0258] At this time, the second portion 441-2 and the third portion 441-3 of the first buffer layer 441 may have different arrangement structures. For example, the second portion 441-2 of the first buffer layer 441 may include an open region, and the third portion 441-3 of the first buffer layer 441 may not include an open region.

[0259] For example, the first circuit pattern layer 421 may include a plurality of patterns. For example, the first circuit pattern layer 421 may include a first pattern 421-1 and a second pattern 421-2.

[0260] The first pattern 421-1 of the first circuit pattern layer 421 may indicate a pattern directly contacting the through electrode 432 in the first circuit pattern layer 421. For example, the first pattern 421-1 of the first circuit pattern layer 421 may indicate a pattern vertically overlapping the through electrode 432.

[0261] In addition, the second pattern 421-2 of the first circuit pattern layer 421 may represent a pattern in the first circuit pattern layer 421 that does not directly contact the through electrode 432. For example, the second pattern 421-2 of the first circuit pattern layer 421 may represent a pattern that does not vertically overlap the through electrode 432.

[0262] The second portion 441-2 of the first buffer layer 441 may partially cover the surface of the first pattern 421-1 of the first circuit pattern layer 421. For example, the second portion 441-2 of the first buffer layer 441 may completely cover the side surface of the first pattern 421-1. For example, the second portion 441-2 of the first buffer layer 441 may partially cover the upper surface of the first pattern 421-1. For example, the second portion 441-2 of the first buffer layer 441 may be selectively disposed in an area of ​​the upper surface of the first pattern 421-1 that does not vertically overlap with the through electrode 432. For example, the second portion 441-2 of the first buffer layer 441 may include an opening area disposed on the upper surface of the first pattern 421-1 and vertically overlapping with the through electrode 432. Therefore, the through electrode 432 may be disposed in the opening area of ​​the second portion 441-2 of the first buffer layer 441, thereby directly contacting the upper surface of the first pattern 421-1 of the first circuit pattern layer 421. For example, the through electrode 432 may penetrate the second portion 441 - 2 of the first buffer layer 441 while penetrating the second insulating layer 412 . In addition, at least a portion of a side surface of the through electrode 432 may contact the second portion 441 - 2 of the first buffer layer 441 .

[0263] Therefore, the second portion 441-2 of the first buffer layer 441 may serve to improve adhesion between the first pattern 421-1 of the first circuit pattern layer 421 and the second insulating layer 412. In addition, the second portion 441-2 of the first buffer layer 441 may serve to improve adhesion between the first pattern 421-1 of the first circuit pattern layer 421 and the through electrode 432.

[0264] Meanwhile, the third portion 441-3 of the first buffer layer 441 may not include an opening region. For example, the third portion 441-3 of the first buffer layer 441 may completely cover the side surface and the upper surface of the second pattern 421-2 of the first circuit pattern layer 421. Therefore, the second pattern 421-2 of the first circuit pattern layer 421 may not directly contact the second insulating layer 412. For example, the lower surface of the second pattern 421-2 of the first circuit pattern layer 421 may contact the first insulating layer 411, and the side surface and the upper surface of the second pattern 421-2 of the first circuit pattern layer 421 may contact the first buffer layer 441.

[0265] Embodiments may improve adhesion between the first insulating layer 411 and the second insulating layer 412 , adhesion between the first circuit pattern layer 421 and the second insulating layer 412 , and adhesion between the first circuit pattern layer 421 and the through electrode 432 by using the first buffer layer 441 .

[0266] Figure 4 is a cross-sectional view explaining an arrangement structure of a second buffer layer according to the first embodiment.

[0267] refer to Figure 4 , the second buffer layer 442 is disposed on the second insulating layer 412. At this time, when the second insulating layer 412 is composed of multiple layers, the second buffer layer 442 may be disposed between the plurality of second insulating layers. Hereinafter, the second buffer layer disposed on the second insulating layer disposed adjacent to the first protective layer 450 will be described.

[0268] The second buffer layer 442 may be disposed between the second insulating layer 412 and the first protective layer 450. In addition, the second buffer layer 442 may be disposed between the second circuit pattern layer 422 and the first protective layer 450.

[0269] That is, the second buffer layer 442 of the first embodiment may be formed in a state where the second circuit pattern layer 422 is disposed on the second insulating layer 412. Therefore, the second buffer layer 442 of the first embodiment may not be disposed between the second insulating layer 412 and the second circuit pattern layer 422.

[0270] The second buffer layer 442 may include a plurality of parts.

[0271] The second buffer layer 442 may include a first portion 442 - 1 . The first portion 442 - 1 of the second buffer layer 442 may refer to a region disposed on the upper surface of the second insulating layer 412 among the entire region of the second buffer layer 442 .

[0272] The first portion 442-1 of the second buffer layer 442 may be disposed between the upper surface of the second insulating layer 412 and the lower surface of the first protective layer 450. Thus, the first portion 442-1 of the second buffer layer 442 may improve adhesion between the second insulating layer 412 and the first protective layer 450.

[0273] In addition, the second buffer layer 442 may include a second portion 442 - 2 and a third portion 442 - 3 .

[0274] The second portion 442 - 2 and the third portion 442 - 3 of the second buffer layer 442 may refer to a region disposed on the surface of the second circuit pattern layer 422 among the entire region of the second buffer layer 442 .

[0275] At this time, the second portion 442-2 and the third portion 442-3 of the second buffer layer 442 may have different arrangement structures. For example, the second portion 442-2 of the second buffer layer 442 may include an opening region, and the third portion 442-3 of the second buffer layer 442 may not include an opening region.

[0276] For example, the second circuit pattern layer 422 may include a plurality of patterns. For example, the second circuit pattern layer 422 may include a first pattern 422-1 and a second pattern 422-2.

[0277] The first pattern 422-1 of the second circuit pattern layer 422 may represent a pattern of the second circuit pattern layer 422 vertically overlapping the first opening 451 of the first protection layer 450. For example, the first pattern 422-1 of the second circuit pattern layer 422 may represent a pad coupled to a semiconductor device or an external substrate.

[0278] In addition, the second pattern 422 - 2 of the second circuit pattern layer 422 may mean a pattern of the second circuit pattern layer 422 that does not vertically overlap the first opening 451 of the first protection layer 450 .

[0279] The second portion 442-2 of the second buffer layer 442 may partially cover the surface of the first pattern 422-1 of the second circuit pattern layer 422. For example, the second portion 442-2 of the second buffer layer 442 may completely cover the side surface of the first pattern 422-1 of the second circuit pattern layer 422. For example, the second portion 442-2 of the second buffer layer 442 may partially cover the upper surface of the first pattern 422-1 of the second circuit pattern layer 422. For example, the second portion 442-2 of the second buffer layer 442 may be selectively disposed in an area of ​​the upper surface of the first pattern 422-1 of the second circuit pattern layer 422 that does not vertically overlap with the first opening 451 of the first protective layer 450. For example, the second portion 442-2 of the second buffer layer 442 may include an opening area disposed on the upper surface of the first pattern 422-1 of the second circuit pattern layer 422 and vertically overlapping with the first opening 451 of the first protective layer 450.

[0280] Therefore, the second portion 442 - 2 of the second buffer layer 442 may serve to improve adhesion between the first pattern 422 - 1 of the second circuit pattern layer 422 and the first protection layer 450 .

[0281] Meanwhile, the third portion 442-3 of the second buffer layer 442 may not include an opening area. For example, the third portion 442-3 of the second buffer layer 442 may completely cover the side surface and the upper surface of the second pattern 422-2 of the second circuit pattern layer 422. Thus, the second pattern 422-2 of the second circuit pattern layer 422 may not directly contact the first protective layer 450. For example, the lower surface of the second pattern 422-2 of the second circuit pattern layer 422 may contact the second insulating layer 412, and the side surface and the upper surface of the second pattern 422-2 of the second circuit pattern layer 422 may contact the second buffer layer 442.

[0282] Embodiments may improve adhesion between the second insulating layer 412 and the first protective layer 450 and adhesion between the second circuit pattern layer 422 and the first protective layer 450 by using the second buffer layer 442 .

[0283] Figure 5 is a cross-sectional view explaining an arrangement structure of a second buffer layer according to a second embodiment.

[0284] refer to Figure 5 , the second buffer layer 442 is disposed on the second insulating layer 412 .

[0285] The second buffer layer 442 may be disposed between the second insulating layer 412 and the first protective layer 450. In addition, the second buffer layer 442 may be disposed between the second insulating layer 412 and the first protective layer 450.

[0286] That is, the second buffer layer 442 of the second embodiment is disposed on the second insulating layer 412 before forming the second circuit pattern layer 422. Preferably, the second buffer layer 442 may be formed after forming a through hole in the second insulating layer 412 and before forming the through electrode 432 and the second circuit pattern layer 422.

[0287] Therefore, the second buffer layer 442 of the second embodiment may not be disposed between the second circuit pattern layer 422 and the first protective layer 450. However, the embodiment is not limited thereto. For example, the embodiment may perform the process of forming the second buffer layer 442 multiple times. Therefore, the second buffer layer 442 may have a combination of the structure of the second embodiment described below and the structure of the first embodiment described above.

[0288] The second buffer layer 442 may include a plurality of parts.

[0289] The second buffer layer 442 may include a first portion 442 - 1 . The first portion 442 - 1 of the second buffer layer 442 may refer to a region disposed between the second insulating layer 412 and the first protective layer 450 among the entire region of the second buffer layer 442 .

[0290] The first portion 442-1 of the second buffer layer 442 may be disposed between the upper surface of the second insulating layer 412 and the lower surface of the first protective layer 450. Thus, the first portion 442-1 of the second buffer layer 442 may improve adhesion between the second insulating layer 412 and the first protective layer 450.

[0291] In addition, the second buffer layer 442 may include a second portion 442 - 2 and a third portion 442 - 3 .

[0292] The second portion 442-2 of the second buffer layer 442 may represent a region disposed between the second insulating layer 412 and the second circuit pattern layer 442-2 among the entire region of the second buffer layer 442. Thus, the second portion 442-2 of the second buffer layer 442 may improve adhesion between the second insulating layer 412 and the second circuit pattern layer 442-2.

[0293] In addition, the third portion 442-3 of the second buffer layer 442 may be disposed on the inner wall of the through hole of the second insulating layer 412. That is, the second buffer layer 442 is formed after the through hole is formed in the second insulating layer 412. Therefore, the second buffer layer 442 may include the third portion 442-3 disposed on the inner wall of the through hole of the second insulating layer 412.

[0294] The third portion 442 - 3 of the second buffer layer 442 is disposed between the second insulating layer 412 and the through electrode 432 . Thus, the third portion 442 - 3 of the second buffer layer 442 may improve adhesion between the second insulating layer 412 and the through electrode 432 .

[0295] The circuit board of the embodiment can improve adhesion between a plurality of layers.

[0296] Specifically, the circuit board of the embodiment includes a first insulating layer and a second insulating layer, the first insulating layer includes a first insulating material, and the second insulating layer is disposed on the first insulating layer and includes a second insulating material different from the first insulating material.

[0297] At this time, the embodiment includes a buffer layer disposed between the first insulating layer and the second insulating layer. The buffer layer can be used as an adhesive layer to improve the adhesion between the first insulating layer and the second insulating layer. The buffer layer can be an oxide layer. For example, the buffer layer can include aluminum oxide.

[0298] Thus, embodiments may improve adhesion between the first insulating layer and the second insulating layer, thereby improving physical reliability and / or electrical reliability of a circuit board and a semiconductor package including the circuit board.

[0299] In addition, the first insulating layer may include a thermosetting resin, and the second insulating layer may include a photocurable resin. By including the second insulating layer of the photocurable resin, the embodiment can improve the physical reliability and electrical reliability of the circuit pattern layer and the through electrode disposed on the second insulating layer. In addition, by including the second insulating layer of the photocurable resin, the circuit pattern layer and the through electrode disposed on the second insulating layer can be miniaturized.

[0300] At this time, the photocurable resin has a relatively high content of ceramic particles and a relatively high curing shrinkage, and therefore, there may be a problem in that the adhesion between the photocurable resin and other layers is reduced.

[0301] In contrast, the embodiment includes a buffer layer disposed on the surface of the photocurable resin. Therefore, even if the second insulating layer includes the photocurable resin, the embodiment can miniaturize the circuit pattern layer and the through-electrode without affecting the adhesiveness.

[0302] Therefore, embodiments may improve the circuit integration of a circuit board and further improve the physical reliability and / or electrical reliability of the circuit board.

[0303] At the same time, the buffer layer of the embodiment is also disposed between the second insulating layer and the circuit pattern layer. Therefore, the embodiment can improve the adhesion between the second insulating layer and the circuit pattern layer.

[0304] In addition, the buffer layer of the embodiment is also disposed between the second insulating layer and the through electrode. Therefore, the embodiment can improve the adhesion between the second insulating layer and the through electrode.

[0305] In addition, the buffer layer of the embodiment is also disposed between the second insulating layer and the first protective layer. Therefore, the embodiment can improve the adhesion between the second insulating layer and the first protective layer.

[0306] In addition, the buffer layer of the embodiment is also disposed between the circuit pattern layer and the first protective layer. Therefore, the embodiment can improve the adhesion between the circuit pattern layer and the first protective layer.

[0307] The embodiment may improve adhesion between a plurality of layers constituting a circuit board by forming a buffer layer having a structure as described above, and may accordingly improve product reliability.

[0308] Figure 6 2 is a diagram showing a circuit board according to a second embodiment.

[0309] refer to Figure 6 , the circuit board of the second embodiment may have Figure 2 The circuit board of the second embodiment has a substantially similar structure to the circuit board of the first embodiment. However, compared with the circuit board of the first embodiment, the circuit board of the second embodiment may be provided with a cavity C in the second insulating layer. Therefore, the circuit board of the second embodiment is different from the circuit board of the first embodiment in the structure of the second insulating layer including the cavity C and the second buffer layer provided in the second insulating layer.

[0310] Hereinafter, the circuit board of the second embodiment will be described, focusing on features that are different from those of the circuit board of the first embodiment.

[0311] The circuit board includes a first insulating layer 511 and a second insulating layer 512. A first circuit pattern layer 521 is disposed on the first insulating layer 511.

[0312] In addition, although omitted in the drawings, a first buffer layer may be disposed on the first insulating layer 511 .

[0313] Meanwhile, the second buffer layer 542 is disposed on the second insulating layer 512. At this time, the arrangement structure of the second buffer layer 542 may be similar to Figure 5 The structure shown.

[0314] However, the second insulating layer 512 includes the cavity C. Therefore, the second buffer layer 542 may include a portion additionally formed in a region corresponding to the cavity C.

[0315] That is, the second insulating layer 512 includes the cavity C penetrating the upper surface and the lower surface. At this time, the cavity C of the second insulating layer 512 may be formed together with a through hole corresponding to the through electrode 532 penetrating the second insulating layer 512 .

[0316] The first circuit pattern layer 521 further includes a third pattern 521 - 3 vertically overlapping the cavity C.

[0317] The third pattern 521 - 3 of the first circuit pattern layer 521 may include an upper surface exposed through the cavity C. The third pattern 521 - 3 of the first circuit pattern layer 521 may be a semiconductor device disposed in the cavity C or a pad coupled to an external substrate.

[0318] Meanwhile, the second buffer layer 542 disposed on the second insulating layer 512 may include a plurality of parts.

[0319] The second buffer layer 542 may include a first portion 542 - 1 disposed between the second insulating layer 512 and the first protective layer 550 .

[0320] In addition, the second buffer layer 542 may include a second portion 542 - 2 disposed between an inner wall of the through hole of the second insulating layer 512 and the through electrode 532 .

[0321] In addition, the second buffer layer 542 may include a third portion 542 - 3 disposed on an inner wall of the cavity C of the second insulating layer 512 .

[0322] In addition, the second buffer layer 542 may include a fourth portion 542-4 disposed at a lower surface of the cavity C of the second insulating layer 512. At this time, the fourth portion 542-4 of the second buffer layer 542 may be a portion of the first buffer layer described above.

[0323] Unlike the circuit board of the first embodiment, the second buffer layer 542 included in the circuit board of the second embodiment includes a third portion 542 - 3 disposed on the inner wall of the cavity C and a fourth portion 542 - 4 disposed on the lower surface of the cavity C.

[0324] The third portion 542 - 3 of the second buffer layer 542 is disposed on the inner wall of the cavity C. At this time, the embodiment may prevent debris from being exposed through the inner wall of the cavity C by using the third portion 542 - 3 of the second buffer layer 542 . For example, when the cavity C is formed in the second insulating layer 512 , debris such as burrs may exist on the inner wall of the cavity C depending on the processing process of the cavity C.

[0325] Therefore, in the conventional technology, a desmear process is additionally performed to remove the smear.

[0326] In contrast, the embodiment forms the third portion 542-3 of the second buffer layer 542 on the inner wall of the cavity C. Therefore, the embodiment can solve the reliability problem that may occur due to smear through the third portion 542-3 of the second buffer layer 542. In addition, the embodiment can omit the desmear process by arranging the third portion 542-3 of the second buffer layer 542, thereby simplifying the manufacturing process.

[0327] In addition, the embodiment includes a fourth portion 542-4 of the second buffer layer 542 disposed on the lower surface of the cavity C. At this time, the lower surface of the cavity C substantially corresponds to the upper surface of the first insulating layer 511. Therefore, the fourth portion 542-4 of the second buffer layer 542 may also be referred to as a portion of the first buffer layer 441 described in the previous embodiment.

[0328] The fourth portion 542 - 4 of the second buffer layer 542 is disposed at the lower surface of the cavity C, and thus, a portion of the insulating material included in the first insulating layer 511 may be prevented from being exposed through the cavity C.

[0329] For example, when the desmear process is performed after forming the cavity C, the surface of the first insulating layer 511 may also be removed during the desmear process. In addition, during the desmear process, a portion of the reinforcing fiber disposed in the first insulating layer 511 may be exposed through the cavity C. In addition, if the reinforcing fiber is exposed through the cavity C, a physical reliability or electrical reliability problem may occur during a mounting process of a semiconductor device or a bonding process of an external substrate.

[0330] In contrast, in the embodiment, the fourth portion 542-4 of the second buffer layer 542 is disposed on the lower surface of the cavity C. In addition, the fourth portion 542-4 of the second buffer layer 542 may be used as a barrier layer to protect the surface of the first insulating layer 511 during the desmear process. Thus, the embodiment may prevent the reinforcing fibers included in the first insulating layer 511 from being exposed through the cavity C, thereby improving the overall physical and electrical reliability of the circuit board.

[0331] Meanwhile, the fourth portion 542-4 of the second buffer layer 542 may include an open area exposing the surface of the third pattern 521-3 of the first circuit pattern layer 521. For example, the fourth portion 542-4 of the second buffer layer 542 may completely expose the upper surface of the third pattern 521-3 of the first circuit pattern layer 521. In addition, the fourth portion 542-4 of the second buffer layer 542 may expose at least a portion of the side surface of the third pattern 521-3 of the first circuit pattern layer 521.

[0332] Meanwhile, in the drawings, the cavity C is shown as penetrating one layer of the second insulating layer 512, but is not limited thereto. For example, the cavity C may also penetrate at least two layers of the second insulating layer.

[0333] As described above, the circuit board according to the second embodiment may include a cavity, thereby improving the overall product reliability of the circuit board.

[0334] That is, the second insulating layer includes a cavity. At this time, the buffer layer may also be disposed on the inner wall of the cavity of the second insulating layer. Therefore, the embodiment may omit the desmearing process for removing the smear remaining on the inner wall of the cavity. Therefore, the embodiment may simplify the manufacturing process of the circuit board. In addition, the embodiment may prevent the size of the cavity from expanding due to the desmearing process by omitting the desmearing process, thereby forming a cavity with an optimal size. Therefore, the embodiment may reduce the volume of the circuit board.

[0335] In addition, the buffer layer may also be disposed on the lower surface of the cavity. In addition, if a desmear process is performed after the cavity is formed, the buffer layer disposed on the lower surface of the cavity may be used as a barrier layer. In addition, the embodiment may prevent the reinforcing fibers included in the first insulating layer from being exposed during the desmear process by the barrier layer. Therefore, the embodiment may further improve product reliability.

[0336] Figure 7a is a sectional view showing a circuit board according to a third embodiment, Figure 7b yes Figure 7a A plan view of a circuit board.

[0337] refer to Figure 7a and Figure 7b The circuit board of the third embodiment has a structure similar to that of the circuit board of the second embodiment, except that the fourth pattern 542 - 4 is disposed on the first insulating layer 511 .

[0338] At this time, the second insulating layer 512 of the embodiment includes a photocurable resin. Therefore, when forming the cavity C in the second insulating layer 512, the embodiment may perform an exposure and development process instead of laser processing.

[0339] Here, the first insulating layer 511 includes a thermosetting resin. Therefore, when performing a development process for forming the cavity C in the second insulating layer 512, the first insulating layer 511 may not be removed. Therefore, the embodiment can form the cavity C penetrating only the second insulating layer 512 without a barrier for forming the cavity C.

[0340] Therefore, embodiments may provide the fourth pattern 521 - 4 of the first circuit pattern layer 521 in a region vertically overlapping the cavity C, which is directly connected to the third pattern 521 - 3 of the first circuit pattern layer 521 .

[0341] That is, since the conventional structure has a barrier for forming the cavity C, the third pattern vertically overlapping the cavity and the fifth pattern not vertically overlapping the cavity in the first circuit pattern layer cannot be directly connected to each other. Therefore, conventionally, the third pattern and the fifth pattern of the first circuit pattern layer are connected to each other using a through electrode penetrating the first insulating layer 511.

[0342] In contrast, the second insulating layer 512 of the embodiment includes a photocurable resin, and thus, a stopper required to form the cavity C may be removed.

[0343] Therefore, the embodiment may set the fourth pattern 521-4 on the first insulating layer 511 vertically overlapping the cavity C. The fourth pattern 521-4 may be a trace directly connecting the third pattern 521-3 vertically overlapping the cavity C and the fifth pattern 521-5 not vertically overlapping the cavity C. At this time, the fifth pattern 521-5 of the first circuit pattern layer 521 may represent the first pattern 421-1 and / or the second pattern 421-2 of the first circuit pattern layer 421 included in the circuit board of the first embodiment.

[0344] Therefore, the fourth pattern 521-4 of the first circuit pattern layer 521 of the embodiment may be divided into a plurality of parts. The fourth pattern 521-4 of the first circuit pattern layer 521 may include a first part 521-41 directly connected to the third pattern 521-3 and vertically overlapping the cavity C. In addition, the fourth pattern 521-4 of the first circuit pattern layer 521 may include a second part 521-42 extending from the first part 521-41 and not vertically overlapping the cavity C.

[0345] That is, the first portion 521-41 of the fourth pattern 521-4 of the first circuit pattern layer 521 may refer to a portion directly connected to the third pattern 521-3 while being exposed by the cavity C. In addition, the second portion 521-42 of the fourth pattern 521-4 of the first circuit pattern layer 521 may refer to a portion covered by the second insulating layer 512 and connecting the first portion 521-41 of the fourth pattern 521-4 and the fifth pattern 521-5.

[0346] Therefore, embodiments can directly connect the third pattern 521-3 and the fifth pattern 521-5 by using the fourth pattern 521-4. Therefore, embodiments can minimize a signal transmission distance of a semiconductor device or an external substrate disposed on the third pattern 521-3, thereby minimizing signal transmission loss.

[0347] Meanwhile, the second buffer layer 542 may further include a fifth portion 542-5. The fifth portion 542-5 of the second buffer layer 542 may be disposed to cover the side surface and the upper surface of the first portion 521-41 of the fourth pattern 521-4 exposed through the cavity C. Therefore, the embodiment may stably protect the fourth pattern 521-4 exposed through the cavity C. In addition, when a mold layer filling the cavity C is formed, the embodiment may improve adhesion to the mold layer.

[0348] Figure 8 1 is a diagram showing a semiconductor package according to a seventh embodiment, Fig. 9 2 is a diagram showing a semiconductor package according to an eighth embodiment.

[0349] refer to Figure 8 , the semiconductor package of the seventh embodiment includes a connecting member 610 disposed on the third pattern 521 - 3 of the first circuit pattern layer 521 exposed through the cavity C.

[0350] In addition, the semiconductor package of the seventh embodiment includes a semiconductor device 620 disposed on a connection member 610. The semiconductor device 620 includes a terminal 625, and the terminal 625 may be electrically connected to the third pattern 521-3 of the first circuit pattern layer 521 through the connection member 610.

[0351] In addition, refer to Fig. 9 The semiconductor package of the eighth embodiment may further include a mold layer 630 filling the cavity C. In addition, the mold layer 630 may contact the second buffer layer 542 .

[0352] Hereinafter, a method for manufacturing a circuit board according to an embodiment will be described in order of processes.

[0353] Figures 10 to 17 1 is a cross-sectional view for explaining a method for manufacturing a circuit board of an embodiment in a process order. Hereinafter, a method for manufacturing a circuit board including a cavity will be described. However, for ease of explanation, the description will focus on the layers sequentially arranged above the first insulating layer 511 based on the first insulating layer 511.

[0354] refer to Fig.10 , the embodiment prepares the first insulating layer 511. Thereafter, the embodiment forms a through hole penetrating the first insulating layer 511. Thereafter, the embodiment performs a process of forming a through electrode 531 filling the through hole of the first insulating layer 511 and a first circuit pattern layer 521 disposed on the upper surface of the first insulating layer 511.

[0355] Next, refer to Fig.11 , the embodiment may perform a process of forming the first buffer layer 541. At this time, the first buffer layer 541 may be completely formed on the exposed surface of the first insulating layer 511 and the exposed surface of the first circuit pattern layer 521. Thereafter, the embodiment may perform a process of removing the area vertically overlapping with the through-electrode penetrating the second insulating layer from the entire area of ​​the first buffer layer 541. However, the removal process may be performed after the through hole is formed in the second insulating layer 512. Hereinafter, the removal process will be described as being performed after the through hole is formed in the second insulating layer 512.

[0356] Afterwards, refer to Fig.12 , the embodiment may perform a process of stacking the second insulating layer 512 on the first buffer layer 541. The second insulating layer 512 may include a photocurable resin.

[0357] Next, refer to Fig.13 , embodiments may perform a process of treating the second insulating layer 512. Specifically, the treating process may refer to a process of exposing and developing the second insulating layer 512.

[0358] For example, embodiments may remove the region where the through hole TH is to be formed in the second insulating layer 512 by exposure and development. In addition, embodiments may remove the region where the cavity C is to be formed in the second insulating layer 512 by exposure and development. At this time, the process of forming the through hole TH and the process of forming the cavity C may be performed simultaneously, but are not limited thereto.

[0359] Next, refer to Fig.14 , the embodiment may perform a process of forming a second buffer layer 542 on the second insulating layer 512. At this time, the second buffer layer 542 may be respectively disposed on the upper surface of the second insulating layer 512, the inner wall of the through hole TH, and the inner wall of the cavity C. In addition, at least a portion of the second buffer layer 542 may be connected to the first buffer layer 541.

[0360] Afterwards, refer to Fig.15 , the embodiment may perform a process of removing the area vertically overlapping with the through hole TH among the entire area of ​​the first buffer layer 541. That is, the embodiment may perform a process of removing the first buffer layer 541 to expose the upper surface 521U of the first circuit pattern layer 521 vertically overlapping with the through hole TH in the first circuit pattern layer 521. The process of removing the first buffer layer 541 may be performed using a wet method, or alternatively, may be performed using a dry method. When the wet method is used, a portion of the first buffer layer 541 may be selectively removed using hydrofluoric acid chemicals. In addition, when the dry method is used, a portion of the first buffer layer 541 may be selectively removed using a laser.

[0361] In addition, embodiments may perform a process of removing a region of the first buffer layer 541 or the second buffer layer 542 adjacent to the third pattern 521-3 of the first circuit pattern layer 521 exposed through the cavity C. For example, embodiments may remove at least a portion of the first buffer layer 541 and the second buffer layer 542 to expose at least a portion of a side surface and an upper surface of the third pattern 521-3 vertically overlapping the cavity C.

[0362] Next, refer to Fig.16 , embodiments may perform a process of forming the through-electrode 532 filling the through hole TH of the second insulating layer 512 and the second circuit pattern layer 522 disposed on the second insulating layer 512 .

[0363] Afterwards, refer to Fig.17, embodiments may perform a process of forming a first protective layer 550 on the second buffer layer 542 . The first protective layer 550 may include an opening vertically overlapping the cavity C. In addition, a process of removing at least a portion of the first protective layer 550 of the upper surface of the second circuit pattern layer 522 may be performed.

[0364] On the other hand, when the circuit board having the above-mentioned features of the present invention is used for IT equipment or household appliances (such as smart phones, server computers, TVs, etc.), functions such as signal transmission or power supply can be stably performed. For example, when the circuit board having the features of the present invention performs a semiconductor packaging function, it can safely protect the semiconductor chip from external moisture or pollutants, or alternatively, it can solve the problems of leakage current, electrical short circuit and electrical open circuit of the terminals provided to the semiconductor chip. In addition, when the signal transmission function is dominant, the noise problem can be solved. Thus, the circuit board having the above-mentioned features of the present invention can maintain the stable function of IT equipment or household appliances, so that the entire product and circuit board to which the present invention is applied can achieve functional unification or technical interlocking with each other.

[0365] When the circuit board having the above features of the present invention is used in a transportation device such as a vehicle, the problem of signal distortion transmitted to the transportation device can be solved, or alternatively, the safety of the transportation device can be further improved by externally safely protecting the semiconductor chip controlling the transportation device and solving the problem of leakage current or electrical short circuit between terminals provided to the semiconductor chip or electrical open circuit of the terminals. Therefore, the transportation device and the circuit board to which the present invention is applied can achieve functional unification or technical interlocking with each other.

[0366] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to one embodiment. In addition, a person skilled in the art of the embodiment can combine or modify the features, structures, effects, etc. shown in each embodiment for other embodiments. Therefore, the contents related to such combinations and changes should be interpreted as included in the scope of the embodiments.

[0367] In the above, the embodiments have been mainly described, but this is only an example and does not limit the embodiments. It will be understood by those skilled in the art that various modifications and applications not shown above are possible without departing from the basic features of the embodiments. For example, each component specifically shown in the embodiments can be implemented by modification. In addition, the differences related to these modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. A semiconductor package, comprising: Photosensitive insulating layer; a first circuit pattern layer, wherein the first circuit pattern layer is embedded in the photosensitive insulating layer; as well as A lower oxide layer is disposed at an interface between the photosensitive insulating layer and the first circuit pattern layer.

2. The semiconductor package according to claim 1, wherein The lower oxide layer is also disposed on a lower surface of the photosensitive insulating layer that does not vertically overlap with the first circuit pattern layer.

3. The semiconductor package according to claim 2, further comprising: an additional insulating layer, the additional insulating layer being arranged on the lower surface of the photosensitive insulating layer, Wherein, the lower oxide layer disposed on the lower surface of the photosensitive insulating layer contacts the upper surface of the additional insulating layer.

4. The semiconductor package according to claim 2, wherein: The additional insulating layer includes an insulating material different from an insulating material of the photosensitive insulating layer.

5. The semiconductor package according to claim 2, wherein: The additional insulating layer comprises reinforcing fibers.

6. The semiconductor package according to claim 3, wherein: The additional insulating layer is a thermosetting insulating layer.

7. The semiconductor package according to claim 1, further comprising: A through electrode, wherein the through electrode passes through the photosensitive insulating layer; as well as a second circuit pattern layer, the second circuit pattern layer being disposed on the photosensitive insulating layer, Wherein, the lower oxide layer includes an opening area vertically overlapping with the lower surface of the through electrode.

8. The semiconductor package according to claim 7, further comprising: An upper oxide layer is disposed on the photosensitive insulating layer.

9. The semiconductor package according to claim 8, wherein: At least one of the upper oxide layer and the lower oxide layer includes aluminum oxide.

10. The semiconductor package according to claim 8, further comprising: a protective layer, the protective layer being disposed on the upper oxide layer, Wherein, the upper oxide layer comprises: a first portion, the first portion being disposed at an interface between the photosensitive insulating layer and the protective layer, and The second portion is disposed at an interface between the second circuit pattern layer and the protection layer.

Images