Infrared detector reading circuit based on dark current suppression structure

Abstract

The invention provides an infrared detector reading circuit based on a dark current suppression structure, which comprises a dark current suppression circuit, an integrating circuit, a double sampling circuit, a source follower, a differential amplification circuit and an output buffer circuit which are electrically connected in sequence, and also comprises a sequential logic circuit, the dark current suppression circuit is used for generating a controllable current which is not influenced by temperature change, and the current is mirrored and then used for counteracting the dark current of the infrared detector; the sequential logic circuit is used for providing row selection logic, column selection logic and a sampling time sequence when a target pixel is selected from an infrared detector pixel array; the reading circuit can read the current signal of the target pixel according to the row selection logic, the column selection logic and the sampling time sequence; according to the invention, the signal-to-noise ratio of the readout system is improved by suppressing dark current, the function of reading out according to the column is realized based on the sequential logic circuit, the noise interference among the readout circuits in the array can be effectively reduced, and the focal plane array readout circuit is suitable for preparing a large-array-scale focal plane array readout circuit.

Description

Technical Field

[0001] The invention relates to the technical field of infrared detectors, and in particular to an infrared detector readout circuit based on a dark current suppression structure. Background Art

[0002] The infrared focal plane array is composed of a detector array and a readout circuit. A good readout circuit is crucial to the infrared focal plane. With the integration of infrared focal plane arrays, miniaturization, high-speed intelligence, and color diversification, the development of readout circuits has also become highly integrated, with reduced power consumption, increased speed, and diversified functions. At present, infrared detectors have been used in military fields such as "night combat" and "precision guidance" and in civilian fields such as "medical examination" and "airport security". For infrared detectors, especially photoconductive infrared detectors, dark current and noise in the dark state will seriously affect the signal-to-noise ratio of infrared detectors.

[0003] In addition, when large-scale array readout circuits are used in practical engineering applications, the dark current and noise of each readout circuit will interfere with each other, further reducing the signal-to-noise ratio of the infrared detector. This problem also needs to be solved urgently. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present invention proposes an infrared detector readout circuit based on a dark current suppression structure to solve the deficiencies in the prior art.

[0005] The technical solution adopted by the present invention is as follows:

[0006] In a first aspect, an infrared detector readout circuit based on a dark current suppression structure is provided, comprising:

[0007] A dark current suppression circuit, an integration circuit, a double sampling circuit, a source follower, a differential amplifier circuit and an output buffer circuit electrically connected in sequence, and also includes a sequential logic circuit;

[0008] The dark current suppression circuit is used to generate a controllable current that is not affected by temperature changes, and the current is mirrored to offset the dark current of the infrared detector to obtain a net photocurrent;

[0009] The integration circuit is used to integrate and amplify the net photocurrent and convert it into a voltage signal;

[0010] The double sampling circuit is used to suppress the noise of the voltage signal and output a sampled voltage;

[0011] The source follower is used to buffer the sampled voltage;

[0012] The differential amplifier circuit is used to perform differential operation on the buffered sampling voltage;

[0013] The output buffer circuit is used for buffering the voltage signal read out from the output;

[0014] The timing logic circuit is used to provide row selection logic, column selection logic and sampling timing when selecting target pixels from the infrared detector pixel array; the timing logic circuit includes a row selection logic circuit, a column selection logic circuit and a sampling logic circuit, the row selection logic circuit includes a row selection switch arranged between the dark current suppression circuit and the integration circuit, the column selection logic circuit includes a column selection switch connected to the source follower, and the sampling logic circuit is used to provide sampling timing to the dual sampling circuit.

[0015] Furthermore, the dark current suppression circuit includes 2 bipolar PNP transistors, 6 NMOS field effect transistors and 3 PMOS field effect transistors, wherein:

[0016] The base and collector of the first bipolar PNP transistor B1 and the second bipolar PNP transistor B2 are grounded; the emitter of the transistor B1 is connected to the drain of the NMOS transistor MN0, and the emitter of the transistor B2 is connected to the drain of the NMOS transistor MN1;

[0017] The gates of the zeroth NMOS tube MN0 and the first NMOS tube MN1 are connected, and the gate voltage is adjustable; the sources of the NMOS tubes MN0 and MN1 are grounded, the drain of the NMOS tube MN0 is connected to the emitter of the transistor B1, and the drain of the NMOS tube MN1 is connected to the emitter of the transistor B2;

[0018] The second NMOS tube MN2 has a drain connected to the gate of the NMOS tube MN3 and the source of the NMOS tube MN4, a gate connected to the drain of the NMOS tube MN3 and the source of the NMOS tube MN5, and a source connected to the drain of the NMOS tube MN0;

[0019] The third NMOS tube MN3 has a drain connected to the gate of the NMOS tube MN2 and the source of the NMOS tube MN5, a gate connected to the drain of the NMOS tube MN2 and the source of the NMOS tube MN4, and a source connected to the drain of the NMOS tube MN1;

[0020] The fourth NMOS tube MN4 has a drain connected to the drain of the PMOS tube MP1 and the gate of the NMOS tube MN5, a gate connected to the gate of the NMOS tube MN5, and a source connected to the drain of the NMOS tube MN2 and the gate of the NMOS tube MN3;

[0021] A fifth NMOS tube MN5, a drain electrode connected to the drain electrode of the PMOS tube MP2 and the gate electrode of the PMOS tube MP3, a gate electrode connected to the gate electrode of the NMOS tube MN4, and a source electrode connected to the gate electrode of the NMOS tube MN2 and the drain electrode of the NMOS tube MN3;

[0022] The first PMOS tube MP1 and the second PMOS tube MP2 have their sources connected to the voltage VDD and their gates connected to the gate of the PMOS tube MP3; the drain of the PMOS tube MP1 is connected to the drain of the NMOS tube MN4 and the gate of the NMOS tube MN5; the drain of the PMOS tube MP2 is connected to the drain of the NMOS tube MN5;

[0023] The third PMOS transistor MP3 has a source connected to the voltage VDD, a gate connected to the gates of the PMOS transistor MP1 and the PMOS transistor MP2, and a drain connected to the row selection switch.

[0024] Furthermore, the integration circuit is a capacitive feedback transimpedance structure, including a first integrating operational amplifier, three capacitors with different capacitances, a reset switch and two capacitor switching switches, wherein:

[0025] The negative input terminal of the first integrating operational amplifier is connected to the infrared detector via the row selection switch, and the positive input terminal is connected to the reference voltage;

[0026] One end of the first integrating capacitor C1 is connected to the negative input end of the first integrating operational amplifier, and the other end is connected to the output end of the first integrating operational amplifier;

[0027] The first capacitor switching switch S1 is connected to the negative input terminal of the first integrating operational amplifier; the first capacitor switching switch S1 and the third integrating capacitor C3 are connected in series and then connected in parallel with the first integrating capacitor C1;

[0028] The second capacitor switching switch S2 is connected to the negative input terminal of the first integrating operational amplifier; the second capacitor switching switch S2 is connected in series with the second integrating capacitor C2, and then connected in parallel with the first integrating capacitor C1;

[0029] One end of the reset switch RST is connected to the negative input end of the first integrating operational amplifier, and the other end of the reset switch RST is connected to the output end of the first integrating operational amplifier.

[0030] Furthermore, the double sampling circuit includes two sampling control switches and two sampling capacitors, wherein:

[0031] The first sampling control switch SHR and the second sampling control switch SHR are both connected to the output end of the integration circuit;

[0032] The first sampling capacitor C SHR The upper plate is connected to the first control switch SHR, and the lower plate is grounded;

[0033] The second sampling capacitor C SHS The upper plate is connected to the second control switch SHR, and the lower plate is grounded.

[0034] 5. The infrared detector readout circuit based on the dark current suppression structure according to claim 1, characterized in that the source follower comprises a first branch source follower and a second branch source follower, wherein:

[0035] The first branch source follower includes a seventh NMOS transistor MN7 and an eighth NMOS transistor MN8; the drain of the NMOS transistor MN7 is connected to the first column selection switch, the gate is connected to the output end of the double sampling circuit, and the source is connected to the input end of the differential amplifier circuit; the drain of the NMOS transistor MN8 is connected to the input end of the differential amplifier circuit, and the gate is connected to the voltage V b , source grounded;

[0036] The second branch source follower includes a tenth NMOS transistor MN10 and an eleventh NMOS transistor MN11; the drain of the NMOS transistor MN10 is connected to the second column selection switch, the gate is connected to the output end of the double sampling circuit, and the source is connected to the input end of the differential amplifier circuit; the drain of the NMOS transistor MN11 is connected to the input end of the differential amplifier circuit, and the gate is connected to the voltage V b , the source is grounded.

[0037] Furthermore, the differential amplifier circuit includes an operational amplifier and four resistors with equal resistance values, wherein: one end of the zeroth resistor R0 is connected to the first branch source follower, and the other end is connected to the negative input terminal of the second operational amplifier; one end of the first resistor R1 is connected to the negative input terminal of the second operational amplifier, and the other end is connected to the output terminal of the second operational amplifier; one end of the second resistor R2 is connected to the second branch source follower, and the other end is connected to the positive input terminal of the second operational amplifier; one end of the third resistor R3 is connected to the positive input terminal of the second operational amplifier, and the other end is grounded.

[0038] Furthermore, the row selection logic circuit uses a trigger, a NAND gate and a NOR gate to form a first counter to control the row selection logic;

[0039] The column selection logic circuit uses a trigger, a NAND gate and a NOR gate to form a second counter with a set terminal to control the column selection logic.

[0040] Further, the integration circuit includes a reset switch, and the sampling circuit includes two sampling control switches;

[0041] The control signals generated by the sequential logic circuit include: a row selection control signal, a column selection control signal, a reset control signal, a first sampling control signal and a second sampling control signal; the row selection switch is controlled by the row selection signal generated by the row selection logic circuit; the column selection switch is controlled by the column selection signal generated by the column selection logic circuit; the first sampling control switch, the second sampling control switch and the reset switch are controlled by the first sampling control signal, the second sampling control signal and the reset control signal generated by the sampling logic circuit.

[0042] Furthermore, the row parallel integration, column serial readout and sampling process of the sequential logic circuit includes:

[0043] The row selection switch is turned on, and the current signal of the first row of infrared detectors is input into the integration circuit; the reset switch is closed, the integration capacitor is reset, and the first sampling is performed before the reset switch is turned on; the reset switch is turned on, the integration capacitor integrates the input current, and the second sampling is performed just before the end of the integration, and the integration ends; the column selection switch is turned on, and the two sampling results are input into the differential amplifier circuit.

[0044] In a second aspect, an infrared detector readout device is provided, which uses the infrared detector readout circuit based on the dark current suppression structure described in the first aspect, and reads the current of the infrared detector in an array manner through row selection logic and column selection logic and outputs a voltage signal.

[0045] It can be seen from the above technical solution that the beneficial technical effects of the present invention are as follows:

[0046] 1. Improve the signal-to-noise ratio of the readout system by suppressing dark current; use a capacitive feedback transimpedance input stage structure and a high-gain operational amplifier to ensure good injection efficiency and output linearity.

[0047] 2. The function of column-by-column readout is realized through row selection logic, column selection logic, and sampling logic, which can effectively reduce the noise interference between the readout circuits in the array and reduce the layout area of ​​the readout circuit. It is suitable for preparing large-scale focal plane array readout circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for the specific embodiments or the prior art description. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn according to the actual scale.

[0049] Figure 1 1 is a schematic diagram of a unit structure of an infrared detector readout circuit based on a dark current suppression structure according to an embodiment of the present invention;

[0050] Figure 2 is the I generated by the dark current suppression circuit of the present invention dark Waveform diagram with temperature variation;

[0051] Figure 3 It is a schematic diagram of the first integrating operational amplifier and the bias structure in the integrating circuit of the present invention;

[0052] Figure 4 It is a working timing diagram of the row parallel integration, column serial readout and sampling process of the present invention;

[0053] Figure 5 It is a schematic diagram of the line selection logic circuit of the present invention;

[0054] Figure 6 It is a schematic diagram of the column selection logic circuit generated by the present invention;

[0055] Figure 7 It is a schematic diagram of the sampling logic circuit of the present invention;

[0056] Figure 8 is an output signal waveform diagram of the overall readout circuit of the present invention;

[0057] Fig. 9 It is the output signal linearity waveform diagram of the present invention. DETAILED DESCRIPTION

[0058] The following embodiments of the technical solution of the present invention are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and are therefore only used as examples, and cannot be used to limit the protection scope of the present invention.

[0059] It should be noted that, unless otherwise specified, the technical terms or scientific terms used in this application should have the common meanings understood by those skilled in the art to which the present invention belongs.

[0060] Example

[0061] In order to suppress dark current and improve signal-to-noise ratio, the inventors conducted the following research:

[0062] Changes in ambient temperature, ambient light, and thermal effects of electronic components in the readout circuit will affect the magnitude of the dark current in the dark state. Therefore, for detectors in different situations, adjustable suppression current is a very important factor, which can accurately suppress the dark current in different environments.

[0063] High sensitivity and high dynamic range are important parameters of the readout circuit. Therefore, while suppressing the dark current, it is also necessary to consider ensuring the injection efficiency of the input stage of the infrared detector readout circuit and the good output linearity of the output stage. Typical input stages of the infrared detector readout circuit include: self-integration structure, direct injection structure, source follower structure, capacitive feedback transimpedance structure, etc. Among them, the capacitive feedback transimpedance structure has the characteristics of high injection efficiency, stable bias voltage, and high linearity. The infrared detector is connected to the input end of the op amp. Due to the large input impedance of the op amp, the output resistance of the infrared detector has little effect on the injection efficiency; according to Miller's law, the equivalent input capacitance is (1+A)Cint, which can reduce input noise. The gain of the amplifier in the capacitive feedback transimpedance structure is adjustable, and the injection efficiency can be improved by increasing the gain. Different integral capacitors are required for different light intensities. When the light intensity is large, the photocurrent generated is also large. To prevent oversaturation, a larger integral capacitor is required; when the light intensity is small, the photocurrent generated is also small. A smaller integral capacitor is required to improve the injection efficiency.

[0064] Regarding the mutual interference between dark current and noise of each readout circuit, the inventor discovered through research and development that it is mainly because the timing logic is complex and chaotic. Therefore, a simple and appropriate timing logic is needed to reduce the noise interference of high-frequency timing on the readout circuit.

[0065] In combination with the above research results, this embodiment provides an infrared detector readout circuit based on a dark current suppression structure. Through the working mode of integration first and then readout, the current signal output by the detection is subjected to dark current suppression, integration, double sampling, differentiation, and buffer output in the manner of row parallel integration and column serial readout to complete one frame of image acquisition. The circuit unit structure is as follows: Figure 1 As shown, including:

[0066] The dark current suppression circuit, integration circuit, dual sampling circuit, source follower, differential amplifier circuit, output buffer circuit, which are electrically connected in sequence, also include a sequential logic circuit, wherein the sequential logic circuit includes a row selection logic circuit, a column selection logic circuit and a sampling logic circuit, the row selection logic circuit includes a row selection switch arranged between the dark current suppression circuit and the integration circuit, the column selection logic circuit includes a column selection switch connected to the source follower, and the sampling logic circuit is used to provide sampling timing to the dual sampling circuit. The following is a description of each circuit:

[0067] 1. Dark current suppression circuit

[0068] The dark current suppression circuit is used to realize the current regulation function and the current mirror function, including 2 bipolar PNP transistors, 6 NMOS field effect transistors and 3 PMOS field effect transistors. Specifically:

[0069] The base and collector of the first bipolar PNP transistor B1 and the second bipolar PNP transistor B2 are grounded; the emitter of the transistor B1 is connected to the drain of the NMOS transistor MN0, and the emitter of the transistor B2 is connected to the drain of the NMOS transistor MN1.

[0070] The gates of the zeroth NMOS tube MN0 and the first NMOS tube MN1 are connected, and the gate voltage can be adjusted to Vc; the sources of the NMOS tubes MN0 and MN1 are grounded, the drain of the NMOS tube MN0 is connected to the emitter of the transistor B1, and the drain of the NMOS tube MN1 is connected to the emitter of the transistor B2.

[0071] The second NMOS tube MN2 has a drain connected to the gate of the NMOS tube MN3 and the source of the NMOS tube MN4, a gate connected to the drain of the NMOS tube MN3 and the source of the NMOS tube MN5, and a source connected to the drain of the NMOS tube MN0.

[0072] The third NMOS tube MN3 has a drain connected to the gate of the NMOS tube MN2 and the source of the NMOS tube MN5, a gate connected to the drain of the NMOS tube MN2 and the source of the NMOS tube MN4, and a source connected to the drain of the NMOS tube MN1.

[0073] The fourth NMOS tube MN4 has a drain connected to the drain of the PMOS tube MP1 and the gate of the NMOS tube MN5 , a gate connected to the gate of the NMOS tube MN5 , and a source connected to the drain of the NMOS tube MN2 and the gate of the NMOS tube MN3 .

[0074] The fifth NMOS transistor MN5 has a drain connected to the drain of the PMOS transistor MP2 and the gate of the PMOS transistor MP3, a gate connected to the gate of the NMOS transistor MN4, and a source connected to the gate of the NMOS transistor MN2 and the drain of the NMOS transistor MN3.

[0075] The first PMOS tube MP1 and the second PMOS tube MP2 have sources connected to the voltage VDD and gates connected to the gate of the PMOS tube MP3; the drain of the PMOS tube MP1 is connected to the drain of the NMOS tube MN4 and the gate of the NMOS tube MN5; the drain of the PMOS tube MP2 is connected to the drain of the NMOS tube MN5.

[0076] The third PMOS transistor MP3 has a source connected to the voltage VDD, a gate connected to the gates of the PMOS transistor MP1 and the PMOS transistor MP2, and a drain connected to the row selection switch.

[0077] The dark current suppression circuit uses the negative temperature coefficient of the base-emitter voltage of a single transistor and the positive temperature coefficient of the base-emitter voltage difference of two transistors with different current densities to perform temperature compensation to generate a current with a low temperature coefficient. By controlling the gate voltage Vc of the NMOS tube in the linear region, the current in the branch is controlled to achieve the function of current adjustment and generate a controllable current that is not affected by temperature changes; then the current of the branch is mirrored to I dark Offset the dark current of infrared detectors. Figure 1 Middle I det is the net photocurrent I D and I used to offset the dark current dark The sum of I det The circuit pointed by the arrow is the equivalent model of the infrared detector, including I D , resistor R D and capacitor C D .

[0078] refer to Figure 2 , is the I generated by the dark current suppression circuit dark The waveform changes with temperature. In the temperature range of -20℃~90℃, I dark The maximum offset is 0.032μA.

[0079] 2. Integrator circuit

[0080] The integration circuit is used to integrate and amplify the net photocurrent and convert it into a voltage signal. It is a capacitor feedback transimpedance structure integration circuit, including a first integration operational amplifier composed of a high-gain folded common source and common gate amplifier with a PMOS input, three capacitors with different capacitances, a reset switch and two capacitor switching switches. The input stage of the capacitor feedback transimpedance structure adopts a high-gain operational amplifier to ensure good injection efficiency and output linearity. Specifically:

[0081] The negative input terminal of the first integrating operational amplifier is connected to the infrared detector via the row selection switch, and the positive input terminal is connected to the reference voltage;

[0082] One end of the first integrating capacitor C1 is connected to the negative input end of the first integrating operational amplifier, and the other end is connected to the output end of the first integrating operational amplifier;

[0083] The first capacitor switching switch S1 is connected to the negative input terminal of the first integrating operational amplifier; the first capacitor switching switch S1 and the third integrating capacitor C3 are connected in series and then connected in parallel with the first integrating capacitor C1;

[0084] The second capacitor switching switch S2 is connected to the negative input terminal of the first integrating operational amplifier; the second capacitor switching switch S2 is connected in series with the second integrating capacitor C2, and then connected in parallel with the first integrating capacitor C1;

[0085] One end of the reset switch RST is connected to the negative input end of the first integrating operational amplifier, and the other end is connected to the output end of the first integrating operational amplifier;

[0086] When working, the reset switch is controlled by the sampling logic circuit to generate a reset control signal to control the integration process and the reset process; the capacitor switching switch controls the integration capacitor used for different input currents. The row selection switch is used to select the readout pixel row, the integration switch is turned on, and the integration capacitor integrates; the integration switch is turned off and the integration capacitor is reset. The current under different light intensities is adjusted through the capacitor switching switch to prevent oversaturation.

[0087] refer to Figure 3 , is a schematic diagram of the internal circuit structure of the first integrating operational amplifier. This structure is a single-stage amplifier. The amplifier has a large gain and does not require Miller compensation. The first integrating operational amplifier has a positive input connected to a reference voltage and an inverting input connected to an infrared detector pixel, providing a stable bias voltage for the infrared detector. The op amp bias uses a wide swing current mirror to increase the output swing of the op amp.

[0088] 3. Double sampling circuit

[0089] A double sampling circuit is used to suppress the noise of the voltage signal output by the integration circuit and output the sampling voltage; it includes two sampling control switches and two sampling capacitors;

[0090] The first sampling control switch SHR and the second sampling control switch SHR are both connected to the output end of the integration circuit;

[0091] The first sampling capacitor C SHR The upper plate is connected to the first control switch SHR, and the lower plate is grounded;

[0092] The second sampling capacitor C SHS The upper plate is connected to the second control switch SHR, and the lower plate is grounded.

[0093] When working, the first sampling control signal and the second sampling control signal generated by the sampling logic circuit in the sequential logic circuit control the on and off of the first sampling control switch and the second sampling control switch, and control the sampling state and the holding state. The entire sampling process is divided into the first sampling and the second sampling. After the two samplings are completed, the column selection switch is controlled by the column selection logic circuit in the sequential logic circuit, and the sampling result is output to the source follower.

[0094] 4. Source Follower

[0095] The source follower is used to output the sampled voltage to the differential amplifier circuit after buffering, and comprises a first branch source follower and a second branch source follower; wherein:

[0096] The first branch source follower includes a seventh NMOS transistor MN7 and an eighth NMOS transistor MN8; the drain of the NMOS transistor MN7 is connected to the first column selection switch, the gate is connected to the output end of the double sampling circuit, and the source is connected to the input end of the differential amplifier circuit; the drain of the NMOS transistor MN8 is connected to the input end of the differential amplifier circuit, and the gate is connected to the voltage V b , the source is grounded.

[0097] The second branch source follower includes a tenth NMOS transistor MN10 and an eleventh NMOS transistor MN11; the drain of the NMOS transistor MN10 is connected to the second column selection switch, the gate is connected to the output end of the double sampling circuit, and the source is connected to the input end of the differential amplifier circuit; the drain of the NMOS transistor MN11 is connected to the input end of the differential amplifier circuit, and the gate is connected to the voltage V b , the source is grounded.

[0098] The first sampling result and the second sampling result are buffered by the source followers in the two branches and then output to the differential amplifier circuit.

[0099] 5. Differential amplifier circuit

[0100] The differential amplifier circuit is used to perform differential operation on the buffered sampling voltage, including an operational amplifier and four resistors; specifically:

[0101] One end of the zeroth resistor R0 is connected to the first branch source follower, and the other end is connected to the negative input terminal of the second operational amplifier;

[0102] One end of the first resistor R1 is connected to the negative input end of the second operational amplifier, and the other end is connected to the output end of the second operational amplifier;

[0103] One end of the second resistor R2 is connected to the second branch source follower, and the other end is connected to the positive input terminal of the second operational amplifier;

[0104] One end of the third resistor R3 is connected to the positive input terminal of the second operational amplifier, and the other end is grounded.

[0105] When working, the differential amplifier circuit uses the "virtual short" and "virtual open" characteristics of the high-gain second operational amplifier and the characteristics of the negative feedback circuit to set the resistance values ​​of the four resistors to be equal, thereby achieving the purpose of subtracting the results of two samplings, and inputting the differential result into the output buffer circuit.

[0106] 6. Output buffer circuit

[0107] The output buffer circuit drives the output through the high-gain third operational amplifier, and the output signal is the read voltage signal.

[0108] 7. Sequential logic circuit

[0109] The timing logic circuit is used to provide row selection logic, column selection logic and sampling timing when selecting the target pixel from the infrared detector pixel array. When the target pixel of the infrared detector is connected to the readout circuit, the readout circuit can read the current signal of the target pixel according to the row selection logic, column selection logic and sampling timing.

[0110] The control signals generated by the sequential logic circuit include: a row selection control signal, a column selection control signal, a reset control signal, a first sampling control signal and a second sampling control signal; the row selection switch is controlled by the row selection signal generated by the row selection logic circuit; the column selection switch is controlled by the column selection signal generated by the column selection logic circuit; the first sampling control switch, the second sampling control switch and the reset switch are controlled by the first sampling control signal, the second sampling control signal and the reset control signal generated by the sampling logic circuit.

[0111] refer to Figure 4 , which is a timing diagram of the row parallel integration, column serial readout and sampling process of the sequential logic circuit. The specific working process is: the row selection switch H is turned on, and the current signal of the first row of infrared detectors is input into the integration circuit; the reset switch is closed, the integration capacitor is reset, and the first sampling is performed before the reset switch is turned on; the reset switch is turned on, the integration capacitor integrates the input current, and the second sampling is performed just before the end of the integration, and the integration ends; the column selection switch Q is turned on, and the two sampling results are input into the differential amplifier structure, and the difference between the two sampling results is taken.

[0112] In a specific implementation, the row selection logic circuit uses a trigger, a NAND gate, and a NOR gate to form a first counter to control the row selection logic. The schematic diagram of the row selection logic circuit is shown in FIG. Figure 5 ;

[0113] The column selection logic circuit uses a trigger, a NAND gate, and a NOR gate to form a second counter with a set terminal to control the column selection logic. The schematic diagram of the column selection logic circuit is shown in Figure 6 ;

[0114] Sampling Logic Circuit Schematic Reference Figure 7 ; List the driving equations for the integration process, Driving equation for the sampling process The reset signal and the second sampling signal are followed by a trigger to delay one cycle, so that the complete integration and sampling timing can be obtained.

[0115] For an example of adopting the technical solution of this embodiment, refer to Figure 8, is the output waveform of the entire readout circuit under the net photocurrent of 100nA, 200nA, 300nA, 400nA, 500nA, 600nA, 700nA, and 800nA, with an integration time of 4μS, and a row output by column. In this example, the integration capacitor in the integration circuit is 150fF (femtofarad) and the power supply voltage is 5V.

[0116] refer to Fig. 9 , is the output signal linearity waveform. According to the IV curves of input current and output voltage, it can be observed that the output voltage linearity of the readout circuit is very good.

[0117] In some embodiments, an infrared detector readout device is also provided, which uses the infrared detector readout circuit based on the dark current suppression structure described above, reads the current of the infrared detector in an array manner through row selection logic and column selection logic, and outputs a voltage signal.

[0118] The technical solution of this embodiment can generate a controllable current that is not affected by temperature changes to suppress the dark current generated by the detector; a capacitive feedback transimpedance input stage structure is used, and a high-gain operational amplifier is adopted to ensure good injection efficiency and output linearity; the function of column readout is realized through row selection logic, column selection logic, and sampling logic, which can effectively reduce the noise interference between the readout circuits in the array and reduce the layout area of ​​the readout circuit, and is suitable for preparing a large-array-scale focal plane array readout circuit.

[0119] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be included in the scope of the claims and specification of the present invention.

Claims

1. An infrared detector readout circuit based on a dark current suppression structure, characterized in that: include: A dark current suppression circuit, an integration circuit, a double sampling circuit, a source follower, a differential amplifier circuit and an output buffer circuit electrically connected in sequence, and also includes a sequential logic circuit; The dark current suppression circuit is used to generate a controllable current that is not affected by temperature changes, and the current is mirrored to offset the dark current of the infrared detector to obtain a net photocurrent; The integration circuit is used to integrate and amplify the net photocurrent and convert it into a voltage signal; The double sampling circuit is used to suppress the noise of the voltage signal and output a sampled voltage; The source follower is used to buffer the sampled voltage; The differential amplifier circuit is used to perform differential operation on the buffered sampled voltage; The output buffer circuit is used for buffering the voltage signal read out from the output; The timing logic circuit is used to provide row selection logic, column selection logic and sampling timing when selecting target pixels from the infrared detector pixel array; The timing logic circuit includes a row selection logic circuit, a column selection logic circuit and a sampling logic circuit. The row selection logic circuit includes a row selection switch arranged between the dark current suppression circuit and the integration circuit. The column selection logic circuit includes a column selection switch connected to the source follower. The sampling logic circuit is used to provide sampling timing to the dual sampling circuit.

2. The infrared detector readout circuit based on the dark current suppression structure according to claim 1, characterized in that: The dark current suppression circuit includes 2 bipolar PNP transistors, 6 NMOS field effect transistors and 3 PMOS field effect transistors, wherein: The base and collector of the first bipolar PNP transistor B1 and the second bipolar PNP transistor B2 are grounded; the emitter of the transistor B1 is connected to the drain of the NMOS transistor MN0, and the emitter of the transistor B2 is connected to the drain of the NMOS transistor MN1; The gates of the zeroth NMOS tube MN0 and the first NMOS tube MN1 are connected, and the gate voltage is adjustable; the sources of the NMOS tubes MN0 and MN1 are grounded, the drain of the NMOS tube MN0 is connected to the emitter of the transistor B1, and the drain of the NMOS tube MN1 is connected to the emitter of the transistor B2; The second NMOS tube MN2 has a drain connected to the gate of the NMOS tube MN3 and the source of the NMOS tube MN4, a gate connected to the drain of the NMOS tube MN3 and the source of the NMOS tube MN5, and a source connected to the drain of the NMOS tube MN0; The third NMOS tube MN3 has a drain connected to the gate of the NMOS tube MN2 and the source of the NMOS tube MN5, a gate connected to the drain of the NMOS tube MN2 and the source of the NMOS tube MN4, and a source connected to the drain of the NMOS tube MN1; The fourth NMOS tube MN4 has a drain connected to the drain of the PMOS tube MP1 and the gate of the NMOS tube MN5, a gate connected to the gate of the NMOS tube MN5, and a source connected to the drain of the NMOS tube MN2 and the gate of the NMOS tube MN3; A fifth NMOS tube MN5, a drain electrode connected to the drain electrode of the PMOS tube MP2 and the gate electrode of the PMOS tube MP3, a gate electrode connected to the gate electrode of the NMOS tube MN4, and a source electrode connected to the gate electrode of the NMOS tube MN2 and the drain electrode of the NMOS tube MN3; The first PMOS tube MP1 and the second PMOS tube MP2 have their sources connected to the voltage VDD and their gates connected to the gate of the PMOS tube MP3; the drain of the PMOS tube MP1 is connected to the drain of the NMOS tube MN4 and the gate of the NMOS tube MN5; the drain of the PMOS tube MP2 is connected to the drain of the NMOS tube MN5; The third PMOS transistor MP3 has a source connected to the voltage VDD, a gate connected to the gates of the PMOS transistor MP1 and the PMOS transistor MP2, and a drain connected to the row selection switch.

3. The infrared detector readout circuit based on the dark current suppression structure according to claim 1, characterized in that: The integration circuit is a capacitive feedback transimpedance structure, including a first integrating operational amplifier, three capacitors with different capacitances, a reset switch and two capacitor switching switches, wherein: The negative input terminal of the first integrating operational amplifier is connected to the infrared detector via the row selection switch, and the positive input terminal is connected to the reference voltage; One end of the first integrating capacitor C1 is connected to the negative input end of the first integrating operational amplifier, and the other end is connected to the output end of the first integrating operational amplifier; The first capacitor switching switch S1 is connected to the negative input terminal of the first integrating operational amplifier; the first capacitor switching switch S1 and the third integrating capacitor C3 are connected in series and then connected in parallel with the first integrating capacitor C1; The second capacitor switching switch S2 is connected to the negative input terminal of the first integrating operational amplifier; the second capacitor switching switch S2 is connected in series with the second integrating capacitor C2, and then connected in parallel with the first integrating capacitor C1; One end of the reset switch RST is connected to the negative input end of the first integrating operational amplifier, and the other end of the reset switch RST is connected to the output end of the first integrating operational amplifier.

4. The infrared detector readout circuit based on the dark current suppression structure according to claim 1, characterized in that: The double sampling circuit includes two sampling control switches and two sampling capacitors, wherein: The first sampling control switch SHR and the second sampling control switch SHR are both connected to the output end of the integration circuit; The first sampling capacitor C SHR The upper plate is connected to the first control switch SHR, and the lower plate is grounded; The second sampling capacitor C SHS The upper plate is connected to the second control switch SHR, and the lower plate is grounded.

5. The infrared detector readout circuit based on the dark current suppression structure according to claim 1, characterized in that: The source follower comprises a first branch source follower and a second branch source follower, wherein: The first branch source follower includes a seventh NMOS transistor MN7 and an eighth NMOS transistor MN8; the drain of the NMOS transistor MN7 is connected to the first column selection switch, the gate is connected to the output end of the double sampling circuit, and the source is connected to the input end of the differential amplifier circuit; the drain of the NMOS transistor MN8 is connected to the input end of the differential amplifier circuit, and the gate is connected to the voltage V b , source grounded; The second branch source follower includes a tenth NMOS transistor MN10 and an eleventh NMOS transistor MN11; the drain of the NMOS transistor MN10 is connected to the second column selection switch, the gate is connected to the output end of the double sampling circuit, and the source is connected to the input end of the differential amplifier circuit; the drain of the NMOS transistor MN11 is connected to the input end of the differential amplifier circuit, and the gate is connected to the voltage V b , the source is grounded.

6. The infrared detector readout circuit based on the dark current suppression structure according to claim 1, characterized in that: The differential amplifier circuit includes an operational amplifier and four resistors with equal resistance values, wherein: One end of the zeroth resistor R0 is connected to the first branch source follower, and the other end is connected to the negative input terminal of the second operational amplifier; One end of the first resistor R1 is connected to the negative input end of the second operational amplifier, and the other end is connected to the output end of the second operational amplifier; One end of the second resistor R2 is connected to the second branch source follower, and the other end is connected to the positive input terminal of the second operational amplifier; One end of the third resistor R3 is connected to the positive input terminal of the second operational amplifier, and the other end is grounded.

7. The infrared detector readout circuit based on the dark current suppression structure according to claim 1, characterized in that: The row selection logic circuit uses a trigger, a NAND gate and a NOR gate to form a first counter to control the row selection logic; The column selection logic circuit uses a trigger, a NAND gate and a NOR gate to form a second counter with a set terminal to control the column selection logic.

8. The infrared detector readout circuit based on the dark current suppression structure according to claim 1, characterized in that: The integration circuit includes a reset switch, and the sampling circuit includes two sampling control switches; The control signals generated by the sequential logic circuit include: a row selection control signal, a column selection control signal, a reset control signal, a first sampling control signal and a second sampling control signal; the row selection switch is controlled by the row selection signal generated by the row selection logic circuit; the column selection switch is controlled by the column selection signal generated by the column selection logic circuit; the first sampling control switch, the second sampling control switch and the reset switch are controlled by the first sampling control signal, the second sampling control signal and the reset control signal generated by the sampling logic circuit.

9. The infrared detector readout circuit based on the dark current suppression structure according to claim 7, characterized in that: The row parallel integration, column serial readout and sampling process of the sequential logic circuit includes: The row selection switch is turned on, and the current signal of the first row of infrared detectors is input into the integration circuit; the reset switch is closed, the integration capacitor is reset, and the first sampling is performed before the reset switch is turned on; the reset switch is turned on, the integration capacitor integrates the input current, and the second sampling is performed just before the end of the integration, and the integration ends; the column selection switch is turned on, and the two sampling results are input into the differential amplifier circuit.

10. An infrared detector readout device, characterized in that: Using the infrared detector readout circuit based on the dark current suppression structure described in any one of claims 1 to 9, the current of the infrared detector is read in array form through row selection logic and column selection logic, and a voltage signal is output.

Images