FPGA function test method and device based on IOBUF

Abstract

An IOBUF-based FPGA function test method and device are used for performing function test on an IOBUF or other modules of an FPGA, and the method comprises the following steps: when a to-be-tested module is an IOBUF, after test data are input into an IOBUF output path, acquiring recovery data through an IOBUF input path, and determining whether the function of the IOBUF is normal based on the test data and the recovery data; when the to-be-tested module is other modules, after the test data are input into the IOBUF output path, the recovery data are obtained through the IOBUF input path, the recovery data are input into the to-be-tested module, output data are obtained, and whether the function of the to-be-tested module is normal or not is determined based on the test data and the output data; or the test data is input into the to-be-tested module, the output data of the to-be-tested module is input into the IOBUF to obtain the recovery data, whether the function of the to-be-tested module is normal or not is determined based on the test data and the recovery data, the test does not depend on the performance of the ATE test machine, the test of different modules is based on the test mode of the IOBUF, the test mode is simple, maintenance and management are easy, and the test efficiency is high. And the FPGA function test efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to an IOBUF-based FPGA functional testing method and device. Background Art

[0002] At present, automatic test equipment (ATE for short, full name Automatic Test Equipment) is generally used to test FPGA. ATE can automatically complete the function, performance and reliability test of FPGA. With the development of integrated circuits, FPGA chips are becoming more and more integrated, with larger areas and more and more complex functions. The number of chip IOs is also increasing, and the number of circuit modules supporting IO is also increasing. Correspondingly, the number and types of functional modules increase, and more and more test modes are required. ATE also needs to modify the test mode to meet the test of FPGAs with different packaging structures, resulting in more and more bloated test modes of ATE, which is quite difficult to manage and maintain. In addition, the ATE test method depends on the performance of the ATE test machine, which is not friendly to the high-frequency test of FPGA. The test difficulty is increasing. There is an urgent need for a universal and concise test method to improve the efficiency of FPGA functional testing. Summary of the invention

[0003] The embodiment of the present application provides an IOBUF-based FPGA functional testing method and device, which is independent of the performance of an ATE tester and is more likely to implement high-frequency testing. The testing of different modules is based on the IOBUF test mode, and the test mode is simple and easy to maintain and manage, thereby improving the efficiency of FPGA functional testing.

[0004] On the one hand, an embodiment of the present application provides an IOBUF-based FPGA functional testing method for performing functional testing on the IOBUF of the FPGA or other modules other than the IOBUF, including: When the module to be tested is the IOBUF, after the test data is input into the IOBUF output path, the recovered data is obtained through the IOBUF input path, and whether the function of the IOBUF is normal is determined based on the test data and the recovered data; When the module to be tested is the other module, after the test data is input into the IOBUF output path, the collected data is obtained through the IOBUF input path, the collected data is input into the module to be tested and the output data is obtained, and whether the function of the module to be tested is normal is determined based on the test data and the output data; or, the test data is input into the module to be tested, the output data of the module to be tested is input into the IOBUF to obtain the collected data, and whether the function of the module to be tested is normal is determined based on the test data and the collected data.

[0005] On the other hand, the embodiment of the present application further provides an IOBUF-based FPGA functional testing device, comprising: IOBUF, used to perform functional testing on the IOBUF or other modules of the FPGA, including an IOBUF output path and an IOBUF input path; When the module to be tested is the IOBUF, the IOBUF is used to input the test data into the IOBUF output path, and then obtain the recovered data through the IOBUF input path, wherein the recovered data is used to determine whether the function of the IOBUF is normal in combination with the test data; When the module to be tested is the other module, the IOBUF is used to input the test data into the IOBUF output path, and then obtain the recovered data through the IOBUF input path, wherein the recovered data is used to input the module to be tested to obtain output data, and the output data is used to determine whether the function of the module to be tested is normal in combination with the test data; or, the IOBUF is used to input the output data of the module to be tested into the IOBUF to obtain the recovered data, wherein the output data is obtained after the test data is input into the module to be tested, and the recovered data is used to determine whether the function of the module to be tested is normal in combination with the test data.

[0006] Compared with the related art, the FPGA functional testing method and device based on IOBUF in the embodiment of the present application can conveniently test each module in the FPGA based on the built-in IOBUF of the FPGA, does not rely on the performance of the ATE tester, and is easier to implement high-frequency testing. It can not only implement the test of the IOBUF, but also combine the IOBUF with other modules to implement the test of other modules. The tests of different modules are all based on the test mode of the IOBUF. The test mode is simple, easy to maintain and manage, and the efficiency of FPGA functional testing is improved.

[0007] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0009] Figure 1 A flow chart of an IOBUF-based FPGA functional testing method according to an embodiment of the present application; Figure 2A test diagram of IOBUF of an embodiment of the present application; Figure 3 A schematic diagram of a serial-to-parallel test of an IOL according to an embodiment of the present application; Figure 4 A schematic diagram of a parallel-to-serial test of an IOL according to an embodiment of the present application; Figure 5 A schematic diagram of an IOBUF-based FPGA functional testing device according to an embodiment of the present application; Figure 6 A schematic diagram of another IOBUF-based FPGA functional testing device according to an embodiment of the present application; Figure 7 A schematic diagram of a data input controller according to an embodiment of the present application; Figure 8 A schematic diagram of a data output controller according to an embodiment of the present application; Fig. 9 A schematic diagram of an IOBUF function test device according to an embodiment of the present application; Fig.10 Schematic diagram of other module function test device based on IOBUF of FPGA in the embodiment of the present application Figure 1 ; Fig.11 Schematic diagram of other module function test device based on IOBUF of FPGA in the embodiment of the present application Figure 2 . DETAILED DESCRIPTION

[0010] The present application describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present application. Although many possible feature combinations are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0011] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in the present application may also be combined with any conventional features or elements to form a unique invention scheme. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme. Therefore, it should be understood that any feature shown and / or discussed in the present application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other restrictions. In addition, various modifications and changes may be made within the scope of protection of the attached claims.

[0012] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps of the specific order described. As will be understood by those of ordinary skill in the art, other sequences of steps are also possible. Therefore, the specific sequence of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to the steps of performing them in the order written, and those skilled in the art can easily understand that these sequences can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0013] There are many kinds of functional modules in FPGA. In order to achieve stable and reliable operation of FPGA, it is necessary to perform functional tests on each module of FPGA. For example, the circuits that implement data input and output functions in FPGA include IOBUF (Input / Output Buffer) and IOL (Input / Output Logic). Generally, each input and output pin PAD corresponds to an IOBUF. IOBUF can send the signal generated by the internal logic of FPGA to external devices, and can also receive input signals from external devices and convert them into the level required by the internal logic of FPGA. IOL is the I / O logic unit in FPGA, which mainly realizes data interaction between FPGA fabric and IOBUF.

[0014] As the integration of FPGA chips becomes higher and higher, the functions become more and more complex, and the chip area becomes larger and larger, the testing requirements for various functional modules of FPGA are also increasing, and the testing difficulty is also increasing. This includes the functional testing of IOBUF and IOL. In the existing ATE testing technology, FPGAs with different package structures require different test modes. Even in FPGAs with the same package structure, different test modes are used for testing different modules such as IOBUF and IOL, resulting in more and more test modes for ATE testers, which are becoming more and more bloated. The existing ATE testing technology often applies test logic to the module to be tested of the FPGA to make the PAD output data, and uses the ATE tester to test the accuracy of the PAD output data, or the ATE tester inputs data to the PAD, outputs it to the PAD after passing through the internal logic of the module to be tested, and uses the ATE tester to test the accuracy of the PAD output data. Such a testing method is limited by the performance of the ATE tester during high-frequency testing and cannot achieve efficient testing of FPGAs.

[0015] The embodiment of the present application provides an IOBUF-based FPGA functional testing method for performing functional testing on the IOBUF of the FPGA or other modules other than the IOBUF, including steps S100-S200, such as Figure 1 As shown: S100: when the module to be tested is the IOBUF, after inputting the test data into the IOBUF output path, acquiring the recovered data through the IOBUF input path, and determining whether the function of the IOBUF is normal based on the test data and the recovered data; S200: When the module to be tested is the other module, after the test data is input into the IOBUF output path, the collected data is obtained through the IOBUF input path, the collected data is input into the module to be tested and the output data is obtained, and whether the function of the module to be tested is normal is determined based on the test data and the output data; or, the test data is input into the module to be tested, the output data of the module to be tested is input into the IOBUF to obtain the collected data, and whether the function of the module to be tested is normal is determined based on the test data and the collected data.

[0016] In this embodiment, the IOBUF-based FPGA functional testing method can be used for functional testing of IOBUF and other modules in FPGA. Other modules include IOL, EBR (full name Embedded Block RAM, embedded block random access memory), DSP (full name Digital Signal Processor, digital signal processor), registers, latches and other modules in FPGA.

[0017] In this embodiment, the IOBUF output path is a path for the FPGA to output data to the outside, and the IOBUF input path is a path for the outside to input data to the FPGA; when executing step S100, when the IOBUF of the FPGA is functionally tested, the test data is output through the IOBUF output path, and then retrieved into the FPGA through the IOBUF input path to obtain the retrieved data, and the functional test of the IOBUF can be implemented based on the retrieved data and the test data.

[0018] In this embodiment, when executing step S200, other modules serving as modules to be tested are combined with IOBUF, and the modules to be tested are connected to IOBUF in a one-to-one correspondence. Step S200 includes two testing methods: the first testing method is to output the test data through the IOBUF output path, and then retrieve it to the inside of the FPGA through the IOBUF input path to obtain the recovered data, input the recovered data to the module to be tested to obtain the output data, and implement the functional test of the module to be tested based on the output data and the test data; the second testing method is to input the test data into the module to be tested to obtain the output data, output the output data through the IOBUF output path, and then retrieve it to the inside of the FPGA through the IOBUF input path to obtain the recovered data, and implement the functional test of the module to be tested based on the recovered data and the test data.

[0019] In this embodiment, step S100 may be performed first, and after determining that the IOBUF functions normally, step S200 may be performed using the IOBUF that functions normally.

[0020] The IOBUF-based FPGA functional testing method in this embodiment can conveniently test each module in the FPGA based on the built-in IOBUF of the FPGA, does not rely on the performance of the ATE tester, and is easier to implement high-frequency testing. It can not only implement the test of the IOBUF, but also combine the IOBUF with other modules to implement the test of other modules. The tests of different modules are all based on the test mode of the IOBUF. The test mode is simple, easy to maintain and manage, and improves the efficiency of the FPGA functional testing.

[0021] In an exemplary embodiment, the "after inputting the test data into the IOBUF output path, obtaining the recovered data through the IOBUF input path" in step S100 and step S200 may include: After the test data is input into the IOBUF output path, it is input into the IOBUF input path after passing through the input / output pin PAD corresponding to the IOBUF, and the recovered data is obtained at the recovery end of the IOBUF; The recovery end of the IOBUF is the data output end of the IOBUF input path, and the IOBUF and PAD correspond one to one, such as Figure 2shown.

[0022] In this embodiment, IOBUF includes an input end, an output end and a recovery end. The input end and the output end are two sections of the IOBUF output path. The output end is connected to PAD (full name Peripheral Access Device). IOBUF and PAD correspond one to one. PAD is an input and output pin located at the periphery of FPGA, which is responsible for the connection, communication and data transmission between FPGA and the outside, and supports bidirectional data transmission. The data returned by PAD is transmitted to the recovery end through the IOBUF input path. For the functional test of IOBUF, the data flow is: test data - IOBUF output path - PAD - IOBUF input path - recovery end obtains recovery data, such as Figure 2 As shown, Figure 2 The dashed lines in the figure represent data flow.

[0023] In an exemplary embodiment, step S100 may include steps S110 and S120: S110: when the single-ended input / output function test is performed on the IOBUF, after the test data is input into the single-ended output path of the IOBUF, data is retrieved through the single-ended input path of the IOBUF to obtain the retrieved data; S120: When performing a differential input / output function test on the IOBUF, after the test data is input into the IOBUF differential output path, data is retrieved through the IOBUF differential input path to obtain the retrieved data.

[0024] In this embodiment, step S110 is a test of the single-ended input and output function of the IOBUF. When the single-ended input and output function of the IOBUF is normal, the IOBUF single-ended output path and the IOBUF single-ended input path will not change the data flowing through, and the retrieved data is consistent with the test data; otherwise, when the single-ended input and output function of the IOBUF is abnormal, the IOBUF single-ended output path or the IOBUF single-ended input path may change the data flowing through, resulting in inconsistency between the retrieved data and the test data.

[0025] In this embodiment, step S120 is a test of the differential input and output function of IOBUF. When the differential input and output function of IOBUF is normal, the IOBUF differential output path and the IOBUF differential input path will not change the data flowing through, and the retrieved data will be consistent with the test data; otherwise, when the differential input and output function of IOBUF is abnormal, the IOBUF differential output path or the IOBUF differential input path may change the data flowing through, resulting in inconsistency between the retrieved data and the test data.

[0026] In an exemplary embodiment, when the module to be tested is an IO logic unit IOL, and a serial-to-parallel function test is performed on the IOL, the input end of the IOL is connected to the return end of the IOBUF, such as Figure 3 As shown, the step S200 of "after inputting the test data into the IOBUF output path, obtaining the recovered data through the IOBUF input path, inputting the recovered data into the module to be tested and obtaining the output data, and determining whether the function of the module to be tested is normal based on the test data and the output data" may include steps S211-S213: S211: After the serial test data is input into the IOBUF single-ended output path, data is retrieved through the IOBUF single-ended input path to obtain the retrieved data; S212: inputting the retrieved data into the IOL for serial-to-parallel data conversion, and obtaining parallel output data at the output end of the IOL; S213: Determine whether the serial-to-parallel conversion function of the IOL is normal based on the serial test data and the parallel output data.

[0027] In this embodiment, IOBUF corresponds to IOL one by one, and the serial-to-parallel function test of IOL can be implemented by executing steps S211-S213. The serial-to-parallel conversion of IOL can realize the IDES8 (Input Serial-to-Parallel Converter with 8-bit Data Width) mode of FPGA; before executing steps S211-S213, the recovery end of IOBUF needs to be connected to the input end of IOL. The data flow of IOBUF in step S211 is the same as that in step S100, but step S212 needs to be executed for the recovered data, that is, the recovered data is input into the IOL to be tested, and the serial-to-parallel data conversion is implemented for the recovered data to generate parallel output data. The serial-to-parallel function test of IOL is implemented based on the parallel output data and serial test data. The data flow is: serial test data-IOBUF output channel-PAD-IOBUF input channel-the recovery end obtains the recovered data-IOL performs serial-to-parallel conversion-parallel output data, such as Figure 3 As shown, Figure 3 The dotted lines in the figure are data flows.

[0028] In an exemplary embodiment, when the module to be tested is an IO logic unit IOL, and a parallel-to-serial function test is performed on the IOL, the output end of the IOL is connected to the input end of the IOBUF, wherein the input end of the IOBUF is the data input end of the IOBUF output path, such as Figure 4As shown, the step S200 of "inputting the test data into the module to be tested, inputting the output data of the module to be tested into the IOBUF to obtain the recovered data, and determining whether the function of the module to be tested is normal based on the test data and the recovered data" may include steps S221-S223: S221: inputting parallel test data into the IOL, performing parallel-to-serial data conversion, and obtaining converted serial output data at the output end of the IOL; S222: after the serial output data is input into the IOBUF single-ended output path, data is retrieved through the IOBUF single-ended input path to obtain the retrieved data; S223: Determine whether the parallel-to-serial function of the IOL is normal based on the parallel test data and the retrieved data.

[0029] In this embodiment, IOBUF corresponds to IOL one by one, and the parallel-to-serial function test of IOL can be implemented by executing steps S221-S223. The parallel-to-serial conversion of IOL can realize the OSER (Output Parallel-to-Serial logic resources) mode of FPGA; before executing steps S221-S223, the output end of IOL needs to be connected to the input end of IOBUF, and the parallel test data is input into IOL for parallel-to-serial data conversion to generate serial output data, and the serial output data is input into IOBUF to obtain the recovered data; in step S222, compared with step S100, except for the different input data, the data flow of IOBUF for obtaining the recovered data is the same, and the parallel-to-serial function test of IOL is implemented based on the parallel test data and the recovered data, and the data flow is: parallel test data - IOL performs parallel-to-serial conversion to obtain serial output data - IOBUF output path - PAD - IOBUF input path - the recovered data is obtained at the recovery end, such as Figure 4 As shown, Figure 4 The dotted lines in the figure are data flows.

[0030] In this embodiment, when functional testing is performed on other modules in the FPGA except IOBUF and IOL, the testing method is similar to the testing method of IOL, and one of the following methods can be selected for testing according to the functions of other modules to be tested: connecting the recovery end of the IOBUF to the input end of the module to be tested, inputting test data into the IOBUF to obtain recovery data, inputting the recovery data into the module to be tested to obtain output data, and judging whether the function of the module to be tested is normal based on the test data and the output data; or, connecting the output end of the module to be tested to the input end of the IOBUF, inputting test data into the module to be tested to obtain output data, inputting the output data into the IOBUF to obtain recovery data, and judging whether the function of the module to be tested is normal based on the test data and the recovery data.

[0031] In an exemplary embodiment, multiple IOBUFs or multiple IOLs may be tested; When there are multiple IOBUFs, the input ends of all IOBUFs are connected to the output bus BUS1 of the data input controller, and the return ends of all IOBUFs are connected to the input bus BUS2 of the data output controller; the input end of the IOBUF is the data input end of the IOBUF output path; When there are multiple IOLs, and when performing serial-to-parallel function test on each IOL to be tested: the input ends of all IOBUFs are connected to the output bus BUS1 of the data input controller, and the output ends of all IOLs are connected to the input bus BUS2 of the data output controller, wherein the IOBUFs correspond to the IOLs one by one, and the return end of each IOBUF is connected to the input end of the corresponding IOL; When there are multiple IOLs and each IOL to be tested is subjected to a parallel-to-serial function test: the input ends of all IOLs are connected to the output bus BUS1 of the data input controller, and the return ends of all IOBUFs are connected to the input bus BUS2 of the data output controller, wherein the IOBUFs correspond one-to-one to the IOLs, and the output end of each IOL is connected to the input end of the corresponding IOBUF.

[0032] In this embodiment, when multiple IOBUFs are tested, based on Figure 5 The IOBUF-based FPGA functional test device shown in the figure is executed; when multiple identical other modules are tested, Figure 6 The IOBUF-based FPGA functional test device shown is executed, wherein other modules may be IOLs to implement testing of multiple IOLs; Figure 5 and Figure 6 The IOBUF-based FPGA functional test devices include a data input controller, a data output controller, a parallel checker, and a serial checker.

[0033] In this embodiment, the parallel checker includes multiple parallel check units, and the parallel check units correspond one-to-one to the IOBUF to be tested, or the parallel check units correspond one-to-one to other modules to be tested, and all the parallel check units can work independently and in parallel; the parallel checker can also include a multi-input and one-output logic processing unit. After each parallel check unit obtains the inspection result, the corresponding inspection result is input into the logic processing unit. The logic processing unit can further process all the inspection results and simplify them into one data for output.

[0034] In this embodiment, the data input controller includes: a two-way selection switch, an output bus BUS1, a one-input multi-output switch, a first switch controller, such as Figure 7 As shown; the data input controller includes two paths: a first path in which two-way selection switches are directly connected to the output bus BUS1; and a second path in which the two-way selection switches and the output bus BUS1 are connected via a one-input multiple-output switch; wherein the second path includes a plurality of second sub-paths, each of which can be turned on in turn via the one-input multiple-output switch, and the second sub-paths correspond one-to-one to the IOBUF to be tested or other modules to be tested; Figure 7 The data input terminal in is the input terminal of the two-way selection switch, and is also the data input terminal of the data input controller; Figure 7 The data output end in is the data output end of the output bus BUS1, and is also the data output end of the data output controller.

[0035] In this embodiment, the data output controller includes: an input bus BUS2, an output bus BUS3, a bus switch, a multi-input one-output switch, a single output terminal, and a second switch controller. Figure 8 As shown; the data output controller includes two paths: a third path connecting the input bus BUS2 and the output bus BUS3 through a bus switch, and a fourth path connecting the input bus BUS2 and the single output terminal through a multi-input-output switch, wherein the fourth path includes a plurality of fourth sub-paths, and each of the fourth sub-paths can be turned on in sequence through the multi-input-output switch, and the fourth sub-paths correspond one-to-one to the IOBUF to be tested or other modules to be tested; Figure 8 The input bus BUS2 is the data input end of the data output controller, the output bus BUS3 and the single output end are the data output ends of the data output controller, when the third path is turned on, the output bus BUS3 is the data output end of the data output controller; when the fourth path is turned on, the single output end is the data output end of the data output controller.

[0036] In this embodiment, the bit widths of the output bus BUS1 of the data input controller, the input bus BUS2 of the data output controller, and the output bus BUS3 match the number of IOBUFs to be tested or the number of other modules to be tested to ensure that the bit width of each bus can meet the parallel testing requirements of multiple IOBUFs or multiple identical other modules.

[0037] In this embodiment, the output end of the data generator is connected to the input end of the two-way selection switch of the data input controller, the input end of the serial checker, and the input end of each parallel check unit in the parallel checker, and the data generator is used to generate the test data; the output bus BUS3 of the data output controller is connected to the parallel checker, and the single-way output end of the data output controller is connected to the serial checker; the output end of the serial-parallel selector is respectively connected to the first switch controller of the data input controller and the second switch controller of the data output controller, and sends a serial test control signal or a parallel test control signal to the first switch controller and the second switch controller, such as Figure 5 and Figure 6 shown.

[0038] In this embodiment, Figure 5 and Figure 6 The IOBUF-based FPGA functional testing device may also include an output selection switch with two inputs and one output, which may include a fifth path and a sixth path, wherein the fifth path is used to output the result of the parallel checker, and the sixth path is used to output the result of the serial checker; the output end of the serial-parallel selector may also be connected to the output selection switch to send a serial test control signal or a parallel test control signal to the output selection switch.

[0039] In this embodiment, when the serial-parallel selector sends a parallel test control signal to the first switch controller, the second switch controller and the output selection switch, the data input controller turns on the first path, the data output controller turns on the third path, and the output selection switch turns on the fifth path, so as to realize parallel testing of multiple IOBUFs or multiple identical other modules; when the serial-parallel selector sends a serial test control signal to the first switch controller, the second switch controller and the output selection switch, the data input controller turns on the second path, the data output controller turns on the fourth path, and the output selection switch turns on the sixth path, so as to realize serial testing of multiple IOBUFs or multiple identical other modules.

[0040] In an exemplary embodiment, when N IOBUFs are tested in parallel, the parallel detection units correspond to the IOBUFs one by one, N≥2, and the step S100 of "after inputting the test data into the IOBUF output path, obtaining the recovered data through the IOBUF input path, and determining whether the function of the IOBUF is normal based on the test data and the recovered data" may include steps S1001-S1003: S1001: The data generator sends test data to N parallel detection units, and sends the test data to N IOBUF output paths in parallel through the data input controller; S1002: Acquire the recovered data through each of the IOBUF input channels, and send N recovered data to N parallel detection units through the data output controller, wherein the recovered data of the nth IOBUF is sent to the nth parallel detection unit, n=1, 2, ...N; S1003: Each parallel detection unit compares the received test data with the collected data. When the collected data is consistent with the test data, the IOBUF corresponding to the parallel detection unit functions normally. Otherwise, the IOBUF corresponding to the parallel detection unit functions abnormally.

[0041] In this embodiment, parallel testing of multiple IOBUFs can be achieved by executing steps S1001-S1003. Before executing step S1001, the serial-parallel selector can send a parallel test control signal to the first switch controller of the data input controller, the second switch controller of the data output controller and the output selection switch, and the data input controller turns on the first path, the data output controller turns on the third path, and the output selection switch turns on the fifth path.

[0042] In this embodiment, when executing step S1001, the data generator sends the test data to the input ends of the two-way selection switches of the data input controller and the N parallel detection units, and the test data can be sent in parallel to the N IOBUF output paths through the first path of the data input controller; when executing step S1002, the N retrieved data are sent to the N parallel detection units through the third path of the data output controller, and the retrieved data correspond one-to-one to the parallel detection units, that is, the retrieved data of the nth IOBUF is transmitted to the nth parallel detection unit.

[0043] In this embodiment, a parallel test of single-ended input and output functions of N IOBUFs can be implemented, or a parallel test of differential input and output functions of N IOBUFs can be implemented.

[0044] In an exemplary embodiment, when N IOBUFs are serially tested, N≥2, the step S100 of "after inputting the test data into the IOBUF output path, obtaining the recovered data through the IOBUF input path, and determining whether the function of the IOBUF is normal based on the test data and the recovered data" may include steps S1004-S1006: S1004: The data generator sends the test data to the serial checker, and executes the following operations N times in a loop to test the N IOBUFs in sequence: S1005: when the nth IOBUF is tested, the data input controller sends the test data to the nth IOBUF output path, obtains the retrieved data through the nth IOBUF input path, and sends the retrieved data to the serial checker through the data output controller, n=1, 2, ...N; S1006: The serial checker compares the received test data with the retrieved data. When the retrieved data is consistent with the test data, the nth IOBUF functions normally. Otherwise, the nth IOBUF functions abnormally.

[0045] In this embodiment, by executing steps S1004-S1006, a serial test of multiple IOBUFs can be implemented, that is, a sequential test of multiple IOBUFs. Before executing step S1004, when the serial-parallel selector sends a serial test control signal to the first switch controller of the data input controller, the second switch controller of the data output controller, and the output selection switch, the data input controller turns on the second path, the data output controller turns on the fourth path, and the output selection switch turns on the sixth path; when testing N IOBUFs, the serial test control signal may include N signals, each signal corresponds to a sending time, and an interval length may be set between adjacent signals. When the nth signal is sent, the nth signal is sent, and the nth signal can control the one-input multi-output switch of the data input controller and the multi-input one-output switch of the data output controller to select the nth IOBUF, wherein the one-input multi-output switch is a one-input N-output switch, and the multi-input one-output switch is an N-input one-output switch. When testing the nth IOBUF, the nth second sub-path in the second path and the nth fourth sub-path in the fourth path are turned on.

[0046] In this embodiment, when executing step S1004, the data generator sends the test data to the input ends of the two-way selection switches of the serial checker and the data input controller; when executing step S1005, the test data is input into the nth IOBUF output path through the nth second sub-path, and then the collected data corresponding to the nth IOBUF is obtained through the nth IOBUF input path, and the collected data corresponding to the nth IOBUF is transmitted to the serial checker through the nth fourth sub-path; for N IOBUFs, steps S1005-S1006 are executed in sequence, thereby realizing the sequential testing of N IOBUFs.

[0047] In this embodiment, a serial test of single-ended input and output functions of N IOBUFs may be implemented, or a serial test of differential input and output functions of N IOBUFs may be implemented.

[0048] In an exemplary embodiment, when the serial-to-parallel functions of N IOLs are tested in parallel, the parallel detection unit corresponds to the IOL one-to-one, the IOL corresponds to the IOBUF one-to-one, N≥2, and the step S200 of "after inputting the test data into the IOBUF output path, obtaining the retrieved data through the IOBUF input path, inputting the retrieved data into the module to be tested and obtaining the output data, and determining whether the function of the module to be tested is normal based on the test data and the output data" may include steps S2001-S2003: S2001: The data generator sends serial test data to N parallel detection units, and sends the serial test data in parallel to N IOBUF single-ended output paths through the data input controller; S2002: Acquire the collected data through each IOBUF single-ended input channel, send N collected data to N IOLs for serial-to-parallel conversion to obtain parallel output data, and send the N parallel output data to N parallel detection units through the data output controller, wherein the collected data of the nth IOBUF single-ended input channel is sent to the nth IOL, and the parallel output data output by the nth IOL is sent to the nth parallel detection unit, n=1, 2, ...N; S2003: Each parallel detection unit converts the received serial test data into parallel data, and compares the parallel data with the parallel output data. When the parallel output data is consistent with the parallel data, the serial-to-parallel function of the IOL corresponding to the parallel detection unit is normal; otherwise, the serial-to-parallel function of the IOL corresponding to the parallel detection unit is abnormal.

[0049] In this embodiment, parallel testing of multiple IOLs can be achieved by executing steps S2001-S2003. Before executing step S2001, the serial-parallel selector can send a parallel test control signal to the first switch controller of the data input controller, the second switch controller of the data output controller and the output selection switch, and the data input controller turns on the first path, the data output controller turns on the third path, and the output selection switch turns on the fifth path.

[0050] In this embodiment, when executing step S2001, the data generator sends serial test data to the input ends of the two-way selection switches of the data input controller and the N parallel detection units, and the serial test data can be sent in parallel to the N IOBUF single-ended output paths through the first path of the data input controller; when executing step S2002, the N parallel output data are sent to the N parallel detection units through the third path of the data output controller, and the parallel output data correspond to the parallel detection units one by one, that is, the parallel output data of the nth IOL is transmitted to the nth parallel detection unit.

[0051] In an exemplary embodiment, when serial-to-parallel functions of N IOLs are serially tested, IOLs correspond to IOBUFs one by one, N≥2, and the step S200 of "after inputting test data into the IOBUF output path, obtaining retrieved data through the IOBUF input path, inputting the retrieved data into the module to be tested and obtaining output data, and determining whether the function of the module to be tested is normal based on the test data and the output data" may include steps S2004-S2006: S2004: The data generator sends the serial test data to the serial checker, and executes the following operations N times in a loop to test the N IOLs in sequence: S2005: when testing the nth IOL, the data input controller sends the serial test data to the nth IOBUF single-ended output path, obtains the collected data through the nth IOBUF single-ended input path, and sends the collected data to the nth IOL for serial-to-parallel conversion to obtain parallel output data, and sends the parallel output data to the serial checker, n=1, 2, ...N; S2006: The serial checker converts the received serial test data into parallel data, and compares the parallel data with the parallel output data. When the parallel output data is consistent with the parallel data, the serial-to-parallel function of the nth IOL is normal; otherwise, the serial-to-parallel function of the nth IOL is abnormal.

[0052] In this embodiment, by executing steps S2004-S2006, a serial test of multiple IOLs can be implemented, that is, a sequential test of multiple IOLs. Before executing step S2004, when the serial-parallel selector sends a serial test control signal to the first switch controller of the data input controller, the second switch controller of the data output controller, and the output selection switch, the data input controller turns on the second path, the data output controller turns on the fourth path, and the output selection switch turns on the sixth path; when testing N IOLs, the serial test control signal may include N signals, each signal corresponds to a sending time, and an interval length may be set between adjacent signals. When the nth signal is sent, the nth signal is sent, and the nth signal may control the one-input multi-output switch of the data input controller and the multi-input one-output switch of the data output controller to select the nth IOL, wherein the one-input multi-output switch is a one-input N-output switch, and the multi-input one-output switch is an N-input one-output switch. When testing the nth IOL, the nth second sub-path in the second path and the nth fourth sub-path in the fourth path are turned on.

[0053] In this embodiment, when executing step S2004, the data generator sends serial test data to the input ends of the two-way selection switches of the serial checker and the data input controller; when executing step S2005, the serial test data is input into the nth IOBUF output path through the nth second sub-path, and then the collected data corresponding to the nth IOBUF is obtained through the nth IOBUF input path, and the collected data corresponding to the nth IOBUF is input into the nth IOL for serial-to-parallel conversion, and the obtained parallel output data is transmitted to the serial checker through the nth fourth sub-path; for N IOLs, steps S2005-S2006 are executed in sequence, thereby realizing the sequential testing of N IOLs.

[0054] In an exemplary embodiment, when the parallel-to-serial functions of N IOLs are tested in parallel, the parallel detection units correspond to the IOLs one by one, and the IOLs correspond to the IOBUFs one by one, and N≥2. The step S200 of "inputting the test data into the module to be tested, inputting the output data of the module to be tested into the IOBUF to obtain the retrieved data, and determining whether the function of the module to be tested is normal based on the test data and the retrieved data" may include steps S2007-S2009: S2007: the data generator sends the parallel test data to the N parallel detection units, and sends the parallel test data to the N IOLs in parallel through the data input controller for parallel-to-serial conversion to obtain serial output data; S2008: inputting N serial output data into N IOBUF single-ended output channels, obtaining collected data through the N IOBUF single-ended input channels, and sending the N collected data to the N parallel detection units, wherein the serial output data of the nth IOL is input into the nth IOBUF single-ended output channel, obtaining collected data from the nth IOBUF single-ended input channel, and sending the nth collected data to the nth parallel detection unit, n=1, 2, ...N; S2009: Each parallel detection unit converts the received parallel test data into serial data, and compares the serial data with the retrieved data. When the retrieved data is consistent with the serial data, the parallel-to-serial function of the IOL corresponding to the parallel detection unit is normal; otherwise, the parallel-to-serial function of the IOL corresponding to the parallel detection unit is abnormal.

[0055] In this embodiment, parallel testing of multiple IOLs can be achieved by executing steps S2007-S2009. Before executing step S2007, the serial-parallel selector can send a parallel test control signal to the first switch controller of the data input controller, the second switch controller of the data output controller and the output selection switch, and the data input controller turns on the first path, the data output controller turns on the third path, and the output selection switch turns on the fifth path.

[0056] In this embodiment, when executing step S2007, the data generator sends parallel test data to the input ends of the two-way selection switches of the data input controller and the N parallel detection units, and the parallel test data can be sent in parallel to the N IOBUF single-ended output paths through the first path of the data input controller; when executing step S2008, the N retrieved data are sent to the N parallel detection units through the third path of the data output controller, and the retrieved data correspond one-to-one to the parallel detection units, that is, the retrieved data of the IOBUF corresponding to the nth IOL is transmitted to the nth parallel detection unit.

[0057] In an exemplary embodiment, when a serial test is performed on the parallel-to-serial functions of N IOLs, the IOLs correspond to the IOBUFs one by one, and N≥2. The step S200 of "inputting the test data into the module to be tested, inputting the output data of the module to be tested into the IOBUF to obtain the retrieved data, and determining whether the function of the module to be tested is normal based on the test data and the retrieved data" may include steps S210-S2012: S2010: The data generator sends the parallel test data to the serial checker, and executes the following operations N times in a loop to test the N IOLs in sequence: S2011: when testing the nth IOL, the data input controller sends the parallel test data to the nth IOL for parallel-to-serial conversion to obtain serial output data, inputs the serial output data into the nth IOBUF single-ended output path, obtains the retrieved data through the nth IOBUF single-ended input path, and sends the retrieved data to the serial checker, n=1, 2, ...N; S2012: The serial checker converts the received parallel test data into serial data, and compares the serial data with the retrieved data. When the retrieved data is consistent with the serial data, the parallel-to-serial function of the nth IOL is normal; otherwise, the parallel-to-serial function of the nth IOL is abnormal.

[0058] In this embodiment, by executing steps S2010-S2012, a serial test of multiple IOLs can be implemented, that is, a sequential test of multiple IOLs. Before executing step S2010, when the serial-parallel selector sends a serial test control signal to the first switch controller of the data input controller, the second switch controller of the data output controller, and the output selection switch, the data input controller turns on the second path, the data output controller turns on the fourth path, and the output selection switch turns on the sixth path; when testing N IOLs, the serial test control signal may include N signals, each signal corresponds to a sending time, and an interval length may be set between adjacent signals. When the nth signal is sent, the nth signal is sent, and the nth signal may control the one-input multi-output switch of the data input controller and the multi-input one-output switch of the data output controller to select the nth IOL, wherein the one-input multi-output switch is a one-input N-output switch, and the multi-input one-output switch is an N-input one-output switch. When testing the nth IOL, the nth second sub-path in the second path and the nth fourth sub-path in the fourth path are turned on.

[0059] In this embodiment, when executing step S2010, the data generator sends parallel test data to the input ends of the two-way selection switches of the serial checker and the data input controller; when executing step S2011, the serial test data is input into the nth IOL through the nth second sub-path for parallel-to-serial conversion, the serial output data output by the nth IOL is input into the nth IOBUF output path, and then the collected data is obtained through the nth IOBUF input path, and the collected data corresponding to the nth IOBUF is transmitted to the serial checker through the nth fourth sub-path; for N IOLs, steps S2011-S2012 are executed in sequence, thereby realizing sequential testing of the N IOLs.

[0060] The FPGA functional testing method based on IOBUF in the embodiment of the present application utilizes the bidirectional transmission characteristics of IOBUF to retrieve the data output to PAD into the FPGA. There is no need to perform data comparison and judgment in PAD, and it is not dependent on ATE testing and is no longer limited by the performance of the ATE testing machine. It can implement single-ended input and output functional testing and differential input and output functional testing on the IOBUF of the FPGA. It can implement parallel-to-serial and serial-to-parallel functional testing of IOL based on IOBUF. It can implement testing of modules other than IOL based on IOBUF. It can implement parallel and serial testing of multiple modules to be tested. Each module to be tested can be tested independently without interference. For all modules to be tested, the test mode is unified, the test method is simple, and it is easy to maintain and manage, thereby improving the efficiency of FPGA functional testing.

[0061] The embodiment of the present application also provides an IOBUF-based FPGA functional testing device, including: IOBUF, used to perform functional testing on the IOBUF or other modules of the FPGA, including an IOBUF output path and an IOBUF input path; When the module to be tested is the IOBUF, the IOBUF is used to input the test data into the IOBUF output path, and then obtain the retrieved data through the IOBUF input path, wherein the retrieved data is used to determine whether the function of the IOBUF is normal in combination with the test data, such as Fig. 9 As shown; When the module to be tested is the other module, the IOBUF is used to input the test data into the IOBUF output path, and then obtain the recovered data through the IOBUF input path, wherein the recovered data is used to input the module to be tested to obtain output data, and the output data is used to determine whether the function of the module to be tested is normal in combination with the test data, such as Fig.10 As shown; or, the IOBUF is used to input the output data of the module to be tested into the IOBUF to obtain the recovered data, wherein the output data is obtained after the test data is input into the module to be tested, and the recovered data is used to determine whether the function of the module to be tested is normal in combination with the test data, such as Fig.11 shown.

[0062] In this embodiment, the IOBUF-based FPGA functional test device may further include a data generator, a serial-parallel selector, a data input controller, a data output controller, a serial checker, a parallel checker, and an output selection switch; wherein the parallel checker includes a plurality of parallel check units and a logic processing unit, and the data input controller includes a plurality of parallel check units and a logic processing unit. Figure 7 As shown, the data output controller is as follows Figure 8When testing multiple IOBUFs, you can use Figure 5 The IOBUF-based FPGA functional test device shown in FIG. 1 is used to perform parallel or serial testing. When testing multiple identical other modules, the following can be used: Figure 6 The IOBUF-based FPGA functional testing device shown performs parallel or serial testing, and multiple identical other modules can be multiple IOLs. The functions of each part are as described in the above embodiment and will not be repeated one by one.

[0063] In order to illustrate the IOBUF-based FPGA functional testing method of the embodiment of the present application, eight specific examples are described in detail below: Specific example 1: Parallel test of IOBUF single-ended input and output functions: N IOBUFs are tested simultaneously, with parallel detection units corresponding to IOBUFs one by one, and IOBUFs corresponding to PADs one by one, including the following steps: Step 1: The serial-parallel selector sends a parallel test control signal to the first switch controller, the second switch controller, and the output selection switch. The first switch controller turns on the first path of the data input controller, the second switch controller turns on the third path of the data output controller, and turns on the fifth path of the output selection switch. Step 2: The data generator sends the test data to the input end of the two-way selection switch and each parallel detection unit; Step 3: The data input controller sends the test data to the N IOBUF single-ended output paths through the first path; the data output controller sends the collected data of the nth IOBUF to the nth parallel detection unit through the third path, n=1,2,...N; The data flow of each IOBUF is: test data - first channel - IOBUF single-ended output channel - through PAD - IOBUF single-ended input channel - IOBUF recovery end obtains recovery data - third channel - parallel detection unit; Step 4: Each parallel detection unit compares the received test data with the collected data. When the collected data is consistent with the test data, the IOBUF corresponding to the parallel detection unit functions normally, and the parallel detection unit sends an indication signal 1 to the logic processing unit. Otherwise, the IOBUF corresponding to the parallel detection unit functions abnormally, and the parallel detection unit sends an indication signal 0 to the logic processing unit. Step 5: The logic processing unit performs a logic AND operation based on the N indication signals received. When the N indication signals are all 1, the output signal 1 is output through the fifth channel of the output selection switch, indicating that the single-ended input and output functions of the N IOBUFs of the FPGA are normal; when at least one of the N indication signals is 0, the output signal 0 is output through the fifth channel of the output selection switch, indicating that there is an abnormality in the single-ended input and output functions of the N IOBUFs of the FPGA.

[0064] Specific example 2: Serial test of IOBUF single-ended input and output function: N IOBUFs are tested in sequence, with IOBUF and PAD corresponding one by one, including the following steps: Step 1: The serial-parallel selector sends a serial test control signal to the first switch controller, the second switch controller, and the output selection switch to turn on the sixth path of the output selection switch; Loop the following steps N times to complete the test of N IOBUFs in sequence: Step 2: The first switch controller turns on the second sub-path connected to the nth IOBUF in the second path through the one-input multi-output switch, and the second switch controller turns on the fourth sub-path connected to the nth IOBUF in the fourth path through the multi-input one-output switch, where n=1, 2, ...N; Step 3: The data generator sends the test data to the input terminals of the two-way selector switch and the serial checker; Step 4: The data input controller sends the test data to the IOBUF single-ended output path of the nth IOBUF through the currently turned-on second sub-path; the data output controller sends the nth retrieved data to the serial checker through the currently turned-on fourth sub-path; The data flow of the nth IOBUF is: test data - the second sub-path - the nth IOBUF single-ended output path - through the nth PAD - the nth IOBUF single-ended input path - the nth IOBUF recovery end obtains the nth recovery data - the fourth sub-path - the serial checker; Step 5: The serial checker compares the received test data with the nth collected data. When the nth collected data is consistent with the test data, the single-ended input and output function of the nth IOBUF is normal, and the serial checker outputs the indication signal 1 through the sixth path of the output selection switch; otherwise, the single-ended input and output function of the nth IOBUF is abnormal, and the serial checker outputs the indication signal 0 through the sixth path of the output selection switch.

[0065] Specific example 3: Parallel test of IOBUF differential input and output functions: N IOBUFs are tested simultaneously, with parallel detection units corresponding to IOBUFs one by one, and IOBUFs corresponding to PADs one by one, including the following steps: Step 1: The serial-parallel selector sends a parallel test control signal to the first switch controller, the second switch controller, and the output selection switch. The first switch controller turns on the first path of the data input controller, the second switch controller turns on the third path of the data output controller, and turns on the fifth path of the output selection switch. Step 2: The data generator sends the differential test data to the input ends of the two-way selection switches and each parallel detection unit; Step 3: The data input controller sends the differential test data to the N IOBUF differential output paths through the first path; the data output controller sends the retrieved data of the nth IOBUF to the nth parallel detection unit through the third path, n=1,2,...N; The data flow of each IOBUF is: differential test data - first channel - IOBUF differential output channel - through PAD - IOBUF differential input channel - IOBUF recovery end obtains recovery data - third channel - parallel detection unit; Step 4: Each parallel detection unit compares the received differential test data with the recovered data. When the recovered data and the differential test data are consistent, the IOBUF corresponding to the parallel detection unit functions normally, and the parallel detection unit sends an indication signal 1 to the logic processing unit. Otherwise, the IOBUF corresponding to the parallel detection unit functions abnormally, and the parallel detection unit sends an indication signal 0 to the logic processing unit. Step 5: The logic processing unit performs a logic AND operation based on the N indication signals received. When the N indication signals are all 1, the output signal 1 is output through the fifth channel of the output selection switch, indicating that the differential input and output functions of the N IOBUFs of the FPGA are normal; when at least one of the N indication signals is 0, the output signal 0 is output through the fifth channel of the output selection switch, indicating that there is an abnormality in the differential input and output function of the N IOBUFs of the FPGA.

[0066] Specific example 4: Serial test of IOBUF differential input and output function: N IOBUFs are tested in sequence, with IOBUF and PAD corresponding one by one, including the following steps: Step 1: The serial-parallel selector sends a serial test control signal to the first switch controller, the second switch controller, and the output selection switch to turn on the sixth path of the output selection switch; Loop the following steps N times to complete the test of N IOBUFs in sequence: Step 2: The first switch controller turns on the second sub-path connected to the nth IOBUF in the second path through the one-input multi-output switch, and the second switch controller turns on the fourth sub-path connected to the nth IOBUF in the fourth path through the multi-input one-output switch, where n=1, 2, ...N; Step 3: The data generator sends differential test data to the input of the two-way selector switch and the serial checker; Step 4: the data input controller sends the differential test data to the IOBUF differential output path of the nth IOBUF through the currently turned-on second sub-path; the data output controller sends the nth retrieved data to the serial checker through the currently turned-on fourth sub-path; The data flow of the nth IOBUF is: differential test data - the second sub-path - the nth IOBUF differential output path - through the nth PAD - the nth IOBUF differential input path - the nth IOBUF recovery end obtains the nth recovery data - the fourth sub-path - the serial checker; Step 5: The serial checker compares the received differential test data with the nth collected data. When the nth collected data is consistent with the differential test data, the differential input and output functions of the nth IOBUF are normal, and the serial checker outputs the indication signal 1 through the sixth path of the output selection switch; otherwise, the differential input and output functions of the nth IOBUF are abnormal, and the serial checker outputs the indication signal 0 through the sixth path of the output selection switch.

[0067] Specific example 5: Parallel test of IOL serial-to-parallel function: N IOLs are tested simultaneously, with parallel detection units corresponding to IOLs one by one, IOLs corresponding to IOBUFs one by one, and IOBUFs corresponding to PADs one by one. The following steps are performed: Step 1: The serial-parallel selector sends a parallel test control signal to the first switch controller, the second switch controller, and the output selection switch. The first switch controller turns on the first path of the data input controller, the second switch controller turns on the third path of the data output controller, and turns on the fifth path of the output selection switch. Step 2: The data generator sends the serial test data to the input ends of the two-way selector switch and each parallel detection unit; Step 3: The data input controller sends the serial test data to the N IOBUF single-ended output paths through the first path, and the data output controller sends the parallel output data of the nth IOL to the nth parallel detection unit through the third path, n=1,2,...N; The data flow of each IOL is: serial test data - first channel - IOBUF single-ended output channel - through PAD - IOBUF single-ended input channel - IOBUF acquisition end obtains acquisition data - IOL performs serial-to-parallel conversion - parallel output data - third channel - parallel detection unit; Step 4: Each parallel detection unit converts the received serial test data into parallel data, and compares the parallel data with the parallel output data. When the parallel output data is consistent with the parallel data, the serial-to-parallel function of the IOL corresponding to the parallel detection unit is normal, and the parallel detection unit sends an indication signal 1 to the logic processing unit. Otherwise, the serial-to-parallel function of the IOL corresponding to the parallel detection unit is abnormal, and the parallel detection unit sends an indication signal 0 to the logic processing unit. Step 5: The logic processing unit performs a logic AND operation based on the N indication signals received. When the N indication signals are all 1, the output signal 1 is output through the fifth path of the output selection switch, indicating that the serial-to-parallel functions of the N IOLs of the FPGA are normal; when at least one of the N indication signals is 0, the output signal 0 is output through the fifth path of the output selection switch, indicating that there is an abnormality in the serial-to-parallel function of the N IOLs of the FPGA.

[0068] Specific example 6: Serial test of IOL serial-to-parallel function: N IOLs are tested in sequence, with IOBUF and PAD corresponding one by one, including the following steps: Step 1: The serial-parallel selector sends a serial test control signal to the first switch controller, the second switch controller, and the output selection switch to turn on the sixth path of the output selection switch; The following steps are executed N times in a loop to complete the test of N IOLs in sequence: Step 2: The first switch controller turns on the second sub-path corresponding to the nth IOL in the second path through a one-input multi-output switch, and the second switch controller turns on the fourth sub-path corresponding to the nth IOL in the fourth path through a multi-input one-output switch, where n=1, 2, ..., N; Step 3: The data generator sends the serial test data to the input terminals of the two-way selector switch and the serial checker; Step 4: The data input controller sends the serial test data to the IOBUF single-ended output path of the nth IOBUF through the currently turned-on second sub-path, and the data output controller sends the nth parallel output data to the serial checker through the currently turned-on fourth sub-path; The data flow of the nth IOL is: serial test data - the second sub-path - the nth IOBUF single-ended output path - through the nth PAD - the nth IOBUF single-ended input path - the nth IOBUF acquisition end obtains the nth acquisition data - the nth IOL performs serial-to-parallel conversion - the nth parallel output data - the fourth sub-path - the serial checker; Step 5: The serial checker converts the received serial test data into parallel data, and compares the parallel data with the nth parallel output data. When the nth parallel output data is consistent with the parallel data, the serial-to-parallel function of the nth IOL is normal, and the serial checker outputs the indication signal 1 through the sixth path of the output selection switch; otherwise, the serial-to-parallel function of the nth IOL is abnormal, and the serial checker outputs the indication signal 0 through the sixth path of the output selection switch.

[0069] Specific example 7: Parallel test of IOL parallel-to-serial function: N IOLs are tested simultaneously, with parallel detection units corresponding to IOLs one by one, IOLs corresponding to IOBUFs one by one, and IOBUFs corresponding to PADs one by one, including the following steps: Step 1: The serial-parallel selector sends a parallel test control signal to the first switch controller, the second switch controller, and the output selection switch. The first switch controller turns on the first path of the data input controller, the second switch controller turns on the third path of the data output controller, and turns on the fifth path of the output selection switch. Step 2: The data generator sends the parallel test data to the input ends of the two-way selection switches and each parallel detection unit; Step 3: The data input controller sends the parallel test data to the N IOLs through the first path, and the data output controller sends the retrieved data of the nth IOBUF to the nth parallel detection unit through the third path, n=1,2,...N; The data flow of each IOL is: parallel test data - first channel - IOL performs parallel-serial conversion - serial output data - IOBUF single-ended output channel - through PAD - IOBUF single-ended input channel - IOBUF acquisition end obtains acquisition data - third channel - parallel detection unit; Step 4: Each parallel detection unit converts the received parallel test data into serial data, and compares the serial data with the retrieved data. When the retrieved data and the serial data are consistent, the parallel-to-serial function of the IOL corresponding to the parallel detection unit is normal, and the parallel detection unit sends an indication signal 1 to the logic processing unit. Otherwise, the parallel-to-serial function of the IOL corresponding to the parallel detection unit is abnormal, and the parallel detection unit sends an indication signal 0 to the logic processing unit. Step 5: The logic processing unit performs a logic AND operation based on the N indication signals received. When the N indication signals are all 1, the output signal 1 is output through the fifth path of the output selection switch, indicating that the parallel-to-serial functions of the N IOLs of the FPGA are normal; when at least one of the N indication signals is 0, the output signal 0 is output through the fifth path of the output selection switch, indicating that there is an abnormality in the parallel-to-serial function of the N IOLs of the FPGA.

[0070] Specific example 8: Serial test of IOL parallel-to-serial function: N IOLs are tested in sequence, with IOBUF and PAD corresponding one by one, including the following steps: Step 1: The serial-parallel selector sends a serial test control signal to the first switch controller, the second switch controller, and the output selection switch to turn on the sixth path of the output selection switch; The following steps are executed N times in a loop to complete the test of N IOLs in sequence: Step 2: The first switch controller turns on the second sub-path corresponding to the nth IOL in the second path through a one-input multi-output switch, and the second switch controller turns on the fourth sub-path corresponding to the nth IOL in the fourth path through a multi-input one-output switch, where n=1, 2, ..., N; Step 3: The data generator sends parallel test data to the input terminals of the two-way selector switch and the serial checker; Step 4: The data input controller sends the parallel test data to the nth IOL through the second sub-path currently turned on, and the data output controller sends the nth retrieved data to the serial checker through the fourth sub-path currently turned on; The data flow of the nth IOL is: parallel test data - the second sub-path - the nth IOL performs parallel-serial conversion - the nth serial output data - the nth IOBUF single-ended output path - through the nth PAD - the nth IOBUF single-ended input path - the nth IOBUF acquisition end obtains the nth acquisition data - the fourth sub-path - the serial checker; Step 5: The serial checker converts the received parallel test data into serial data, and compares the serial data with the nth collected data. When the nth collected data and the serial data are consistent, the parallel-to-serial function of the nth IOL is normal, and the serial checker outputs the indication signal 1 through the sixth path of the output selection switch; otherwise, the parallel-to-serial function of the nth IOL is abnormal, and the serial checker outputs the indication signal 0 through the sixth path of the output selection switch.

[0071] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As is known to those skilled in the art, the term "computer storage medium" includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims

1. An IOBUF-based FPGA functional testing method, used to perform functional testing on the IOBUF of the FPGA or other modules except the IOBUF, characterized in that: include: When the module to be tested is the IOBUF, after the test data is input into the IOBUF output path, the recovered data is obtained through the IOBUF input path, and whether the function of the IOBUF is normal is determined based on the test data and the recovered data; When the module to be tested is the other module, after inputting the test data into the IOBUF output path, obtaining the recovered data through the IOBUF input path, inputting the recovered data into the module to be tested and obtaining the output data, and determining whether the function of the module to be tested is normal based on the test data and the output data; Alternatively, the test data is input into the module to be tested, the output data of the module to be tested is input into the IOBUF to obtain the recovered data, and whether the function of the module to be tested is normal is determined based on the test data and the recovered data.

2. The FPGA functional testing method based on IOBUF as claimed in claim 1, characterized in that: After the test data is input into the IOBUF output path, the recovered data is obtained through the IOBUF input path, including: After the test data is input into the IOBUF output path, it is input into the IOBUF input path after passing through the input / output pin PAD corresponding to the IOBUF, and the recovered data is obtained at the recovery end of the IOBUF; The recovery end of the IOBUF is the data output end of the IOBUF input path, and the IOBUF and PAD correspond one to one.

3. The FPGA functional testing method based on IOBUF as claimed in claim 1, characterized in that: When the module to be tested is the IOBUF, after the test data is input into the IOBUF output path, the retrieved data is obtained through the IOBUF input path, including: When the single-ended input and output function test is performed on the IOBUF, after the test data is input into the single-ended output path of the IOBUF, data is retrieved through the single-ended input path of the IOBUF to obtain the retrieved data; When the differential input and output function test is performed on the IOBUF, after the test data is input into the differential output path of the IOBUF, data is retrieved through the differential input path of the IOBUF to obtain the retrieved data.

4. The IOBUF-based FPGA functional testing method as claimed in claim 2, wherein: When the module to be tested is an IO logic unit IOL, and a serial-to-parallel function test is performed on the IOL, the input end of the IOL is connected to the recovery end of the IOBUF, after the test data is input into the IOBUF output path, the recovery data is obtained through the IOBUF input path, the recovery data is input into the module to be tested and the output data is obtained, and whether the function of the module to be tested is normal is determined based on the test data and the output data, including: After the serial test data is input into the IOBUF single-ended output path, data is retrieved through the IOBUF single-ended input path to obtain the retrieved data; Inputting the retrieved data into the IOL for serial-to-parallel data conversion, and obtaining parallel output data at the output end of the IOL; It is determined whether the serial-to-parallel conversion function of the IOL is normal based on the serial test data and the parallel output data.

5. The IOBUF-based FPGA functional testing method as claimed in claim 2, wherein: When the module to be tested is an IO logic unit IOL, and a parallel-to-serial function test is performed on the IOL, the output end of the IOL is connected to the input end of the IOBUF, wherein the input end of the IOBUF is the data input end of the IOBUF output path, the test data is input into the module to be tested, the output data of the module to be tested is input into the IOBUF to obtain the retrieved data, and whether the function of the module to be tested is normal is determined based on the test data and the retrieved data, including: Inputting parallel test data into the IOL, performing parallel-to-serial data conversion, and obtaining converted serial output data at the output end of the IOL; After the serial output data is input into the IOBUF single-ended output path, data is retrieved through the IOBUF single-ended input path to obtain the retrieved data; Based on the parallel test data and the retrieved data, it is determined whether the parallel-to-serial function of the IOL is normal.

6. The IOBUF-based FPGA functional testing method according to claim 1, wherein: When there are multiple IOBUFs: the input ends of all IOBUFs are connected to the output bus BUS1 of the data input controller, and the return ends of all IOBUFs are connected to the input bus BUS2 of the data output controller; the input end of the IOBUF is the data input end of the IOBUF output path; When there are multiple IOLs, and when performing serial-to-parallel function test on each IOL to be tested: the input ends of all IOBUFs are connected to the output bus BUS1 of the data input controller, and the output ends of all IOLs are connected to the input bus BUS2 of the data output controller, wherein the IOBUFs correspond to the IOLs one by one, and the return end of each IOBUF is connected to the input end of the corresponding IOL; When there are multiple IOLs and each IOL to be tested is subjected to a parallel-to-serial function test: the input ends of all IOLs are connected to the output bus BUS1 of the data input controller, and the return ends of all IOBUFs are connected to the input bus BUS2 of the data output controller, wherein the IOBUFs correspond one-to-one to the IOLs, and the output end of each IOL is connected to the input end of the corresponding IOBUF.

7. The IOBUF-based FPGA functional testing method according to claim 6, wherein: When N IOBUFs are tested in parallel, the parallel detection units correspond to the IOBUFs one by one, N≥2, and after the test data is input into the IOBUF output path, the recovered data is obtained through the IOBUF input path, and whether the function of the IOBUF is normal is determined based on the test data and the recovered data, including: The data generator sends the test data to the N parallel detection units, and sends the test data to the N IOBUF output paths in parallel through the data input controller; Acquire the recovered data through each of the IOBUF input channels, and send N recovered data to N parallel detection units through the data output controller, wherein the recovered data of the nth IOBUF is sent to the nth parallel detection unit, n=1, 2, ... N; Each parallel detection unit compares the received test data with the collected data. When the collected data is consistent with the test data, the IOBUF corresponding to the parallel detection unit functions normally. Otherwise, the IOBUF corresponding to the parallel detection unit functions abnormally.

8. The IOBUF-based FPGA functional testing method according to claim 6, wherein: When N IOBUFs are tested serially, N≥2, after the test data is input into the IOBUF output path, the recovered data is obtained through the IOBUF input path, and whether the function of the IOBUF is normal is determined based on the test data and the recovered data, including: The data generator sends the test data to the serial checker, and executes the following operations N times in a loop to test N IOBUFs in sequence: When the nth IOBUF is tested, the data input controller sends the test data to the nth IOBUF output path, obtains the retrieved data through the nth IOBUF input path, and sends the retrieved data to the serial checker through the data output controller, n=1, 2, ... N; The serial checker compares the received test data with the retrieved data. When the retrieved data is consistent with the test data, the nth IOBUF functions normally. Otherwise, the nth IOBUF functions abnormally.

9. The IOBUF-based FPGA functional testing method according to claim 6, wherein: When the serial-to-parallel functions of N IOLs are tested in parallel, the parallel detection unit corresponds to the IOL one-to-one, the IOL corresponds to the IOBUF one-to-one, N≥2, after the test data is input into the IOBUF output path, the retrieved data is obtained through the IOBUF input path, the retrieved data is input into the module to be tested and the output data is obtained, and whether the function of the module to be tested is normal is determined based on the test data and the output data, including: The data generator sends serial test data to the N parallel detection units, and sends the serial test data in parallel to the N IOBUF single-ended output paths through the data input controller; Acquire the collected data through each IOBUF single-ended input channel, send N collected data to N IOLs for serial-to-parallel conversion to obtain parallel output data, and send the N parallel output data to N parallel detection units through the data output controller, wherein the collected data of the nth IOBUF single-ended input channel is sent to the nth IOL, and the parallel output data output by the nth IOL is sent to the nth parallel detection unit, n=1, 2, ...N; Each parallel detection unit converts the received serial test data into parallel data, and compares the parallel data with the parallel output data. When the parallel output data is consistent with the parallel data, the serial-to-parallel function of the IOL corresponding to the parallel detection unit is normal; otherwise, the serial-to-parallel function of the IOL corresponding to the parallel detection unit is abnormal.

10. The IOBUF-based FPGA functional testing method according to claim 6, wherein: When serial-to-parallel functions of N IOLs are tested serially, IOLs correspond to IOBUFs one by one, N≥2, after inputting test data into the IOBUF output path, acquiring retrieved data through the IOBUF input path, inputting the retrieved data into the module to be tested and acquiring output data, and determining whether the function of the module to be tested is normal based on the test data and the output data, including: The data generator sends serial test data to the serial checker, which loops and executes the following operations N times to test N IOLs in sequence: When the nth IOL is tested, the data input controller sends the serial test data to the nth IOBUF single-ended output path, obtains the collected data through the nth IOBUF single-ended input path, and sends the collected data to the nth IOL for serial-to-parallel conversion to obtain parallel output data, and sends the parallel output data to the serial checker, n=1, 2, ...N; The serial checker converts the received serial test data into parallel data, and compares the parallel data with the parallel output data. When the parallel output data is consistent with the parallel data, the serial-to-parallel function of the nth IOL is normal, otherwise, the serial-to-parallel function of the nth IOL is abnormal.

11. The IOBUF-based FPGA functional testing method according to claim 6, wherein: When the parallel-to-serial functions of N IOLs are tested in parallel, the parallel detection units correspond to the IOLs one by one, the IOLs correspond to the IOBUFs one by one, N≥2, the test data is input to the module to be tested, the output data of the module to be tested is input to the IOBUF to obtain the retrieved data, and whether the function of the module to be tested is normal is determined based on the test data and the retrieved data, including: The data generator sends the parallel test data to the N parallel detection units, and sends the parallel test data to the N IOLs in parallel through the data input controller for parallel-to-serial conversion to obtain serial output data; Inputting N serial output data into N IOBUF single-ended output channels, obtaining the collected data through the N IOBUF single-ended input channels, and sending the N collected data to the N parallel detection units, wherein the serial output data of the nth IOL is input into the nth IOBUF single-ended output channel, obtaining the collected data from the nth IOBUF single-ended input channel, and sending the nth collected data to the nth parallel detection unit, n=1, 2, ...N; Each parallel detection unit converts the received parallel test data into serial data, and compares the serial data with the retrieved data. When the retrieved data is consistent with the serial data, the parallel-to-serial function of the IOL corresponding to the parallel detection unit is normal; otherwise, the parallel-to-serial function of the IOL corresponding to the parallel detection unit is abnormal.

12. The IOBUF-based FPGA functional testing method according to claim 6, wherein: When a serial test is performed on the parallel-to-serial functions of N IOLs, the IOLs correspond to the IOBUFs one by one, and N≥2. The test data is input into the module to be tested, the output data of the module to be tested is input into the IOBUF to obtain the retrieved data, and whether the function of the module to be tested is normal is determined based on the test data and the retrieved data, including: The data generator sends parallel test data to the serial checker, which loops and executes the following operations N times to test N IOLs in sequence: When the nth IOL is tested, the data input controller sends the parallel test data to the nth IOL for parallel-to-serial conversion to obtain serial output data, inputs the serial output data into the nth IOBUF single-ended output path, obtains the retrieved data through the nth IOBUF single-ended input path, and sends the retrieved data to the serial checker, n=1, 2, ...N; The serial checker converts the received parallel test data into serial data, and compares the serial data with the retrieved data. When the retrieved data is consistent with the serial data, the parallel-to-serial function of the nth IOL is normal, otherwise, the parallel-to-serial function of the nth IOL is abnormal.

13. An IOBUF-based FPGA functional test device, characterized in that: include: IOBUF, used to perform functional testing on the IOBUF or other modules of the FPGA, including an IOBUF output path and an IOBUF input path; When the module to be tested is the IOBUF, the IOBUF is used to input the test data into the IOBUF output path, and then obtain the recovered data through the IOBUF input path, wherein the recovered data is used to determine whether the function of the IOBUF is normal in combination with the test data; When the module to be tested is the other module, the IOBUF is used to input the test data into the IOBUF output path, and then obtain the recovered data through the IOBUF input path, wherein the recovered data is used to input the module to be tested to obtain output data, and the output data is used to determine whether the function of the module to be tested is normal in combination with the test data; or, the IOBUF is used to input the output data of the module to be tested into the IOBUF to obtain the recovered data, wherein the output data is obtained after the test data is input into the module to be tested, and the recovered data is used to determine whether the function of the module to be tested is normal in combination with the test data.

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