System, method and device for synchronizing high-speed clock based on low-speed clock, and medium

Abstract

The invention provides a system for synchronizing a high-speed clock based on a low-speed clock and a method, a device and a medium thereof, the system comprises an external clock source and a plurality of receiving devices, in the receiving devices, rising edge acquisition signals are output to a synchronous arbiter in response to the rising edge of the external clock, after the trigger edge count of the internal clock reaches a period count value, a period completion signal is output to the synchronous arbiter, and the period count value is used for representing the period multiple value of the internal clock and the external clock; and when the period completion signal and the rising edge acquisition signal do not arrive at the synchronous arbiter at the same time, clock synchronization is carried out on a post-stage processor through the synchronous processor. According to the technical scheme of the embodiment of the invention, the synchronous arbiter determines that the frequency offset occurs according to the fact that the period completion signal and the rising edge acquisition signal do not arrive at the same time, and triggers the synchronous processor to realize clock synchronization on the post-stage processor, thereby realizing cross-board synchronization of any number of receiving devices by one external clock, and improving the synchronization efficiency. And the hardware complexity and cost are reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of clock synchronization of ATE test equipment, and in particular to a system and method, device and medium thereof for synchronizing a high-speed clock based on a low-speed clock. Background Art

[0002] In ATE test equipment with multiple boards, different boards use different clock sources. Even if the clock sources are of the same frequency, there will be a certain frequency deviation. Due to the existence of frequency deviation, after long-term use, the clocks on different boards will be misaligned, resulting in misalignment of control and data between boards, resulting in control asynchrony and data asynchrony, affecting the normal operation of ATE test equipment.

[0003] In some related technologies, some solutions are proposed to use external clocks to synchronize the clock inside the board, such as using an external clock to synchronize a clock inside the board, or synchronizing multiple external clock sources to an internal clock domain. However, this requires that the phase of the external clock is the same as that of the clock inside the board, and the frequency of the clock inside the board is an integer multiple of the external clock. Therefore, the clock synchronization of the related technology has high requirements for the external clock and the clock inside the board, resulting in high hardware complexity and design difficulty. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes a system and method, device, and medium based on synchronizing a high-speed clock with a low-speed clock, which can synchronize multiple internal clocks with one external clock without a restrictive relationship between the internal clock and the external clock, thereby reducing hardware complexity.

[0005] In a first aspect, an embodiment of the present invention provides a system for synchronizing a high-speed clock based on a low-speed clock, comprising:

[0006] An external clock source, the external clock source is used to output an external clock;

[0007] A plurality of receiving devices, wherein the receiving devices include an external clock rising edge collector, an internal clock counter, a synchronous arbitrator, an offset processing module, a synchronous processor and a post-processor, wherein the external clock rising edge collector is connected to the external clock source, the external clock rising edge collector and the internal clock counter are connected to the input end of the synchronous arbitrator, the output end of the synchronous arbitrator is connected to the input end of the offset processing module, the output end of the offset processing module is connected to the synchronous processor, and the synchronous processor is connected to the post-processor;

[0008] Wherein, the external clock rising edge collector outputs a rising edge collection signal to the synchronous arbiter in response to the rising edge of the external clock, and the internal clock counter is used to count the trigger edge of the internal clock, and output a cycle completion signal when the count value of the trigger edge reaches a preset cycle count value, and the cycle count value is used to represent the multiple between the cycle of the external clock and the cycle of the internal clock, and the cycle of the external clock is greater than the cycle of the internal clock;

[0009] Wherein, the synchronous arbitrator is used to trigger the offset processing module to send a synchronous trigger signal to the synchronous processor when the cycle completion signal and the rising edge acquisition signal do not arrive at the same time;

[0010] The synchronous processor adjusts the processing cycle of the post-processor to be the same as the external clock based on the offset between the internal clock and the external clock in response to the synchronous trigger signal.

[0011] According to some embodiments of the present invention, the offset processing module includes a stop processor, an output of the stop processor is connected to an input of the synchronization processor, and an input of the stop processor is connected to an output of the synchronization arbitrator;

[0012] Wherein, when the rising edge acquisition signal arrives at the synchronous arbiter later than the cycle completion signal, the synchronous arbiter is used to trigger the stop processor to output a pause enable signal to the synchronous processor, and the synchronous processor responds to the pause enable signal, determines the pause duration according to the arrival time difference between the cycle completion signal and the rising edge acquisition signal, and controls the post-processor to pause operation based on the pause duration;

[0013] When the external clock rising edge collector detects the next rising edge collection signal, the next processing cycle of the post-processor is restarted through the synchronization processor.

[0014] According to some embodiments of the present invention, the offset processing module further includes an advance processor, the output end of the advance processor is connected to the input end of the synchronization processor, and the input end of the advance processor is respectively connected to the output end of the synchronization arbitrator;

[0015] Wherein, when the rising edge acquisition signal arrives at the synchronous arbiter earlier than the cycle completion signal, the synchronous arbiter is used to trigger the advance processor to output an advance enable signal to the synchronous processor, and the synchronous processor responds to the advance enable signal, determines the advance duration according to the arrival time difference, determines the target item of the current cycle based on the advance duration, controls the post-processor to process the target item in advance and start the next processing cycle. According to some embodiments of the present invention, the external clock rising edge collector is connected to the internal clock counter, and the internal clock counter clears the count value of the trigger edge in response to the rising edge acquisition signal.

[0016] In a second aspect, an embodiment of the present invention provides a method for synchronizing a high-speed clock based on a low-speed clock, which is applied to the system for synchronizing a high-speed clock based on a low-speed clock according to the first aspect, and the method includes:

[0017] The external clock source sends the external clock to each receiving device, and after the external clock rising edge collector detects the rising edge of the external clock, it sends a rising edge collection signal to the synchronous arbitrator;

[0018] Counting the trigger edge of the internal clock by an internal clock counter, and sending a cycle completion signal to the synchronous arbitrator when the count value of the trigger edge reaches a preset cycle count value, wherein the cycle count value is used to represent the multiple between the cycle of the external clock and the cycle of the internal clock, and the cycle of the external clock is greater than the cycle of the internal clock;

[0019] When the rising edge acquisition signal and the cycle completion signal arrive at different times, the synchronous arbitrator triggers the offset processing module to send a synchronous trigger signal to the synchronous processor, and the synchronous processor adjusts the processing cycle of the post-processor to be the same as the external clock based on the offset between the internal clock and the external clock.

[0020] According to some embodiments of the present invention, the offset processing module includes a stop processor and an advance processor, the output end of the stop processor and the output end of the advance processor are respectively connected to the input end of the synchronization processor, and the input end of the stop processor and the input end of the advance processor are respectively connected to the output end of the synchronization arbitrator;

[0021] The synchronous arbitrator triggers the offset processing module to send a synchronous trigger signal to the synchronous processor, and the synchronous processor adjusts the processing cycle of the post-processor to be the same as the external clock based on the offset between the internal clock and the external clock, including:

[0022] When the rising edge acquisition signal reaches the synchronous arbiter later than the cycle completion signal, the synchronous arbiter triggers the stop processor to output a pause enable signal to the synchronous processor;

[0023] The synchronous processor determines the pause duration according to the arrival time difference between the cycle completion signal and the rising edge acquisition signal in response to the pause enable signal, and controls the post-processor to pause operation based on the pause duration;

[0024] When the external clock rising edge collector detects the next rising edge collection signal, the next processing cycle of the post-processor is restarted through the synchronization processor.

[0025] According to some embodiments of the present invention, the synchronous arbitrator triggers the offset processing module to send a synchronous trigger signal to the synchronous processor, and the synchronous processor adjusts the processing cycle of the post-processor to be the same as the external clock based on the offset between the internal clock and the external clock, including:

[0026] When the rising edge acquisition signal reaches the synchronous arbiter earlier than the cycle completion signal, the synchronous arbiter triggers the advance processor to output the advance enable signal to the synchronous processor;

[0027] The synchronization processor determines the advance duration according to the arrival time difference in response to the advance enable signal;

[0028] The target items of the current cycle are determined based on the advance time, and the post-processor is controlled to process the target items in advance and start the next processing cycle.

[0029] According to some embodiments of the present invention, the external clock rising edge collector is connected to the internal clock counter, and after sending a cycle completion signal to the synchronous arbitrator, the method further includes:

[0030] The internal clock counter stops counting;

[0031] When the rising edge acquisition signal is obtained, the current count value of the trigger edge is cleared and the counting is restarted.

[0032] In the third aspect, an embodiment of the present invention provides a device for synchronizing a high-speed clock based on a low-speed clock, comprising at least one control processor and a memory for communicating with the at least one control processor; the memory stores instructions executable by the at least one control processor, and the instructions are executed by the at least one control processor so that the at least one control processor can execute the system for synchronizing a high-speed clock based on a low-speed clock as described in the second aspect above.

[0033] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute the system for synchronizing a high-speed clock based on a low-speed clock as described in the first aspect above.

[0034] The system based on low-speed clock synchronization with high-speed clock according to the embodiment of the present invention has at least the following beneficial effects: an external clock source, the external clock source is used to output an external clock; a plurality of receiving devices, the receiving devices include an external clock rising edge collector, an internal clock counter, a synchronous arbitrator, an offset processing module, a synchronous processor and a post-processor, the external clock rising edge collector is connected to the external clock source, the external clock rising edge collector and the internal clock counter are connected to the input end of the synchronous arbitrator, the output end of the synchronous arbitrator is connected to the input end of the offset processing module, the output end of the offset processing module is connected to the synchronous processor, and the synchronous processor is connected to the post-processor; wherein the external clock rising edge collector responds to the external clock source. The rising edge of the clock outputs a rising edge acquisition signal to the synchronous arbitrator, the internal clock counter is used to count the trigger edge of the internal clock, and outputs a cycle completion signal when the count value of the trigger edge reaches a preset cycle count value, the cycle count value is used to characterize the multiple between the cycle of the external clock and the cycle of the internal clock, and the cycle of the external clock is greater than the cycle of the internal clock; wherein the synchronous arbitrator is used to trigger the offset processing module to send a synchronization trigger signal to the synchronous processor when the cycle completion signal and the rising edge acquisition signal do not arrive at the same time; wherein the synchronous processor adjusts the processing cycle of the post-processor to be the same as the external clock based on the offset between the internal clock and the external clock in response to the synchronization trigger signal. According to the technical solution of the embodiment of the present invention, each receiving device outputs a cycle completion signal according to its own cycle count value, and determines the occurrence of frequency deviation by using the fact that the cycle completion signal and the rising edge acquisition signal do not arrive at the synchronous arbitrator at the same time, and realizes cycle synchronization through the synchronous processor, thereby realizing cross-board synchronization of any number of receiving devices by an external clock, reducing hardware complexity and cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a clock connection diagram of an external clock and a receiving device provided by an embodiment of the present invention;

[0036] Figure 2 is a functional module connection schematic diagram of a receiving device provided by another embodiment of the present invention;

[0037] Figure 3 is a working flow chart of a system for synchronizing a high-speed clock based on a low-speed clock provided by another embodiment of the present invention;

[0038] Figure 4 is a flow chart of a method for synchronizing a high-speed clock based on a low-speed clock provided by another embodiment of the present invention;

[0039] Figure 5 It is a structural diagram of a device for synchronizing a high-speed clock based on a low-speed clock provided by another embodiment of the present invention.

[0040] Description of reference numerals:

[0041] 10 external clock source; 20 receiving device; 21 external clock rising edge collector; 22 internal clock counter; 23 synchronization arbitrator; 24 stop processor; 25 advance processor; 26 synchronization processor DETAILED DESCRIPTION

[0042] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0043] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0044] In the description of the present invention, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed" etc. are understood as not including the number itself, and "above", "below", "within" etc. are understood as including the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing the technical features, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0045] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0046] The embodiment of the present invention provides a system based on low-speed clock synchronization of high-speed clock and its method, device and medium, wherein the system based on low-speed clock synchronization of high-speed clock includes: an external clock source, the external clock source is used to output an external clock; multiple receiving devices, the receiving devices include an external clock rising edge collector, an internal clock counter, a synchronous arbitrator, an offset processing module, a synchronous processor and a post-processor, the external clock rising edge collector is connected to the external clock source, the external clock rising edge collector and the internal clock counter are connected to the input end of the synchronous arbitrator, the output end of the synchronous arbitrator is connected to the input end of the offset processing module, the output end of the offset processing module is connected to the synchronous processor, and the synchronous processor is connected to the post-processor; wherein the external clock source is connected to the external clock source, the external clock source is connected to the internal clock counter, the output end of the synchronous arbitrator is connected to the input end of the offset processing module, the output end of the offset processing module is connected to the synchronous processor, and the synchronous processor is connected to the post-processor; The clock rising edge collector outputs a rising edge acquisition signal to the synchronous arbitrator in response to the rising edge of the external clock, and the internal clock counter is used to count the trigger edge of the internal clock, and outputs a cycle completion signal when the count value of the trigger edge reaches a preset cycle count value, and the cycle count value is used to characterize the multiple between the cycle of the external clock and the cycle of the internal clock, and the cycle of the external clock is greater than the cycle of the internal clock; wherein the synchronous arbitrator is used to trigger the offset processing module to send a synchronization trigger signal to the synchronous processor when the cycle completion signal and the rising edge acquisition signal do not arrive at the same time; wherein the synchronous processor adjusts the processing cycle of the post-processor to the same as the external clock based on the offset between the internal clock and the external clock in response to the synchronization trigger signal. According to the technical solution of the embodiment of the present invention, each receiving device outputs a cycle completion signal according to its own cycle count value, and determines the occurrence of frequency deviation by using the fact that the cycle completion signal and the rising edge acquisition signal do not arrive at the synchronous arbitrator at the same time, and realizes cycle synchronization through the synchronous processor, thereby realizing cross-board synchronization of any number of receiving devices by an external clock, reducing hardware complexity and cost.

[0047] First, refer to Figures 1 to 3 The system for synchronizing a high-speed clock based on a low-speed clock provided by an embodiment of the present application includes:

[0048] An external clock source 10, the external clock source 10 is used to output an external clock;

[0049] A plurality of receiving devices 20, the receiving devices 20 comprising an external clock rising edge collector 21, an internal clock counter 22, a synchronous arbitrator 22, an offset processing module, a synchronous processor 26 and a post-processor, the external clock rising edge collector 21 being connected to an external clock source 10, the external clock rising edge collector 21 and the internal clock counter 22 being connected to an input end of the synchronous arbitrator 22, the output end of the synchronous arbitrator 22 being connected to an input end of the offset processing module, the output end of the offset processing module being connected to the synchronous processor 26, and the synchronous processor 26 being connected to a post-processor;

[0050] The external clock rising edge collector 21 outputs a rising edge collection signal to the synchronous arbiter 22 in response to the rising edge of the external clock. The internal clock counter 22 is used to count the trigger edge of the internal clock, and outputs a cycle completion signal when the count value of the trigger edge reaches a preset cycle count value. The cycle count value is used to represent the multiple between the cycle of the external clock and the cycle of the internal clock. The cycle of the external clock is greater than the cycle of the internal clock.

[0051] The synchronous arbiter 22 is used to trigger the offset processing module to send a synchronous trigger signal to the synchronous processor 26 when the cycle completion signal and the rising edge acquisition signal do not arrive at the same time;

[0052] The synchronization processor 26 responds to the synchronization trigger signal and adjusts the processing cycle of the subsequent processor to be the same as the external clock based on the offset between the internal clock and the external clock.

[0053] It should be noted that the external clock source 10 and the receiving device 20 of this embodiment have a one-to-many relationship, that is, one external clock source 10 is connected to multiple receiving devices 20, and the external clock generated by the external clock source 10 is input to each receiving device 20 at the same time. Each receiving device 20 independently executes the clock synchronization scheme of this embodiment, which can reduce the number of external clock sources 10 and simplify the hardware complexity.

[0054] It should be noted that the external clock rising edge collector 21 can detect the rising edge by beating two beats. After beating the external clock, it determines whether the electrical level between the two beats meets the rising edge rule. If so, a rising edge collection signal is generated and sent to the synchronization arbitrator 22.

[0055] It should be noted that the receiving device 20 is internally provided with an internal clock source, through which the internal clock is provided. The internal clock counter 22 is used to count the trigger edges of the internal clock. The trigger edges include rising edges and falling edges. Each time a trigger edge is detected, a count is performed. After the count is completed according to the cycle count value, a cycle completion signal is generated and sent to the synchronous arbiter 22.

[0056] It should be noted that the external clock of this embodiment is a low-speed clock, and it is only necessary to ensure that the external clock is an equal-length clock. The internal clock is a high-speed clock, that is, the period of the external clock is greater than the internal clock. The period count value can be obtained by dividing the period of the external clock by the period of the internal clock, and the period count value is an integer greater than 1. The number of trigger edges of the internal clock between two rising edges should be equal to the period count value.

[0057] Therefore, if the internal and external clocks are synchronized, it can be determined that the rising edge acquisition signal and the cycle completion signal are generated at the same time, and the synchronization arbiter 22 will receive the above two signals at the same time. In this embodiment, whether the synchronization arbiter 22 receives the rising edge acquisition signal and the cycle completion signal at the same time is used as the basis for judging the synchronization of the internal and external clocks. When the above two signals arrive synchronously, it is determined that the internal and external clocks are synchronized, and the judgment of the next cycle continues. If the above two signals arrive asynchronously, there is a deviation between the internal and external clocks. The offset processing module sends a synchronization trigger signal to the synchronization processor 26, and the synchronization processor 26 controls the subsequent processor to suspend processing or advance processing, so that the subsequent processor aligns with the external clock.

[0058] Through the technical solution of this embodiment, the cycle count value can be set in each receiving device 20 according to the cycle multiples of the internal and external clocks, and the rising edge acquisition signal can be triggered after the rising edge of the external clock is detected. The cycle completion signal is triggered after the counting of the cycle count value based on the trigger edge of the internal clock is completed. When the rising edge acquisition signal and the cycle completion signal arrive at the synchronization arbitrator 22 at different times, the synchronization arbitrator 22 determines that the internal and external clocks are not synchronized, and sends a synchronization trigger signal to the synchronization processor 26 through the offset processing module. The synchronization processor 26 suspends or advances the processing of the subsequent processor, so that the processing cycle of the subsequent processor is aligned with the cycle of the external clock, thereby synchronizing the high-speed internal clock through the low-speed external clock. Each receiving device 20 can independently run the above steps according to its own internal clock, so as to synchronize multiple receiving devices 20 with one external clock, simplify the hardware equipment, and still achieve the accuracy of clock synchronization under long-term operation.

[0059] In addition, in one embodiment, referring to Figure 2 and Figure 3 , the offset processing module includes a stop processor 24, an output end of the stop processor 24 is connected to an input end of a synchronization processor 26, and an input end of the stop processor 24 is connected to an output end of a synchronization arbitrator 22;

[0060] When the rising edge acquisition signal arrives at the synchronous arbiter 22 later than the cycle completion signal, the synchronous arbiter 22 is used to trigger the stop processor 24 to output a pause enable signal to the synchronous processor 26. The synchronous processor 26 responds to the pause enable signal and determines the pause duration according to the arrival time difference between the cycle completion signal and the rising edge acquisition signal, and controls the subsequent processor to pause operation based on the pause duration.

[0061] When the external clock rising edge collector 21 detects the next rising edge collection signal, the next processing cycle of the subsequent processor is restarted through the synchronization processor 26 .

[0062] It should be noted that if Figure 2 and Figure 3As shown, when the rising edge acquisition signal arrives at the synchronous arbiter 22 later than the cycle completion signal, it is likely that the external clock runs slower than the internal clock due to factors such as frequency deviation, cycle jitter, and acquisition differences, and the post-processor needs to be paused for a period of time. Based on the condition that the rising edge acquisition signal arrives later than the cycle completion signal, the synchronous arbiter 22 of this embodiment sends a pause enable signal to the synchronous processor 26 by stopping the processor 24. The synchronous processor 26 determines the pause duration according to the arrival time difference between the cycle completion signal and the rising edge acquisition signal, and controls the post-processor to pause all processing until the external clock rising edge collector 21 detects the next rising edge of the external clock, and then restarts the post-processor to ensure that the processing cycle of the post-processor is consistent with the external clock cycle, thereby achieving internal and external clock alignment.

[0063] In addition, in one embodiment, referring to Figure 2 and Figure 3 , the offset processing module further includes an advance processor 25, the output end of the advance processor 25 is connected to the input end of the synchronization processor 26, and the input end of the advance processor 25 is respectively connected to the output end of the synchronization arbitrator 22;

[0064] Among them, when the rising edge acquisition signal arrives at the synchronous arbiter 22 earlier than the cycle completion signal, the synchronous arbiter 22 is used to trigger the advance processor 25 to output an advance enable signal to the synchronous processor 26. The synchronous processor 26 responds to the advance enable signal, determines the advance duration according to the arrival time difference, determines the target item of the current cycle based on the advance duration, controls the subsequent processor to process the target item in advance and start the next processing cycle.

[0065] It should be noted that if Figure 2 and Figure 3 As shown, when the rising edge acquisition signal arrives at the synchronous arbiter 22 earlier than the cycle completion signal, it is very likely that the external clock runs faster than the internal clock due to factors such as frequency deviation, cycle jitter, and acquisition difference. The synchronous arbiter 22 of this embodiment sends an advance enable signal to the synchronous processor 26 through the advance processor 25 based on the condition that the rising edge acquisition signal arrives earlier than the cycle completion signal. The synchronous processor 26 determines the advance time according to the arrival time difference between the cycle completion signal and the rising edge acquisition signal, determines all processing items within the advance time as target items, controls the subsequent processor to advance all target items, and immediately starts processing the next cycle, thereby realizing internal and external clock alignment.

[0066] In addition, in one embodiment, referring to Figure 2 and Figure 3 The external clock rising edge collector 21 is connected to the internal clock counter 22, and the internal clock counter 22 clears the count value of the trigger edge in response to the rising edge collection signal.

[0067] It should be noted that the internal clock counter 22 is cleared and recounted in response to the rising edge acquisition signal. When the internal clock is synchronized with the external clock, the count value is equal to the cycle count value when the rising edge acquisition signal arrives, so the internal clock can count in a complete cycle.

[0068] It should be noted that if the external clock is earlier than the internal clock, the rising edge acquisition signal will be detected before the internal clock counter 22 completes the counting of the cycle count value. At this time, it will be directly cleared and a new count will be performed. This can cooperate with the advance processing operation of the above-mentioned embodiment to align the internal and external clocks, and ensure that the cycle completion signal and the rising edge acquisition signal arrive at the synchronous arbiter 22 synchronously in the next cycle.

[0069] It should be noted that if the external clock is later than the internal clock, after the internal clock counter 22 completes the counting based on the cycle count value, it pauses the counting and waits for the rising edge acquisition signal, and after obtaining the rising edge acquisition signal, it is cleared and a new count is performed. It can cooperate with the pause processing operation of the above embodiment to align the internal and external clocks, and ensure that the cycle completion signal and the rising edge acquisition signal arrive at the synchronization arbiter 22 synchronously in the next cycle.

[0070] In addition, the embodiment of the present invention provides a method for synchronizing a high-speed clock based on a low-speed clock, which is applied to Figures 1 to 3 The system based on low-speed clock synchronizing high-speed clock in the embodiment shown in FIG. Figure 4 The method includes but is not limited to the following steps:

[0071] S10, the external clock source sends the external clock to each receiving device, and the external clock rising edge collector detects the rising edge of the external clock and then sends a rising edge collection signal to the synchronous arbitrator;

[0072] S20, counting the trigger edge of the internal clock through the internal clock counter, and sending a cycle completion signal to the synchronous arbiter when the count value of the trigger edge reaches a preset cycle count value, wherein the cycle count value is used to represent the multiple between the cycle of the external clock and the cycle of the internal clock, and the cycle of the external clock is greater than the cycle of the internal clock;

[0073] S30, when the rising edge acquisition signal and the cycle completion signal arrive at different times, the synchronous arbitrator triggers the offset processing module to send a synchronous trigger signal to the synchronous processor. The synchronous processor adjusts the processing cycle of the post-processor to be the same as the external clock based on the offset between the internal clock and the external clock.

[0074] It should be noted that the technical principle of clock synchronization based on the internal functional module of the receiving device can be referred to Figures 1 to 3 The description of the illustrated embodiment will not be repeated here.

[0075] Through the technical solution of this embodiment, the cycle count value can be set according to the cycle multiples of the internal and external clocks in each receiving device, and the rising edge acquisition signal can be triggered after the rising edge of the external clock is detected. The cycle completion signal is triggered after the counting of the cycle count value based on the trigger edge of the internal clock is completed. When the rising edge acquisition signal and the cycle completion signal arrive at the synchronization arbitrator at different times, the synchronization arbitrator determines that the internal and external clocks are not synchronized, and sends a synchronization trigger signal to the synchronization processor through the offset processing module. The synchronization processor suspends or advances the processing of the post-processor so that the processing cycle of the post-processor is aligned with the cycle of the external clock, thereby synchronizing the high-speed internal clock through the low-speed external clock. Each receiving device can independently run the above steps according to its own internal clock, so as to synchronize multiple receiving devices with one external clock, simplify the hardware equipment, and still achieve the accuracy of clock synchronization under long-term operation.

[0076] In addition, in one embodiment, step S30 specifically includes but is not limited to the following steps:

[0077] S311, when the rising edge acquisition signal reaches the synchronous arbiter later than the cycle completion signal, the synchronous arbiter triggers the stop processor to output a pause enable signal to the synchronous processor;

[0078] S312, the synchronization processor responds to the pause enable signal, determines the pause duration according to the arrival time difference between the cycle completion signal and the rising edge acquisition signal, and controls the subsequent processor to pause operation based on the pause duration;

[0079] S313, when the external clock rising edge collector detects the next rising edge collection signal, the next processing cycle of the subsequent processor is restarted through the synchronization processor.

[0080] It should be noted that the principle of pausing the subsequent processor to achieve clock synchronization based on the stop processor and the synchronization arbitrator can refer to the above Figure 2 and Figure 3 The description of the illustrated embodiment will not be repeated here.

[0081] In addition, in one embodiment, step S30 specifically includes but is not limited to the following steps:

[0082] S321, when the rising edge acquisition signal reaches the synchronous arbiter earlier than the cycle completion signal, the synchronous arbiter triggers the advance processor to output an advance enable signal to the synchronous processor;

[0083] S322, the synchronization processor determines the advance duration according to the arrival time difference in response to the advance enable signal;

[0084] S323, determining the target items of the current cycle based on the advance time, controlling the subsequent processor to process the target items in advance and start the next processing cycle.

[0085] It should be noted that the principle of implementing clock synchronization by pre-processing the post-processor based on the pre-processor and the synchronous arbitrator can refer to the above Figure 2 and Figure 3 The description of the illustrated embodiment will not be repeated here.

[0086] In addition, in one embodiment, the external clock rising edge collector is connected to the internal clock counter, and after executing step S20, the following steps are also included but not limited to:

[0087] S21, the internal clock counter stops counting;

[0088] S22, when the rising edge acquisition signal is obtained, the count value of the current trigger edge is cleared and the counting is restarted.

[0089] It should be noted that the principle of stopping and restarting the internal clock counter can refer to the above Figure 2 and Figure 3 The description of the illustrated embodiment will not be repeated here.

[0090] like Figure 5 As shown, Figure 5 : is a structural diagram of a device for synchronizing a high-speed clock based on a low-speed clock according to an embodiment of the present invention. The present invention also provides a device for synchronizing a high-speed clock based on a low-speed clock, comprising:

[0091] The processor 501 may be implemented by a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0092] The memory 502 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 502 can store an operating system and other application programs. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 502, and the processor 501 calls and executes the method of synchronizing a high-speed clock based on a low-speed clock in the embodiment of this application;

[0093] Input / output interface 503, used to implement information input and output;

[0094] Communication interface 504, used to realize communication interaction between the device and other devices, which can be realized through wired mode (such as USB, network cable, etc.) or wireless mode (such as mobile network, WI FI, Bluetooth, etc.);

[0095] A bus 505 that transmits information between the various components of the device (e.g., the processor 501, the memory 502, the input / output interface 503, and the communication interface 504);

[0096] The processor 501 , the memory 502 , the input / output interface 503 and the communication interface 504 are connected to each other in communication within the device via the bus 505 .

[0097] An embodiment of the present application also provides an electronic device, including the device for synchronizing a high-speed clock based on a low-speed clock as described above.

[0098] An embodiment of the present application further provides a storage medium, which is a computer-readable storage medium and stores a computer program. When the computer program is executed by a processor, the method for synchronizing a high-speed clock based on a low-speed clock is implemented.

[0099] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and are implemented to be located in one place, or may also be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0100] It will be appreciated by those skilled in the art that all or some of the steps and systems in the disclosed method above may be implemented as software, firmware, hardware and appropriate combinations thereof. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that may be used to store desired information and may be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically include computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0101] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above-mentioned implementation mode. Technical personnel familiar with the field can also make various equivalent deformations or substitutions under the shared conditions without violating the spirit of the present invention. These equivalent deformations or substitutions are all included in the scope defined by the claims of the present invention.

Claims

1. A system based on synchronizing a high-speed clock with a low-speed clock, characterized in that: include: An external clock source, the external clock source is used to output an external clock; A plurality of receiving devices, wherein the receiving devices include an external clock rising edge collector, an internal clock counter, a synchronous arbitrator, an offset processing module, a synchronous processor and a post-processor, wherein the external clock rising edge collector is connected to the external clock source, the external clock rising edge collector and the internal clock counter are connected to the input end of the synchronous arbitrator, the output end of the synchronous arbitrator is connected to the input end of the offset processing module, the output end of the offset processing module is connected to the synchronous processor, and the synchronous processor is connected to the post-processor; Wherein, the external clock rising edge collector outputs a rising edge collection signal to the synchronous arbiter in response to the rising edge of the external clock, and the internal clock counter is used to count the trigger edge of the internal clock, and output a cycle completion signal when the count value of the trigger edge reaches a preset cycle count value, and the cycle count value is used to represent the multiple between the cycle of the external clock and the cycle of the internal clock, and the cycle of the external clock is greater than the cycle of the internal clock; Wherein, the synchronous arbitrator is used to trigger the offset processing module to send a synchronous trigger signal to the synchronous processor when the cycle completion signal and the rising edge acquisition signal do not arrive at the same time; The synchronous processor adjusts the processing cycle of the post-processor to be the same as the external clock based on the offset between the internal clock and the external clock in response to the synchronous trigger signal.

2. The system based on synchronizing a high-speed clock with a low-speed clock according to claim 1, characterized in that: The offset processing module includes a stop processor, an output end of the stop processor is connected to an input end of the synchronization processor, and an input end of the stop processor is connected to an output end of the synchronization arbitrator; Wherein, when the rising edge acquisition signal arrives at the synchronous arbiter later than the cycle completion signal, the synchronous arbiter is used to trigger the stop processor to output a pause enable signal to the synchronous processor, and the synchronous processor responds to the pause enable signal, determines the pause duration according to the arrival time difference between the cycle completion signal and the rising edge acquisition signal, and controls the post-processor to pause operation based on the pause duration; When the external clock rising edge collector detects the next rising edge collection signal, the next processing cycle of the post-processor is restarted through the synchronization processor.

3. The system based on synchronizing a high-speed clock with a low-speed clock according to claim 2, characterized in that: The offset processing module further includes an advance processor, the output end of the advance processor is connected to the input end of the synchronization processor, and the input end of the advance processor is respectively connected to the output end of the synchronization arbitrator; Among them, when the rising edge acquisition signal arrives at the synchronous arbitrator earlier than the cycle completion signal, the synchronous arbitrator is used to trigger the advance processor to output an advance enable signal to the synchronous processor, and the synchronous processor responds to the advance enable signal, determines the advance duration according to the arrival time difference, determines the target item of the current cycle based on the advance duration, controls the post-processor to process the target item in advance and start the next processing cycle.

4. The system based on synchronizing a high-speed clock with a low-speed clock according to claim 1, characterized in that: The external clock rising edge collector is connected to the internal clock counter, wherein the internal clock counter stops counting after outputting the cycle completion signal, and restarts counting after clearing the count value of the trigger edge in response to the rising edge collection signal.

5. A method for synchronizing a high-speed clock based on a low-speed clock, characterized in that: The method applied to the system based on synchronizing a high-speed clock with a low-speed clock according to any one of claims 1 to 4 comprises: The external clock source sends the external clock to each receiving device, and after the external clock rising edge collector detects the rising edge of the external clock, the rising edge collection signal is sent to the synchronous arbitrator; Counting the trigger edge of the internal clock by an internal clock counter, and sending a cycle completion signal to the synchronous arbitrator when the count value of the trigger edge reaches a preset cycle count value, wherein the cycle count value is used to represent the multiple between the cycle of the external clock and the cycle of the internal clock, and the cycle of the external clock is greater than the cycle of the internal clock; When the rising edge acquisition signal and the cycle completion signal arrive at different times, the synchronous arbitrator triggers the offset processing module to send a synchronous trigger signal to the synchronous processor, and the synchronous processor adjusts the processing cycle of the post-processor to be the same as the external clock based on the offset between the internal clock and the external clock.

6. The method for synchronizing a high-speed clock based on a low-speed clock according to claim 5, characterized in that: The offset processing module includes a stop processor and an advance processor, the output end of the stop processor and the output end of the advance processor are respectively connected to the input end of the synchronization processor, and the input end of the stop processor and the input end of the advance processor are respectively connected to the output end of the synchronization arbitrator; The synchronous arbitrator triggers the offset processing module to send a synchronous trigger signal to the synchronous processor, and the synchronous processor adjusts the processing cycle of the post-processor to be the same as the external clock based on the offset between the internal clock and the external clock, including: When the rising edge acquisition signal reaches the synchronous arbiter later than the cycle completion signal, the synchronous arbiter triggers the stop processor to output a pause enable signal to the synchronous processor; The synchronization processor determines the pause duration according to the arrival time difference between the cycle completion signal and the rising edge acquisition signal in response to the pause enable signal, and controls the post-processor to pause operation based on the pause duration; When the external clock rising edge collector detects the next rising edge collection signal, the next processing cycle of the post-processor is restarted through the synchronization processor.

7. The method for synchronizing a high-speed clock based on a low-speed clock according to claim 6, characterized in that: The synchronous arbitrator triggers the offset processing module to send a synchronous trigger signal to the synchronous processor, and the synchronous processor adjusts the processing cycle of the post-processor to be the same as the external clock based on the offset between the internal clock and the external clock, including: When the rising edge acquisition signal reaches the synchronous arbiter earlier than the cycle completion signal, the synchronous arbiter triggers the advance processor to output an advance enable signal to the synchronous processor; The synchronization processor determines the advance duration according to the arrival time difference in response to the advance enable signal; The target items of the current cycle are determined based on the advance time, and the post-processor is controlled to process the target items in advance and start the next processing cycle.

8. The method for synchronizing a high-speed clock based on a low-speed clock according to claim 5, characterized in that: The external clock rising edge collector is connected to the internal clock counter. After sending a cycle completion signal to the synchronous arbitrator, the method further includes: The internal clock counter stops counting; When the rising edge acquisition signal is obtained, the current count value of the trigger edge is cleared and the counting is restarted.

9. A device for synchronizing a high-speed clock based on a low-speed clock, characterized in that: It includes at least one control processor and a memory for communicating with the at least one control processor; the memory stores instructions that can be executed by the at least one control processor, and the instructions are executed by the at least one control processor to enable the at least one control processor to execute the method for synchronizing a high-speed clock based on a low-speed clock as described in any one of claims 5 to 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the method for synchronizing a high-speed clock based on a low-speed clock as described in any one of claims 5 to 8.

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