AI accelerator architecture and method for dual-assembly-line task collaboration and electronic chip

Abstract

The invention provides an AI accelerator architecture and method for dual-assembly-line task collaboration and an electronic chip, and the architecture comprises a task control module and a calculation module, the task control module is connected with the calculation module, and the calculation module comprises a plurality of calculation units; the task control module comprises a first configuration state register, a first memory direct access unit, a task FIFO unit and a cooperative control unit, the first configuration state register is connected with an external central processing unit, and the first memory direct access unit is connected with the first configuration state register, the task FIFO unit and an external main memory; the computing unit comprises a second configuration state register and a second memory direct access unit, the second configuration state register is respectively connected with the cooperative control unit and the second memory direct access unit, and the second memory direct access unit is connected with the main memory. The flexibility of AI acceleration task distribution is improved, the design is relatively simple, and the area is smaller.

Description

Technical Field

[0001] The present invention relates to the field of processor architecture technology, and specifically to an AI accelerator architecture, method and electronic chip for dual-pipeline task collaboration. Background Art

[0002] The design inspiration of neural networks mainly comes from the biological understanding of the nervous system. The inspiration of neural networks comes from the working principle and information processing method of neurons in the human brain. By combining a large number of neurons into neural networks in a specific connection method, the information processing process of the brain is simulated. The structure and algorithm design of neural networks are mainly based on the inspiration of biological neural networks. Through the combination of multiple layers of neurons, neural networks can perform high-level abstraction and reasoning, thereby achieving tasks similar to human intelligence, such as speech recognition, image recognition, natural language processing, etc.

[0003] The multi-layer artificial neural network used in deep learning is the preferred architecture for AI (Artificial Intelligence) applications today. There are two main types of AI accelerator architectures. One is the AI ​​acceleration dedicated ASIC (Application Specific Integrated Circuit) architecture, which designs dedicated chips based on the characteristics of AI computing and does not rely on instruction sets. The advantage of this approach is good AI computing performance, and dedicated AI accelerators are designed for different networks. The disadvantage is poor reusability, requiring the CPU to be used as the main control, and the operator expansion requires hardware modification, which may cause the hardware to fail to keep up with the evolution of AI algorithms. The other is the CPU+NPU (Neural Processing Unit) architecture, which uses the traditional CPU core as the main core and the NPU as the secondary core to accelerate AI computing. The advantage of this architecture is that it can give full play to the performance of the CPU and NPU, and has high flexibility. The disadvantage is that it is less specialized and has inferior performance.

[0004] An existing implementation solution is a CNN (Convolutional Neural Networks) hardware acceleration device for AI chips, which is only used for CNN convolution calculations, does not rely on instruction sets, and needs to frequently occupy an MCU (Microcontroller Unit) as the main control.

[0005] Another existing implementation scheme is a processing architecture consisting of a main core and multiple sub-cores. Using the RISC-V basic instruction set control, the AI ​​acceleration tasks can be disassembled and distributed to multiple sub-cores for parallel processing. Specifically, the main core reads the AI ​​acceleration instructions and source data according to the RV32I basic integer instructions, distributes the acceleration tasks to the sub-cores, and the sub-cores read the source data according to the distributed acceleration tasks. This solution still needs to be implemented based on the instruction set, and the design is relatively complex.

[0006] Another existing solution is composed of a controller and multiple computing units of different structural types. The controller is used to decompose the computational graph of the neural network to be processed into multiple computational subtasks and distribute them to the corresponding task queues of each computing unit. This method requires the controller to decompose the computational graph, which is more complicated to design. Summary of the invention

[0007] The first objective of the present invention is to provide an AI accelerator architecture with dual-pipeline task collaboration that is relatively simple in design and highly flexible.

[0008] A second object of the present invention is to provide an electronic chip comprising the above-mentioned dual-pipeline task collaborative AI accelerator architecture.

[0009] The third object of the present invention is to provide an AI acceleration method for the above-mentioned dual-pipeline task collaboration that occupies less central processing unit master control and has higher flexibility.

[0010] In order to achieve the above-mentioned first purpose, the present invention provides an AI accelerator architecture with dual-pipeline task collaboration, which includes: a task control module and a computing module, the task control module is connected to the computing module, and the computing module includes multiple computing units; the task control module includes a first configuration status register, a first memory direct access unit, a task FIFO unit, and a collaborative control unit, the first configuration status register is connected to an external central processing unit, and the first memory direct access unit is respectively connected to the first configuration status register, the task FIFO unit and the external main memory; the computing unit includes a second configuration status register and a second memory direct access unit, the second configuration status register is respectively connected to the collaborative control unit and the second memory direct access unit, and the second memory direct access unit is connected to the main memory; the central processing unit is used to configure a first data state of the first configuration status register, the first memory direct access unit is used to obtain a task queue from the main memory according to the first data state and to cache the tasks in the task queue to the task FIFO unit, the collaborative control unit is used to configure a target second data state of the target second configuration status register according to the states of the target computing unit and the task FIFO unit, and the target second memory direct access unit accesses the main memory according to the target second data state.

[0011] As can be seen from the above scheme, the present invention is provided with a task control module and a computing module. The task control module reads the task queue from the main memory through the first memory direct access unit, greatly reducing the occupation of the central processing unit main control, and distributes tasks to the computing unit of the computing module through the task FIFO unit collaborative control unit, so that the task control module realizes functions similar to the CPU main control, improves the flexibility and parallel processing capabilities of the computing module, and at the same time, the computing unit is highly specialized, so that the computing unit has a fast computing speed, can increase or decrease functions according to different neural network computing requirements, better optimize the AI ​​accelerator area, and improve resource utilization. Compared with the prior art, the present invention does not need to be based on an instruction set, and the design is relatively simple and the area is smaller. In addition, the task control module is not the main core and has no AI-related computing functions. It is only used for the distribution and control of the tasks of the computing unit. The design method of the task control module is relatively simple, and it can ensure that the control has good flexibility.

[0012] A further solution is that the central processing unit is connected to a second configuration status register.

[0013] It can be seen that the second data state of the second configuration state register can be configured by the task control module or directly by the central processing unit.

[0014] A further solution is that the task FIFO unit includes a serial task FIFO unit and a parallel task FIFO unit; the task queue includes a serial task queue and a parallel task queue, the tasks of the serial task queue are cached to the serial task FIFO unit, and the tasks of the parallel task queue are cached to the parallel task FIFO unit.

[0015] It can be seen that the computing units can process AI tasks in parallel and serially, greatly reducing the occupancy of the main control.

[0016] A further solution is that a task in a task queue includes at least one configuration instruction of a second configuration status register.

[0017] A further solution is that the computing module includes at least one of the following computing units: a matrix computing unit, a vector computing unit, a pooling computing unit and an operator computing unit.

[0018] It can be seen that the type and quantity of computing units can be set according to actual needs.

[0019] In order to achieve the second purpose mentioned above, the present invention provides an electronic chip, including a shell, wherein: the shell includes an AI accelerator architecture with dual-pipeline task collaboration as mentioned above.

[0020] In order to achieve the above-mentioned third purpose, the present invention provides an AI acceleration method for dual-pipeline task collaboration, which includes the following steps: after the external central processing unit configures the first data state of the first configuration status register of the task management module, the first memory direct access unit of the task management module obtains the task queue from the external main memory according to the first data state; the first memory direct access unit caches the tasks in the task queue to the task FIFO unit of the task management module; the collaborative control unit of the task management module configures the target second data state of the target second configuration status register of the target computing module according to the status of the target computing module and the task FIFO unit, and the second memory direct access unit of the target computing module accesses the main memory according to the target second data state.

[0021] It can be seen from the above scheme that after the present invention configures the task management module through an external central processing unit, the task management module controls the distribution of the tasks of the main memory to different computing units, thereby reducing the occupation of the central processing unit as the main control, and the task control distribution flexibility is high.

[0022] A further solution is that the task FIFO unit includes a serial task FIFO unit and a parallel task FIFO unit; the first memory direct access unit caches the tasks of the serial task queue in the task queue to the serial task FIFO unit, and caches the tasks of the parallel task queue in the task queue to the parallel task FIFO unit.

[0023] A further solution is that the collaborative control unit configures the target second data state according to the status of the target computing module, the serial task FIFO unit and the parallel task FIFO unit, including the following steps: after determining that the serial task FIFO unit is ready, and determining that the target computing unit corresponding to the current task currently cached by the serial task FIFO unit is idle and the previous cached task of the serial task FIFO unit is completed, configure the target second configuration status register of the target computing unit corresponding to the current task cached by the serial task FIFO unit according to the current task cached by the serial task FIFO unit; after determining that the parallel task FIFO unit is ready, and determining the target computing unit corresponding to the current task currently cached by the parallel task FIFO unit, configure the target second configuration status register of the target computing unit corresponding to the current task cached by the parallel task FIFO unit according to the current task cached by the parallel task FIFO unit.

[0024] It can be seen that parallel and serial collaborative processing of AI tasks is achieved through the parallel task FIFO unit and the serial task FIFO unit.

[0025] A further solution is that the collaborative control unit configures the target second data state of the target second configuration status register of the target computing module according to the target computing module, the status of the task FIFO unit, and the value indicating the priority setting in the first configuration status register.

[0026] It can be seen that, according to the priority setting, it can be determined whether to give priority to the tasks in the parallel task FIFO unit or the tasks in the serial task FIFO unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is an overall architecture diagram of an AI acceleration processor implemented in an embodiment of an AI accelerator architecture with dual-pipeline task collaboration of the present invention.

[0028] Figure 2 It is a specific architecture diagram of the task control module in the AI ​​accelerator architecture embodiment of the dual-pipeline task collaboration of the present invention.

[0029] Figure 3 It is a schematic diagram of the connection relationship between the task control module, the computing module and the main memory in the embodiment of the dual-pipeline task collaborative AI accelerator architecture of the present invention.

[0030] Figure 4 It is a flow chart of an embodiment of the AI ​​acceleration method for dual-pipeline task collaboration of the present invention.

[0031] Figure 5 yes Figure 4 Specific flow chart of step S3 in FIG.

[0032] Figure 6 yes Figure 5 Specific flow chart of step S34 in FIG.

[0033] The present invention is further described below in conjunction with the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0034] In the dual-pipeline task-coordinated AI accelerator architecture of the present invention, each computing unit of the task control module and the computing module is provided with an independent configuration status register (CSR) and a memory direct access unit implemented based on DMA (Direct Memory Access) technology, so that each computing unit can work independently or in cooperation with each other according to the data state of the configuration status register, thereby improving the resource utilization and bandwidth utilization of the accelerator. The present invention also provides an electronic chip including the above dual-pipeline task-coordinated AI accelerator architecture and a dual-pipeline task-coordinated AI acceleration method.

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the examples described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] Implementation example of dual-pipeline task-coordinated AI accelerator architecture: See also Figure 1 The dual-pipeline task-coordinated AI accelerator architecture 100 of this embodiment includes a task control module 21 and a computing module 31, and the task control module 21 is connected to the computing control module 31. The computing module 31 includes a plurality of independent computing units.

[0037] The task control module 21 is used to configure each computing unit of the computing module 31. Each computing unit of the computing module 31 is responsible for different computing tasks.

[0038] The task control module 21 is also connected to the external central processor 11 and the main memory 41, and the computing module 31 is connected to the external main memory 41. Under the configuration of the external central processor 11, the task control module 21 obtains the task queue from the main memory 41 and assigns the tasks in the task queue to the corresponding computing units in the computing module 31 for processing. The computing units in the computing module 31 can access the main memory 41 and perform calculations according to the instructions corresponding to the assigned tasks to complete the assigned tasks.

[0039] See also Figure 2 The task control module 21 includes a first configuration status register 211, a first memory direct access unit 212, a FIFO (First Input First Output) unit 901 and a collaborative control unit 215, and the task FIFO unit 901 includes a serial task FIFO unit 213 and a parallel task FIFO unit 214.

[0040] The first configuration status register 211 is connected to the external central processor 11, and the first memory direct access unit 212 is respectively connected to the first configuration status register 211, the serial task FIFO unit 213, the parallel task FIFO unit 214 and the main memory 41.

[0041] Each computing unit in the computing module 31 includes a second configuration status register and a second memory direct access unit. The second configuration status register of each computing unit is respectively connected to the cooperative control unit 215 and the second memory direct access unit, and the second memory direct access unit is connected to the main memory 41.

[0042] The first data state of the first configuration status register 211 is configured by the central processing unit 11 through the Advanced Peripheral Bus (APB). The specific content of the first configuration status register 211 configured by the central processing unit 11 includes the starting address and length of the parallel task queue instruction in the task queue, the starting address and length of the serial task queue instruction in the task queue, the interrupt configuration, the number of tasks, etc.

[0043] The second data state of the second configuration state register is configured by the task control module 21. In other embodiments, the second configuration state register is also connected to the central processor 11, and the central processor 11 can also configure the second configuration state register through the peripheral bus.

[0044] The first direct memory access unit 212 is used to directly access the main memory 41 without passing through the central processor 11. The first direct memory access unit 212 is used to obtain the task queue from the main memory 41 according to the first data state, and to cache the tasks in the task queue to the task FIFO unit 901. The tasks in the task queue are cached in the task FIFO unit 901 in the form of configuration instructions of the second configuration status register.

[0045] In the task FIFO unit 901, the serial task FIFO unit 213 and the parallel task FIFO unit 214 respectively cache the configuration instructions of the second configuration status register. When the computing unit is not working and the serial task FIFO unit 213 or the parallel task FIFO unit 214 is ready, the collaborative control unit 215 writes the corresponding configuration data into the corresponding second configuration status register according to the configuration instruction, and the computing unit accesses the main memory 41 to obtain data and calculates according to the status in the second configuration status register, and writes the calculated result into the main memory 41.

[0046] For tasks that need to be executed in sequence, they are processed through the serial task FIFO unit 213. The serial task FIFO unit 213 can only be used to configure the computing unit for use after the previous task of the current task is completed and the computing unit corresponding to the configuration instruction is not currently working. For example, activation calculation is generally required after convolution calculation, and the input of the vector calculation unit depends on the output data of the matrix calculation unit. After the vector calculation unit completes the data calculation, it may perform pooling calculation, or it may directly write the data to the main memory through its own second memory direct access unit.

[0047] For tasks that do not need to be executed in sequence, the configuration instructions of the parallel task FIFO unit 214 can be configured into the second configuration status register of the computing unit by the collaborative control unit 215 only when the corresponding computing unit is not currently working, without waiting for the previous task to be completed.

[0048] When the configuration instructions cached in the serial task FIFO unit 213 and the parallel task FIFO unit 214 correspond to the same computing unit, the configuration is performed according to the value indicating the priority setting in the first configuration status register. For example, if the value indicating the priority setting in the first configuration status register is 1, then the serial task FIFO unit 213 takes precedence over the parallel task FIFO unit 214, and the collaborative control unit 215 writes the corresponding configuration data into the second configuration status register of the computing unit according to the configuration instructions in the serial task FIFO unit 213; when the value indicating the priority setting in the first configuration status register is 0, then the parallel task FIFO unit 214 takes precedence over the serial task FIFO unit 213, and the collaborative control unit 215 writes the corresponding configuration data into the second configuration status register of the computing unit according to the configuration instructions in the parallel task FIFO unit 214.

[0049] The input and output of each computing unit of the computing module 31 are determined by the second configuration status register of the computing unit. The second memory direct access unit is used to achieve direct access to the main memory 41 without going through the central processing unit 11. The second memory direct access unit implements, according to the second data state of the second configuration status register: obtaining data from the main memory 41, calculating based on the obtained data to obtain the output result, and writing the output result to the main memory 41 or outputting it to the next computing unit as the input of the next computing unit. Through the configuration of the second configuration status register, each computing unit can operate interdependently or independently. When operating interdependently, the input of the lower level is generally the output of the upper level. Only when the output of the upper level is ready can the lower level start to calculate, and the upper level can only calculate normally when the lower level can receive the calculation result, otherwise it will be subject to back pressure.

[0050] The collaborative control unit 215 is used to determine a target computing unit among multiple computing units in the computing module 31 according to the current task cached in the FIFO unit 901, and configure the target second data state of the target second configuration state register of the target computing unit according to the state of the target unit and the state of the task FIFO unit 901. The target second memory direct access unit of the target computing unit accesses the main memory according to the target second data state to implement the execution of a specific computing task.

[0051] See also Figure 3The computing module 11 of this embodiment includes a matrix computing unit 311, a vector computing unit 312, a pooling computing unit 313 and an operator computing unit 314. The matrix computing unit 311 is connected to the vector computing unit 312, and the vector computing unit 312 is connected to the pooling computing unit 313. The task control module 21 is connected to each computing unit of the computing unit 11, and each computing unit is respectively connected to the external main memory 41.

[0052] The matrix calculation unit 311 is used for matrix multiplication and addition calculations, including convolution, deconvolution, dilated convolution, depthwise separable convolution, etc. Its feature image input and weights are generally read from the main memory 41 through DMA (direct memory access) technology.

[0053] The vector calculation unit 312 is used for various linear and nonlinear operations, including Rectified Linear Unit (ReLU), Parametric Rectified Linear Unit (PReLU), precision scaling, batch normalization, bias addition, sigmoid function, hyperbolic tangent, etc.

[0054] The pooling calculation unit 313 is used for pooling calculation, including maximum pooling (max pooling), minimum pooling (minpooling), and average pooling (mean pooling).

[0055] The operator calculation unit 314 is an operator responsible for independent calculations, and performs data pre-processing, format conversion, quantization, etc. on the data.

[0056] It can be understood that the number and types of computing units in the computing module 31 can be set according to actual needs.

[0057] Electronic chip embodiment: The electronic chip of this embodiment includes a shell, and the shell includes the dual-pipeline task-coordinated AI accelerator architecture of the above-mentioned embodiment.

[0058] Optionally, the housing of this embodiment also includes the central processing unit and main memory of the above embodiment.

[0059] Implementation example of AI acceleration method for dual-pipeline task collaboration: This embodiment is implemented based on the above-mentioned dual-pipeline task collaborative AI accelerator architecture embodiment.

[0060] See also Figure 4 , this embodiment includes the following steps: S1: Compile the content of neural network calculation through middleware.

[0061] S2: Write the compiled content of the middleware into a task queue and write it into the main memory.

[0062] S3: The AI ​​accelerator performs calculations based on the task queue and completes the tasks in the task queue.

[0063] In the above steps S1 and S2, the content of the neural network calculation needs to be compiled into a task queue matching the present embodiment through the middleware tool. Specifically, the space required for calculation and the input data are planned in the main memory through software, including the input data, weights, parameters, output address space of the neural network, and the task queue instruction space (i.e., the space corresponding to the task queue). The task queue instruction space includes a parallel task instruction space and a serial task instruction space.

[0064] In the above step S3, the AI ​​accelerator implemented based on the above dual-pipeline task collaborative AI accelerator architecture embodiment performs data conversion, quantization, convolution, activation and other calculations to complete each task in the task queue.

[0065] See also Figure 5 , step S3 specifically includes the following steps: S31: After the first configuration status register is configured by the central processing unit, the task queue mode is started.

[0066] S32: The first memory direct access unit reads the task queue from the main memory according to the first data state of the first configuration state register.

[0067] S33: The serial task FIFO unit and the parallel task FIFO unit cache the tasks in the task queue.

[0068] S34: The collaborative control unit configures the target second configuration status register according to the status of the target computing unit, the serial task FIFO unit and the parallel task FIFO unit, and the target second memory direct access unit accesses the main memory according to the target second configuration status register to complete the current task.

[0069] S35: After completing all tasks in the task queue, the collaborative control unit issues an interrupt.

[0070] In the above step S31, the CPU configures the first data state of the first configuration state register of the task control module, including the starting address and length of the task queue, and starts the task queue mode. In the task queue mode, the first memory direct access unit of the task control module starts to read the tasks in the task queue from the memory and distributes the tasks to the computing module for execution.

[0071] In the above step S35, the cooperative control unit turns off all module clocks after all tasks in the task queues are executed.

[0072] See also Figure 6 In the above step S34, the following steps are also included: S341: Determine the status of the serial task FIFO unit, the parallel task FIFO unit, and the target computing unit corresponding to the current task.

[0073] S342: Determine whether the serial task FIFO unit is ready.

[0074] After determining that the serial task FIFO is ready, it can be determined that a configuration instruction corresponding to a task in the task queue is cached in the serial task FIFO, and step S343 can be continued to be executed, otherwise step S345 is executed.

[0075] S343: Determine whether the target computing unit corresponding to the current task is idle and its previous task is completed.

[0076] Since the execution of tasks cached by the serial task FIFO unit has a sequence, it is necessary to determine whether the target computing unit corresponding to the current task currently cached by the serial task FIFO unit is idle and whether the previous task of the current task currently cached by the serial task FIFO unit has been completed. When the judgment result is yes, continue to execute step S344. When the judgment result is no, it is necessary to wait until the previous task of the current task currently cached by the serial task FIFO unit has been completed and / or the target computing unit corresponding to the current task currently cached by the serial task FIFO unit is idle, that is, re-enter step S343.

[0077] S344: Configure the target second configuration status register of the target computing unit according to the current task, and the target computing unit completes the current task according to the target second configuration status register.

[0078] Among them, the target second configuration status register of the target computing unit corresponding to the current task currently cached by the serial task FIFO unit is configured according to the configuration instruction corresponding to the current task currently cached by the serial task FIFO unit, so that the target computing unit completes the current task currently cached by the serial task FIFO unit according to its target second configuration status register, and then jumps to step S348 to determine whether all tasks in the task queue have been completed.

[0079] S345: Determine whether the parallel task FIFO unit is ready.

[0080] After it is determined that the parallel task FIFO is ready, it can be determined that a configuration instruction corresponding to a task in the task queue is cached in the parallel task FIFO, and step S346 can be continued to be executed, otherwise it returns to step S341.

[0081] S346: Determine whether there is free space in the target computing unit corresponding to the current task.

[0082] Since the execution of tasks cached by the parallel task FIFO unit does not have a sequential order requirement, it is only necessary to determine whether the target computing unit corresponding to the current task currently cached by the parallel task FIFO unit is free. When the determination result is yes, continue to execute step S347. When the determination result is no, it is necessary to wait for the target computing unit corresponding to the current task currently cached by the parallel task FIFO unit to be free, that is, re-enter step S346.

[0083] S347: Configure the target second configuration status register of the target computing unit according to the current task, and the target computing unit completes the current task according to the target second configuration status register.

[0084] Among them, the target second configuration status register of the target computing unit corresponding to the current task currently cached by the parallel task FIFO unit is configured according to the configuration instruction corresponding to the current task currently cached by the parallel task FIFO unit, so that the target computing unit completes the current task currently cached by the parallel task FIFO unit according to its target second configuration status register, and then jumps to step S348 to determine whether all tasks in the task queue have been completed.

[0085] S348: Determine whether all tasks in the task queue have been completed.

[0086] If the judgment result is yes, continue to execute step S35, otherwise return to step S341.

[0087] In summary, the dual-pipeline task collaboration architecture of the present invention adopts a coprocessor solution and realizes parallel and serial collaborative processing of tasks by each computing unit of the computing module through the task queue mode of the task control module, thereby improving the flexibility and parallel processing capability of the computing module. The design is relatively simple and has a smaller area. In addition, the design method of the task control module is relatively simple and can ensure good flexibility in AI task distribution.

Claims

1. A dual-pipeline task collaborative AI accelerator architecture, characterized in that: include: A task control module and a computing module, wherein the task control module is connected to the computing module, and the computing module includes a plurality of computing units; The task control module includes a first configuration status register, a first memory direct access unit, a task FIFO unit, and a collaborative control unit, wherein the first configuration status register is connected to an external central processing unit, and the first memory direct access unit is respectively connected to the first configuration status register, the task FIFO unit, and an external main memory; The computing unit comprises a second configuration status register and a second memory direct access unit, the second configuration status register is respectively connected to the collaborative control unit and the second memory direct access unit, and the second memory direct access unit is connected to the main memory; The central processing unit is used to configure a first data state of the first configuration status register, the first memory direct access unit is used to obtain a task queue from the main memory according to the first data state and to cache the tasks in the task queue to the task FIFO unit, the collaborative control unit is used to configure a target second data state of a target second configuration status register according to the states of a target computing unit and the task FIFO unit, and the target second memory direct access unit accesses the main memory according to the target second data state.

2. The dual-pipeline task collaborative AI accelerator architecture according to claim 1, characterized in that: The central processing unit is connected to the second configuration status register.

3. The dual-pipeline task collaborative AI accelerator architecture according to claim 1, characterized in that: The task FIFO unit includes a serial task FIFO unit and a parallel task FIFO unit; The task queue includes a serial task queue and a parallel task queue. The tasks of the serial task queue are cached in the serial task FIFO unit, and the tasks of the parallel task queue are cached in the parallel task FIFO unit.

4. The dual-pipeline task collaborative AI accelerator architecture according to claim 1, characterized in that: A task in the task queue includes at least one configuration instruction of the second configuration status register.

5. The dual-pipeline task-coordinated AI accelerator architecture according to claim 1, characterized in that: The computing module includes at least one of the following computing units: a matrix computing unit, a vector computing unit, a pooling computing unit and an operator computing unit.

6. An electronic chip, comprising a housing, characterized in that: The shell includes an AI accelerator architecture for dual-pipeline task collaboration as described in any one of claims 1 to 5 above.

7. A dual-pipeline task collaborative AI acceleration method, characterized in that: The following steps are involved: After the external central processor configures the first data state of the first configuration state register of the task management module, the first direct memory access unit of the task management module obtains the task queue from the external main memory according to the first data state; The first direct memory access unit caches the tasks in the task queue to the task FIFO unit of the task management module; The collaborative control unit of the task management module configures the target second data state of the target second configuration state register of the target computing module according to the states of the target computing module and the task FIFO unit, and the second memory direct access unit of the target computing module accesses the main memory according to the target second data state.

8. The dual-pipeline task collaborative AI acceleration method according to claim 7, characterized in that: The task FIFO unit includes a serial task FIFO unit and a parallel task FIFO unit; The first direct memory access unit caches the tasks of the serial task queue in the task queue to the serial task FIFO unit, and caches the tasks of the parallel task queue in the task queue to the parallel task FIFO unit.

9. The dual-pipeline task collaborative AI acceleration method according to claim 8, characterized in that: The collaborative control unit configures the target second data state according to the states of the target computing module, the serial task FIFO unit, and the parallel task FIFO unit, including the following steps: After determining that the serial task FIFO unit is ready, and determining that the target computing unit corresponding to the current task currently cached by the serial task FIFO unit is idle and the last cached task of the serial task FIFO unit is completed, configuring the target second configuration status register of the target computing unit corresponding to the current task cached by the serial task FIFO unit according to the current task cached by the serial task FIFO unit; After determining that the parallel task FIFO unit is ready and determining the target computing unit corresponding to the current task currently cached by the parallel task FIFO unit, the target second configuration status register of the target computing unit corresponding to the current task cached by the parallel task FIFO unit is configured according to the current task cached by the parallel task FIFO unit.

10. The dual-pipeline task collaborative AI acceleration method according to claim 9, characterized in that: The collaborative control unit configures a target second data state of a target second configuration status register of the target computing module according to the target computing module, the state of the task FIFO unit, and the value indicating the priority setting in the first configuration status register.

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