Method and device for quickly accessing memory between PCIe devices and medium

Abstract

The invention discloses a fast memory access method and device between PCIe devices and a medium, and relates to the technical field of PCIe. The method comprises the following steps: sending memory region information of a GPU of a first PCIe device to a second PCIe device; wherein the memory area information comprises a memory initial virtual address and a memory area length; mapping a memory area of the GPU of the first PCIe device to an address space of a second PCIe device; and performing Memory Pinning operation on the address space of the second PCIe device so as to fix the address space into the physical memory of the second PCIe device.

Description

Technical Field

[0001] The present application relates to the field of PCIe technology, and in particular to a method, device and medium for fast memory access between PCIe devices. Background Art

[0002] The arrival of 5G has once again promoted the development of the Internet of Things, and with it comes massive amounts of data. Massive data requires timely processing because it takes up a lot of space and resources to store. Heterogeneous computing is a special and novel parallel computing method that can assign different computing tasks to different computing units according to their structural characteristics. It shows advantages that traditional architectures do not have in improving server computing performance, energy efficiency, and computing real-time performance. Therefore, heterogeneous computing technology is an important means to solve the energy efficiency problem of future data centers. There are multiple computing units involved in heterogeneous systems. In order to give full play to the performance of each computing unit, it is necessary to achieve real-time data transmission between them with high bandwidth and low latency.

[0003] However, the current heterogeneous computing field still faces many challenges, which seriously limit its full performance. The following issues are summarized: (1) OpenCL is more versatile, but for actual computing tasks, programming is complex and difficult, and the correctness of the calculation results is difficult to guarantee; (2) During high-load computing, the shared memory communication method puts too much pressure on PCIe device communication, limiting the performance of each computing unit; (3) The computing unit scheduling strategy is basically not considered, which cannot adapt to future data center applications.

[0004] Therefore, how to solve the problem that the CPU memory is used as a transit memory area to copy data in the traditional solution, thereby affecting the data transmission efficiency. Summary of the invention

[0005] The embodiments of the present application provide a method, device and medium for fast memory access between PCIe devices, which are used to solve the following technical problem: the problem that in the traditional solution, the CPU memory is used as a transit memory area to copy data, which affects the data transmission efficiency.

[0006] In a first aspect, an embodiment of the present application provides a method for fast memory access between PCIe devices, the method comprising: sending memory area information of a first PCIe device GPU to a second PCIe device; wherein the memory area information comprises a memory starting virtual address and a memory area length; mapping the memory area of ​​the first PCIe device GPU to the address space of the second PCIe device; and performing a Memory Pinning operation on the address space of the second PCIe device to fix the address space to the physical memory of the second PCIe device.

[0007] In one implementation of the present application, the memory area of ​​the GPU of the first PCIe device is mapped to the address space of the second PCIe device, specifically including: constructing a memory translation table in the second PCIe device according to the starting virtual address and the memory area length information, and sending the memory translation table to the hardware of the second PCIe device for memory registration; wherein the memory translation table contains several pieces of memory area information of the GPU of the first PCIe device; the hardware of the second PCIe device constructs a corresponding memory protection table according to each piece of memory area information in the memory translation table; wherein the memory protection table contains physical address information to be stored.

[0008] In one implementation of the present application, before performing a Memory Pinning operation on the address space of the second PCIe device, the method also includes: determining whether the physical memory of the second PCIe device meets the requirements of the fixed address space; if the physical memory of the second PCIe device does not meet the fixed requirements, identifying storage occupancy information, and initiating a content release request based on the storage occupancy information.

[0009] In one implementation of the present application, after performing a Memory Pinning operation on the address space of the second PCIe device, the method further includes: sending a confirmation message to the first PCIe device; wherein the confirmation message includes an identification that the second PCIe device has successfully pinned the address space; after the first PCIe device receives the confirmation message, opening the access restriction of the memory area to the second PCIe device to allow the second PCIe device to copy the memory area.

[0010] In one implementation of the present application, after opening access restrictions to the memory area to the second PCIe device, the method also includes: constructing a status information table entry for the memory area in a memory translation table; wherein the status information is used to identify whether the memory area is being accessed or has been locked.

[0011] In one implementation of the present application, the method also includes: when the second PCIe device accesses the memory area, querying the status information in the memory translation table to determine whether the memory area is being accessed or has been locked; if the memory area is being accessed or has been locked, monitoring the status information, and when the status information changes to an accessible state, accessing the memory area to perform a data copy task.

[0012] In one implementation of the present application, a memory area is accessed to perform a data copy task, specifically including: based on the memory area information contained in a memory translation table, the memory area is accessed and the data to be transmitted in the memory area is copied; based on the memory protection table contained in the memory translation table, a corresponding memory protection table is determined, and based on the physical address information to be stored contained in the memory protection table, the copied data to be transmitted is stored in the physical memory of the second PCIe device.

[0013] In one implementation of the present application, the method further includes: recording an access log when the second PCIe device accesses the memory area; wherein the access log includes the access time, the access device identifier, and the accessed memory area information.

[0014] In a second aspect, an embodiment of the present application also provides a fast memory access device between PCIe devices, the device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute a fast memory access method between PCIe devices such as any one of the above items.

[0015] In a third aspect, an embodiment of the present application further provides a non-volatile computer storage medium for fast memory access between PCIe devices, storing computer executable instructions, which, when executed, implement a method for fast memory access between PCIe devices such as any of the above.

[0016] The embodiments of the present application provide a method, device and medium for fast memory access between PCIe devices, which have the following beneficial effects: 1. Improve memory access speed: By directly sending the memory area information of the first PCIe device (such as GPU) to the second PCIe device and mapping it to the address space of the second PCIe device, and performing the Memory Pinning operation to fix the address space, the address conversion and memory management overhead during memory access are reduced, thereby significantly improving the memory access speed between PCIe devices. This improvement is particularly important for application scenarios that require high-speed data transmission and processing, such as high-performance computing, real-time data processing, etc.

[0017] 2. Enhanced memory management flexibility: The memory mapping and memory pinning operations in the present invention can dynamically adjust the access rights and pinning status of the memory area according to actual needs. At the same time, by constructing a memory translation table and a memory protection table, accurate management and protection of the memory area is achieved, which not only ensures the security of memory access, but also improves the flexibility of memory management.

[0018] 3. Optimize memory resource utilization: Before executing the Memory Pinning operation, the present invention effectively avoids the waste of memory resources by judging whether the physical memory of the second PCIe device meets the pinning requirements and initiating a content release request based on the storage occupancy information. In addition, by constructing a state information table entry of the memory area and monitoring the access status of the memory area in real time, the utilization efficiency of memory resources is further improved.

[0019] 4. Simplify the memory access process: The present invention simplifies the memory access process between PCIe devices by constructing a memory translation table and a memory protection table. After receiving the confirmation information, the first PCIe device can open the access restrictions of the memory area to the second PCIe device without the need for complex address conversion and permission verification processes, thereby reducing the complexity and delay of memory access.

[0020] 5. Enhanced data security: The present invention achieves fine control and tracking of memory area access by constructing a memory protection table and recording access logs. When accessing a memory area, it is necessary to query the status information in the memory translation table to ensure that the memory area is not occupied or locked by other devices, thereby effectively preventing data conflicts and illegal access. At the same time, the recording of access logs also provides strong support for subsequent data analysis and troubleshooting. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 A flowchart of a method for fast memory access between PCIe devices provided in an embodiment of the present application; Figure 2 A schematic diagram of the internal structure of a memory fast access device between PCIe devices provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0023] The embodiments of the present application provide a method, device and medium for fast memory access between PCIe devices, which are used to solve the following technical problem: the problem that in the traditional solution, the CPU memory is used as a transit memory area to copy data, which affects the data transmission efficiency.

[0024] The technical solution proposed in the embodiments of the present application is described in detail below with reference to the accompanying drawings.

[0025] Figure 1 A flowchart of a method for fast memory access between PCIe devices provided in an embodiment of the present application. Figure 1 As shown, a method for fast memory access between PCIe devices provided in an embodiment of the present application specifically includes the following steps: Step 101: Send memory area information of a first PCIe device GPU to a second PCIe device.

[0026] In the embodiment of the present application, the memory area information includes the memory starting virtual address and the memory area length.

[0027] In one embodiment, in a typical heterogeneous computing system environment, it is assumed that the first PCIe device is a high-performance GPU, which undertakes tasks such as graphics rendering and large-scale data parallel computing, and has a large amount of data to be processed or processed stored in its video memory (memory area). The second PCIe device can be an FPGA board for specific data processing, or other PCIe devices with data processing requirements. When the data interaction demand arises, the GPU sends the memory area information of the data that needs to be shared or transmitted in its own memory area to the second PCIe device. For example, the memory area is used to store image data after GPU acceleration processing, and its memory starting virtual address is 0x10000000, and the memory area length is 1024KB. The GPU uses a specific communication protocol and driver to accurately pass this information to the second PCIe device through the PCIe bus. This process is the starting point of the entire fast memory access process and provides basic data for subsequent operations.

[0028] Step 102: Map the memory area of ​​the first PCIe device GPU to the address space of the second PCIe device.

[0029] In one embodiment of the present application, after the memory area information of the GPU of the first PCIe device is sent to the second PCIe device, the memory area of ​​the GPU of the first PCIe device is mapped to the address space of the second PCIe device.

[0030] Specifically, according to the starting virtual address and the memory area length information, a memory translation table is constructed in the second PCIe device, and the memory translation table is sent to the hardware of the second PCIe device for memory registration; wherein the memory translation table includes several pieces of memory area information of the GPU of the first PCIe device; the hardware of the second PCIe device constructs a corresponding memory protection table according to each piece of memory area information in the memory translation table; wherein the memory protection table includes physical address information to be stored.

[0031] In one embodiment, after receiving the memory area information (memory starting virtual address and memory area length) of the GPU, the second PCIe device will build a memory translation table in its own system. For example, if the page length is set to 4KB, and the received memory area length is 1024KB, 256 memory translation table entries need to be built. Each table entry corresponds to a physical page starting address in the GPU memory area. Assuming that the memory starting virtual address is 0x10000000, the first table entry may record the physical page starting address 0x20000000 corresponding to the virtual address. After the construction is completed, the memory translation table is sent to the hardware of the second PCIe device for memory registration so that the hardware can recognize and use this mapping information.

[0032] Furthermore, the hardware of the second PCIe device constructs corresponding memory protection tables according to each memory area information in the memory translation table. The memory protection table contains the physical address information to be stored, which is used to ensure the security and accuracy of data during transmission and storage. For example, for the memory area corresponding to the first memory translation table entry mentioned above, the memory protection table will record the access rights of the area (such as read-only, read-write, etc.), memory range, and corresponding physical storage address information to prevent illegal access and data damage.

[0033] Step 103: Perform a Memory Pinning operation on the address space of the second PCIe device to pin the address space to the physical memory of the second PCIe device.

[0034] In one embodiment of the present application, after mapping the memory area of ​​the GPU of the first PCIe device to the address space of the second PCIe device, it is first necessary to determine whether the physical memory of the second PCIe device meets the requirements of the fixed address space.

[0035] Specifically, it is determined whether the physical memory of the second PCIe device meets the requirement of the fixed address space; if the physical memory of the second PCIe device does not meet the fixed requirement, the storage occupancy information is identified, and based on the storage occupancy information, a content release request is initiated.

[0036] In one embodiment, the operating system or related management program of the second PCIe device monitors the usage of physical memory in real time and calculates the size of the currently available continuous physical memory space. Assuming that a large amount of memory has been allocated in the current system for other tasks, the remaining continuous physical memory space is 512KB, and the length of the GPU memory area that needs to be fixed is 1024KB. At this time, the physical memory does not meet the fixed requirements. When it is found that the physical memory does not meet the fixed requirements, the system will further identify the storage occupancy information. Through the memory management module, analyze which processes or tasks occupy too much memory resources, and determine which memory areas can be safely released. For example, it is found that a temporary data storage process occupies a large amount of memory, and some of the data in the process is no longer used. The system will initiate a content release request to the process and notify it to release the corresponding memory space. After the process responds to the request and releases the memory, recheck whether the physical memory meets the requirements until the conditions for the Memory Pinning operation are met.

[0037] In one embodiment of the present application, when it is determined that the physical memory of the second PCIe device meets the requirements of the fixed address space, a Memory Pinning operation is performed on the address space of the second PCIe device to fix the address space to the physical memory of the second PCIe device.

[0038] In one embodiment, after confirming that the physical memory of the second PCIe device meets the requirements, a MemoryPinning operation is performed. This operation is implemented through the memory management function of the operating system kernel, and the mapped GPU memory area address space is fixed to the physical memory of the second PCIe device. For example, a specific system call (such as a related memory locking function that may be involved in the Linux system) is used to establish a stable mapping relationship between the previously mapped memory area and the physical memory, ensuring that the physical address of the memory area will not change during the data transmission process, and ensuring that the DMA device can stably access the memory area.

[0039] In one embodiment of the present application, after performing a Memory Pinning operation on the address space of the second PCIe device, a confirmation message is sent to the first PCIe device; wherein the confirmation message includes an identification that the second PCIe device has successfully pinned the address space; after the first PCIe device receives the confirmation message, the access restriction of the memory area is opened to the second PCIe device to allow the second PCIe device to copy the memory area.

[0040] In one embodiment of the present application, after the access restriction of the memory area is opened to the second PCIe device, a state information table entry of the memory area is constructed in the memory translation table; wherein the state information is used to identify whether the memory area is being accessed or has been locked.

[0041] In one embodiment of the present application, when the second PCIe device accesses the memory area, the status information in the memory translation table is queried to determine whether the memory area is being accessed or has been locked; if the memory area is being accessed or has been locked, the status information is monitored, and when the status information changes to an accessible state, the memory area is accessed to perform a data copy task.

[0042] In one embodiment of the present application, a memory area is accessed to perform a data copy task, specifically including: based on the memory area information contained in the memory translation table, the memory area is accessed, and the data to be transmitted in the memory area is copied; based on the memory protection table contained in the memory translation table, the corresponding memory protection table is determined, and based on the physical address information to be stored contained in the memory protection table, the copied data to be transmitted is stored in the physical memory of the second PCIe device.

[0043] In one embodiment, the second PCIe device uses a hardware component such as a DMA engine to access the memory area based on the memory area information contained in the memory translation table. For example, according to the physical page start address recorded in the memory translation table, the data in the GPU memory area is read in sequence, and the data to be transmitted is copied. Assuming that a series of image pixel data is stored in the memory area, the DMA engine reads these pixel data block by block and temporarily stores them in the internal buffer according to the set transmission rules. The corresponding memory protection table is determined based on the memory protection table contained in the memory translation table, and the copied data to be transmitted is stored in the physical memory of the second PCIe device according to the physical address information to be stored contained in the memory protection table. For example, the memory protection table specifies a storage address of 0x30000000, and the DMA engine stores the temporarily stored image pixel data in the physical memory of the second PCIe device accurately according to the address information, completing the data transmission and storage process.

[0044] In one embodiment of the present application, when the second PCIe device accesses the memory area, an access log is recorded; wherein the access log includes the access time, the access device identifier, and the accessed memory area information.

[0045] In one embodiment, during the entire access process, the second PCIe device will record a detailed access log. The log recording module will record the access time, accurate to milliseconds, such as "2024-10-01 10:10:10.123"; the access device identifier, that is, its own device ID, assumed to be "0x0001"; the accessed memory area information, such as the memory start virtual address and length, etc. These log information is stored in a specific storage area of ​​the device (such as a log buffer in local flash memory or memory), which provides an important basis for subsequent data analysis, performance optimization, and troubleshooting. For example, by analyzing the access log, it can be found that frequent accesses in certain time periods have caused system performance to degrade, and then the memory access strategy can be optimized in a targeted manner.

[0046] The above is an embodiment of the method proposed in this application. Based on the same inventive concept, this application embodiment also provides a memory fast access device between PCIe devices, and its structure is as follows: Figure 2 shown.

[0047] Figure 2 A schematic diagram of the internal structure of a PCIe device memory fast access device provided in an embodiment of the present application. Figure 2 As shown, the device includes: at least one processor 201; and, a memory 202 communicatively connected to the at least one processor; The memory 202 stores instructions that can be executed by at least one processor, and the instructions are executed by at least one processor 201 to enable at least one processor 201 to: Sending memory area information of the first PCIe device GPU to the second PCIe device; wherein the memory area information includes a memory start virtual address and a memory area length; Mapping a memory area of ​​the first PCIe device GPU to an address space of the second PCIe device; A Memory Pinning operation is performed on the address space of the second PCIe device to pin the address space to the physical memory of the second PCIe device.

[0048] Some embodiments of the present application provide corresponding Figure 1 A non-volatile computer storage medium for fast memory access between PCIe devices, storing computer executable instructions, wherein the computer executable instructions are set as: Sending memory area information of the first PCIe device GPU to the second PCIe device; wherein the memory area information includes a memory start virtual address and a memory area length; Mapping a memory area of ​​the first PCIe device GPU to an address space of the second PCIe device; A Memory Pinning operation is performed on the address space of the second PCIe device to pin the address space to the physical memory of the second PCIe device.

[0049] Each embodiment in this application is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the IoT device and medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0050] The system and medium provided in the embodiments of the present application correspond one-to-one to the method. Therefore, the system and medium also have similar beneficial technical effects to the corresponding methods. Since the beneficial technical effects of the methods have been described in detail above, the beneficial technical effects of the system and medium will not be repeated here.

[0051] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0052] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0053] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0054] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0055] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0056] Memory may include non-permanent storage in a computer-readable medium, in the form of random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0057] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0058] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0059] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A method for fast memory access between PCIe devices, characterized in that: The method comprises: Sending memory area information of the first PCIe device GPU to the second PCIe device; wherein the memory area information includes a memory start virtual address and a memory area length; Mapping the memory area of ​​the first PCIe device GPU to the address space of the second PCIe device; A Memory Pinning operation is performed on the address space of the second PCIe device to pin the address space to the physical memory of the second PCIe device.

2. A method for fast memory access between PCIe devices according to claim 1, characterized in that: Mapping the memory area of ​​the first PCIe device GPU to the address space of the second PCIe device specifically includes: According to the starting virtual address and the memory region length information, a memory translation table is constructed in the second PCIe device, and the memory translation table is sent to the hardware of the second PCIe device for memory registration; wherein the memory translation table includes a plurality of pieces of memory region information of the GPU of the first PCIe device; The hardware of the second PCIe device constructs a corresponding memory protection table according to each piece of memory area information in the memory translation table; wherein the memory protection table includes physical address information to be stored.

3. A method for fast memory access between PCIe devices according to claim 1, characterized in that: Before performing a Memory Pinning operation on the address space of the second PCIe device, the method further includes: Determining whether the physical memory of the second PCIe device meets the requirement of fixing the address space; If the physical memory of the second PCIe device does not meet the fixed requirement, storage occupancy information is identified, and a content release request is initiated based on the storage occupancy information.

4. A method for fast memory access between PCIe devices according to claim 2, characterized in that: After performing a Memory Pinning operation on the address space of the second PCIe device, the method further includes: Sending confirmation information to the first PCIe device; wherein the confirmation information includes an identification that the second PCIe device has successfully fixed the address space; After receiving the confirmation information, the first PCIe device opens the access restriction of the memory area to the second PCIe device to allow the second PCIe device to copy the memory area.

5. A method for fast memory access between PCIe devices according to claim 4, characterized in that: After opening the access restriction of the memory area to the second PCIe device, the method further includes: A state information table entry of the memory area is constructed in the memory translation table; wherein the state information is used to identify whether the memory area is being accessed or has been locked.

6. A method for fast memory access between PCIe devices according to claim 5, characterized in that: The method further comprises: When the second PCIe device accesses the memory area, querying the status information in the memory translation table to determine whether the memory area is being accessed or has been locked; If the memory area is being accessed or has been locked, the state information is monitored, and when the state information changes to an accessible state, the memory area is accessed to perform a data copy task.

7. A method for fast memory access between PCIe devices according to claim 6, characterized in that: Accessing the memory area to perform a data copy task specifically includes: Based on the memory area information contained in the memory translation table, access the memory area and copy the data to be transmitted in the memory area; A corresponding memory protection table is determined based on the memory protection table included in the memory translation table, and based on the physical address information to be stored included in the memory protection table, the copied data to be transmitted is stored in the physical memory of the second PCIe device.

8. A method for fast memory access between PCIe devices according to claim 7, characterized in that: The method further comprises: When the second PCIe device accesses the memory area, an access log is recorded; wherein the access log includes access time, access device identification, and accessed memory area information.

9. A memory fast access device between PCIe devices, characterized in that: The device comprises: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute a method for fast memory access between PCIe devices as described in any one of claims 1-8.

10. A non-volatile computer storage medium for fast memory access between PCIe devices, storing computer executable instructions, characterized in that: When the computer executable instructions are executed, a method for fast memory access between PCIe devices as described in any one of claims 1-8 is implemented.

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