Optimization scheme of interposer architecture of 2.5 D multi-chip integrated system

Abstract

The invention relates to an optimization scheme for an intermediate layer architecture of a 2.5 D multi-core-particle integrated system, and aims to improve the communication efficiency among core particles and improve the expandability of the multi-core-particle integrated system. The invention provides an intermediary layer architecture based on a routing-free network, which is used for replacing a traditional network-on-chip (NoC) solution based on a router on an intermediary layer. According to the architecture, the core particles are connected through the well-designed loop structure, so that the complexity and power consumption of the router are eliminated, the communication delay among the core particles is reduced, and the data transmission efficiency is improved. The partition construction method provided by the invention can effectively optimize intermediary layer wiring and ensure efficient communication between the core particles. Hardware structure design is simplified, an injection module, a pop-up module, an input module, an output module and an expansion buffer area module are included, and efficient transmission of data packets is achieved through a pre-calculated routing table. The scheme has the advantages of excellent expandability, low delay, low power consumption and the like, and can support integration of more core particles.

Description

Technical Field

[0001] The present invention relates to the field of computer system architecture design, and in particular to a 2.5D multi-chip integrated system intermediate layer architecture optimization solution. Background Art

[0002] With the continuous development of semiconductor technology, the complexity and functionality of chips are growing exponentially. Constrained by many factors such as the "area wall", the traditional monolithic integrated circuit (SoC) architecture is gradually unable to meet the needs of high bandwidth, low latency and low power consumption in fields such as artificial intelligence applications and high-performance computing. In this context, chiplet technology has gradually emerged and become a breakthrough in the development of chip technology; by decomposing complex monolithic chips into multiple modular sub-chips (chiplets) and then interconnecting them through an interposer, this technology can not only reduce the complexity of design and production, but also greatly improve the chip yield and reduce manufacturing costs.

[0003] On this basis, the application of 2.5D and 3D integration technology has gradually become the focus of the industry. Especially driven by data centers and artificial intelligence applications, chiplet technology has gradually matured and has been widely adopted. Compared with the traditional SoC architecture, the chiplet architecture has significant advantages. First, the modular design can better cope with the increasingly complex chip functional requirements; second, the separation design of the chiplets can effectively improve the manufacturing yield, because each chiplet can be independently designed, manufactured, and tested, avoiding the low yield problem that occurs when large-size single chips are produced. However, despite the obvious advantages, challenges in practical applications still exist. Data transmission across chiplets requires signal conversion, and due to the limited bandwidth caused by pin limitations, the communication delay between chiplets is much higher than the communication delay within the chiplet, resulting in cross-chiplet data transmission becoming a communication bottleneck for 2.5D multi-chiplet integrated systems. How to achieve efficient communication between chiplets has become a major technical problem.

[0004] At present, 2.5D chip integration mainly realizes communication between chiplets by deploying on-chip networks on silicon interposers, while traditional on-chip networks (NoCs) usually use routers and link structures to manage communication between chip cores or chiplets. Although routers have strong scalability in forwarding data packets and support parallel communication, the complexity, power consumption and area occupied by routers themselves have gradually become limiting factors. Especially in large-scale chiplet systems, the superposition of multiple routers not only brings significant delays, but also greatly increases power consumption, creating a bottleneck for the communication efficiency of large-scale chiplet systems.

[0005] In the field of traditional NoC, a new communication architecture has been proposed in recent years - Routerless NoC. Unlike traditional router networks, routerless NoC replaces complex routers with carefully designed loop structures. This design uses the wiring resources on the chip to directly connect communication nodes through loops. Through the reasonable design of the interface hardware structure of each node, it not only ensures routing correctness, but also achieves reduced power consumption, reduced area, reduced latency overhead, and increased throughput.

[0006] There are some recent works that propose different optimization schemes for 2.5D chiplet interposers to achieve high scalability or reduce communication bottlenecks and other optimization goals. Li et al. proposed GIA, a reusable general interposer architecture and an end-to-end design automation framework, which provides a scalable and reusable solution for 2.5D chiplet integration, significantly reducing the development time and cost of custom interposer design; Wang et al. proposed a network-on-interposer (NoI) design based on an interposer for flexible neural network processor (NNP) chip customization, which can significantly reduce communication delays and reduce the area cost of hardware implementation. However, the above works are still based on traditional NoC for design optimization, or optimization for specific application scenarios. There is no work on applying non-routed on-chip networks to interposers. How to seamlessly integrate non-routed on-chip networks into the interposer and optimize them for the characteristics of inter-chiplet communication is the key to improving the efficiency of inter-chiplet data communication and improving the performance of 2.5D multi-chiplet integration systems. Summary of the invention

[0007] In order to solve the problem that the intermediary layer of the 2.5D chip architecture generally adopts the traditional on-chip network based on router for interconnection, but the efficiency of inter-chip communication is not high, the present invention proposes an intermediary layer architecture optimization scheme applied to the 2.5D multi-chip integrated system, so as to determine the optimal architecture of the intermediary layer network connecting multiple chips, reduce the transmission delay of inter-chip communication, and improve the communication efficiency.

[0008] First, the basic chiplet architecture of the study is determined, and the chiplet system consisting of four 4×4 chiplets connected by an intermediate layer network with 4×4 nodes is used as the basic architecture. Then, based on this architecture, the different requirements for link connection between inter-chiplet communication and intra-chiplet communication, as well as the essential differences in the functions of the intermediate layer and chiplet are analyzed.

[0009] Conclusion 1: Intra-chip communication requires that any two nodes are connected, but inter-chip communication only requires the router set responsible for connecting two different cores on the intermediary layer to be connected. Taking the infrastructure mentioned above as an example, the node set of the intermediary layer network is R = {r0, r1, …, r15}, the node set connected to Chiplet1 is R1 = {r0, r1, r4, r5}, and the node set connected to Chiplet2 is R2 = {r2, r3, r6, r7}. It is sufficient to ensure that there is a path between α and β, and for R1, there is no communication requirement between any two nodes.

[0010] The second conclusion is that the router on the intermediary layer is not directly connected to the Core, but is only responsible for routing. Therefore, the cost-effectiveness of applying the NoC Router to the intermediary layer is low. Therefore, considering the simple hardware structure without routing structure and simple routing mechanism, it is very suitable for deployment in the intermediary layer.

[0011] Several existing non-routing loop line schemes are not fully suitable for inter-chip communication. Therefore, based on the characteristics of inter-chip communication, a partition construction method is proposed. This method can find a set of loops that meet the connectivity requirements and wiring resource constraints. Through this set of cleverly placed loops, the routers on the chip are connected to achieve inter-chip communication.

[0012] The present invention applies a new type of network architecture without routing intermediate layers on 2.5D core particles. Different from the NoC network architecture, the routing node does not have the input buffer, cross switch, link distributor and other hardware in the NoC router, but only consists of links, routing tables, a simple link selector and an extended buffer. Although the number of hardware seems to be the same, the actual hardware logic is simplified several times. To create a new network structure, it is necessary to take into account possible network anomalies such as intra-chip deadlock and inter-chip livelock. Our design concept is to set relatively loose conditions to trigger the processing process, while ensuring correctness and minimizing the performance impact as much as possible.

[0013] To achieve the above purpose, the specific technical solutions adopted are as follows:

[0014] In a first aspect, the present invention provides an interposer wiring method customized according to the characteristics of inter-chiplet communication, the method comprising:

[0015] Acquire multiple groups of architecture diagrams of the 2.5D multi-chip integrated system, each group of the architecture diagrams comprising: a system architecture diagram and an intermediate layer node network architecture diagram, the system architecture diagram being a node connection diagram of the multi-chip integrated system, and the intermediate layer node network architecture diagram being a network connection diagram composed of nodes of the intermediate layer of the 2.5D multi-chip integrated system;

[0016] According to the application scenario analysis of the chiplet technology, it is concluded that the scale of chiplets connected to the intermediary layer is small, and the number of cores is generally 4×4. Connecting to 4 nodes on the intermediary layer through 4 border routers is sufficient to meet the inter-chip communication needs of chiplets. Therefore, the problem is simplified, and it is determined that each chiplet connects to 4 nodes of the intermediary layer. Then, a square ring wiring method is proposed for the 4×4, 6×6, 8×8 or even larger node scales of the intermediary layer. The ring refers to a ring structure, connected end to end, and the square ring means that the geometric shape of each ring mapping is a square.

[0017] Use two-tuple<a,b> represents a square ring, a is the node number of the upper left corner of the square ring, b is the node number of the lower right corner of the square ring, and the 4×4 nodes are numbered from left to right and from top to bottom, and partitioned according to the different core particles connected to the nodes on the intermediary layer. Taking the above 4×4 infrastructure as an example, the node set R on the intermediary layer network is R={r0,r1,…,r 15 According to the different connected chiplets, it is divided into four sets: R1 = {r0, r1, r4, r5}, R2 = {r2, r3, r6, r7}, R3 = {r8, r9, r10} 12 ,r 13}, R4={r 11 ,r 12 ,r 14 ,r 15}.

[0018] The wiring method takes a 4×4 node network as an example. The 4×4 node network can be divided into two layers. The first layer is all the nodes outside the 4×4 node network, and the second layer is r5, r6, r9, r 10Four nodes. Select the square ring from the outer layer, and add the square ring <0,15> corresponding to the outermost layer to the square ring set U. Take the upper left corner node r0 of the first layer as the fixed node, and gradually increase the area of ​​the square ring. There are two options <0,5> and <0,10>, but all the nodes connected by the <0,5> square ring are from the same R set. For the intermediate layer that needs to meet the communication requirements between core particles, such wiring is meaningless, so it is excluded. Add the <0,10> square ring to the square ring set U, and then change the fixed node to the upper right corner node r3 of the first layer. Follow the same screening method. Select the rule, add <1,11> to the square ring set U, and so on. After the first layer of square ring screening is completed, the set U = {<0,15>, <0,10>, <1,11>, <4,14>, <5,15>}. The second layer has only four nodes, and the <5,10> square ring also meets the conditions and is added to U. Therefore, the final wiring set of the 4×4 node set consists of six square rings, among which the link directions of the square rings <0,15> and <5,10> corresponding to the first and second layers are counterclockwise, and the link directions of the other square rings are clockwise. Based on this method, it can also be expanded to 6×6 or even larger node scales to screen square rings for wiring.

[0019] According to the specified loop scheme, the loop is determined to be connected by multiple directed links, and the final loop forms a complete cycle. It is stipulated that all loop connections must satisfy the requirement that data packets can be routed in the same direction on the loop, clockwise or counterclockwise.

[0020] In a second aspect, the present invention provides a novel hardware structure of an interposer node of a 2.5D multi-chip integrated system, the hardware structure comprising:

[0021] The injection module is used to inject data packets from the core particles into the intermediate layer network, and is composed of a routing table, vertical links connected to the core particles, and links connected to the ring.

[0022] The pop-up module is used to pop the data packet to the upper target core particle, and is composed of a pop-up link with two flit-sized buffers, a link distributor, and a link connected to the ring.

[0023] The input module is used to receive data packets from the ring, and is composed of x links with a buffer of 1flit size, where x is greater than 1 and less than n-1 (the number of nodes in the intermediate layer is n×n).

[0024] The output module is used to forward the data packet to the next hop of the ring. It consists of x links, where x is greater than 1 and less than n-1. This part of the links has no buffer attached.

[0025] The extended buffer module is composed of multiple extended buffers. The length of an extended buffer is equal to the length of a maximum data packet. The module is connected to the link distributor and x loops, where x is greater than 1 and less than n-1. This part can be used to temporarily store flits.

[0026] Thirdly, we established the logical architecture of the entire 2.5D multi-chip integrated system, and then verified the routing accessibility and correctness of data packets on this system. The feasibility of the entire solution was confirmed by proving the problems of livelock, inter-chip deadlock, intra-chip deadlock, and starvation.

[0027] Compared with the prior art, the present invention has the following advantages:

[0028] 1. The architecture proposed in the present invention is easily expandable and can support more core integration without significantly increasing the design complexity, which allows future systems to be dynamically expanded according to demand.

[0029] 2. The architecture proposed by the present invention has no forwarding delay of routers, so data packets can be transmitted between chiplets more quickly, thereby improving the communication efficiency of inter-chip communication.

[0030] 3. The architecture proposed by the present invention reduces power consumption by eliminating complex routers. Traditional on-chip networks require a large number of routers and buffers, while router-free networks rely on a simplified loop structure, which significantly reduces energy consumption.

[0031] 4. The architecture proposed in the present invention can promote interoperability between chiplets from different manufacturers due to its excellent scalability. The standardized interconnection protocol helps to form an open ecosystem and reduce the integration complexity between different chiplets.

[0032] 5. Since the complexity of the router is eliminated, the design and manufacturing process becomes simpler. This not only reduces development costs, but also speeds up the time to market of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a schematic diagram of the 2.5D core particle system architecture;

[0034] Figure 2 A loop routing scheme for the interposer of 4×4 nodes;

[0035] Figure 3 It is the hardware structure of the intermediate layer node. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings and examples.

[0037] The present invention designs a 2.5D multi-chip integrated system intermediate layer architecture optimization scheme, a non-routing network structure applied to the 2.5D chiplet intermediate layer, and the intermediate layer uses the 2.5D chiplet architecture of the traditional NoC solution. Figure 1 As shown, data packets are generated on chiplets and can be divided into on-chip data packets and off-chip data packets. The difference lies in whether they are transmitted across chiplets. The present invention only focuses on the cross-chiplet transmission of off-chip data packets. It is believed that the load of the four vertical links transmitted by each chiplet to the intermediate layer through the border router is relatively balanced. The present invention innovates the internal structure and interconnection method of the nodes on the intermediate layer. The design mainly includes the design of the wiring method, hardware structure, routing mechanism and the proof of routing correctness. From proposing the wiring method to proving the correctness of routing, the specific design steps are as follows:

[0038] Step 1: Based on the structure of 2.5D Chiplet and the characteristics of inter-chip communication, a routing-free network wiring method is proposed to optimize the goal of reducing the latency overhead and power consumption of inter-chip communication. The 4×4 wiring scheme is as follows: Figure 2 shown.

[0039] In this embodiment, the entire 2.5D Chiplet is composed of four 4×4 chiplets and an interposer with 4×4 nodes. The four chiplets are interconnected through the interposer and wiring is performed on the interposer. Due to the limitations of wiring resources and area overhead, the wiring objectives and limitations are as follows:

[0040] Wiring target:

[0041] Find a set of square rings so that any intermediate layer node is connected to all intermediate layer nodes except the nodes connected to the same chiplet as this node.

[0042] Wiring constraints:

[0043] 1. The nodes connected by the square ring must be nodes connected to different chiplets.

[0044] 2. The maximum number of links between any two nodes is n-1 (the number of nodes in the intermediate layer is described as n×n).

[0045] Design the routing method according to the routing goals and routing constraints. The steps to formulate the routing method are as follows:

[0046] S1: Divide the nodes on the intermediate layer into different sets according to the different connected chiplets. The number of nodes on the intermediate layer is n×n, which is simplified as k. The number of chiplets is m. Each chiplet is connected to four nodes on the intermediate layer. The divided sets can be expressed as R1={r0,r1,r n ,r n+1}, R2={r2,r3,r n+2 ,r n+3}, …, R k / 4 = {r n×(n-1)-2 ,r n×(n-1)-1 ,r n×n-2 ,r n×n-1}.

[0047] S2: Initialize the square ring set U to an empty set and define an integer i with an initial value of 1

[0048] S3: Define the upper left node UL to be numbered (n+1)×(i-1), and the lower right node LR to be numbered n 2 -n×q+nq, if the ring<UL,LR> The connected node set Q is not equal to any set R in step S1, so the ring<UL,LR> Add to the square ring set U

[0049] S4: Define an integer j, with an initial value of 1

[0050] S5: Get the Ring<UL,LR-(n+1)×j> ,<UL+(n+1)×j,LR> ,<UL+j,LR-n×j> ,<UL+n×j,LR-j> , judge these four rings in turn, if the corresponding node set Q is not equal to any set R in step S1, then add the ring to the square ring set U

[0051] S6: Determine whether the integer j is less than If yes, the value of j is increased by 1, and the process returns to step S5 to start the sequential execution. Otherwise, the process goes to step S7.

[0052] S7: Determine whether the integer i is less than n / 2. If so, increase the value of i by 1 and return to step S3 to start execution. Otherwise, the step ends.

[0053] According to the above steps, we get a set of square rings, among which<UL,LR> The square ring is wired in a counter-clockwise direction, and the remaining square rings are wired in a clockwise direction.

[0054] Step 2: Use most of the hardware structure of RouterlessNoC, combine it with the characteristics of the current wiring scheme, and consider the correctness of routing, and improve it to design the hardware structure that best meets the characteristics of this wiring method and inter-chip communication, such as Figure 3As shown in the figure, it consists of an injection module, a pop-up module, an input module, an output module, and an extended buffer module. The specific hardware consists of links, routing tables, link arbitrators, and extended buffers.

[0055] Step 3: Determine the routing accessibility of the network connected by the new hardware structure and the new wiring solution.

[0056] When any data packet is routed from one chiplet to another, the actions that occur on the intermediary layer are as follows:

[0057] The chiplet numbered i injects a data packet p containing nf flits to the node a on the intermediate layer through the border router. First, the routing table is queried according to the number of the target chiplet. Since the loop is predetermined, the routing table is also pre-calculated. If there are multiple links to reach the target chiplet, they are selected in turn. This can make the use of different loops more balanced and reduce the link failure rate.

[0058] Assume that I loop is selected for transmission. When the injection process starts, if nf>1 and it is not connected to other EXBs, an idle EXB is assigned to I and the output port of I is kept for nf cycles. During these nf cycles, any flit arriving through the input port of I is queued to the EXB and released when the buffer slot of the EXB is exhausted. Once the head flit of the packet p arrives at the destination node, the pop-up process begins. However, there is a problem that if there are k loop-reachable nodes X, it may receive up to k headflits at the same time and all of them need to be popped out, but the link width is limited. To solve this problem, we use the fact that the probability of multiple data packets arriving at the same destination in the same cycle is very low. Considering that using multiple vertical links for upward transmission will increase manufacturing costs and introduce additional design costs for chiplet manufacturers, a 2-flit buffer is added to the pop-up link. Data packets are first stored in the buffer and then popped out. When more than 2 head flops arrive, the excess data packets are forcibly deflected. These deflected data packets will continue their respective cycles and return to the destination later. By introducing a livelock avoidance mechanism, it is ensured that the data packets can eventually be popped out and the complete routing process is completed.

[0059] Step 4: Verify the correctness of the route and ensure that there are no routing anomalies. The proof is as follows:

[0060] Livelock:

[0061] If a data packet circulates indefinitely in the network and has no chance to be popped out, a livelock may occur. The following solution is adopted: add a 1-byte long loop counter at each head flit to solve this problem. The initial value is 0. Whenever a data packet is forcibly deflected by the current node because the pop-up link is busy, the counter is increased by 1. If the counter of data packet p reaches 127, but the pop-up link is not available, the node will mark the pop-up link as reserved, and then the data packet completes the last deflection. After the marked pop-up link completes the current data packet, it will not pop out any data packets until data packet p returns to the current node and is popped out through the pop-up link. After p is popped out, the node will cancel the mark of the pop-up link to make it work normally.

[0062] On-chip deadlock:

[0063] Since the data packets arriving at each hop will be immediately ejected or forwarded, there will be no circular dependency, and the necessary conditions for deadlock will not be met, so there will be no deadlock caused by routing. The data packets can always reach the destination node without being blocked by other data packets.

[0064] Deadlock between core particles:

[0065] In order for an inter-chip deadlock to occur, a complete circular dependency line must be formed between the two chiplets, and part of the line must pass through the intermediary layer. As described in the above description of the intra-chip deadlock problem, the network on the intermediary layer does not have a situation where one node depends on another node. Therefore, part of this circular dependency line will not appear on the intermediary layer, and this circular dependency line will not be formed, so it will not cause inter-chip deadlock.

[0066] hunger:

[0067] Starvation is theoretically possible, but the nodes on the intermediate layer network are not directly connected to the Core, but only have routing functions and are passive forwarding. However, in fact, as long as the chiplet routing function is normal, the probability of starvation in the intermediate layer network is almost 0. This situation has never occurred in any experiment conducted, so this problem is not dealt with.

[0068] In the present invention, due to the simple structure of the non-routing structure itself, the hardware overhead is naturally low compared to the NoC router, so the optimization goal mainly considers latency, data throughput and scalability, and the wiring scheme, hardware structure and routing process are gradually refined until the effect is optimal.

Claims

1. 2.5D multi-chip integrated system interposer architecture optimization solution, characterized by: include: Obtain multiple groups of architecture diagrams of the 2.5D multi-chip integrated system, each group of architecture diagrams includes: a system architecture diagram and an intermediate layer node network architecture diagram, the system architecture diagram is a node connection diagram of the multi-chip integrated system, and the intermediate layer node network architecture diagram is a network connection diagram composed of nodes of the intermediate layer of the 2.5D multi-chip integrated system; Set routing goals and routing constraints: Wiring target: Find a set of square rings so that any intermediate layer node is connected to all intermediate layer nodes except the nodes connected to the same chiplet as this node; Wiring constraints: 1) The nodes connected by the square ring must be nodes connected to different chiplets; 2). The maximum number of links between any two nodes is n-1, and the number of nodes in the intermediate layer is described as n×n; The steps to develop a wiring method are as follows: S1: The nodes on the intermediate layer are divided into different sets according to the different connected chiplets. The number of nodes on the intermediate layer is n×n, which is simplified as k. The number of chiplets is m. Each chiplet is connected to four nodes on the intermediate layer. The divided set is represented by R1={r0,r1,r n ,r n+1 }, R2={r2,r3,r n+2 ,r n+3 }, …, R k / 4 = {r n×(n-1)-2 ,r n×(n-1)-1 ,r n×n-2 ,r n×n-1 }; S2: Initialize the square ring set U to an empty set and define an integer i with an initial value of 1; S3: Define the upper left node UL to be numbered (n+1)×(i-1), and the lower right node LR to be numbered n 2 -n×q+nq, if the ring<UL,LR> The connected node set Q is not equal to any set R in step S1, so the ring<UL,LR> Add to the square ring set U; S4: Define an integer j with an initial value of 1; S5: Get the Ring<UL,LR-(n+1)×j> ,<UL+(n+1)×j,LR> ,<UL+j,LR-n×j> ,<UL+n×j,LR-j> , judge these four rings in turn, if the corresponding node set Q is not equal to any set R in step S1, then add the ring to the square ring set U; S6: Determine whether the integer j is less than That is, the value of LR / n is rounded down. If it is, the value of j is increased by 1, and the process returns to step S5 to start the sequential execution. Otherwise, the process goes to step S7. S7: Determine whether the integer i is less than n / 2. If so, increase the value of i by 1 and return to step S3 to start execution. Otherwise, the step ends. According to the above steps, we get a set of square rings, among which<UL,LR> The square ring is wired in a counter-clockwise direction, and the remaining square rings are wired in a clockwise direction.

2. The solution according to claim 1, characterized in that The number of nodes applicable to the routing method is 2n×2n, n=2,3,4,…, and each chiplet is connected to four nodes on the interposer, that is, the number of chiplets is n×n, n=2,3,4,….

3. The solution according to claim 1, characterized in that: Each square ring transmits data in a clockwise or counterclockwise direction. The link is unidirectional. After obtaining the square ring set U according to the wiring steps, all<UL,LR> The square ring is wired in a counter-clockwise direction, and the remaining square rings are wired in a clockwise direction.

4. A hardware structure for implementing the solution of claim 1, characterized in that: The hardware structure includes: The injection module is used to inject data packets from the core particles into the intermediate layer network, which consists of a routing table, vertical links connected to the core particles, and links connected to the ring; The pop-up module is used to pop the data packet to the upper target core particle, which consists of a pop-up link with two flit-sized buffers, a link distributor, and a link connected to the ring; The input module is used to receive data packets from the ring, which consists of x links with a buffer of 1flit size, x is greater than 1 and less than n-1, and the number of intermediate layer nodes is n×n; The output module is used to forward the data packet to the next hop of the loop. It consists of x links, where x is greater than 1 and less than n-1. This part of the links does not have a buffer. The extended buffer module is composed of multiple extended buffers, one extended buffer is equal to the length of a maximum data packet, and the module is connected to the link distributor and x loops, where x is greater than 1 and less than n-1.

5. The hardware structure according to claim 4, characterized in that: The pop-up link part adds two single-flit-sized buffers to temporarily store multiple head flits when resource competition occurs, so as to alleviate the competition pressure of the pop-up link.

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