Fault relief design method, system and equipment for instrument control card, and storage medium

Abstract

The invention provides a fault mitigation design method, system and device for an instrument control card, and a storage medium, and the method comprises the steps: obtaining an initial model of the instrument control card; performing failure mode and influence analysis on the initial model to determine a target element in the initial model; and fault mitigation design is carried out on the target element, and the initial model after the fault mitigation design is used as a target model. According to the invention, the reliability and availability of the card are improved, and the probability of card fault occurrence and the degree of influence on functions are reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of nuclear power equipment reliability management, and in particular to a fault mitigation design method, system, equipment, and storage medium for an instrumentation and control card. Background Art

[0002] As the I&C system has high requirements for stability and availability, and the system becomes more and more complex, higher requirements are placed on key components. As an important part of the system, the failure of I&C cards may cause the performance of the entire system to degrade or even stop working. Therefore, reliability-based fault mitigation of the cards is crucial.

[0003] However, the existing card fault mitigation design technologies mainly include redundancy design, monitoring design and protection design. However, the above card fault mitigation design technologies not only increase the complexity of card circuit design, but may also introduce new card failure modes. Therefore, how to reduce the probability of instrumentation and control card failure and the degree of impact on function through reasonable fault mitigation design is a topic. Summary of the invention

[0004] The technical problem to be solved by the present disclosure is to overcome the defects of the fault mitigation design technology in the prior art that it is complex, costly and may introduce new faults, and to provide a fault mitigation design method, system, device and storage medium for instrumentation and control card components.

[0005] The present invention solves the above technical problems through the following technical solutions:

[0006] The present disclosure provides a fault mitigation design method for an instrumentation control card component, the fault mitigation design method comprising:

[0007] Obtaining an initial model of the instrumentation and control card component;

[0008] Performing a failure mode and effect analysis on the initial model to determine the card failure mode and target element in the initial model;

[0009] A fault mitigation design is performed for the target component, and the initial model after the fault mitigation design is used as the target model.

[0010] Optionally, the fault mitigation design includes a derating design; and performing the fault mitigation design on the target component and using the initial model after the fault mitigation design as the target model comprises:

[0011] performing the derating design for the target component;

[0012] The initial model that completes the derating design is used as the target model.

[0013] Optionally, performing the derating design on the target component includes:

[0014] Acquire a first thermal simulation result for the target element;

[0015] The derating design is performed on the target component according to the first thermal simulation result.

[0016] Optionally, the fault mitigation design includes thermal simulation; and taking the initial model for completing the derating design as the target model includes:

[0017] Performing the thermal simulation on the initial model that has completed the derating design to obtain a second thermal simulation result;

[0018] In response to the second thermal simulation result satisfying the first preset thermal simulation condition, taking the initial model that completes the derating design as the target model;

[0019] and / or,

[0020] In response to the second thermal simulation result not satisfying the second preset thermal simulation condition, the derating design is repeated according to the second thermal simulation result until the second thermal simulation result satisfies the second preset thermal simulation condition.

[0021] Optionally, the fault mitigation design includes a sneak path analysis; performing the fault mitigation design on the target element and using the initial model after the fault mitigation design as the target model includes:

[0022] Performing the latent path analysis on the instrumentation and control card containing the target element;

[0023] The initial model that completes the latent pathway analysis is used as the target model.

[0024] Optionally, taking the initial model that completes the latent path analysis as the target model includes:

[0025] In response to the analysis result of the sneak path analysis satisfying the first preset circuit condition, taking the initial model that completes the sneak path analysis as the target model;

[0026] and / or,

[0027] In response to an analysis result of the sneak path analysis not satisfying a second preset circuit condition, the sneak path analysis is repeatedly performed according to the analysis result until the analysis result satisfies the second preset circuit condition.

[0028] The present disclosure provides a fault mitigation design system for an instrumentation control card component, the fault mitigation design system comprising:

[0029] An acquisition module, used to acquire an initial model of the instrumentation and control card component;

[0030] An analysis module, used for performing a failure mode and effect analysis on the initial model to determine a card failure mode and a target element in the initial model;

[0031] The design module is used to perform fault mitigation design on the target component and use the initial model after the fault mitigation design as the target model, wherein the fault mitigation design includes at least one of the following: derating design, thermal simulation and sneak path analysis.

[0032] Optionally, the fault mitigation design includes a derating design; and the design module is specifically used to:

[0033] performing the derating design for the target component;

[0034] The initial model that completes the derating design is used as the target model.

[0035] Optionally, the design module is specifically used to:

[0036] Acquire a first thermal simulation result for the target element;

[0037] The derating design is performed on the target component according to the first thermal simulation result.

[0038] Optionally, the fault mitigation design includes thermal simulation; and the design module is specifically used for:

[0039] Performing the thermal simulation on the initial model that has completed the derating design to obtain a second thermal simulation result;

[0040] In response to the second thermal simulation result satisfying the first preset thermal simulation condition, taking the initial model that completes the derating design as the target model;

[0041] and / or,

[0042] In response to the second thermal simulation result not satisfying the second preset thermal simulation condition, the derating design is repeated according to the second thermal simulation result until the second thermal simulation result satisfies the second preset thermal simulation condition.

[0043] Optionally, the fault mitigation design includes a sneak path analysis; and the design module is specifically used to:

[0044] Performing the latent path analysis on the instrumentation and control card containing the target element;

[0045] The initial model that completes the latent pathway analysis is used as the target model.

[0046] Optionally, the design module is specifically used to:

[0047] In response to the analysis result of the sneak path analysis satisfying the first preset circuit condition, taking the initial model that completes the sneak path analysis as the target model;

[0048] and / or,

[0049] In response to an analysis result of the sneak path analysis not satisfying a second preset circuit condition, the sneak path analysis is repeatedly performed according to the analysis result until the analysis result satisfies the second preset circuit condition.

[0050] The present disclosure provides an electronic device, including a memory, a processor, and a computer program stored in the memory and used to run on the processor, wherein the processor implements any of the above-mentioned fault mitigation design methods for instrumentation and control card components when executing the computer program.

[0051] The present disclosure provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the fault mitigation design method for an instrumentation and control card component described in any one of the above is implemented.

[0052] The present disclosure provides a computer program product, including a computer program, which, when executed by a processor, implements the fault mitigation design method for an instrumentation and control card component as described in any one of the above.

[0053] On the basis of being in accordance with the common sense in the art, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.

[0054] The positive progress of the present disclosure is that by obtaining the initial model of the instrumentation and control card, and performing failure mode and effect analysis to determine the target element in the initial model, and then performing fault mitigation design for the target element, not only the reliability and availability of the card are improved, but also the probability of card failure and the degree of impact on the function are reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 A flowchart of a fault mitigation design method for an instrumentation and control card component provided by an exemplary embodiment of the present disclosure;

[0056] Figure 2 A flowchart of step 103 provided for an exemplary embodiment of the present disclosure;

[0057] Figure 3 Another flowchart of step 103 provided for an exemplary embodiment of the present disclosure;

[0058] Figure 4A module schematic diagram of a fault mitigation design system for an instrumentation and control card component provided by an exemplary embodiment of the present disclosure;

[0059] Figure 5 The present invention provides a schematic structural diagram of an electronic device according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0060] The present disclosure is further described below by way of examples, but the present disclosure is not limited to the scope of the examples.

[0061] Prefixes such as "first" and "second" are used in the embodiments of the present disclosure only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. The use of prefixes such as ordinal numbers to distinguish description objects in the embodiments of the present disclosure does not constitute a limitation on the described objects. For the statement of the described objects, please refer to the description in the context of the claims or embodiments, and no unnecessary limitation should be constituted due to the use of such prefixes. In addition, in the description of the present embodiment, unless otherwise specified, the meaning of "plurality" is two or more.

[0062] Example 1

[0063] Figure 1 A flowchart of a fault mitigation design method for an instrument control card component provided by an exemplary embodiment of the present disclosure is provided.

[0064] The present disclosure provides a fault mitigation design method for an instrumentation control card component, the fault mitigation design method comprising:

[0065] Step 101: Obtain an initial model of an instrumentation and control card component.

[0066] In this step, assume that an I&C card for a nuclear power plant reactor cooling system is being designed. In this example, it is necessary to obtain an initial model of the I&C card for comprehensive analysis and evaluation. Specifically, obtaining an initial model of the I&C card may include the following:

[0067] 1. Hardware architecture diagram: shows the connection relationship between various components in the instrumentation and control card, such as sensors, actuators, communication interfaces, etc.

[0068] 2. Schematic diagram: The schematic diagram is a graphical representation of the internal circuit connection and working principle of the instrumentation and control card. It includes the connection relationship between all key components (such as sensors, actuators, communication interfaces, etc.), and how they work together to realize the overall function of the card.

[0069] 3. Simulation model: In the design stage, in order to verify the performance and reliability of the instrumentation and control components, a virtual model is usually built using simulation software. This model can simulate the behavior of the components under different working conditions, including normal mode and various failure modes. Through simulation analysis, it is possible to predict the problems that the components may encounter in actual operation and optimize the design in advance.

[0070] 4. Technical Specifications: Describes the technical parameters and performance indicators of the instrumentation and control components, such as measurement range, accuracy requirements, response time, etc.

[0071] 5. Component list: Lists all key components used in the instrumentation and control cards, such as microprocessors, memory, power modules, etc., as well as their models and specifications.

[0072] 6. Software code: realizes the basic functions and logical control of instrumentation and control cards, such as data acquisition, processing, transmission, etc.

[0073] By obtaining these initial model data, we can conduct a comprehensive analysis and evaluation of the instrumentation and control components, identify potential failure points and weak links, and take appropriate fault mitigation measures to improve their reliability and stability. For example, we can use the FMEA (Failure Mode and Effect Analysis) method to conduct a failure mode and effect analysis on the instrumentation and control components to determine which components or modules may cause serious consequences when they fail, thus becoming the focus of fault mitigation design.

[0074] Step 102: Perform failure mode and effect analysis on the initial model to determine the card failure mode and target component in the initial model.

[0075] Step 102 In the I&C system, performing a failure mode and effects analysis (FMEA) on the initial model is a key step to identify potential failure modes and their impact on system functions. Through this analysis, it is possible to determine which components or modules may cause serious consequences when they fail, thus becoming the focus of fault mitigation design. Specifically, the FMEA process can include the following key steps:

[0076] 1. Define the scope: Clarify the object and scope of FMEA, such as specific instrumentation and control components or their subsystems.

[0077] 2. List potential failure modes: Based on experience and historical data, list all possible failure modes of I&C components. These failure modes may include hardware failure, software error, human error, etc.

[0078] 3. Evaluate the impact of failures: Evaluate each failure mode to determine its specific impact on system functionality. This includes impacts on security, availability, performance, etc.

[0079] 4. Determine the card failure mode and target components: Based on the analysis results of the failure impact, determine the key components or modules that may cause serious consequences when different failure modes occur. These components will become the focus of subsequent fault mitigation design.

[0080] For example, suppose you are performing an FMEA on an I&C card used in the reactor cooling system of a nuclear power plant. In this example, the following potential failure modes and their effects may be found:

[0081] 1. Sensor failure: If the temperature sensor fails, the reactor cooling system may not be able to accurately monitor the temperature of the reactor, thus causing a safety accident. Therefore, the temperature sensor is an important target component.

[0082] 2. Communication interface failure: If the communication interface between the instrumentation and control card and the upper control system fails, the control instructions may not be transmitted correctly, affecting the normal operation of the reactor. Therefore, the communication interface is also an important target component.

[0083] 3. Power module failure: If the power module fails, it may cause the entire instrumentation and control card to lose power supply and thus fail completely. Therefore, the power module is also an important target component.

[0084] Through such FMEA, it is possible to identify which components or modules have the greatest impact on system functions when a failure occurs, so that fault mitigation design can be carried out in a targeted manner. This helps to improve the reliability and stability of instrumentation and control components and reduce the probability and impact of failures.

[0085] Step 103: perform fault mitigation design on the target component, and use the initial model after the fault mitigation design as the target model.

[0086] In the design process of the instrumentation and control system, once the target components are determined through FMEA, the next step is to perform fault mitigation design on these target components. The purpose of fault mitigation design is to reduce or eliminate the faults that may be caused by these target components, thereby improving the reliability and stability of the entire system.

[0087] Specifically, fault mitigation design may include the following methods:

[0088] 1. Derating design: Improve the reliability of target components by reducing their working stress. For example, for power modules, their operating temperature can be reduced by adding heat dissipation devices or selecting components that are more resistant to high temperatures, thereby extending their service life and reducing the probability of failure.

[0089] 2. Thermal simulation: Perform thermal simulation analysis on the target component to evaluate its thermal performance under different working conditions. Adjust the design or working environment of the target component based on the simulation results to ensure that it operates within a safe temperature range.

[0090] 3. Potential Path Analysis: Conduct in-depth analysis of circuit design to identify and fix potential circuit path problems, such as potential paths, potential timing, etc. This helps ensure the stability and reliability of the circuit.

[0091] 4. Redundancy design: Add redundant components or backup systems on the critical path to cope with system failures caused by single point failures. For example, for communication interfaces, dual-channel transmission or error detection and correction mechanisms can be used to improve the reliability of data transmission.

[0092] 5. Software optimization: For instrumentation and control cards that include software control, the fault tolerance and recovery capabilities of the system can be improved by optimizing software algorithms and logic. For example, functions such as exception handling mechanisms, regular self-tests, and data backup can be added.

[0093] After the fault mitigation design is completed, the improved initial model needs to be updated to the target model, which will serve as the basis for subsequent design, production, and testing.

[0094] Optionally, the fault mitigation design includes a derating design; step 103 specifically includes:

[0095] Step 1031 , performing derating design for a target component.

[0096] In this step, derating design is a method to improve the reliability of the target component by reducing its working stress. Specifically, derating design can be achieved in the following ways:

[0097] 1. Reduce the operating voltage: By choosing electronic components that can work properly at lower voltages, the risk of component damage caused by excessive voltage can be significantly reduced. For example, for a sensor with a rated operating voltage of 5V, you can choose to work at 3.3V, which ensures safe operation of the component even in the case of power fluctuations or transient high voltage.

[0098] 2. Reduce operating temperature: High temperature is one of the main factors that lead to aging and failure of electronic components. Through maximum temperature derating design, such as junction temperature derating, ambient temperature derating or power derating, the operating temperature of the component can be effectively reduced, thereby improving its reliability. For example, for a power amplifier module, the junction temperature can be reduced from 105°C to 95°C through maximum junction temperature derating design, thereby extending its service life.

[0099] 3. Reduce operating frequency: In some applications, reducing the operating frequency of electronic components can reduce their heat and stress, thereby improving reliability. For example, for a high-frequency communication module, if its operating frequency is appropriately reduced, the electromagnetic interference and thermal stress caused by high-frequency operation can be reduced, thereby reducing the failure rate.

[0100] 4. Increase the safety factor: When designing a circuit, the reliability of the system can be improved by increasing the safety factor. For example, for a power module, its rated output current can be designed to be a certain percentage higher than the actual demand, so that the normal operation of the system can be guaranteed even when the performance of some components deteriorates.

[0101] Optionally, step 1031 specifically includes: obtaining a first thermal simulation result for the target component, and performing a derating design on the target component according to the first thermal simulation result. This is a reliability enhancement measure for the target component. Specifically, this step includes two key steps:

[0102] 1. Get the first thermal simulation results for the target component: This means evaluating the thermal performance of the target component under the expected working environment through computer simulation or experimental testing in the early stage of design. Thermal simulation can help design engineers understand the temperature distribution, hot spots and possible overheating risks of the component under different working conditions.

[0103] 2. Derating the target component based on the first thermal simulation results: Based on the results of the thermal simulation, the design engineer will adjust the operating parameters of the component to reduce its operating stress. This may involve measures such as reducing the power output of the component, reducing the current density, and improving the heat dissipation efficiency. In this way, it can be ensured that the component operates within its rated specifications, thereby extending its service life and reducing the failure rate.

[0104] For example, suppose a transformer in a power module is the target component. In preliminary thermal simulation, it is found that the transformer temperature is too high under high load, close to the maximum temperature limit of its material. To solve this problem, the design engineer may choose to reduce the maximum output power of the transformer, or add a heat sink (such as a heat sink) to improve heat transfer. Such a derating design can effectively prevent the transformer from being damaged due to overheating and improve the reliability of the entire power module.

[0105] Step 1032: Use the initial model that has completed the derating design as the target model.

[0106] After the derating design is completed, the improved initial model needs to be updated to the target model. This target model will include all the changes in the derating design and serve as the basis for subsequent design, production and testing. For example, a derating design is being performed on an instrumentation and control card for the reactor cooling system of a nuclear power plant. After completing these derating designs, an improved target model will be obtained. This target model will have higher reliability and stability and can better meet the needs of the reactor cooling system of a nuclear power plant.

[0107] Through such fault mitigation design, the performance and reliability of instrumentation and control components can be significantly improved, the probability and impact of faults can be reduced, thereby ensuring the safe and stable operation of the system.

[0108] Optionally, the fault mitigation design includes thermal simulation. Step 1032 specifically includes: performing thermal simulation on the initial model that has completed the derating design to obtain a second thermal simulation result. In response to the second thermal simulation result satisfying the first preset thermal simulation condition, the initial model that has completed the derating design is used as the target model; and / or, in response to the second thermal simulation result not satisfying the second preset thermal simulation condition, repeating the derating design according to the second thermal simulation result until the second thermal simulation result satisfies the second preset thermal simulation condition.

[0109] Among them, the initial model that has completed the derating design is subjected to thermal simulation to obtain the second thermal simulation result, which means that after the initial derating design is performed on the target component, a thermal simulation test needs to be performed again to evaluate the effect of the derating design. This simulation will provide data on the temperature distribution and thermal performance of the component under the new working conditions. If the results of the second thermal simulation meet the predetermined thermal performance standards (for example, the temperature is below a certain safety threshold), then the derating design can be considered successful, and the derating model can be determined as the target model. If the results of the second thermal simulation do not meet the expected standards, then the design needs to be adjusted again based on these results, which may be to further reduce the operating voltage, temperature or other parameters, and then perform thermal simulation tests again until the results meet the requirements.

[0110] For example, suppose you are designing a power module for an instrumentation and control card in a nuclear power plant reactor cooling system. In the preliminary derating design, the maximum output power of the power module has been reduced, and a heat sink has been added. Next, this derating model is subjected to a second thermal simulation test. If the test results show that the operating temperature of the power module is still too high, it may be necessary to further reduce its output power or improve the heat dissipation system, and then conduct a thermal simulation test again until the temperature drops to a safe range. Only when the thermal simulation results meet all the preset safety standards will this model be determined as the final target model.

[0111] Optionally, the fault mitigation design includes a sneak path analysis. Step 103 may also specifically include:

[0112] Step 1033: perform potential path analysis on the instrumentation and control card containing the target component.

[0113] In this step, the purpose of latent path analysis is to identify circuit paths that are unintentionally designed in the instrumentation and control card, which may cause the card to produce undesired functions or inhibit desired functions (i.e., possible failure modes of the card). The overall circuit design and functional design of the instrumentation and control card are analyzed, and local circuits in the instrumentation and control card can also be tested and verified according to actual needs. Among them, unintentionally designed circuit paths are usually not considered or identified in the normal circuit design process, and they may be activated under specific operating conditions or fault conditions. Unintentionally designed circuit paths may cause problems such as electrical short circuits, overheating, and signal interference, thereby affecting the performance and safety of the card.

[0114] Specific example:

[0115] Suppose you are performing a sneak path analysis on an I&C card used in a nuclear power plant reactor cooling system. The card contains multiple electronic components, such as a power module, sensor interface, processor, and communication interface. When performing a sneak path analysis, you need to check the following aspects:

[0116] 1. Review the overall circuit design:

[0117] Obtain detailed circuit diagrams and physical layouts of the I&C components to ensure that all components and connections are accurately represented. Review the design of the entire circuit, especially those portions that are not active under normal operation, to identify possible unintentional circuit paths.

[0118] 2. Use simulation tools for sneak path analysis:

[0119] The entire circuit is simulated using electronic design automation (EDA) tools or specialized sneak path analysis software. In the simulation, various operating conditions and fault conditions are simulated to observe whether unexpected current paths are formed. Among them, for simple circuits or small projects, EDA tools or specialized software may not be needed to perform sneak path analysis. Analysts can identify sneak paths by manually inspecting circuit diagrams and using basic circuit theory. However, for large and complex circuit networks, the use of graph-based block analysis methods and specialized sneak path analysis software (such as SATool) can greatly improve the efficiency and accuracy of the analysis.

[0120] 3. Identify potential problems:

[0121] Suppose that during simulation it is discovered that under a certain fault mode, a protection diode of the power module may conduct, thereby forming an unintended current path and causing signal distortion at the sensor interface.

[0122] 4. Develop mitigation measures:

[0123] Modify the circuit design or add protection measures for the problems found. For example, you can change the location or type of protection diodes, or add additional filtering circuits to prevent signal distortion.

[0124] 5. Re-verify:

[0125] After implementing mitigation measures, re-perform the sneak path analysis to ensure that all potential issues are addressed.

[0126] Through this example, we can see how step 1033 helps identify and solve potential potential path problems in instrumentation and control components, thereby improving the reliability and safety of the system.

[0127] Step 1034: The initial model that has completed the latent path analysis is used as the target model.

[0128] After completing the sneak path analysis, if any potential issues are found, the design needs to be modified accordingly. These modifications may include replacing components, adjusting the circuit layout, adding additional protection measures, etc. Once all potential issues are resolved or mitigated, and the design meets all safety and performance standards, this modified model can be determined as the target model.

[0129] Specific example:

[0130] Continuing with the example in step 1033, if the sneak path analysis finds that a capacitor in the power management module may overheat under certain conditions, it may need to be replaced with a capacitor with a higher temperature rating. In addition, it may be necessary to rearrange other components on the circuit board to improve the overall thermal distribution. After these modifications are completed, the sneak path analysis will be performed again to ensure that all potential issues have been resolved. Only when all tests and analyses show that the design is safe will this model be determined as the final target model.

[0131] Through such a process, the reliability and safety of instrumentation and control components can be significantly improved, ensuring that they can operate stably in actual applications and maintain their performance even under extreme or unexpected conditions.

[0132] Optionally, step 1034 may specifically include: in response to the analysis result of the sneak path analysis satisfying a first preset circuit condition, taking the initial model that completes the sneak path analysis as the target model; and / or, in response to the analysis result of the sneak path analysis not satisfying a second preset circuit condition, repeating the sneak path analysis according to the analysis result until the analysis result satisfies the second preset circuit condition.

[0133] Step 1034 describes how to decide whether to determine the current model as the target model or whether further analysis and modification are required after the latent path analysis is completed. This step ensures the reliability and security of the design, and specifically includes the following key actions:

[0134] 1. In response to the analysis result of the sneak path analysis satisfying the first preset circuit condition, the initial model that has completed the sneak path analysis is used as the target model: This means that if the result of the sneak path analysis meets the predetermined safety and performance standards (for example, no problems that may cause unexpected current paths are found), then the current design can be considered reliable, and the model that has undergone the sneak path analysis can be determined as the target model.

[0135] 2. In response to the analysis result of the sneak path analysis not meeting the second preset circuit condition, repeat the sneak path analysis according to the analysis result until the analysis result meets the second preset circuit condition: If the results of the sneak path analysis do not meet the expected standards, then it is necessary to analyze and modify again based on these results. This may involve replacing components, adjusting the circuit layout, adding additional protection measures, etc. Then perform the sneak path analysis test again until the results meet the requirements.

[0136] The "first preset circuit condition" and "second preset circuit condition" mentioned above are standards or thresholds for evaluating and verifying the reliability and safety of circuit designs. These conditions are usually based on industry standards, design specifications or specific application requirements. They can include factors such as temperature limits, current density, voltage drop, power dissipation, etc. For example, in the design of a power module, the first preset circuit condition may include the stability of the power supply output voltage and the maximum allowable value of the ripple voltage. If the power module can keep the output voltage within the specified range under any operating conditions and the ripple voltage is lower than the maximum allowable value, then it can be considered that the preset circuit conditions are met. The first preset circuit condition and the second preset circuit condition can be set to be the same or different according to actual needs.

[0137] Specific example:

[0138] Assume that a power management module is being designed for an instrumentation and control card for a nuclear power plant reactor cooling system. During the initial latent path analysis, it was found that a capacitor in the power management module could overheat under certain conditions, leading to potential safety issues. To address this issue, the following measures were taken:

[0139] 1. Replace components: Replace the original capacitor with one with a higher temperature rating.

[0140] 2. Adjust the circuit layout: Rearrange other components on the circuit board to improve the overall heat distribution.

[0141] 3. Added protection measures: An over-temperature protection device was added to the circuit to prevent possible overheating problems in the future.

[0142] After completing these modifications, sneak path analysis was performed again. This time, it showed that all potential issues had been resolved and the operating temperature of the power management block was within a safe range. Therefore, this modified model could be determined as the target model.

[0143] Through such a process, the reliability and safety of instrumentation and control components can be significantly improved, ensuring that they can operate stably in actual applications and maintain their performance even under extreme or unexpected conditions.

[0144] It should be understood that in the design and development process of the instrumentation and control system, FMEA (refer to step 102 and related steps), derating design (refer to step 1031 and related steps), thermal simulation (refer to step 1032 and related steps) and latent path analysis (refer to step 1033 and related steps) are important steps to ensure the reliability and safety of the system. The execution order of these steps can be adjusted according to the specific needs and resource conditions of the project. FMEA can be performed first. Through FMEA, potential failure modes and their effects in the system can be identified, so as to determine the target components that need to be focused on. This helps to discover and solve possible problems at an early stage. For the target components identified in FMEA, derating design is performed to reduce their working stress and improve their reliability. Derating design can be performed in the device selection stage and the circuit design stage. After the derating design is completed, thermal simulation is performed on the target model to evaluate its thermal performance. If the thermal simulation results meet the preset conditions, you can proceed to the next step; if not, you need to repeat the derating design according to the analysis results until the conditions are met. Finally, the model that has been verified by derating design and thermal simulation is subjected to sneak path analysis to ensure that there are no unexpected current paths. If the results of the sneak path analysis meet the preset conditions, the model can be determined as the target model; if not, it needs to be analyzed and modified again.

[0145] In some cases, it may also be necessary to perform a derating design first, especially when the derating requirements have been considered in the device selection stage. This ensures that the selected components have sufficient reliability margins in subsequent design and analysis. After the derating design is completed, FMEA is performed. The advantage of this is that the derating design has reduced the working stress of the components and may reduce some potential failure modes, making FMEA more efficient and accurate. The next steps are the same as above, that is, thermal simulation is performed first to evaluate the thermal performance, and then sneak path analysis is performed to ensure that there are no unexpected current paths. In some projects, the thermal performance of the system may be focused on first, especially in high temperature or high power applications. In this case, thermal simulation can be performed first to evaluate the thermal distribution and heat dissipation of the system. The thermal simulation results can provide important information for FMEA and derating design. For example, if the temperature rise in a certain area is found to be too high, it may be necessary to derating the components in that area or take other heat dissipation measures. At the same time, special attention can be paid to the components in these high temperature areas in FMEA. Finally, sneak path analysis is performed on the model optimized by thermal simulation and derating design to ensure the reliability and safety of the system.

[0146] Based on the above steps, this application proposes the following optional solutions:

[0147] Option 1: Standard Sequential Execution

[0148] 1. Conduct FMEA:

[0149] Purpose: To identify potential failure modes in a system and their effects.

[0150] Output: Identify target components that require special attention.

[0151] 2. Perform derating design:

[0152] Purpose: To carry out derating design for target components identified in FMEA to reduce their working stress.

[0153] Output: Initial model after de-rating.

[0154] 3. Perform thermal simulation:

[0155] Purpose: To evaluate the thermal performance of an initial model after de-rating.

[0156] Output: Thermal simulation results.

[0157] 4. Conduct latent pathway analysis:

[0158] Purpose: To ensure that no unintended current paths exist.

[0159] Output: Sneak Path Analysis Results.

[0160] 5. Adjust the design based on the analysis results (if necessary):

[0161] If the thermal simulation or sneak path analysis results do not meet the preset conditions, repeat the corresponding steps according to the analysis results until the conditions are met.

[0162] Solution 2: Derating design first

[0163] 1. Perform derating design:

[0164] Purpose: Consider derating requirements at the device selection stage and select components with sufficient reliability margin.

[0165] Output: Initial model after de-rating.

[0166] 2. Conduct FMEA:

[0167] Purpose: To identify potential failure modes in a system and their effects.

[0168] Output: Identify target components that require special attention.

[0169] 3. Perform thermal simulation:

[0170] Purpose: To evaluate the thermal performance of an initial model after de-rating.

[0171] Output: Thermal simulation results.

[0172] 4. Conduct latent pathway analysis:

[0173] Purpose: To ensure that no unintended current paths exist.

[0174] Output: Sneak Path Analysis Results.

[0175] 5. Adjust the design based on the analysis results (if necessary):

[0176] If the thermal simulation or sneak path analysis results do not meet the preset conditions, repeat the corresponding steps according to the analysis results until the conditions are met.

[0177] Option 3: Perform thermal simulation first

[0178] 1. Perform thermal simulation:

[0179] Purpose: To evaluate the thermal distribution and heat dissipation effectiveness of a system, especially in high temperature or high power applications.

[0180] Output: Thermal simulation results.

[0181] 2. Conduct FMEA:

[0182] Purpose: To identify potential failure modes in a system and their effects.

[0183] Output: Identify target components that require special attention.

[0184] 3. Perform derating design:

[0185] Purpose: To carry out derating design for target components identified in FMEA to reduce their working stress.

[0186] Output: Initial model after de-rating.

[0187] 4. Conduct latent pathway analysis:

[0188] Purpose: To ensure that no unintended current paths exist.

[0189] Output: Sneak Path Analysis Results.

[0190] 5. Adjust the design based on the analysis results (if necessary):

[0191] If the thermal simulation or sneak path analysis results do not meet the preset conditions, repeat the corresponding steps according to the analysis results until the conditions are met.

[0192] These solutions are just examples that show the possibility of different execution orders. Each solution has its applicable scenarios and advantages, and is not limited to the above three examples in actual application. Which solution to choose depends on the specific needs of the project, resource conditions, and the experience of the design team. It is important to ensure that each step is fully considered and executed to maximize the reliability and safety of the system. In general, the execution order of these steps is not fixed, but can be adjusted according to the specific circumstances and needs of the project. It is important to ensure that each step is fully considered and executed to maximize the reliability and safety of the system.

[0193] Example 2

[0194] Corresponding to the aforementioned fault mitigation design method embodiment and technical effects of the instrumentation and control card component, the present disclosure also provides an embodiment of a fault mitigation design system for the instrumentation and control card component.

[0195] Figure 4 A schematic diagram of a module of a fault mitigation design system for an instrumentation and control card component provided by an exemplary embodiment of the present disclosure, the system comprising:

[0196] An acquisition module 21 is used to acquire an initial model of an instrumentation and control card component;

[0197] An analysis module 22, for performing a failure mode and effect analysis on the initial model to determine the card failure mode and target component in the initial model;

[0198] The design module 23 is used to perform fault mitigation design on the target component and use the initial model after the fault mitigation design as the target model. The fault mitigation design includes at least one of the following: derating design, thermal simulation and latent path analysis.

[0199] Optionally, the fault mitigation design includes a derating design; a design module specifically for:

[0200] Perform derating design for target components;

[0201] The initial model that has completed the derating design is used as the target model.

[0202] Optionally, a design module is specifically configured to:

[0203] Acquire a first thermal simulation result for a target component;

[0204] A derating design is performed on the target component according to the first thermal simulation result.

[0205] Optionally, the fault mitigation design includes thermal simulation; a design module specifically for:

[0206] Performing thermal simulation on the initial model that has completed the derating design to obtain a second thermal simulation result;

[0207] In response to the second thermal simulation result satisfying the first preset thermal simulation condition, the initial model that completes the derating design is used as the target model;

[0208] and / or,

[0209] In response to the second thermal simulation result not satisfying the second preset thermal simulation condition, the derating design is repeatedly performed according to the second thermal simulation result until the second thermal simulation result satisfies the second preset thermal simulation condition.

[0210] Optionally, the fault mitigation design includes sneak path analysis; a design module specifically for:

[0211] Conduct latent path analysis on target components;

[0212] The initial model that completed the latent pathway analysis was used as the target model.

[0213] Optionally, a design module is specifically configured to:

[0214] In response to the analysis result of the sneak path analysis satisfying the first preset circuit condition, the initial model that completes the sneak path analysis is used as the target model;

[0215] and / or,

[0216] In response to the analysis result of the sneak path analysis not satisfying the second preset circuit condition, the sneak path analysis is repeatedly performed according to the analysis result until the analysis result satisfies the second preset circuit condition.

[0217] As for the system embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The system embodiment described above is only illustrative, wherein the units described as separate components may or may not be physically separated, and the components as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the disclosed solution.

[0218] Example 3

[0219] Figure 5 This is a structural schematic diagram of an electronic device shown in an example embodiment of the present disclosure, the electronic device includes a memory, a processor, and a computer program stored in the memory and used to run on the processor, and when the processor executes the computer program, the fault mitigation design method for the instrumentation and control card component described in any of the above embodiments is implemented. Figure 5 The electronic device 90 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0220] like Figure 5 As shown, the electronic device 90 may be in the form of a general-purpose computing device, for example, it may be a server device. The components of the electronic device 90 may include, but are not limited to: at least one processor 91, at least one memory 92, and a bus 93 connecting different system components (including the memory 92 and the processor 91).

[0221] The bus 93 includes a data bus, an address bus, and a control bus.

[0222] The memory 92 may include a volatile memory, such as a random access memory (RAM) 921 and / or a cache memory 922 , and may further include a read only memory (ROM) 923 .

[0223] The memory 92 may also include a program tool 925 (or utility) having a set (at least one) of program modules 924, such program modules 924 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0224] The processor 91 executes various functional applications and data processing by running the computer program stored in the memory 92, such as the fault mitigation design method for the instrumentation and control card provided in any of the above embodiments.

[0225] The electronic device 90 may also communicate with one or more external devices 94 (e.g., keyboards, pointing devices, etc.). Such communication may be performed via an input / output (I / O) interface 95. Furthermore, the electronic device 90 may also communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) via a network adapter 96. As shown, the network adapter 96 communicates with other modules of the electronic device 90 via a bus 93. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 90, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID (disk array) systems, tape drives, and data backup storage systems, etc.

[0226] It should be noted that although several units / modules or sub-units / modules of the electronic device are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functions of one unit / module described above can be further divided into multiple units / modules to be embodied.

[0227] Example 4

[0228] The embodiments of the present disclosure further provide a computer-readable storage medium having a computer program stored thereon, and when the program is executed by a processor, the fault mitigation design method for an instrumentation and control card component provided in any of the above embodiments is implemented.

[0229] The readable storage medium may include but is not limited to: a portable disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical storage device, a magnetic storage device or any suitable combination of the above.

[0230] Example 5

[0231] The embodiment of the present disclosure further provides a computer program product, including a computer program, which, when executed by a processor, implements any of the above-mentioned fault mitigation design methods for instrumentation and control card components.

[0232] Among them, the program code for executing the computer program product of the present disclosure can be written in any combination of one or more programming languages, and the program code can be executed completely on the user device, partially on the user device, as an independent software package, partially on the user device and partially on a remote device, or completely on the remote device.

[0233] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.

Claims

1. A fault mitigation design method for an instrumentation control card, characterized in that: The fault mitigation design method comprises: Obtaining an initial model of the instrumentation and control card component; Performing a failure mode and effect analysis on the initial model to determine the card failure mode and target element in the initial model; A fault mitigation design is performed for the target component, and the initial model after the fault mitigation design is used as the target model.

2. The fault mitigation design method according to claim 1, characterized in that: The fault mitigation design includes a derating design; the fault mitigation design is performed on the target component, and the initial model after the fault mitigation design is used as the target model, including: performing the derating design for the target component; The initial model that completes the derating design is used as the target model.

3. The fault mitigation design method according to claim 2, characterized in that: The performing the derating design on the target component includes: Acquire a first thermal simulation result for the target element; The derating design is performed on the target component according to the first thermal simulation result.

4. The fault mitigation design method according to claim 2, characterized in that: The fault mitigation design includes thermal simulation; The step of taking the initial model for completing the derating design as the target model comprises: Performing the thermal simulation on the initial model that has completed the derating design to obtain a second thermal simulation result; In response to the second thermal simulation result satisfying the first preset thermal simulation condition, taking the initial model that completes the derating design as the target model; and / or, In response to the second thermal simulation result not satisfying the second preset thermal simulation condition, the derating design is repeated according to the second thermal simulation result until the second thermal simulation result satisfies the second preset thermal simulation condition.

5. The fault mitigation design method according to claim 1, characterized in that: The fault mitigation design includes sneak path analysis; The performing fault mitigation design on the target component and using the initial model after the fault mitigation design as the target model includes: Performing the latent path analysis on the instrumentation and control card containing the target element; The initial model that completes the latent pathway analysis is used as the target model.

6. The fault mitigation design method according to claim 5, characterized in that: The method of using the initial model that completes the latent path analysis as the target model includes: In response to the analysis result of the sneak path analysis satisfying the first preset circuit condition, taking the initial model that completes the sneak path analysis as the target model; and / or, In response to an analysis result of the sneak path analysis not satisfying a second preset circuit condition, the sneak path analysis is repeatedly performed according to the analysis result until the analysis result satisfies the second preset circuit condition.

7. A fault mitigation design system for instrumentation and control components, characterized in that: The fault mitigation design system comprises: An acquisition module, used to acquire an initial model of the instrumentation and control card component; An analysis module, configured to perform a failure mode and effect analysis on the initial model to determine a target element in the initial model; The design module is used to perform fault mitigation design on the target component and use the initial model after the fault mitigation design as the target model, wherein the fault mitigation design includes at least one of the following: derating design, thermal simulation and sneak path analysis.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and used to run on the processor, characterized in that: When the processor executes the computer program, the fault mitigation design method for the instrumentation and control card component described in any one of claims 1 to 6 is implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the fault mitigation design method for an instrumentation and control card component described in any one of claims 1 to 6 is implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the fault mitigation design method for an instrumentation and control card component as described in any one of claims 1 to 6 is implemented.

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