HR neuron circuit bifurcation diagram implementation method based on maximum value detection FPGA technology

Abstract

According to the HR neuron circuit bifurcation diagram implementation method based on the maximum detection FPGA technology, the maximum detection algorithm and the Lagrange interpolation technology are fused, and the current maximum iteration value of a state variable can be accurately captured within the millisecond magnitude, namely, core data for drawing the bifurcation diagram. On an FPGA development platform carrying a 50MHz crystal oscillator, a complex function of an HR neuron system can be generated within microsecond-level time, the running time is remarkably shortened, and the system operation rate is increased. Through efficient maximum value detection, the vacancy of the FPGA for realizing the bifurcation diagram of the HR neuron circuit is made up, the time for constructing a complex function on the FPGA is greatly shortened, the implementation efficiency of the HR neuron circuit on an FPGA platform is greatly improved, and bifurcation diagram construction is accelerated. The bifurcation diagram implementation method has good universality, can be expanded to other neuron circuits, and shows wide application potential and important research value in information encryption and nonlinear neuron research.

Description

Technical Field

[0001] The invention belongs to the field of nonlinear dynamics, and in particular to a method for realizing a bifurcation diagram of a HR neuron circuit based on a maximum value detection FPGA technology. Background Art

[0002] Compared with the famous Moore's Law, the advent of FPGA (Field Programmable Gate Array) lags behind by about 20 years. Since its birth, the development speed of FPGA has exceeded everyone's expectations and has now become the forefront of global digital integrated circuit technology.

[0003] With its excellent data processing capabilities, FPGA plays an important role in the national strategic level in many key fields such as communications, medical health, aerospace, and industrial automation control. In addition, in daily application scenarios such as 5G communication networks, video content processing, data center operations, and smart home life, FPGA has also demonstrated its wide application potential. Similar to the neural network system that has attracted much attention in the field of artificial intelligence in recent years, FPGA provides strong technical support for more accurate simulation of the basic patterns of brain activity, and helps to deeply explore the potential mechanism of abnormal neuronal discharge, thereby providing assistance for the diagnosis of brain diseases. Therefore, from a long-term perspective, exploring the use of circuit technology to simulate the nervous system to capture the discharge sequence and predict the discharge behavior of neurons has become a potential technical path. On this basis, the circuit bifurcation diagram technology can be further used to intuitively depict the dynamic trajectory of the system state as the parameters change, and this complex process can be clearly displayed in physical form. In the design of the circuit system, the stable operating range of the circuit can be accurately determined by in-depth analysis of the bifurcation diagram, which effectively prevents the system from falling into an unstable or chaotic state. This research direction has extremely important scientific value and practical significance.

[0004] By constructing a circuit bifurcation diagram on the FPGA platform, the dynamic evolution process of the system from an ordered state to a chaotic state can be intuitively depicted. This process provides strong support for researchers to deeply understand the essential characteristics of chaotic phenomena and their generation mechanism, and helps to solve practical engineering problems. Specifically, in the study of mechanical vibration systems, harmful bifurcation phenomena can be effectively avoided or the system can be induced to produce the required bifurcation characteristics by adjusting the system parameters; in the field of physics, bifurcation diagrams are widely used as an important analysis tool to explore the motion laws of complex physical systems such as fluid mechanics and celestial mechanics; and in the field of biology, bifurcation diagrams are widely used to reveal the dynamic behavior characteristics and evolution laws of biological systems such as ecosystems and neural networks. In addition, the HR (Hindmarsh-Rose) neuron model has attracted much attention because it can simulate unique explosive oscillation phenomena, that is, it can flexibly switch between static and spike states. The model has been widely used in the field of neuron dynamics research with its concise mathematical expression. It is regarded as an important tool for building neural network models, and provides strong technical support for scientific research in the field of medical health and the continuous development of artificial intelligence technology. However, the method of realizing the bifurcation diagram of HR neuron circuits through FPGA technology has not been mentioned yet.

[0005] The technical differences between this application and the prior art are as follows: Technical comparison with patent CN116720554B "A method for realizing a multi-segment linear fitting neuron circuit based on FPGA technology" Patent CN116720554B uses a multi-segment linear fitting method based on FPGA technology to achieve segmented approximation calculation of hyperbolic tangent function and sine function, and effectively solves the neuron model differential equation by combining the second-order Runge-Kutta method. By constructing a linear fitting parameter storage mechanism and using floating-point converters and RAM addressing technology, patent CN116720554B optimizes the resource consumption and efficiency of complex function calculations, thereby supporting the efficient implementation of the improved FitzHugh-Nagumo model on FPGA, focusing on simulating the electrical activity behavior of neurons and external stimulus responses.

[0006] The present invention proposes an FPGA implementation method based on maximum value detection for drawing bifurcation diagrams of HR neuron models. This application combines Lagrange interpolation technology and state machine control, and achieves accurate capture and rapid drawing of the dynamic characteristics of HR neurons by performing high-precision interpolation fitting of sine functions and constructing a maximum value detection module. Specifically, this application adopts a multi-segment linear storage space optimization strategy and a FIFO storage mechanism, and cooperates with three comparators to realize the maximum value detection of the discharge sequence, providing core data support for drawing bifurcation diagrams.

[0007] Unlike patent CN116720554B, which focuses on the calculation of complex function values ​​and its application in neuron models, the present invention aims at drawing bifurcation diagrams. Through innovative maximum value detection algorithms and accurate dynamic capture of HR models, the efficiency and accuracy of bifurcation diagram drawing are significantly improved. This invention can not only intuitively display the nonlinear dynamic characteristics of the system as the parameters change, but also provide an efficient tool for nonlinear neuron research.

[0008] In response to the dual challenges of high precision and high efficiency faced by the prior art in drawing bifurcation diagrams for HR neuron circuits containing sine functions, the present invention proposes an innovative solution: FPGA technology based on maximum value detection to realize the bifurcation diagram of HR neuron circuits. The present application cleverly combines the maximum value detection algorithm with the Lagrangian interpolation technology, and can obtain the linear fit of the sine function in the mathematical model of HR neurons with high precision. By being equipped with 3 comparators, the present application can accurately capture the maximum value of the current discharge sequence, thereby clearly presenting the bifurcation diagram of the HR neuron on the oscilloscope. Summary of the invention

[0009] In order to solve the above technical problems, the present invention proposes a method for realizing the bifurcation diagram of HR neuron circuit based on maximum detection FPGA technology, sine function is simplified into linear function by using Lagrange interpolation method, and these linear functions are encoded into addressable linear storage space on FPGA by combining state machine and RAMIP core technology, thereby improving the efficiency of high-precision processing of sine function on FPGA.

[0010] To achieve the above object, the technical solution adopted by the present invention is: The method for realizing the bifurcation diagram of HR neuron circuit based on maximum value detection FPGA technology includes the following steps: S1 uses Lagrange interpolation to simplify the sine function into linear functions, and by combining state machines and RAM IP core technology, encodes these linear functions into addressable linear storage modules on the FPGA; S2 designs the HR neuron iterative module based on the second-order Runge-Kutta, which requires calling the function module obtained previously; S3 uses three comparators to detect the maximum value changes in the discharge sequence generated by the HR neuron iteration module in real time, thereby generating a bifurcation diagram of the HR neuron, where the maximum value data is transmitted to the oscilloscope in real time through a floating-point converter and a DA converter for capture.

[0011] As a further improvement of the present invention, the specific process of step S1 is as follows: The Lagrange interpolation method simplifies the sine function into a linear function. The processing steps are as follows: Step 1), divide the hyperbolic tangent function interval into multiple intervals to be approximated according to the engineering accuracy requirements; According to the accuracy requirement of HR neuron iteration, the sine function is The interval within the cycle is divided into multiple continuous fitting intervals. The number of intervals varies according to the requirements of iteration accuracy and is divided into integer multiples of 10. Step 2), using the Lagrange interpolation method, respectively obtain the polynomial fitting coefficients of each interval segment. When the polynomial is a linear function, simplify the complex approximation formula into coefficients containing only the slope term and the constant term through Visual studio C++; Step 3), when the polynomial is a linear function, use Visual studio C++ or MATLAB to write the code to solve Cramer's rule to obtain the coefficients of the slope term and the constant term. The coefficients are grouped in pairs in the form of IEEE754 single precision to form a single 64-bit data and saved in the .coe file for the configuration of the RAM IP core; Step 4), when the polynomial is a linear function, it is only necessary to amplify the independent variable of the sine function through a multiplier to the same multiple as the segmented interval, and then transmit the obtained data to the address, so as to obtain a linear space for storing the coding slope term and the constant term. The storage space occupancy increases with the increase of the segmented interval, and the computing resources including the multiplier, adder and floating-point converter do not change accordingly. When the polynomial is a quadratic function or higher, the computing resources change accordingly.

[0012] As a further improvement of the present invention, the method for processing the sine function independent variable exceeding the fitting period in step 4) is as follows: To exceed The independent variable of the interval performs the remainder, that is, the modulo operation. When the independent variable is When it is not 0, Equivalent to .

[0013] As a further improvement of the present invention, the model of the HR neuron in step S2 is: ; in, is the state variable, Represents the external input current, is the electrical coupling strength as a control parameter, represents the amplitude of the external stimulation current, represents the frequency of the external stimulation current, and all system parameters All are positive numbers.

[0014] As a further improvement of the present invention, the HR neuron iteration based on the second-order Runge-Kutta in step S2 obtains the numerical iteration expression of the HR neuron system as follows: ; In the above digital iteration formula, The current state variables, Represents the external input current, is the electrical coupling strength as a control parameter, represents the amplitude of the external stimulation current, represents the frequency of the external stimulation current, and all system parameters are all positive numbers, Iteration value of the state variable at the next moment is the initial slope of the state variable, The iteration step is 0.001, and the initial iteration time is t Take 0, any time t Take the cumulative value of the previous time plus the step length.

[0015] The advantage of the present invention is that it innovatively combines the maximum detection algorithm with the Lagrangian interpolation technology, providing an efficient and accurate method for realizing the bifurcation diagram of the HR neuron circuit. Specifically, the method can accurately capture the current maximum iteration value of the state variable within milliseconds, which is the core data for drawing the bifurcation diagram, thereby significantly improving the accuracy and speed of data capture. On an FPGA development platform equipped with a 50MHz crystal oscillator, it can quickly generate complex functions in the HR neuron system within microseconds. This advantage enables the present invention to complete the task at a faster speed when constructing the bifurcation diagram of the HR neuron circuit. This advantage makes the present invention have broad application potential and important research value in the fields of information encryption and nonlinear neuron research. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a schematic diagram of Lagrange interpolation; Figure 2 It is a sine function fitting module; Figure 3 This is the overall module diagram of the Verilog algorithm; Figure 4 This is the schematic diagram of module_K1_K2; Figure 5 This is the schematic diagram of module_XB_Re; Figure 6 To design a flow chart; Figure 7 is the bifurcation diagram module; Figure 8 This is the overall connection schematic. DETAILED DESCRIPTION

[0017] The present invention relates to a method for realizing a bifurcation diagram of an HR neuron circuit using FPGA technology based on maximum value detection. The method combines the maximum value detection algorithm with the Lagrange interpolation technology, and can accurately capture the current maximum iteration value of a state variable within milliseconds, that is, the core data for drawing a bifurcation diagram. A programming method for a bifurcation diagram of an HR neuron circuit in Verilog language is provided, and an oscilloscope can be used to capture the bifurcation diagram.

[0018] The specific steps of the algorithm are: First, the processing of the sine function, where the Lagrange interpolation diagram is as follows Figure 1 As shown: Step 1), the sine function is The internal data is divided into 6284 continuous interpolation points, i.e. each interval point is 0.001. Then Lagrange is used to perform polynomial interpolation fitting at each interval point; For example, the schematic diagram of Lagrange quadratic interpolation of sine function fitting in a local interval is as follows Figure 1 As shown, the interpolation formula is: ; In order to facilitate promotion and use, the quadratic interpolation is changed to the linear interpolation, then As a linear function, it can be expressed as in the form of k as well as The value of is solved by Visual Studio C++ program and saved as IEEE754 single-precision data type. When encoding the data into a .coe file, it needs to be reconstructed into a single row of 64-bit data, with the high bit being k The value of The value of .

[0019] Step 2), input parameters The storage space storing IEEE754 floating-point numbers can only be decoded after the two steps of amplification and floating-point conversion. The order of these two steps can be adjusted and does not affect the decoding address. Note that the sine function has periodic properties and odd function properties, so when the input parameter Greater than When decoding, you need to make the input parameters Perform the remainder operation to make it fall into This can greatly reduce the use of RAM storage space, especially when the parameter is too large. The specific sine function fitting module is as follows Figure 2 As shown, the digital resources used by this module are fixed to one RAM IP core, one multiplier, one adder, and one floating-point converter.

[0020] According to the above steps 1), 2), 3), and 4), the neuron model of HR is selected as: ;

[0021] in, is the state variable, Represents the external input current, is the electrical coupling strength as a control parameter, represents the amplitude of the external stimulation current, represents the frequency of the external stimulation current, and all system parameters All are positive numbers.

[0022] When observing and The specific values ​​when drawing the bifurcation diagram are as follows: , initial value , , , , , , ; According to the differential equation of the HR neural system mentioned above, the numerical iteration formula is selected as the second-order Runge-Kutta, and the numerical iteration expression of the HR neural system is obtained as follows: ; In the above digital iteration formula, The current state variables, Represents the external input current, is the electrical coupling strength as a control parameter, represents the amplitude of the external stimulation current, represents the frequency of the external stimulation current, and all system parameters are all positive numbers, Iteration value of the state variable at the next moment is the initial slope of the state variable, The iteration step is 0.001, and the initial iteration time is t Take 0, any time t Take the cumulative value of the previous time plus the step length.

[0023] According to the above iterative formula, the FPGA circuit design obtains the HR neuron circuit iteration, thereby generating the HR neuron discharge sequence, and then stores the three consecutive values ​​of the discharge sequence at any time through the FIFO, and then uses three comparators to compare, obtains its maximum value and outputs it through the DA converter. Note that because the HR neuron system will have a short-term unstable state when changing parameters, it is necessary to discard the previous multiple iteration values, here 10,000 times.

[0024] According to all the above steps, the Verilog iterative algorithm program based on state machine design was carefully constructed on the Xilinx ISE integrated development environment platform. After the design process is completed, it is necessary to write a testbench test file and work with Xilinx ISE and Modelsim simulation tools to implement joint simulation verification. The data produced by the simulation link is then converted into decimal values ​​on the MATLAB platform, and then the effectiveness and accuracy of the algorithm are verified through graphical analysis. In addition, the overall program framework of the Verilog algorithm is as follows Figure 3 shown.

[0025] The main program connects and controls the subprogram module_K1_K2, module_XB_Re, bifurcation module and data conversion module. First, according to the idea of ​​the iterative algorithm, the control module_K1_K2 calculates the initial slopes of the state variables K11, K21, K31, and K41, and then sets the flag position to 1. Secondly, the first function of the control module_XB_Re calculates the terminal slopes K12, K22, K32, and K42 of the state variables, and calls back the second function of the module_XB_Re again to generate a new iteration value, and then clears the flag. Next, the iteration flag is used to determine whether the number of iterations is greater than 3, and the bifurcation module is controlled to detect the maximum value data in the current iteration. Finally, the generated maximum value data is output to the oscilloscope through the data conversion module. The schematic diagram of module_K1_K2 is shown below. Figure 4 As shown, the schematic diagram of module_XB_Re is as follows Figure 5 As shown, the flow chart of module_XB_Re is as follows Figure 6 , the bifurcation diagram module is as follows Figure 7 As shown: When MATLAB successfully converts the Modelsim simulation data into decimal format, and the converted data is completely consistent with the data on the Visual Studio C++ platform, the bit files generated by the comprehensive compilation are burned into the FPGA through the JTAG interface. The block diagram of the physical connection of the object is as follows Figure 8 shown.

[0026] In summary, the present invention implements the bifurcation diagram of the HR neuron circuit based on the FPGA technology of maximum value detection. This method combines the maximum value detection algorithm with the Lagrangian interpolation technology, and can accurately capture the core data for drawing the bifurcation diagram within milliseconds. Thereby filling the gap in the bifurcation diagram of the HR neuron circuit. The above is only one of the embodiments of the present invention. For ordinary technicians in the relevant technical field, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the scope of protection of the present invention.

[0027] The above description is only a preferred embodiment of the present invention and does not constitute any other form of limitation to the present invention. Any modification or equivalent change made based on the technical essence of the present invention still falls within the scope of protection required by the present invention.

Claims

1. A method for realizing a bifurcation diagram of a HR neuron circuit based on maximum value detection FPGA technology, characterized in that: The following steps are involved: S1 uses Lagrange interpolation to simplify the sine function into linear functions, and by combining state machines and RAM IP core technology, encodes these linear functions into addressable linear storage modules on the FPGA; S2 designs the HR neuron iterative module based on the second-order Runge-Kutta, which requires calling the function module obtained previously; S3 uses three comparators to detect the maximum value changes in the discharge sequence generated by the HR neuron iteration module in real time, thereby generating a bifurcation diagram of the HR neuron, where the maximum value data is transmitted to the oscilloscope in real time through a floating-point converter and a DA converter for capture.

2. The method for realizing the bifurcation diagram of HR neuron circuit based on maximum value detection FPGA technology according to claim 1 is characterized in that: The specific process of step S1 is as follows: The Lagrange interpolation method simplifies the sine function into a linear function. The processing steps are as follows: Step 1), divide the hyperbolic tangent function interval into multiple intervals to be approximated according to the engineering accuracy requirements; According to the accuracy requirement of HR neuron iteration, the sine function is The interval within the cycle is divided into multiple continuous fitting intervals. The number of intervals varies according to the requirements of iteration accuracy and is divided into integer multiples of 10. Step 2), using the Lagrange interpolation method, respectively obtain the polynomial fitting coefficients of each interval segment. When the polynomial is a linear function, simplify the complex approximation formula into coefficients containing only the slope term and the constant term through Visual studio C++; Step 3), when the polynomial is a linear function, use Visual studio C++ or MATLAB to write the code to solve Cramer's rule to obtain the coefficients of the slope term and the constant term. The coefficients are grouped in pairs in the form of IEEE754 single precision to form a single 64-bit data and saved in the .coe file for the configuration of the RAM IP core; Step 4), when the polynomial is a linear function, it is only necessary to amplify the independent variable of the sine function through a multiplier to the same multiple as the segmented interval, and then transmit the obtained data to the address, so as to obtain a linear space for storing the coding slope term and the constant term. The storage space occupancy increases with the increase of the segmented interval, and the computing resources including the multiplier, adder and floating-point converter do not change accordingly. When the polynomial is a quadratic function or higher, the computing resources change accordingly.

3. The method for realizing the bifurcation diagram of HR neuron circuit based on maximum value detection FPGA technology according to claim 2 is characterized in that: The method for processing the sine function independent variable exceeding the fitting period in step 4) is as follows: To exceed The independent variable of the interval performs the remainder, that is, the modulo operation. When the independent variable is When it is not 0, Equivalent to .

4. The method for realizing the bifurcation diagram of HR neuron circuit based on maximum value detection FPGA technology according to claim 1, characterized in that: The model of the HR neuron in step S2 is: ； in, is the state variable, Represents the external input current, is the electrical coupling strength as a control parameter, represents the amplitude of the external stimulation current, represents the frequency of the external stimulation current, and all system parameters All are positive numbers.

5. The method for realizing the bifurcation diagram of HR neuron circuit based on maximum value detection FPGA technology according to claim 1, characterized in that: In step S2, based on the second-order Runge-Kutta HR neuron iteration, the numerical iteration expression of the HR neuron system is obtained as follows: ； In the above digital iteration formula, The current state variables, Represents the external input current, is the electrical coupling strength as a control parameter, represents the amplitude of the external stimulation current, represents the frequency of the external stimulation current, and all system parameters are all positive numbers, Iteration value of the state variable at the next moment is the initial slope of the state variable, The iteration step size is 0.001, and the initial iteration time is t Take 0, any time t Take the cumulative value of the previous time plus the step length.

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