Clock tree path information determination method and device, computer equipment and medium

Abstract

The embodiment of the invention is suitable for the technical field of electronics, and provides a clock tree path information determination method and device, computer equipment and a medium, and the method comprises the steps: obtaining the position information of each standard time sequence unit in a clock tree; performing clustering analysis on the position information of each standard time sequence unit to obtain position coordinates of a plurality of target first-stage bifurcation points of a clock source in the clock tree; based on the position coordinates of the target first-level bifurcation points and a set time sequence standard, target mounting information of each target first-level bifurcation point is determined, and the target mounting information comprises information of the standard time sequence unit connected with each target first-level bifurcation point; and taking the position coordinate information of each target first-level bifurcation point and the target mounting information of each target first-level bifurcation point as path information of the clock tree. Through the method, the clock tree in the circuit can meet the time sequence requirement, and the circuit performance is improved.

Description

Technical Field

[0001] The present application belongs to the field of electronic technology, and in particular, relates to a method, device, computer equipment and medium for determining clock tree path information. Background Art

[0002] In digital integrated circuit design, the clock signal is the basis of data transmission. It plays a decisive role in the function, performance and stability of the synchronous digital system, so the characteristics of the clock signal and its distribution network are crucial.

[0003] Clock Tree Synthesis (CTS) is a key step to ensure that clock signals can be reliably and efficiently delivered to each trigger. Traditional clock tree synthesis methods mainly rely on regular structures, focusing on the balance and simple geometric distribution of clock paths, while ignoring the diverse timing requirements in complex circuits, resulting in large timing errors in the clock tree in complex circuits, thereby reducing the performance of integrated circuits. Summary of the invention

[0004] In view of this, the embodiments of the present application provide a method, apparatus, computer equipment and medium for determining clock tree path information, which can enable the clock tree in the circuit to meet the timing requirements and improve the circuit performance.

[0005] A first aspect of an embodiment of the present application provides a method for determining clock tree path information, including:

[0006] Get the location information of each standard timing unit in the clock tree;

[0007] Performing cluster analysis on the position information of each of the standard sequential units to obtain the position coordinates of multiple target first-level bifurcation points of the clock source in the clock tree;

[0008] Based on the position coordinates of each of the target first-level bifurcation points and the set timing standard, determine the target mounting information of each of the target first-level bifurcation points, the target mounting information including the information of the standard timing unit connected to each of the target first-level bifurcation points;

[0009] The position coordinate information of each of the target first-level branching points and the target mounting information of each of the target first-level branching points are used as the path information of the clock tree.

[0010] A second aspect of an embodiment of the present application provides a device for determining clock tree path information, including:

[0011] An acquisition module, used to obtain the position information of each standard timing unit in the clock tree;

[0012] A clustering module, used for performing cluster analysis on the position information of each of the standard timing units to obtain the position coordinates of multiple target first-level bifurcation points of the clock source in the clock tree;

[0013] An analysis module, configured to determine target mounting information of each of the target first-level bifurcation points based on the position coordinates of each of the target first-level bifurcation points and the set timing standard, wherein the target mounting information includes information of the standard timing unit connected to each of the target first-level bifurcation points;

[0014] The determination module is used to use the position coordinate information of each of the target first-level bifurcation points and the target mounting information of each of the target first-level bifurcation points as the path information of the clock tree.

[0015] A third aspect of an embodiment of the present application provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method described in the first aspect when executing the computer program.

[0016] A fourth aspect of an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method described in the first aspect above is implemented.

[0017] A fifth aspect of the embodiments of the present application provides a computer program product. When the computer program product is run on a computer device, the computer device executes the method described in the first aspect.

[0018] Compared with the prior art, the embodiments of the present application have the following advantages:

[0019] The method in the embodiment of the present application can be used to determine the path information in the clock tree. The clock tree may include multiple standard timing units, each of which may have location information. The computer device can perform cluster analysis on the location information of each standard timing unit to obtain the location coordinates of multiple target first-level bifurcation points of the clock source in the clock tree; then, based on the location coordinates of each of the target first-level bifurcation points and the set timing standard, determine the standard timing unit mounted on each of the target first-level bifurcation points, thereby obtaining the path of the clock tree that meets the timing standard. In the embodiment of the present application, the first-level bifurcation point of the clock source in the clock tree can be accurately located by a clustering algorithm, so that the clock signal is more evenly distributed; based on the set timing standard, determine the standard timing unit mounted on each first-level bifurcation point, so that the path in the clock tree can meet the timing requirements. Based on the method in the embodiment of the present application, the path information of the clock tree is determined, and the chip circuit can be optimized, thereby improving the chip performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art.

[0021] Figure 1 is a schematic diagram of a clock tree provided in an embodiment of the present application;

[0022] Figure 2 It is a schematic diagram of the steps of a method for determining clock tree path information provided by an embodiment of the present application;

[0023] Figure 3 It is a schematic diagram of a process for determining a target first-level bifurcation point provided by an embodiment of the present application;

[0024] Figure 4 This is a schematic diagram of a process for determining target mounting information provided by an embodiment of the present application;

[0025] Figure 5 It is a schematic diagram of the steps of another method for determining clock tree path information provided by an embodiment of the present application;

[0026] Figure 6 It is a schematic diagram of a device for determining clock tree path information provided by an embodiment of the present application;

[0027] Figure 7 It is a schematic diagram of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] In the following description, specific details such as specific system structures, technologies, etc. are proposed for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from hindering the description of the present application.

[0029] When designing an integrated circuit, it is necessary to design a clock tree in the integrated circuit to ensure the performance of the integrated circuit. For example, when designing a chip, it is necessary to design a clock tree.

[0030] During the clock tree design process, the signal transmission path affects the accuracy of signal transmission and also affects the winding length in the circuit. Therefore, during the clock tree design process, it is necessary to determine the appropriate clock path to optimize the performance of the clock tree.

[0031] In order to facilitate the introduction of the method provided in the embodiments of the present application, some terms in the embodiments of the present application are first introduced. Figure 1 It is a schematic diagram of a clock tree provided in an embodiment of the present application. Figure 1 The clock source point in is the source of the clock; the clock TAP point is the first-level bifurcation point of the clock source; the clock tree is the path for transmitting clock signals; the clock sink point is a general term for timing logic, and the clock sink point can be a standard timing unit. In the embodiment of the present application, determining the path information of the clock is equivalent to determining the position of the TAP point and the sink point mounted on each TAP point. In this embodiment, the TAP point is described using the first-level bifurcation point, and the sink point is described using the standard timing unit. The determination of the path information of the clock tree in the embodiment of the present application is to determine the position of the first-level bifurcation point and to determine the standard timing unit mounted on each first-level bifurcation point.

[0032] Existing clock tree synthesis methods, such as the H-Tree method and the X-Tree method, mainly focus on the balance of the clock path to ensure that the time difference between the clock signal reaching each trigger is minimized. However, in the existing clock tree synthesis methods, the location of the first-level bifurcation point of the clock tree is completely dependent on the user's manual specification of the location. The positioning of the first-level bifurcation point mainly relies on experience or simple geometric methods, which is difficult to accurately locate in complex and large-scale circuits, resulting in uneven distribution of clock signals. The mounting position of the standard timing unit only considers the physical distance between the first-level bifurcation point and the standard timing unit, while ignoring the diverse timing requirements in complex circuits. In the process of clock tree generation, timing analysis and optimization are usually completed manually, which makes it difficult to efficiently and accurately meet the timing requirements. The establishment of the clock tree in the existing methods lacks a systematic and comprehensive optimization solution.

[0033] With the advancement of electronic technology and the expansion of circuit scale, the design of clock trees is becoming more and more important, but the research on the precise positioning of the first-level bifurcation points and the optimization of clock trees is still limited. Clock tree design and optimization rely more on experience and manual adjustments, and lack efficient automated tools.

[0034] Based on this, an embodiment of the present application provides a method for determining path information for optimizing a clock tree, which is used to optimize the clock tree during the clock tree design process.

[0035] The technical solution of the present application is described below through specific embodiments.

[0036] Reference Figure 2 , shows a schematic flow chart of the steps of a method for determining clock tree path information provided by an embodiment of the present application, which may specifically include the following steps:

[0037] S201, obtaining position information of each standard sequential unit in a clock tree.

[0038] The execution subject of this embodiment may be a computer device, which may be an electronic device such as a desktop computer, a notebook, a PDA, and a server. This embodiment does not limit the specific type of the computer device. The method of this embodiment may be applied to the design of an integrated circuit, thereby optimizing the structure of the integrated circuit. For example, this embodiment may be executed in chip design, thereby optimizing the performance of the clock tree in the chip.

[0039] The above-mentioned standard sequential unit can be used to characterize a sequential logic circuit in an integrated circuit, and can be a trigger, a timer or a register, etc.

[0040] The method in this embodiment can be performed in the design of an integrated circuit. In the design process of the integrated circuit, the position information of multiple standard timing units in the clock tree can be determined.

[0041] S202 , performing cluster analysis on the position information of each of the standard sequential units to obtain the position coordinates of multiple target first-level bifurcation points of the clock source in the clock tree.

[0042] The method in this embodiment can more accurately determine the position of the first-level bifurcation point in the clock tree when optimizing the integrated circuit, thereby improving the performance of the integrated circuit. Therefore, in this embodiment, it is necessary to determine the position coordinates of the first-level bifurcation point.

[0043] In this embodiment, the position coordinates of the first-level bifurcation points can be determined based on cluster analysis. Figure 3 is a schematic diagram of a process for determining a target first-level bifurcation point provided by an embodiment of the present application. Figure 3 , determining the target first-level bifurcation point may include the following steps:

[0044] S301, based on the set multiple values, cluster analysis is performed on the position information of each of the standard timing units by using a k-means clustering algorithm to obtain multiple clustering results, wherein the clustering results include the position coordinates of the first-level bifurcation points corresponding to the values.

[0045] The k-means clustering algorithm can be used to divide a data set into k result classes, and the data in each result class can have similar data features. The above multiple values ​​can be multiple k values ​​of the k-means clustering algorithm. Multiple k values ​​can be pre-set. For example, the value range of the k value is 2-6, and the corresponding multiple values ​​are 2, 3, 4, 5 and 6.

[0046] When a computer device performs cluster analysis on the position information of each standard timing unit through a k-means clustering algorithm, multiple result classes can be obtained, each of which can include one or more standard timing units; the computer device can use the cluster center of each result class as the position coordinates of each first-level bifurcation point.

[0047] In this embodiment, based on each k value, the location information of multiple standard timing units can be clustered and analyzed respectively, so as to obtain corresponding multiple clustering results. After using the k value to perform cluster analysis on the location information of multiple standard timing units, k cluster centers can be obtained, and the k cluster centers are the corresponding k first-level bifurcation point positions. Based on each k value, the computer device can use the k-means clustering algorithm to perform cluster analysis on the location information of multiple standard timing units, so as to obtain clustering results, and the clustering results corresponding to each numerical value can include a first-level bifurcation point position set. Accordingly, multiple first-level bifurcation point position sets can be obtained in the clustering results corresponding to multiple numerical values, and each first-level bifurcation point position set can include corresponding k first-level bifurcation point position coordinates.

[0048] Exemplarily, there are n k values: n1, n2, ···, nk. Based on the n1, n2, ···, nk values, respectively, the k-means clustering algorithm can be used to perform cluster analysis on the position information of multiple standard timing units, thereby obtaining n first-level bifurcation point position sets, and the n first-level bifurcation point position sets include n1, n2, ···, nk first-level bifurcation point position coordinates, respectively.

[0049] S302, selecting a target value from the multiple values ​​according to the multiple clustering results, the position coordinates of the first-level bifurcation point corresponding to the target value being the position coordinates of the target first-level bifurcation point.

[0050] The clustering results corresponding to the multiple numerical values ​​may correspond to multiple first-level bifurcation point position sets. The computer device needs to determine the target first-level bifurcation point position set from the multiple first-level bifurcation point position sets, thereby obtaining the position coordinates of the target first-level bifurcation point of the clock tree.

[0051] Determining a target first-level bifurcation point position set from a plurality of first-level bifurcation point position sets is equivalent to determining a target value from the plurality of values ​​mentioned above.

[0052] In integrated circuit design, it is generally hoped that each standard timing unit is evenly distributed. Therefore, the target value can be determined based on the distribution difference of the standard timing units in the clustering results. When the k-means clustering algorithm performs cluster analysis on the location information of multiple standard timing units, the location information of multiple standard timing units can be finally divided into multiple result classes. The cluster center of each result class can be used as the location coordinate of a first-level bifurcation point, and each result class can include one or more table-sequential timing units. The above distribution difference can be the difference in the number distribution of standard timing units in each result class in the clustering results.

[0053] In a possible implementation, the computer device may calculate the distribution difference values ​​of the standard time sequence units in the clustering results according to the number of the standard time sequence units in each result class, and then use the value corresponding to the minimum distribution difference value as the target value.

[0054] The distribution difference value can be represented by a variance value. Exemplarily, for n clustering results corresponding to n k values, the computer device can respectively determine the k quantity values ​​of the corresponding standard time series units in the k result classes in each clustering result, calculate the variance value of the k quantity values, and use the variance value as the distribution difference value corresponding to the k value. For n k values, n variance values ​​can be obtained, and then the minimum value among the n variance values ​​is determined, and the k value corresponding to the minimum value is used as the target value.

[0055] The distribution difference value can also be represented by a square difference. For example, for n clustering results corresponding to n k values, the computer device can respectively determine the k quantity values ​​of the corresponding standard time series units in the k result classes in each clustering result, calculate the square difference value of the k quantity values, and use the variance value as the distribution difference value corresponding to the k value. For n k values, n square differences can be obtained, and then the minimum value among the n square differences is determined, and the k value corresponding to the minimum value is used as the target value.

[0056] After the target value is determined, a first-level bifurcation point position set corresponding to the target value may be obtained, and each position coordinate in the first-level bifurcation point position set is the position coordinate of each target first-level bifurcation point.

[0057] S203, based on the position coordinates of each of the target first-level bifurcation points and the set timing standard, determine the target mounting information of each of the target first-level bifurcation points, the target mounting information including the information of the standard timing unit connected to each of the target first-level bifurcation points.

[0058] The above timing standards may include constraints on the clock paths in the clock tree. The clock tree needs to meet the set timing standards, so timing analysis can be performed based on the set timing standards to determine the standard timing units mounted on each target first-level bifurcation point.

[0059] Timing analysis can include static timing analysis or dynamic timing analysis. Static timing analysis (STA) is to traverse all the timing paths existing in the integrated circuit, and calculate the propagation delay of the clock signal on each time path according to the timing library under given working conditions (PVT), so as to check whether the setup and hold time of the clock signal meets the constraint requirements, and determine the errors that violate the timing constraints according to the maximum path delay and the minimum path delay. Dynamic timing analysis (DTA) usually gives all input clock signals a stimulus at different times, sets a simulation time, and finally performs timing and functional analysis on the simulation results to determine whether the constraints are met.

[0060] In this embodiment, the computer device may deploy a timing analysis tool, and during the clock tree determination process, the timing analysis tool may be directly called to automatically perform timing analysis.

[0061] Figure 4 This is a flow chart of determining target mount information provided by an embodiment of the present application; Figure 4 , the step of determining the target mount information may include:

[0062] S401 , performing timing analysis according to the position coordinates of each of the target first-level bifurcation points and the position information of each of the standard timing units to obtain first mounting information.

[0063] In this embodiment, the computer device can deploy an existing timing analysis tool, so that the computer device can automatically call the timing analysis tool to perform timing analysis after determining the position coordinates of the target first-level bifurcation point to obtain the first mounting information of each target first-level bifurcation point.

[0064] S402: Detect whether the first mounting information meets the set timing standard.

[0065] After obtaining the first mounting information of each target first-level bifurcation point, the computer device may detect whether the first mounting information meets the set timing standard.

[0066] In one possible implementation, the computer device can determine the clock paths between each target first-level bifurcation point based on the first mounting information; and then determine whether each clock path meets the timing standards respectively; if each clock path meets the timing standards, the computer device can determine that the first mounting information meets the timing standards.

[0067] Exemplarily, the timing standard includes a time error threshold of the clock path. When determining whether each clock path meets the timing standard, for the clock path between any two target first-level bifurcation points, the computer device can determine the path arrival time and the required clock time between the two target first-level bifurcation points in the clock path, where the required clock time can be a preset time value; then calculate the path error time of the path arrival time and the required clock time; if the path error time is lower than the time error threshold, the computer device can determine that the clock path meets the timing standard; if the path error time is higher than or equal to the time error threshold, the computer device can determine that the clock path does not meet the timing standard.

[0068] S403: If the first mounting information does not meet the timing standard, adjust the standard timing unit mounted at each of the target first-level bifurcation points in the first mounting information until the first mounting information meets the timing standard.

[0069] When the first mounting information does not meet the timing standard, it is necessary to continue to optimize the path of the clock tree. The computer device can adjust the standard timing units mounted at each target first-level bifurcation point in the first mounting information, so that the first mounting information meets the timing standard.

[0070] For example, when adjusting the mounting information, the clock path between two target first-level bifurcation points that meet the timing standard can be determined, and then the standard timing units mounted on the two target first-level bifurcation points can be adjusted. This means that after the adjustment, the time paths of the two target first-level bifurcation points can still meet the timing requirements, and at the same time, the path time error of the clock path from the two target first-level bifurcation points to other target first-level bifurcation points can be adjusted.

[0071] For example, when it is detected that the path error time from the target first-level bifurcation point A to the target first-level bifurcation point B is lower than the time error threshold, the standard timing unit mounted after the target first-level bifurcation point B can be adjusted to after the target first-level bifurcation point A. After the adjustment, the path error time from the target first-level bifurcation point A to the target first-level bifurcation point B is still lower than the time error threshold, and the path error time from other target first-level bifurcation points to the target first-level bifurcation point B can be adjusted at the same time.

[0072] S404: If the first mount information meets the timing standard, use the first mount information as the target mount information.

[0073] S204: Use the position coordinate information of each of the target first-level branch points and the target mounting information of each of the target first-level branch points as the path information of the clock tree.

[0074] After determining the mounting information of the position coordinate information of each target first-level bifurcation point, the computer device can use the position coordinate information of each target first-level bifurcation point and the target mounting information of each target first-level bifurcation point as the path information of the clock tree. Based on the determined path information, the computer device can optimize the clock tree in the integrated circuit, thereby determining the final structure of the integrated circuit.

[0075] In this embodiment, when optimizing the structure of the clock tree, the position coordinates of the first-level bifurcation point can be determined according to the clustering algorithm, so that a better first-level bifurcation point position can be obtained, so that the clock signal in the clock tree can be more evenly distributed. In addition, when determining the mounting information of the first-level bifurcation point, analysis and adjustment can be performed based on the set timing standard, so as to ensure that the delay of the clock signal between each first-level bifurcation point is minimized and the timing requirements are met. The method in this application can be executed in the design of an integrated circuit, and the determination of the clock tree path information is automatically completed, so as to automatically optimize the clock tree, thereby improving the automation degree and optimization efficiency of the clock tree design. The method based on the embodiment of the present application can be applied to the design of an integrated circuit to optimize the clock tree structure in the integrated circuit, thereby improving the performance of the integrated circuit.

[0076] It should be noted that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0077] In order to better explain the solution in the present application, a specific embodiment is used below to illustrate the solution in the present application. Figure 5 FIG. 1 is a flow chart of another method for determining clock tree path information provided by an embodiment of the present application. Figure 5As shown, when determining the clock tree path information, the layout database can be imported first. The layout database can be the integrated circuit structure data obtained during the integrated circuit simulation design process. The computer device can extract the location information and name of the timing logic in the layout. The timing logic is the standard timing unit mentioned above. Based on the timing standard set by the user and the k value range of the k-means clustering algorithm, the computer device can calculate the position coordinate information of the first-level bifurcation point corresponding to each k value in the k value range and the mounting information of the standard timing unit through the k-means clustering algorithm. Exemplarily, the timing standard is -20ps, and the value range of k can be 2-10.

[0078] The computer device can check the difference in the distribution quantity of standard timing units after the first-level bifurcation point corresponding to different k values ​​based on the output, and select the k with the smallest difference in standard timing units. The position coordinate information of the first-level bifurcation point corresponding to the k with the smallest difference in standard timing units can be the position coordinates of the target first-level bifurcation point of the obtained clock tree.

[0079] After determining the position coordinates of the target first-level bifurcation point, the computer equipment can perform PR (Place and Route, layout and routing) process and static timing analysis, so that the timing analysis can be performed according to the set process. Perform timing analysis on the standard timing units after any two first-level bifurcation points. If the time path of the standard timing units after the two first-level bifurcation points does not meet the timing standards, remount them. For example, you can check whether the timing slack of the timing path from the first-level bifurcation point A to the first-level bifurcation point B is less than the timing standard. If it is less, mount the standard timing unit mounted after the first-level bifurcation point B to the first-level bifurcation point A, and then re-perform timing analysis.

[0080] If the timing standard is met, the first-level bifurcation point position coordinates and the mounting information of the standard timing unit can be output; if the timing standard is not met, the mounting information can be adjusted until the timing standard is met.

[0081] The method in the embodiment of the present application can constitute an efficient and automated clock tree generation method. In the method in the embodiment of the present application, the k-means clustering algorithm can be used to locate the first-level bifurcation point. Using the k-means clustering algorithm, the computer device accurately calculates the position of the first-level bifurcation point according to the position of each trigger in the circuit, so that the optimal first-level bifurcation point position can be automatically identified and located, ensuring that the clock signal is more evenly distributed, with more intelligent and automated advantages.

[0082] The method in the embodiment of the present application can dynamically evaluate and adjust the k value when using the k-means clustering algorithm. Dynamically evaluating and adjusting the value of the cluster number k in the k-means clustering algorithm can adapt to the circuit design requirements of different scales and complexities, thereby being able to flexibly respond to different design scenarios, further improving the adaptability and versatility of the method in the present application.

[0083] The method in the embodiment of the present application can automatically adjust the mounting logic of the first-level bifurcation point and the standard timing unit. The method in the embodiment of the present application can automatically adjust the mounting logic of the first-level bifurcation point and the standard timing unit according to the timing analysis results, thereby optimizing the clock tree structure; it realizes a fully automated process from timing analysis to mounting logic adjustment, reduces the complexity of manual adjustment, and improves design efficiency and accuracy.

[0084] The method in the embodiment of the present application can continuously evaluate and adjust the first-level bifurcation point and its mounting logic through an iterative optimization process when automatically adjusting the mounting logic of the standard timing unit until all design requirements are met. By using the iterative optimization method, the computer device can ensure that the clock tree finally generated reaches the optimal state in multiple indicators, thereby improving the reliability and performance of the design.

[0085] The method in the embodiment of the present application can adopt a global optimization strategy to comprehensively consider the first-level bifurcation point location, timing requirements and mounting logic. It provides a systematic and comprehensive optimization solution to ensure the optimal configuration of the clock tree in terms of overall performance, overcoming the limitations of the prior art. It greatly improves the automation, accuracy and efficiency of clock tree design.

[0086] The method in the embodiment of the present application can improve the automation, accuracy and efficiency of the clock tree design. Based on the optimization of the clock tree design, the method in the present application can optimize the total winding length of the integrated circuit and improve the performance of the integrated circuit.

[0087] Reference Figure 6 , shows a schematic diagram of a device for determining clock tree path information provided in an embodiment of the present application, which may specifically include an acquisition module 61, a clustering module 62, an analysis module 63 and a determination module 64, wherein:

[0088] An acquisition module 61 is used to acquire the position information of each standard timing unit in the clock tree;

[0089] A clustering module 62, configured to perform cluster analysis on the position information of each of the standard timing units to obtain the position coordinates of multiple target first-level bifurcation points of the clock source in the clock tree;

[0090] An analysis module 63, configured to determine target mounting information of each target first-level bifurcation point based on the position coordinates of each target first-level bifurcation point and the set timing standard, wherein the target mounting information includes information of the standard timing unit connected to each target first-level bifurcation point;

[0091] The determination module 64 is configured to use the position coordinate information of each of the target first-level bifurcation points and the target mounting information of each of the target first-level bifurcation points as the path information of the clock tree.

[0092] In a possible implementation, the clustering module 62 includes:

[0093] The clustering result determination submodule is similar to performing cluster analysis on the position information of each of the standard time series units by using a k-means clustering algorithm based on the set multiple values ​​to obtain multiple clustering results, wherein the clustering results include the position coordinates of the first-level bifurcation points corresponding to the values;

[0094] The target value determination submodule is used to select a target value from the multiple values ​​according to the multiple clustering results, and the position coordinates of the first-level bifurcation point corresponding to the target value are the position coordinates of the target first-level bifurcation point.

[0095] In a possible implementation, the clustering result determination submodule includes:

[0096] A result class determination module, used to perform cluster analysis on the position information of each of the standard time series units by using a k-means clustering algorithm to obtain multiple result classes;

[0097] The first-level bifurcation point determination module is used to use the cluster center of each of the result classes as the position coordinates of each of the first-level bifurcation points.

[0098] In a possible implementation, the clustering result includes a plurality of result classes, each result class includes at least one of the standard time sequence units, and the target value determination submodule includes:

[0099] a distribution difference value determining unit, configured to calculate the distribution difference value of the standard time series units in the clustering result according to the number of the standard time series units in each of the result classes;

[0100] The target value determination unit is used to take the value corresponding to the minimum distribution difference value as the target value.

[0101] In a possible implementation, the analysis module 63 includes:

[0102] A timing analysis submodule, configured to perform timing analysis according to the position coordinates of each of the target first-level bifurcation points and the position information of each of the standard timing units to obtain first mounting information;

[0103] A detection submodule, used to detect whether the first mounting information meets the set timing standard;

[0104] an adjusting submodule, configured to adjust the standard timing units mounted at each of the target first-level bifurcation points in the first mounting information, if the first mounting information does not meet the timing standard, until the first mounting information meets the timing standard;

[0105] The determination submodule is configured to use the first mount information as the target mount information if the first mount information meets the timing standard.

[0106] In a possible implementation, the detecting submodule detecting whether the first mounting information meets the set timing standard includes:

[0107] A clock path determining unit, configured to determine a clock path from each of the target first-level bifurcation points to each of the mounted standard timing units according to the first mounting information;

[0108] A detection unit, used to respectively determine whether each of the clock paths meets the timing standard;

[0109] A determination unit is used to determine that the first mounting information meets the timing standard if each of the clock paths meets the timing standard.

[0110] In a possible implementation, the timing standard includes a time error threshold of a clock path, and the detection unit includes:

[0111] A determination subunit, configured to determine, for any of the clock paths, a path arrival time and a required clock time from the target first-level bifurcation point in the clock path to the mounted standard sequential unit;

[0112] An error calculation subunit, used to calculate the path error time between the path arrival time and the required clock time;

[0113] The judging subunit is configured to determine that the clock path meets the timing standard if the path error time is lower than the time error threshold.

[0114] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiment part.

[0115] Figure 7This is a schematic diagram of the structure of a computer device provided in an embodiment of the present application. Figure 7 As shown, the computer device 7 of this embodiment includes: at least one processor 70 ( Figure 7 Only one is shown in the figure), a memory 71, and a computer program 72 stored in the memory 71 and executable on the at least one processor 70, wherein the processor 70 implements the steps of any of the above-mentioned method embodiments when executing the computer program 72.

[0116] The computer device 7 may be a computing device such as a desktop computer, a notebook, a PDA, or a cloud computing device. The computer device may include, but is not limited to, a processor 70 and a memory 71. Those skilled in the art will appreciate that Figure 7 It is only an example of the computer device 7 and does not constitute a limitation on the computer device 7. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, it may also include input and output devices, network access devices, etc.

[0117] The processor 70 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0118] In some embodiments, the memory 71 may be an internal storage unit of the computer device 7, such as a hard disk or memory of the computer device 7. In other embodiments, the memory 71 may also be an external storage device of the computer device 7, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the computer device 7. Further, the memory 71 may also include both an internal storage unit and an external storage device of the computer device 7. The memory 71 is used to store an operating system, an application program, a boot loader (BootLoader), data, and other programs, such as the program code of the computer program. The memory 71 may also be used to temporarily store data that has been output or is to be output.

[0119] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0120] An embodiment of the present application provides a computer program product. When the computer program product is run on a computer device, the computer device can implement the steps in the above-mentioned method embodiments when executing the computer device.

[0121] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application is described in detail with reference to the above-mentioned embodiments, a person skilled in the art should understand that the technical solutions described in the above-mentioned embodiments can still be modified, or some of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A method for determining clock tree path information, characterized in that: include: Get the location information of each standard timing unit in the clock tree; Performing cluster analysis on the position information of each of the standard sequential units to obtain the position coordinates of multiple target first-level bifurcation points of the clock source in the clock tree; Based on the position coordinates of each of the target first-level bifurcation points and the set timing standard, determine the target mounting information of each of the target first-level bifurcation points, the target mounting information including the information of the standard timing unit connected to each of the target first-level bifurcation points; The position coordinate information of each of the target first-level branching points and the target mounting information of each of the target first-level branching points are used as the path information of the clock tree.

2. The method according to claim 1, characterized in that The cluster analysis is performed on the position information of each of the standard sequential units to obtain the position coordinates of multiple target first-level bifurcation points of the clock source in the clock tree, including: Based on the set multiple values, cluster analysis is performed on the position information of each of the standard time sequence units by using a k-means clustering algorithm to obtain multiple clustering results, wherein the clustering results include the position coordinates of the first-level bifurcation points corresponding to the values; According to the plurality of clustering results, a target value is selected from the plurality of values, and the position coordinates of the first-level bifurcation point corresponding to the target value are the position coordinates of the target first-level bifurcation point.

3. The method according to claim 2, characterized in that Based on the set multiple values, the location information of each of the standard timing units is clustered and analyzed by a k-means clustering algorithm to obtain multiple clustering results, including: Performing cluster analysis on the position information of each of the standard time series units by using a k-means clustering algorithm to obtain multiple result classes; The cluster centers of the result classes are respectively used as the position coordinates of the first-level bifurcation points.

4. The method according to claim 2, characterized in that The clustering result includes a plurality of result classes, each of which includes at least one of the standard time series units, and the selecting a target value from a plurality of the values ​​according to the plurality of the clustering results includes: Calculating the distribution difference value of the standard time sequence units in the clustering result according to the number of the standard time sequence units in each result class; The value corresponding to the smallest distribution difference value is used as the target value.

5. The method according to any one of claims 1 to 4, characterized in that: The step of determining the target mounting information of each of the first-level target bifurcation points based on the position coordinates of each of the first-level target bifurcation points and the set timing standard includes: Performing timing analysis according to the position coordinates of each of the target first-level bifurcation points and the position information of each of the standard timing units to obtain first mounting information; Detecting whether the first mounting information meets the set timing standard; If the first mounting information does not meet the timing standard, adjusting the standard timing unit mounted at each of the target first-level bifurcation points in the first mounting information until the first mounting information meets the timing standard; If the first mount information meets the timing standard, the first mount information is used as the target mount information.

6. The method according to claim 5, characterized in that The detecting whether the first mounting information meets the set timing standard includes: Determine, according to the first mounting information, a clock path between each of the target first-level bifurcation points; Determining whether each of the clock paths meets the timing standard respectively; If each of the clock paths meets the timing standard, it is determined that the first mounting information meets the timing standard.

7. The method according to claim 6, characterized in that The timing standard includes a time error threshold of a clock path, and the step of respectively determining whether each of the clock paths meets the timing standard includes: For any of the clock paths, determining a path arrival time and a required clock time between two target first-level bifurcation points in the clock path; Calculate the path error time between the path arrival time and the required clock time; If the path error time is lower than the time error threshold, it is determined that the clock path meets the timing standard.

8. A device for determining clock tree path information, characterized in that: include: An acquisition module, used to obtain the position information of each standard timing unit in the clock tree; A clustering module, used for performing cluster analysis on the position information of each of the standard timing units to obtain the position coordinates of multiple target first-level bifurcation points of the clock source in the clock tree; An analysis module, configured to determine target mounting information of each of the target first-level bifurcation points based on the position coordinates of each of the target first-level bifurcation points and the set timing standard, wherein the target mounting information includes information of the standard timing unit connected to each of the target first-level bifurcation points; The determination module is used to use the position coordinate information of each of the target first-level bifurcation points and the target mounting information of each of the target first-level bifurcation points as the path information of the clock tree.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

Images