Fault test method and system for phase change memory array

Abstract

The invention discloses a fault test method and system for a phase change memory array, and relates to the technical field of integrated circuits, and the method comprises the steps: analyzing a plurality of fault modes in the phase change memory array, and extracting the necessary and sufficient conditions of each fault mode, the necessary and sufficient conditions being the failure characteristics of a certain unit or a plurality of units in the array; deducing a test sequence suitable for the fault test of the phase change memory array according to the necessary and sufficient conditions; constructing a fault detection circuit based on the test sequence, and embedding the fault detection circuit into a phase change memory array; and performing fault testing on the phase change memory array by using the fault detection circuit, and judging the health state of each memory unit in the array to complete the fault testing. The algorithm provided by the invention can detect the special fault of the PCRAM, which cannot be identified by a traditional detection circuit, so that the fault coverage rate is greatly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a fault testing method and system for a phase change memory array. Background Art

[0002] PCRAM is an emerging memory technology that competes with the current mainstream dynamic random access memory (DRAM) and flash memory (FLASH). Compared with traditional storage technology, PCRAM stores data through resistance states rather than relying on charge storage. This feature frees it from the scaling limitations associated with charge storage and shows wide application potential in multiple fields such as storage technology, memory computing, and logic systems. Therefore, it is expected to become an important alternative to traditional memory in the future. In the read and write operations of PCRAM, data access functions are performed by applying voltage to the storage element. The specific operation process involves controlling the voltage level of the storage cell to achieve data writing and reading. During the READ operation, the appropriate read voltage is applied to the bit line (BL) of the addressed cell, while turning on the pass transistor by biasing its gate terminal. The low voltage on the BL is used to provide the required read current and ensure that the data stored in the addressed cell is not accidentally changed. The SET operation is used to write logic "1" to the addressed cell. This process is achieved by applying a high voltage to the BL and biasing the word line (WL) to turn on the pass transistor. A high current is forced through the memory cell, heating the material to a temperature above the glass transition temperature but below the melting point of the GST material, thereby causing the material to transform into a crystalline phase. The BL, source line (SL), and WL of the unaddressed cells are grounded to inhibit their programming. The RESET operation is used to write a logical "0" to the cell. A high current is applied to the Germanium Antimony Telluride (GST) layer of the selected cell, heating the material to a temperature above the melting point and then rapidly cooling it to form an amorphous state. This operation is achieved by applying a high voltage on the BL and applying a suitable voltage to the gate terminal to turn on the pass transistor. For the unaddressed cells, their BL, SL, and WL are also kept grounded to avoid interference.

[0003] Research has shown that PCRAM not only has static and dynamic faults like conventional memories, but also has some unique special faults. The operation of PCRAM relies on heat changes to store information, so the design and implementation of its storage cells must ensure effective isolation between the cells. In addition, under different operating conditions, the voltage must be kept within the design limit to ensure the normal operation of the device and the reliable preservation of data. If these requirements are not met, a variety of PCRAM special faults may occur. Traditional testing technology cannot accurately distinguish the five states of PCRAM, resulting in many faults not being detected in time. Therefore, in order to improve the coverage of fault detection, it is necessary to develop new test circuits and algorithms for PCRAM. Summary of the invention

[0004] The purpose of this section is to summarize some aspects of embodiments of the present invention and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and the specification abstract and the invention title of this application to avoid blurring the purpose of this section, the specification abstract and the invention title, and such simplifications or omissions cannot be used to limit the scope of the present invention.

[0005] In view of the above existing problems, the present invention is proposed.

[0006] Therefore, the present invention provides a fault testing method and system for a phase change memory array, which can solve the problems mentioned in the background technology.

[0007] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0008] In a first aspect, the present invention provides a method for testing a phase change memory array, which includes: a method for testing a phase change memory array, characterized in that: it includes analyzing multiple failure modes in the phase change memory array, extracting necessary and sufficient conditions for each failure mode, wherein the necessary and sufficient conditions are failure characteristics of a certain unit or multiple units in the array;

[0009] Derivation of a test sequence suitable for phase change memory array fault testing based on the necessary and sufficient conditions;

[0010] constructing a fault detection circuit based on the test sequence and embedding it into a phase change memory array;

[0011] The fault detection circuit is used to perform a fault test on a phase change memory array, determine the health status of each storage unit in the array, and complete the fault test.

[0012] As a preferred solution of the fault testing method of the phase change memory array of the present invention, wherein: the analysis of multiple fault modes in the phase change memory array includes:

[0013] Model the operating characteristics of phase-change memory arrays to analyze the behavior of cells under different conditions;

[0014] Consider the impact of environmental factors on storage units under different working conditions;

[0015] The environmental factors include voltage fluctuations, temperature changes and current density;

[0016] The behavior of phase-change memory under different operating conditions is described through theoretical modeling and experimental data.

[0017] As a preferred solution of the fault testing method of the phase change memory array of the present invention, the testing method further comprises:

[0018] During the test, a fault detection circuit is used, which can monitor the electrical performance of the phase change memory in real time, such as current, voltage, temperature and other parameters, and determine whether the memory cell has a fault based on the monitored parameter changes;

[0019] The fault detection circuit includes multiple modules, including an electrical parameter adjustment module for simulating phase change memory in different fault modes, so as to simulate and detect fault behaviors under various environmental conditions, and test and verify the storage unit according to the simulation results.

[0020] As a preferred solution of the fault testing method of the phase change memory array of the present invention, wherein: the fault mode includes read fault, write fault, hold fault and thermal fault;

[0021] The failure modes extract necessary and sufficient conditions for each failure mode by analyzing the working state and operating conditions of the phase change memory array;

[0022] The necessary and sufficient conditions include the influence of voltage, current, and temperature environmental factors on the storage unit, and the influence of electrical stress and thermal stress on the performance of the storage unit.

[0023] As a preferred solution of the fault testing method of the phase change memory array of the present invention, wherein: the necessary and sufficient condition is to adjust the working current, voltage and ambient temperature of the memory cell to simulate the working state of the memory cell under different operating conditions, and determine the fault behavior of the memory cell under specific working conditions;

[0024] By analyzing the influence of different operating conditions on the phase change memory array, a test sequence is provided for the detection of failure modes.

[0025] As a preferred solution of the fault testing method of the phase change memory array of the present invention, wherein: the test sequence is based on the working characteristics and fault mode of the phase change memory array, and adopts a combination of a sensitization sequence and a detection sequence;

[0026] The sensitization sequence is used to activate potential faults in the array, and the detection sequence is used to determine whether a fault has occurred;

[0027] Trigger and detect failure modes under various operating conditions by optimizing test sequences;

[0028] The test sequence is generated by using the improved March-PCRAM algorithm, and the generation process of the sensitization sequence and the detection sequence is optimized according to the characteristics of the phase change memory array;

[0029] The specific process of the improved March-PCRAM algorithm is as follows:

[0030] {M0↑↓(w0);M1↑(r ref0 w1 r ref1 ); M2↓(w1 r ref1 w0 ref0 ); M3↓(r ref0 w1 r ref1 );M4↑↓(r ref1 )}

[0031] Among them, M0-M4 represent the step elements in the algorithm, ↑ represents that the address is accessed in ascending order, ↓ represents that the address is accessed in descending order, ↑↓ means that the address can be accessed in both ascending and descending order, w0 represents writing logic 0 data to the selected storage unit, w1 represents writing logic 1 data to the selected unit, r0 represents reading the data in the selected unit and the expected value is 0, r1 represents the expected value when reading is 1, and r ref0 and r ref1 It is a special read operation to detect PCRAM-specific faults;

[0032] During the test process, if the read data of a test address does not match the expected value, the address is judged to have a fault, indicating that there is an abnormality in the read and write operations of the PCRAM and the fault detection has failed; if the read data of all addresses are consistent with the expected value, the fault detection is considered to have passed.

[0033] In a second aspect, the present invention provides a fault test circuit for a phase change memory array, comprising:

[0034] The fault detection circuit includes multiple electrical performance monitoring modules and a PRR-based verification module.

[0035] The electrical performance monitoring module is used to monitor the current, voltage and temperature of the storage unit in real time. When an abnormal change is detected, the fault detection circuit can generate an early warning signal and feed it back to the external controller for fault analysis;

[0036] The PRR-based verification module is used to monitor the electrical response of the storage unit in real time during the test, evaluate the health status of the storage unit based on the response, conduct in-depth analysis of the failure mode, and generate a failure test report through a feedback loop, thereby assisting in locating and analyzing potential failures of the storage unit.

[0037] In a third aspect, the present invention provides a fault test system for a phase change memory array, which includes: a fault analysis module, a test sequence module, a test circuit construction module, and a fault detection module;

[0038] The fault analysis module is used to analyze multiple fault modes in the phase change memory array and extract necessary and sufficient conditions for each fault mode, wherein the necessary and sufficient conditions are failure characteristics of a certain unit or multiple units in the array;

[0039] The test sequence module is used to derive a test sequence suitable for phase change memory array fault testing according to the necessary and sufficient conditions;

[0040] The test circuit construction module is used to construct a fault detection circuit based on the test sequence and embed it into the phase change memory array;

[0041] The fault detection module is used to perform a fault test on the phase change memory array using the fault detection circuit, determine the health status of each storage unit in the array, and complete the fault test.

[0042] In a fourth aspect, the present invention provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, wherein: when the processor executes the computer program, the steps of a fault testing method for a phase change memory array are implemented.

[0043] In a fifth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein: when the computer program is executed by a processor, the steps of a fault testing method for a phase change memory array are implemented.

[0044] Compared with the prior art, the beneficial effect of the present invention is that by using four reference currents in parallel to read five states of PCRAM cells, the efficiency is greatly improved compared to the traditional reading circuit that can only set one reference current to distinguish two storage states, and the time required for MBIST circuit fault testing is significantly reduced. The method is based on an in-depth analysis of PCRAM conventional fault models and unique fault models, and derives a March-PCRAM algorithm with a wide coverage. This algorithm can not only detect all static single-cell faults and static double-cell faults, but also effectively detect most dynamic single-cell faults, dynamic double-cell faults and unique faults of PCRAM. Due to the use of four reference currents, the algorithm can detect PCRAM unique faults that cannot be identified by traditional detection circuits, thereby greatly improving the fault coverage. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1An MBIST overall circuit structure diagram of a phase change memory array fault testing method and system provided by one embodiment of the present invention;

[0047] Figure 2 An internal structural diagram of a computer device of a phase change memory array fault testing method and system provided by an embodiment of the present invention;

[0048] Figure 3 A March-PCRAM algorithm for PD fault test waveform of a phase change memory array fault test method and system provided by an embodiment of the present invention;

[0049] Figure 4 A fault testing method and system for a phase change memory array provided by an embodiment of the present invention provides a March-PCRAM algorithm for an IPF fault testing waveform. DETAILED DESCRIPTION

[0050] In order to make the above-mentioned purposes, features and advantages of the present invention more understandable, the specific implementation methods of the present invention are described in detail below in conjunction with the drawings of the specification. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary persons in the art without creative work should fall within the scope of protection of the present invention.

[0051] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0052] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.

[0053] Example 1

[0054] Reference Figure 1-Figure 2 , which is the first embodiment of the present invention, provides a fault testing method for a phase change memory array, comprising:

[0055] The present application provides a method that can effectively solve the above-mentioned problems. Next, a method for implementing a fault test of a phase change memory array will be described in detail in combination with multiple embodiments.

[0056] Figure 1A method flow chart of a fault testing method and system for a phase change memory array is shown, comprising:

[0057] S1: Analyze multiple failure modes in the phase change memory array and extract necessary and sufficient conditions for each failure mode, wherein the necessary and sufficient conditions are failure characteristics of a certain unit or multiple units in the array;

[0058] Furthermore, the functional failure types of the phase change memory array are analyzed to determine the failure characteristics that may be caused by each failure type.

[0059] Based on the working principle of phase change memory array, possible failure modes are identified, including read failure, write failure, retention failure, etc.

[0060] Conduct in-depth analysis of each failure mode to explore how the failure affects the performance of the storage unit and identify possible failure manifestations, such as loss of data retention capability, inability to write or read data, data read and write errors, etc.

[0061] Furthermore, the operating characteristics of the phase-change memory array are modeled to analyze the behavior of the cells under different conditions;

[0062] Consider the impact of environmental factors (such as voltage fluctuations, temperature changes, current density, etc.) on storage cells under different working conditions;

[0063] Through theoretical modeling and experimental data, describe the behavior of phase change memory under different operating conditions, especially the triggering conditions for the occurrence of failure modes (such as too high write current, too low read voltage, etc.);

[0064] The PCRAM fault model covers two categories: special faults and general faults. In order to detect these faults in the memory, it is necessary to derive the sensitization sequence and the detection sequence according to the corresponding fault primitives; the elements of the March-PCRAM algorithm must first stimulate the potential faults through the sensitization sequence, and then determine whether the storage unit has a fault through the detection sequence. This example analyzes the PCRAM fault model and lists all possible fault types, fault causes and their corresponding fault primitives, as shown in Table 1 below.

[0065] Table 1 Fault causes and fault primitives for PCRAM special faults

[0066]

[0067] Based on the array structure and the working mechanism of the storage unit, the necessary and sufficient conditions for each failure mode are identified and summarized, and these conditions are the failure fragments in the detection sequence.

[0068] Based on the physical and electrical characteristics of the unit, necessary and sufficient conditions for each failure mode are proposed to ensure that the detection can effectively trigger and discover the problem.

[0069] In each fault mode, the minimum conditions that cause the fault to occur (such as time, temperature, voltage, etc.) are extracted and converted into necessary and sufficient conditions in the fault detection sequence. Each necessary and sufficient condition should cover the corresponding detection segment or multiple segments.

[0070] The present invention adopts a device-aware test method to perform fault injection, and simulates faults in actual operation by adjusting the electrical parameters of the PCRAM model used. The specific operation is to change the electrical parameters in the Verilog-A model of the PCRAM, and by adjusting the voltage value or programming time of the RESET or SET operation, the insufficient or excessive phase change of the phase change material can be simulated, thereby causing the offset of the resistance value, and then simulating the behavioral characteristics of different faults.

[0071] The specific adjustment methods of electrical parameters in different fault simulation processes are listed in Table 2. By combining the Device-aware test method and the application of the March-PCRAM algorithm, various potential PCRAM faults can be effectively simulated and detected, significantly improving the test coverage and optimizing the design and reliability of the memory.

[0072] Table 2 Electrical parameter adjustment method for PCRAM fault simulation

[0073] Fault name Electrical parameter adjustment method PD Failure <![CDATA[R set : Adjusted from 7K to 100K; R reset :Adjust from 200K to 500K]]> SR Failure <![CDATA[V h : Adjusted from 0.45 to 0.7; V th : Adjusted from 0.8 to 1.0]]> FWR Fault <![CDATA[R on : Adjusted from 0.5K to 10K; R set :Adjust from 7K to 50K]]> SS failure <![CDATA[R set : Adjusted from 7K to 1M; R reset :Adjust from 200K to 1M]]> RRD Failure <![CDATA[V s : Adjusted from 3 to 1.5; I C : Adjusted from 0 to 0.2]]> RD failure <![CDATA[R set : Adjust from 7K to 20K; V h : Adjusted from 0.45 to 0.65]]> IPF Failure <![CDATA[R reset : Adjust from 200K to 1M; V s : Adjusted from 3 to 2.8]]> CDF Failure <![CDATA[V th : Adjusted from 0.8 to 0.5; R set :Adjust from 7K to 10K]]> IRF Failure <![CDATA[I s : Adjusted from 0.6m to 0.3m; V s : Adjusted from 3 to 1.0]]> DRF Failure <![CDATA[R set : Adjusted from 7K to 15K; V h : Adjusted from 0.45 to 0.6]]> PRF Failure <![CDATA[R set : Adjusted from 7K to 50K; R on : Adjust from 0.5K to 5K]]> WPF Troubleshooting <![CDATA[T rc :Adjust from 0.1μ to 0.2μ; V h : Adjusted from 0.45 to 0.5]]> SCF failure <![CDATA[V s : Adjusted from 3 to 0.1; I C Adjust from 0 to 1]]> PDCF Failure <![CDATA[V h : Adjusted from 0.45 to 0.4; R set :Adjusted from 7K to 30K]]>

[0074] The effectiveness of the proposed necessary and sufficient conditions is verified through experiments and simulations to ensure that the failure characteristics of the storage unit can be accurately captured;

[0075] Verify the accuracy and feasibility of the proposed necessary and sufficient conditions through experiments and simulations;

[0076] Implement these necessary and sufficient conditions in the actual phase-change memory array and record whether its performance is as expected. If the conditions are not completely accurate, it is necessary to adjust the parameters or test methods to ensure that the failure characteristics of the phase-change memory cells can be captured.

[0077] S2: deriving a test sequence suitable for phase change memory array fault testing according to the necessary and sufficient conditions;

[0078] Furthermore, based on the necessary and sufficient conditions of the fault mode obtained in step 1, corresponding test sequences are designed to cover different types of faults;

[0079] According to the failure modes and necessary and sufficient conditions, a set of test sequences is constructed to cover all the identified failure modes;

[0080] Each necessary and sufficient condition corresponds to one or more detection segments in the test sequence. Different test strategies are designed according to different fault types, such as read-write faults, retention faults, etc., to ensure accurate detection under different fault modes.

[0081] Furthermore, each detection segment in the test sequence is matched with necessary and sufficient conditions to ensure that the test sequence can effectively trigger the fault and detect the corresponding problem;

[0082] Ensure that each segment in the test sequence can effectively detect specific failure modes;

[0083] Match the segments in the test sequence according to necessary and sufficient conditions to ensure that the test segments are triggered at the appropriate time and detect the fault; for example, for write faults, the test segments should consider different voltage and current conditions to trigger potential write errors.

[0084] Furthermore, according to different fault types, the test sequence is optimized and special test segments (such as read-write stress test, long-term hold test, etc.) are added to enhance the sensitivity of the test.

[0085] According to the particularity of phase change memory array, the test sequence is optimized to enhance its fault detection capability.

[0086] Special segments such as stress tests and temperature change tests are added to the test sequence to simulate the stress and failure modes in the real working environment, ensuring that the test can accurately detect minor faults.

[0087] Furthermore, the tests were conducted in an experimental environment, and the execution order and timing of the sequences were adjusted to ensure maximum coverage of potential faults;

[0088] Verify the integrity and effectiveness of the designed test sequence through experiments;

[0089] The test sequence is executed in the actual phase change memory array and the test results are recorded; if some failure modes cannot be detected, the execution timing or order of the test sequence is adjusted and new detection steps are added.

[0090] S3: constructing a fault detection circuit based on the test sequence and embedding it into the phase change memory array;

[0091] Further, the test circuit includes a 1T1R array storage unit, a read / write circuit and a PRR DFT module;

[0092] The 1T1R array consists of 4×4 memory cells, each of which contains an NMOS tube and a PCRAM element;

[0093] NMOS tube MOS1-MOS in each column storage unit 16The drain of each is connected to the output of the upper tri-state gate, and its source is connected to the NMOS tube MOS 17 -MOS 20 The source of is connected;

[0094] The gate is connected to the input signal terminal WL0-WL3, and the source is connected to the positive terminal of PCRAM;

[0095] The negative terminal of PCRAM is connected to the output terminal of the lower tri-state gate and the NMOS tube MOS 21 -MOS 24 The drain;

[0096] The PRR DFT module consists of a transmission circuit, a reference current generation circuit and an inverter circuit, and is used to generate multiple groups of reference currents required in the test process.

[0097] Further, the MBIST circuit is composed of a control generator, an address generator, a data generator, a comparator and a diagnostic device;

[0098] The control generator is responsible for coordinating the operation of each module in the MBIST circuit and executing the March-PCRAM test algorithm in the order of M0 to M4;

[0099] The address generator and data generator generate the address signal and data signal required by the algorithm respectively; the comparator is used to compare the actual data of the PCRAM unit with the expected data to determine whether the read and write operations of the memory are correct;

[0100] When the test result is correct, the output signal Test_fail remains at a low level, and the fault address recorder does not record any information;

[0101] If an error is detected, the Test_fail signal is set high and triggers the fault address recorder to record the address of the unit where the fault exists.

[0102] The diagnostic device outputs the recorded failed cell address through the address signal Fail_adr.

[0103] During the test, when the read data of a certain address does not match the expected data, the address is judged to have a fault, indicating that the read and write operations of the PCRAM have not passed the test; if the read data of all addresses are consistent with the expected values, the fault detection passes.

[0104] Furthermore, the reference current I ref Generated by the NMOS tube in the PRR DFT circuit. When the read / write circuit is working, the voltage across the PCRAM is the input signal V read In the logic 0 state, the resistance of PCRAM is R HRS ; In the logic 1 state, its resistance is RLRS The working resistance states of PCRAM are divided into five types, and the upper boundary resistance values ​​and definition formulas of these resistance states are listed in Table 3 below.

[0105] Table 3 Upper boundary resistance and definition formula of PCRAM resistance state division

[0106] PCRAM resistance state Upper boundary resistance Defining formulas Deep1 None None Logic 1 state (Logic1) <![CDATA[R ref3 ]]> <![CDATA[R ref3 =R LRS ]]> Undefined State (USF) <![CDATA[R ref2 ]]> <![CDATA[R ref2 =R HRS +2 / 5*(R HRS -R LRS )]]> Logic 0 (Logic0) <![CDATA[R ref1 ]]> <![CDATA[R ref1 =R LRS +3 / 5*(R HRS -R LRS )]]> Deep0 <![CDATA[R ref0 ]]> <![CDATA[R ref0 =R HRS ]]>

[0107] According to the upper boundary resistance of the PCRAM resistance state, the reference current I generated by the four NMOS tubes in the PRR DFT circuit can be calculated respectively. ref0 ,I ref1 ,I ref2 ,I ref3 , the calculation formula is:

[0108]

[0109] Similarly, I ref1 =V read1 / R ref1 , I ref2 =V read2 / R ref2 , I ref3 =V read3 / R ref3 ;

[0110] Will I ref0 ,I ref1 ,I ref2 ,I ref3 Substituting into the calculation formula of the width-to-length ratio W / L of the NMOS tube, the width-to-length ratio of each NMOS tube in the PRRDFT circuit can be calculated respectively:

[0111]

[0112] Among them, V th is the threshold voltage of the NMOS tube, V gs is the voltage between the gate and the source, μ n is the electron mobility, C ox is the gate oxide capacitance per unit area. Through this calculation process, it can be ensured that the reference current generated by each NMOS tube accurately matches the state of the PCRAM to achieve accurate fault detection.

[0113] As a test circuit outside the conventional functions of the PCRAM memory, the MBIST circuit separates the test signal from the external logic signal through a two-to-one data selector, and controls the selector through the BIST_EN enable signal. When the BIST_EN signal is 1, the PCRAM memory enters the test mode and the MBIST circuit starts working. In the test mode, the MBIST circuit performs operations in a preset algorithm sequence. In the read operation executed by the algorithm, the comparator compares the actual signal with the expected signal to check whether there is a fault in the PCRAM. If a fault is detected at the end of the algorithm execution, the Test_fail signal will be pulled high and the corresponding faulty unit address will be recorded. The MBIST circuit includes modules such as a control generator, an address generator, a data generator, a comparator, and a diagnostic device. Figure 1 As shown. Each module works together to execute the test process in the order of the March-PCRAM test algorithm. The following is a detailed description of the functions of each module:

[0114] Control generator: controls the operation of the entire MBIST circuit, and drives each module to perform corresponding operations in sequence according to the steps of the March-PCRAM test algorithm M0-M4. The main function of the control generator is to coordinate the timing of the test process and ensure that each step of the test process is executed in sequence.

[0115] Address generator: responsible for generating the address signals required by the test algorithm. The March-PCRAM test algorithm involves accessing the memory cells one by one, so the address generator will generate the address signal of each memory cell in turn to ensure that the test algorithm can cover all the memory cells of the PCRAM.

[0116] Data generator: used to generate data signals corresponding to the test steps. The March-PCRAM algorithm involves writing different states, so the data generator generates corresponding write data according to the test steps to ensure that each storage unit of the PCRAM can receive the correct write information.

[0117] Comparator: During the test, the comparator is used to compare the actual read data of the PCRAM with the expected data. After each read operation, the comparator compares the actual read memory cell data with the expected data. If they are consistent, it means that the memory cell is not faulty; if they are inconsistent, it means that the memory cell is faulty.

[0118] Test_fail signal: When the comparator detects a data mismatch, the Test_fail signal becomes high, indicating that the test has not passed. If the read and write operations are correct, the Test_fail signal remains low, indicating that the test has passed.

[0119] Fault address recorder: When the Test_fail signal becomes high, the fault address recorder will record the address of the current storage unit. In this way, the recorder can accurately locate the faulty storage unit.

[0120] Diagnostic device: The diagnostic device further records the addresses of all failed storage cells and outputs the specific address of the failed cell through the Fail_adr signal. The address is in coded form to facilitate diagnosis of which NMOS tube PCRAM in the storage array has failed.

[0121] The algorithm covers special and common PCRAM faults. Special PCRAM faults include proximity faults, read faults, read recovery faults, and miswrite faults. In addition, common fault types include static single-cell faults, static double-cell faults, dynamic single-cell faults, and dynamic double-cell faults. The specific process of the March-PCRAM test algorithm is as follows:

[0122] {M0↑↓(w0);M1↑(r ref0 w1 r ref1 ); M2↓(w1 r ref1 w0 ref0 ); M3↓(r ref0 w1 r ref1 );M4↑↓(r ref1 )}

[0123] Among them, M0-M4 represent the step elements in the algorithm, ↑ represents the address access in ascending order, ↓ represents the address access in descending order, and ↑↓ represents that the address can be accessed in both ascending and descending order. w0 represents writing logic 0 data to the selected storage unit, and w1 represents writing logic 1 data to the selected unit; r0 represents reading the data in the selected unit and the expected value is 0, and r1 represents the expected value when reading is 1; r ref0 and r ref1 It is a special read operation to detect PCRAM-specific faults. During the test, if the read data of a test address does not match the expected value, it is determined that the address has a fault, indicating that the read and write operations of the PCRAM are abnormal and the fault detection has failed; if the read data of all addresses are consistent with the expected value, it is considered that the fault detection has passed.

[0124] S4: Use the fault detection circuit to perform a fault test on the phase change memory array to determine the health status of each memory cell in the array.

[0125] Furthermore, a test sequence is executed to monitor each storage unit in real time through the embedded fault detection circuit.

[0126] The embedded fault detection circuit monitors the memory cell status in real time and executes the preset test sequence.

[0127] Start the test sequence, monitor the read and write behavior of each storage unit one by one, determine whether it conforms to the normal state, and record the state changes of each unit in real time.

[0128] Furthermore, the detection data is collected and the health status of each storage unit is analyzed to determine whether there is a fault and the type of fault;

[0129] Combined with the results of the fault test, locate the faulty storage unit and analyze the cause of the fault, such as abnormal voltage and current, too many write times, etc.

[0130] Generates fault detection reports, provides status assessment results for each storage unit, and provides decision support for subsequent repair or replacement.

[0131] Output fault detection reports to provide detailed fault analysis and decision support.

[0132] Based on the fault detection results, a status assessment report for each storage unit is generated, providing detailed information such as the fault type, location, and possible cause to help with subsequent repair or replacement decisions; as shown in Table 4 below, a detailed description of how the March-PCRAM algorithm detects the various PCRAM special faults described in Table 1 is given.

[0133] Table 4: Excitation and detection of PCRAM special faults by March-PCRAM algorithm

[0134]

[0135]

[0136] Furthermore, this embodiment also provides a fault testing system for a phase change memory array, comprising:

[0137] Fault analysis module, test sequence module, test circuit construction module and fault detection module;

[0138] The fault analysis module is used to analyze multiple fault modes in the phase change memory array and extract necessary and sufficient conditions for each fault mode, wherein the necessary and sufficient conditions are failure characteristics of a certain unit or multiple units in the array;

[0139] The test sequence module is used to derive a test sequence suitable for phase change memory array fault testing according to the necessary and sufficient conditions;

[0140] The test circuit construction module is used to construct a fault detection circuit based on the test sequence and embed it into the phase change memory array;

[0141] The fault detection module is used to use the fault detection circuit to perform a fault test on the phase change memory array, determine the health status of each storage unit in the array, and complete the fault test.

[0142] This embodiment also provides a computer device, which may be a terminal, and its internal structure diagram may be as shown in FIG. Figure 2 As shown. The computer device includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be achieved through WIFI, an operator network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a comprehensive evaluation method suitable for orderly access of large-scale distributed power sources is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covered on the display screen, or a key, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse.

[0143] This embodiment further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented:

[0144] Analyze multiple failure modes in a phase change memory array and extract necessary and sufficient conditions for each failure mode, wherein the necessary and sufficient conditions are failure characteristics of a certain unit or multiple units in the array;

[0145] Derivation of a test sequence suitable for phase change memory array fault testing based on the necessary and sufficient conditions;

[0146] constructing a fault detection circuit based on the test sequence and embedding it into a phase change memory array;

[0147] The fault detection circuit is used to perform a fault test on a phase change memory array, determine the health status of each storage unit in the array, and complete the fault test.

[0148] Example 2

[0149] Reference Figure 3 - Figure 4, which is the second embodiment of the present invention, and this embodiment provides a fault testing method for a phase change memory array. In order to verify the beneficial effects of the present invention, scientific demonstration is carried out through economic benefit calculation and simulation experiments.

[0150] The test process used a mixed simulation verification environment, including NC-Verilog and Virtuoso fault simulators, to verify the effectiveness of all algorithms in common fault detection capabilities. The fault detection performance of the March-PCRAM algorithm was demonstrated, with PD faults and IPF faults as examples. Figure 3 and Figure 4 When the BIST_EN signal is driven by the clock signal and the BIST_EN signal is 1, the PCRAM memory enters the test mode and the MBIST circuit starts working; V BLSL The <3:0> signal reflects the complete flow of read and write operations during the execution of the March-PCRAM algorithm; X0-X3 outputs the waveform of the PRR DFT unit. The Test_fail signal is used to mark the fault. When the circuit is fault-free, the Test_fail signal remains at a low level; once a fault occurs, the Test_fail signal rises, and the system outputs the address of the faulty unit through the Fail_adr<3:0> signal. This address is represented by the 4-bit code 8421, covering test units from 0 to 15, corresponding to MOS1-MOS2 in the test array. 16 PCRAM at.

[0151] Figure 3 The test waveform of the PD adjacent interference fault is shown. The fault is excited by the w0 operation of M0 and is transmitted through r in M1. ref0 This fault is explained by the unexpected loss of stored data when the adjacent PCRAM cell is programmed to the RESET state, mainly caused by thermal crosstalk during programming. The victim cell of the PD fault must be in the RESET state before the fault. To stimulate this fault, the MOS 11 The PCRAM neighboring cell at the same location is programmed to the RESET state. 11 The final state of the PCRAM at address 10 changes from the high impedance state of 0001 to the undefined state of 0011. At the same time, the Test_fail signal rises and the Fail_adr<3:0> signal shows 1010, indicating that the March-PCRAM algorithm is at address 10, that is, MOS 11 The PCRAM at the PD successfully detected the PD failure.

[0152] Figure 4 The test waveform of IPF incomplete programming fault is shown. The fault is triggered by the w0 operation in M2 and is triggered by the r ref0Operation detection. This type of failure is prone to occur when the memory cell is in RESET operation, resulting in the cell's resistance being lower than typical, showing a resistance close to the SET state. The cause of the failure is attributed to the presence of contaminants and impurities in the active region of the GST material, which form a low-resistance parallel conductive path, thereby reducing the resistance of the entire memory cell. The final state of the PCRAM at MOS6 changes from a high-resistance state of 0001 to a low-resistance state of 0111, while the Test_fail signal rises and the Fail_adr<3:0> signal shows 0101, indicating that the March-PCRAM algorithm successfully detected the IPF failure at address 5, i.e., the PCRAM at MOS6.

[0153] The fault model of PCRAM includes unique faults and common faults, covering static single-cell faults, static double-cell faults, dynamic single-cell faults and dynamic double-cell faults. Table 5 below summarizes the comparison of fault detection coverage between the March-PCRAM algorithm and the previously developed algorithms.

[0154] Table 5 Fault coverage of the March-PCRAM algorithm and previously developed algorithms

[0155]

[0156]

[0157] It can be seen from Table 5 that this embodiment can effectively cover static single-cell faults, static double-cell faults, dynamic single-cell faults, dynamic double-cell faults, and special faults of PCRAM. By using the March-PCRAM test algorithm, the fault coverage of PCRAM in this embodiment reaches 91.43%, which is a significant improvement compared to other test algorithms, demonstrating higher fault detection capability and coverage.

[0158] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

[0159] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of complete hardware embodiments, complete software embodiments, or embodiments in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code. The scheme in the embodiments of the present application can be implemented in various computer languages, for example, object-oriented programming language Java and literal scripting language JavaScript, etc.

[0160] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0161] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0162] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0163] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0164] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A fault testing method for a phase change memory array, characterized in that: The method includes analyzing multiple failure modes in a phase change memory array and extracting necessary and sufficient conditions for each failure mode, wherein the necessary and sufficient conditions are failure characteristics of a certain unit or multiple units in the array; Derivation of a test sequence suitable for phase change memory array fault testing based on the necessary and sufficient conditions; constructing a fault detection circuit based on the test sequence and embedding it into a phase change memory array; The fault detection circuit is used to perform a fault test on a phase change memory array, determine the health status of each storage unit in the array, and complete the fault test.

2. The fault testing method of a phase change memory array as claimed in claim 1, characterized in that: The analysis of multiple failure modes in the phase change memory array includes: Model the operating characteristics of phase-change memory arrays to analyze the behavior of cells under different conditions; Consider the impact of environmental factors on storage units under different working conditions; The environmental factors include voltage fluctuations, temperature changes and current density; The behavior of phase-change memory under different operating conditions is described through theoretical modeling and experimental data.

3. The fault testing method for a phase change memory array as claimed in claim 2, wherein: The test method further comprises: During the test, a fault detection circuit is used, which can monitor the electrical performance of the phase change memory in real time, such as current, voltage, temperature and other parameters, and determine whether the memory cell has a fault based on the monitored parameter changes; The fault detection circuit includes multiple modules, including an electrical parameter adjustment module for simulating phase change memory in different fault modes, so as to simulate and detect fault behaviors under various environmental conditions, and test and verify the storage unit according to the simulation results.

4. The fault testing method for a phase change memory array as claimed in claim 3, wherein: The failure modes include read failure, write failure, hold failure and thermal failure; The failure modes extract necessary and sufficient conditions for each failure mode by analyzing the working state and operating conditions of the phase change memory array; The necessary and sufficient conditions include the influence of voltage, current, and temperature environmental factors on the storage unit, and the influence of electrical stress and thermal stress on the performance of the storage unit.

5. The fault testing method for a phase change memory array as claimed in claim 4, characterized in that: The necessary and sufficient condition simulates the working state of the storage unit under different operating conditions by adjusting the working current, voltage and ambient temperature of the storage unit, and determines the fault behavior of the storage unit under specific working conditions; By analyzing the influence of different operating conditions on the phase change memory array, a test sequence is provided for the detection of failure modes.

6. The fault testing method of a phase change memory array as claimed in claim 5, characterized in that: The test sequence is based on the operating characteristics and failure modes of the phase change memory array, and uses a combination of a sensitization sequence and a detection sequence; The sensitization sequence is used to activate potential faults in the array, and the detection sequence is used to determine whether a fault has occurred; Trigger and detect failure modes under various operating conditions by optimizing test sequences; The test sequence is generated by using the improved March-PCRAM algorithm, and the generation process of the sensitization sequence and the detection sequence is optimized according to the characteristics of the phase change memory array; The specific process of the improved March-PCRAM algorithm is as follows: {M0↑↓(w0);M1↑(r ref0 w1 r ref1 );M2↓(w1 r ref1 w0 r ref0 );M3↓(r ref0 w1 r ref1 );M4↑↓(r ref1 )} Among them, M0-M4 represent the step elements in the algorithm, ↑ represents that the address is accessed in ascending order, ↓ represents that the address is accessed in descending order, ↑↓ means that the address can be accessed in both ascending and descending order, w0 represents writing logic 0 data to the selected storage unit, w1 represents writing logic 1 data to the selected unit, r0 represents reading the data in the selected unit and the expected value is 0, r1 represents the expected value when reading is 1, and r ref0 and r ref1 It is a special read operation to detect PCRAM-specific faults; During the test process, if the read data of a test address does not match the expected value, the address is judged to have a fault, indicating that there is an abnormality in the read and write operations of the PCRAM and the fault detection has failed; if the read data of all addresses are consistent with the expected value, the fault detection is considered to have passed.

7. A fault test circuit for a phase change memory array, based on the fault test method for a phase change memory array according to any one of claims 1 to 6, characterized in that: The fault detection circuit includes multiple electrical performance monitoring modules and a PRR-based verification module. The electrical performance monitoring module is used to monitor the current, voltage and temperature of the storage unit in real time. When an abnormal change is detected, the fault detection circuit can generate an early warning signal and feed it back to the external controller for fault analysis; The PRR-based verification module is used to monitor the electrical response of the storage unit in real time during the test, evaluate the health status of the storage unit based on the response, conduct in-depth analysis of the failure mode, and generate a failure test report through a feedback loop, thereby assisting in locating and analyzing potential failures of the storage unit.

8. A phase change memory array fault testing system, based on the phase change memory array fault testing method according to any one of claims 1 to 6, characterized in that: Including, a fault analysis module, a test sequence module, a test circuit construction module and a fault detection module; The fault analysis module is used to analyze multiple fault modes in the phase change memory array and extract necessary and sufficient conditions for each fault mode, wherein the necessary and sufficient conditions are failure characteristics of a certain unit or multiple units in the array; The test sequence module is used to derive a test sequence suitable for phase change memory array fault testing according to the necessary and sufficient conditions; The test circuit construction module is used to construct a fault detection circuit based on the test sequence and embed it into the phase change memory array; The fault detection module is used to perform a fault test on the phase change memory array using the fault detection circuit, determine the health status of each storage unit in the array, and complete the fault test.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the fault testing method for the phase change memory array according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the fault testing method for a phase change memory array according to any one of claims 1 to 7 are implemented.

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