Silicon-based capacitor and preparation method thereof

Abstract

The invention belongs to the field of thin film capacitors, and provides a silicon-based capacitor and a preparation method thereof.The silicon-based capacitor comprises a silicon-based substrate, a first electrode layer, a dielectric layer, a second electrode layer and a packaging layer, the silicon-based substrate is provided with a chute, the first electrode layer is evenly laid on the silicon-based substrate, and the dielectric layer is arranged on the silicon-based substrate; the dielectric layer is located between the first electrode layer and the second electrode layer to isolate the first electrode layer from the second electrode layer, the polarity of the first electrode layer is different from that of the second electrode layer, and the packaging layer wraps all the first electrode layer, the dielectric layer, the second electrode layer and the silicon-based substrate for packaging. According to the silicon-based capacitor, the inclined groove is formed in the silicon-based substrate, so that the first electrode layer, the dielectric layer and the second electrode layer which are sequentially and upwards laid along the silicon-based substrate are all in an inclined state, the silicon-based capacitor is flatter in space, the capacitance in the space is higher, the heat dissipation performance is better, and the adaptability to the application environment with the thickness requirement is better.

Description

Technical Field

[0001] The present invention belongs to the field of thin film capacitors, and in particular relates to silicon-based capacitors and a preparation method thereof. Background Art

[0002] With the rapid development of new energy vehicles and communication technology, the performance requirements for silicon-based capacitors are increasing. New energy vehicles require capacitors with high energy density to support their battery systems, and automotive radio frequency systems rely on capacitors with excellent high-frequency performance to ensure the stability of signal transmission. Communication equipment also requires miniaturized high-performance capacitors to adapt to compact design spaces. Therefore, developing a silicon-based capacitor that can meet the performance requirements of capacitor capacity, frequency response, and temperature stability while also having the advantage of a small size has become an industry technology trend.

[0003] Existing silicon-based capacitors are usually packaged as a whole from bottom to top, with the lower electrode-silicon-based substrate-dielectric-upper electrode. In order to adapt to high energy density and high-frequency scenarios, this type of silicon-based capacitor using a smooth silicon-based substrate is usually thickened as a whole, which is contrary to the trend of miniaturization on the one hand, and on the other hand, it is difficult to dissipate heat and reduces temperature stability. The demand for miniaturization is also driving silicon-based capacitors to develop in the direction of smaller size and lighter weight, which is often contradictory to the goal of improving performance. Therefore, the development of a new type of silicon-based capacitor that can provide higher performance and adapt to increasingly compact equipment space has become an important research direction in this field. Summary of the invention

[0004] In order to meet the performance requirements of silicon-based capacitors with high capacity, fast frequency response, good temperature stability and miniaturization, the present application provides silicon-based capacitors and methods for preparing the same.

[0005] The silicon-based capacitor and the preparation method thereof provided in the present application adopt the following technical scheme: A silicon-based capacitor comprises a silicon-based substrate, a first electrode layer, a dielectric layer, a second electrode layer and a packaging layer, wherein the silicon-based substrate is provided with an oblique groove, the first electrode layer is evenly laid on the silicon-based substrate, the dielectric layer is located between the first electrode layer and the second electrode layer to isolate the first electrode layer and the second electrode layer, the first electrode layer and the second electrode layer have different polarities, and the packaging layer covers all of the first electrode layer, the dielectric layer, the second electrode layer and the silicon-based substrate for packaging.

[0006] Beneficial effects: In this case, an inclined groove is set on the silicon-based substrate, so that the first electrode layer, the dielectric layer, and the second electrode layer laid upward in sequence along the silicon-based substrate are all in an inclined state. The first electrode layer-dielectric layer-second electrode layer constitute a capacitor energy storage unit, and all capacitor energy storage units are inclined and flat, so that in the same space, the first electrode layer and the second electrode layer can bear more charge, so that the same size of energy storage unit can have more charge, that is, have a higher capacitance. In addition, the silicon-based capacitor in this case is flatter in space, and it is easy to stack devices, which is suitable for circuit design solutions with requirements on thickness. In addition, due to the presence of the inclined groove, the contact area between the first electrode layer and the silicon-based substrate is increased, and the overall thickness of the silicon-based capacitor is reduced, so that the path during the heat dissipation of the device becomes shorter, so that the silicon-based capacitor has better heat dissipation performance, better heat dissipation uniformity, and more stable device performance.

[0007] Optionally, the inclination angle of the inclined groove is between 0° and 75°.

[0008] Beneficial effects: The setting of the inclination angle of the inclined groove in the silicon-based substrate is planned by the designer. In order to be suitable for current directional etching processes such as electron beam lithography or semiconductor dry etching, the inclination angle is preferably set between 0° and 75°.

[0009] Optionally, the top of the chute is a flat top.

[0010] Beneficial effects: The top type of the chute is planned by the designer, and the top can be flat, sloping, wavy, etc. To facilitate the deposition of the first electrode layer, the second electrode layer and the dielectric layer using atomic layer deposition technology, the top type of the chute is preferably flat.

[0011] Optionally, the first electrode layer and the second electrode layer are laid out with an interval through the dielectric layer, there are a plurality of the first electrode layers, and there are one or more the second electrode layers.

[0012] Beneficial effect: The silicon-based substrate of the present invention supports multiple first electrode layers and second electrode layers to be laid out with dielectric layers between them to form a stacked structure, which increases the number of capacitor energy storage units composed of "first electrode layer-dielectric layer-second electrode layer" and ensures the high capacity of silicon-based capacitors.

[0013] The present invention also provides a method for preparing a silicon-based capacitor, which is used to prepare the above silicon-based capacitor, and the method comprises: Directionally etching the surface of the silicon wafer according to a specified depth, a specified width, and a specified tilt angle to generate a silicon-based substrate with an array of oblique grooves; Depositing a first electrode layer on the silicon-based substrate; sequentially depositing a dielectric layer and a second electrode layer on the first electrode layer; The first electrode layer and the second electrode layer are sealed by a packaging layer, and the silicon-based substrate, the first electrode layer, the dielectric layer and the second electrode layer are packaged to obtain a silicon-based capacitor.

[0014] Beneficial effects: Silicon wafers are selected as the raw materials for silicon-based substrates, and the silicon wafers are directionally etched according to the specified inclination angle specified by the designer to generate an oblique groove of specified depth and specified width; multiple oblique grooves are etched on the surface of the same silicon wafer, and these oblique grooves constitute an oblique groove array to obtain a silicon-based substrate. Among them, the depth, width, inclination angle, plane shape of the bottom of the oblique groove, and whether the top type of the oblique groove is flat or other types can all be set before etching the silicon wafer and executed in the step of etching the silicon-based wafer, or can be directly read and decomposed from the oblique groove cross-section diagram manually set by the designer. The silicon-based substrate in this case supports various types and shapes of oblique grooves, which should be used to generate silicon-based capacitors with different performances. And the first electrode layer, the dielectric layer, and the second electrode layer constitute the capacitive energy storage unit in the silicon-based capacitor, which ensures the traditional energy supply.

[0015] Optionally, before capping the first electrode layer and the second electrode layer, after sequentially depositing a dielectric layer and a second electrode layer on the first electrode layer, the method further includes: The dielectric layer and the first electrode layer are sequentially deposited on the second electrode layer.

[0016] Beneficial effect: The dielectric layer and the second electrode layer are laid in sequence on the first electrode layer, and the dielectric layer and the first electrode layer are laid in sequence on the second electrode layer, to realize the stacked structure of "first electrode layer-dielectric layer-second electrode layer-dielectric layer-first electrode layer", and the number of capacitor energy storage units composed of "first electrode layer-dielectric layer-second electrode layer" is increased, thereby ensuring the capacity of the silicon-based capacitor manufactured by this method.

[0017] Optionally, after the dielectric layer and the second electrode layer are sequentially deposited on the first electrode layer, the steps are cyclically performed to sequentially deposit the dielectric layer and the first electrode layer on the second electrode layer, and sequentially deposit the dielectric layer and the second electrode layer on the first electrode layer.

[0018] Beneficial effect: Multiple first electrode layers and multiple second electrode layers are laid out with dielectric layers at intervals to form a cyclic stacked structure, which increases the number of capacitor energy storage units composed of "first electrode layer-dielectric layer-second electrode layer" and ensures the high capacity of the manufactured silicon-based capacitor.

[0019] Optionally, the designated depth is 50 μm, the designated width is 200 μm, the first electrode layer and the second electrode layer are Au or Pt layers with a thickness of 20 nm, and the dielectric layer is a HfZrO layer with a thickness of 20 nm.

[0020] Optionally, the designated depth is 8 μm, the designated width is 80 μm, the first electrode layer and the second electrode layer are Ni layers with a thickness of 20 nm, and the dielectric layer is an aluminum oxide layer with a thickness of 25 nm.

[0021] Optionally, the directionally-etched silicon wafer surface is processed by electron beam lithography or semiconductor dry etching; and the packaging layer is a ceramic-based packaging layer or a packaging layer for surface-mounted devices.

[0022] Compared with the prior art, the beneficial effects of this application are: (1) The silicon-based substrate is provided with an inclined groove, so that the first electrode layer, the dielectric layer, and the second electrode layer are laid upward in sequence along the silicon-based substrate, so as to achieve a higher capacity under the same volume capacitor. In addition, due to the inclined setting of the inclined groove, the silicon-based capacitor in this case is flatter and thinner in space, and it is easier to stack devices, which is suitable for thinner circuit design solutions.

[0023] (2) Due to the presence of the oblique groove, the overall thickness of the device is reduced, making the heat dissipation path of the device shorter. The silicon-based capacitor can have better heat dissipation energy, better heat dissipation uniformity, and more stable device performance.

[0024] (3) The first electrode layer and the second electrode layer can be cyclically stacked through the dielectric layer to form silicon-based capacitors of various specifications, thereby ensuring the frequency response speed of the silicon-based capacitors, while meeting the requirements of high capacity and miniaturization while also supporting high-speed frequency response. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a flow chart of a method for manufacturing a silicon-based capacitor in a first embodiment of the present invention; Figure 2 for Figure 1 A schematic diagram of step 101 in FIG. Figure 3 for Figure 1 Another schematic diagram of step 101; Figure 4 for Figure 1 A schematic diagram of a silicon-based substrate in which the designated top of the inclined groove in step 101 is an inclined top; Figure 5 for Figure 1 A first schematic diagram of laying a first electrode layer in step 102; Figure 6 for Figure 1 A second schematic diagram of laying the first electrode layer in step 102; Figure 7 for Figure 1 A first schematic diagram of laying a second electrode layer in step 103; Figure 8 for Figure 1 A second schematic diagram of laying the second electrode layer in step 103; Fig. 9 This is a schematic diagram of a first structure of a silicon-based capacitor in a first embodiment of the present invention; Fig.10 A schematic diagram of a second structure of a silicon-based capacitor in the first embodiment of the present invention; Fig.11 is a flow chart of a method for preparing a silicon-based capacitor in a second embodiment of the present invention; Fig.12 A schematic diagram of the structure of a silicon-based capacitor in a second embodiment of the present invention; Fig.13 A schematic diagram of the structure of a silicon-based capacitor in the third embodiment of the present invention; Fig.14 FIG. 4 is another schematic diagram of the structure of a silicon-based capacitor in the third embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0027] A first embodiment of the present invention provides a silicon-based capacitor and a method for manufacturing the same. Figure 1 As shown, the method for manufacturing a silicon-based capacitor comprises the following steps: Step 101 , directionally etching the surface of a silicon wafer according to a specified depth, a specified width, and a specified tilt angle to generate a silicon-based substrate 11 with an array of oblique grooves.

[0028] Specifically, according to the desired requirements of the silicon-based capacitor, the desired tilt angle θ of the skew groove is set. 期望 , the desired chute depth h 期望 , the desired chute width x 期望 , the top type of the desired chute, combined with the directional etching method selected by the staff, after fine-tuning, the specified depth h, the specified width x, the specified inclination angle θ and the specified top type are obtained. Among them, the inclination angle θ of the desired chute is 期望The inclination angle of the inclined groove planned by the designer when designing the silicon-based capacitor, and the expected depth of the inclined groove h 期望 The depth of the inclined groove planned by the designer when designing the silicon-based capacitor is x. 期望 The width of the inclined slot planned by the designer when designing the silicon-based capacitor. The top type of the desired inclined slot is the top type of the inclined slot specified by the designer when designing the silicon-based capacitor. The top of the inclined slot has a variety of top performance types, such as a horizontal top, a wavy top, and a unidirectional inclined top. The inclination angle of the desired inclined slot is θ 期望 , the desired chute depth h 期望 , the desired chute width x 期望 The difference between the expected values ​​of the specified depth h, the specified width x, the specified tilt angle θ and the specified top type of the desired groove and the specified values ​​of the specified depth h, the specified width x, the specified tilt angle θ and the specified top type is determined by the directional etching process. The directional etching process, for example, uses electron beam lithography or semiconductor dry etching to directional etch the surface of the silicon wafer to generate the tilt groove. The specified tilt angle θ is usually set between 0° and 75°. With the improvement of the process, the specified tilt angle θ can also be set in a wider range.

[0029] In some examples, reference Figure 2 , the implementation of step 101 includes: S1-1, directionally etching a preliminary groove on the surface of the silicon wafer according to a specified depth, a specified width and a specified tilt angle; the preliminary groove only needs to meet the specified width and the specified tilt angle, and there is no requirement for the depth.

[0030] S1-2, deepen the groove in a direction so that the groove completes silicon etching in a specific direction to form a silicon wafer with a nanoscale bevel groove array; the specific direction can be a depth direction or other directions, and the groove of S1-1 is further etched. Taking the specific direction as the depth direction as an example, according to the specified depth, this step is continuously repeated to deepen the groove multiple times so that the groove reaches the specified depth requirement, thereby completing the silicon etching action, and the silicon wafer with the nanoscale bevel groove array serves as a silicon-based substrate 11 with a bevel groove array. Among them, the specified depth can be a fixed value, so that the bottom of the cross section of all the bevel grooves in the bevel groove array is horizontal; the specified depth can also be a data set, so as to realize the shape change of the bottom of the groove in the bevel groove array, such as the bottom of the groove is an inclined surface, a curved surface, a wavy surface, etc.

[0031] In other examples, reference Figure 3 , the implementation of step 101 further includes, after step S1-2, executing step S1-3: The distance d between the nearest point at the bottom of the groove and the silicon wafer is calculated. When the distance d is lower than a preset value, in order to ensure the structural stability of the overall capacitor, the structure between the groove corresponding to d and the surface of the silicon wafer is etched into the silicon wafer plane, and then the silicon wafer is used as a silicon-based substrate 11 with an array of oblique grooves. In this example, the fragile and easily damaged parts of the silicon wafer that has undergone multiple steps S1-2 are etched away, so that the structure of the manufactured silicon-based substrate 11 is more stable and not easily damaged.

[0032] In the first case, refer to Figure 4 , decomposed according to the cross-sectional shape of the chute designed by the user, the specified depth h of the chute is 8μm, the specified width x is 80μm, the specified inclination angle θ of the chute is 60°, the specified top type of the chute is an inclined top, and the shape of the bottom of the chute is horizontal. After this step 101, a silicon-based substrate A is generated.

[0033] In the second case, continue with reference 2 and Figure 3 , decomposed according to the cross-sectional shape of the chute designed by the user, the specified depth h of the chute is 50 μm, the specified width x is 200 μm, the specified inclination angle θ of the chute is 70°, the specified top type of the chute is flat top, and the shape of the bottom of the chute is horizontal. After this step 101, a B silicon-based substrate is generated.

[0034] Step 102 : depositing a first electrode layer 12 on the silicon-based substrate 11 .

[0035] Specifically, the electrode layer is deposited on the inclined groove of the silicon-based substrate 11, preferably using the atomic layer deposition technology in semiconductor deposition technology. The thickness of the deposition is the same as the thickness of the first electrode layer 12 in the plan.

[0036] In the first case, step 102 is implemented by referring to Figure 5 On the above A silicon-based substrate, the base metal electrode nickel is deposited using atomic layer deposition technology to form a Ni layer with a thickness of 20 nm as the first electrode layer 12.

[0037] In the second case, step 102 is implemented as follows: Figure 6 On the silicon-based substrate B above, the noble metal electrode Au or Pt is deposited using atomic layer deposition technology to form an Au or Pt layer with a thickness of 20 nm as the first electrode layer 12.

[0038] Step 103 , depositing a dielectric layer 13 and a second electrode layer 14 in sequence on the first electrode layer 12 .

[0039] Specifically, the dielectric layer 13 is deposited on the first electrode layer 12 using atomic layer deposition technology, and the deposition thickness corresponds to the planned thickness of the dielectric layer 13. The dielectric layer 13 wraps the upper end surface of the first electrode layer 12, so that only the left and right ends of the first electrode layer 12 are exposed; the second electrode layer 14 is deposited on the dielectric layer 13 using atomic layer deposition technology, and the deposition thickness corresponds to the planned thickness of the second electrode layer 14. The second electrode layer 14 wraps the dielectric layer 13, so that the dielectric layer 13 is completely wrapped by the second electrode layer 14 and the first electrode layer 12, or only the left and right ends of the dielectric layer 13 are exposed and the upper end surface is wrapped by the second electrode layer 14.

[0040] In the first case, refer to Figure 7 ,exist Figure 5 On the basis of the first electrode layer 12, aluminum oxide is deposited on the first electrode layer 12 by atomic layer deposition technology with a deposition thickness of 25 nm to form a dielectric layer 13. Base metal electrode nickel is deposited again on the dielectric layer 13 with a deposition thickness of 20 nm to form a second electrode layer 14.

[0041] In the second case, refer to Figure 8 ,exist Figure 6 On the basis of the above, a dielectric layer HfZrO is deposited on the first electrode layer 12 by atomic layer deposition technology with a deposition thickness of 20 nm to form a dielectric layer 13. A noble metal electrode Au or Pu is deposited again on the dielectric layer 13 with a deposition thickness of 20 nm to form a second electrode layer 14.

[0042] Step 104 , capping the first electrode layer 12 and the second electrode layer 14 through the encapsulation layer 15 , encapsulating the silicon-based substrate 11 , the first electrode layer 12 , the dielectric layer 13 , and the second electrode layer 14 , to obtain a silicon-based capacitor.

[0043] Specifically, since the first electrode layer 12 covers the silicon-based substrate 11, the dielectric layer 13 covers the first electrode layer 12, and the second electrode layer 14 covers the dielectric layer 13, the packaging layer 15 only needs to cover the outermost layers of the dielectric layer 13 and the second electrode layer 14. Usually, the second electrode layer 14 is the outermost layer, and the packaging layer 15 covers the second electrode layer 14. For terminal sealing, the packaging layer 15 needs to expose both ends of the first electrode layer 12 and the second electrode layer 14, and wrap the other positions to ensure the normal operation of the first electrode layer 12 and the second electrode layer 14 as different electrodes of the silicon-based capacitor. The packaging layer 15 adopts a ceramic-based packaging layer or a surface-mounted device packaging layer 15, refer to Fig. 9 and Fig.10The successfully constructed silicon-based substrate 11, the first electrode layer 12, the dielectric layer 13, and the second electrode layer 14 are encapsulated by the encapsulation layer 15 to complete the processing of the entire silicon-based capacitor. In order to facilitate the port identification during the sealing, the first electrode layer 12 and the second electrode layer 14 can also be partially misaligned to ensure the positive and negative poles of the silicon-based capacitor can be determined after completion.

[0044] The first embodiment of the present invention also provides a silicon-based capacitor obtained by using the above-mentioned method for manufacturing a silicon-based capacitor. Fig. 9 and Fig.10 shown.

[0045] The silicon-based capacitor comprises a silicon-based substrate 11, a first electrode layer 12, a dielectric layer 13, a second electrode layer 14 and a packaging layer 15. The silicon-based substrate 11 is provided with an oblique groove, the first electrode layer 12 is evenly laid on the silicon-based substrate 11, the dielectric layer 13 is laid on the first electrode layer 12, and the second electrode layer 14 is laid on the dielectric layer 13. The dielectric layer 13 is located between the first electrode layer 12 and the second electrode layer 14 to isolate the first electrode layer 12 and the second electrode layer 14, the first electrode layer 12 and the second electrode layer 14 have different polarities, and the packaging layer 15 covers all the first electrode layer 12, the dielectric layer 13, the second electrode layer 14 and the silicon-based substrate 11 for packaging.

[0046] Among them, the setting of the chute follows Figure 2 and Figure 3 As shown, the chute is set according to the specified depth h, the specified width x, the specified inclination angle θ and the specified top type. The first electrode layer 12 and the second electrode layer 14 are both electrode layers, and the materials may be the same or different, and the thickness may be the same or different; when the first electrode layer 12 is the positive electrode, the second electrode layer 14 is the negative electrode; when the first electrode layer 12 is the negative electrode, the second electrode layer 14 is the positive electrode. The inclination angle of the chute, that is, the specified inclination angle is usually set between 0° and 75° to adapt to the overall manufacturing process. The top lines between different chute are parallel to each other, thereby ensuring the feasibility of mass production. The preferred specified top type of the chute is a flat top (same Figure 2 and Figure 3 as shown).

[0047] The second embodiment of the present invention provides a silicon-based capacitor and a method for manufacturing the same. Fig.11 As shown, the difference between the preparation method of the silicon-based capacitor and the preparation method of the first embodiment is that: After step 103 , step 105 is performed to sequentially deposit the dielectric layer 13 and the first electrode layer 12 on the second electrode layer 14 ; and after step 105 is completed, step 104 is performed to generate a silicon-based capacitor.

[0048] refer to Fig.12As shown, the silicon-based capacitor is composed of "silicon-based substrate 11-first electrode layer 12-dielectric layer 13-second electrode layer 14-dielectric layer 13-first electrode layer 12-packaging layer 15", wherein the layout and structure of the silicon-based substrate 11, the first electrode layer 12, the dielectric layer 13, the second electrode layer 14 and the packaging layer 15 are the same as those of the first embodiment described above. In this embodiment, the adjacent first electrode layers 12 in the silicon-based capacitor form a capacitive energy storage unit through the dielectric layer 13 and the second electrode layer 14. The silicon-based capacitor has two electric energy storage units of "first electrode layer 12-dielectric layer 13-second electrode layer 14" and "second electrode layer 14-dielectric layer 13-first electrode layer 12", realizing higher energy storage of the silicon-based capacitor. It is worth mentioning that although the silicon-based capacitor has two first electrode layers 12, the thickness and material of the two first electrode layers 12 can be the same or different.

[0049] The third embodiment of the present invention provides a silicon-based capacitor and a method for manufacturing the same. Fig.12 and Fig.13 As shown, the difference between the preparation method of the silicon-based capacitor and the preparation method of the second embodiment is: Step 103 and step 105 are executed cyclically, that is, the dielectric layer 13 and the second electrode layer 14 are sequentially laid on the first electrode layer 12, and the dielectric layer 13 and the first electrode layer 12 are sequentially laid on the second electrode layer 14. After the number of cycles reaches the target number, step 104 is executed to obtain Fig.13 and Fig.14 The silicon-based capacitor shown in the figure. In the silicon-based capacitor, the adjacent first electrode layer 12-dielectric layer 13-second electrode layer 14 form a capacitance energy storage unit, that is, the silicon-based capacitor has multiple capacitance energy storage units to achieve higher energy storage.

[0050] refer to Fig.13 As shown, the dielectric layer 13 and the second electrode layer 14 are laid on the first electrode layer 12 in sequence, and the dielectric layer 13 and the first electrode layer 12 are laid on the second electrode layer 14 in sequence in a cycle, and the outermost layer is the first electrode layer 12. Subsequently, the packaging layer 15 is used to package the "silicon-based substrate 11-first electrode layer 12-dielectric layer 13-second electrode layer 14-dielectric layer 13-first electrode layer 12-dielectric layer 13-second electrode layer 14-dielectric layer 13 ...-first electrode layer 12" as a whole.

[0051] refer to Fig.14As shown, the dielectric layer 13 and the second electrode layer 14 are laid on the first electrode layer 12 in sequence, and the dielectric layer 13 and the first electrode layer 12 are laid on the second electrode layer 14 in sequence in a cycle, and the outermost layer is the second electrode layer 14. Subsequently, the packaging layer 15 is used to package the entire "silicon-based substrate 11-first electrode layer 12-dielectric layer 13-second electrode layer 14-dielectric layer 13-first electrode layer 12-dielectric layer 13-second electrode layer 14-dielectric layer 13 ...-second electrode layer 14".

[0052] The steps of the above-mentioned various methods are divided only for the purpose of clear description. When implemented, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent. In the present invention, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. The term "multiple" refers to two or more, unless otherwise clearly defined.

[0053] The above description of the embodiments is to facilitate those of ordinary skill in the art to understand and apply the present application. It is obvious that those familiar with the art can easily make various modifications to these embodiments and apply the general principles described herein to other embodiments without having to pay creative labor. Therefore, the present application is not limited to the embodiments herein, and improvements and modifications made by those skilled in the art based on the contents disclosed in the present application without departing from the scope and spirit of the present application are within the scope of the present application.

Claims

1. Silicon-based capacitor, characterized in that, The invention comprises a silicon-based substrate, a first electrode layer, a dielectric layer, a second electrode layer and a packaging layer, wherein the silicon-based substrate is provided with an oblique groove, the first electrode layer is evenly laid on the silicon-based substrate, the dielectric layer is located between the first electrode layer and the second electrode layer to isolate the first electrode layer and the second electrode layer, the first electrode layer and the second electrode layer have different polarities, and the packaging layer covers all of the first electrode layer, the dielectric layer, the second electrode layer and the silicon-based substrate for packaging.

2. The silicon-based capacitor according to claim 1, characterized in that: The inclination angle of the chute is between 0° and 75°.

3. The silicon-based capacitor according to claim 1, characterized in that: The top of the chute is a flat top.

4. The silicon-based capacitor according to claim 1, characterized in that: The first electrode layer and the second electrode layer are laid out with an interval through the dielectric layer. There are a plurality of the first electrode layers and there are one or more the second electrode layers.

5. A method for preparing a silicon-based capacitor, characterized in that: For preparing the silicon-based capacitor according to claim 1, the method comprises: Directionally etching the surface of the silicon wafer according to a specified depth, a specified width, and a specified tilt angle to generate a silicon-based substrate with an array of oblique grooves; Depositing a first electrode layer on the silicon-based substrate; sequentially depositing a dielectric layer and a second electrode layer on the first electrode layer; The first electrode layer and the second electrode layer are sealed by a packaging layer, and the silicon-based substrate, the first electrode layer, the dielectric layer and the second electrode layer are packaged to obtain a silicon-based capacitor.

6. The method for preparing a silicon-based capacitor according to claim 5, characterized in that: Before capping the first electrode layer and the second electrode layer, after sequentially depositing a dielectric layer and a second electrode layer on the first electrode layer, the method further includes: The dielectric layer and the first electrode layer are sequentially deposited on the second electrode layer.

7. The method for preparing a silicon-based capacitor according to claim 6, characterized in that: After the dielectric layer and the second electrode layer are sequentially deposited on the first electrode layer, the steps are performed cyclically. The dielectric layer and the first electrode layer are sequentially deposited on the second electrode layer, and the dielectric layer and the second electrode layer are sequentially deposited on the first electrode layer.

8. The method for preparing a silicon-based capacitor according to claim 6, characterized in that: The designated depth is 50 μm, the designated width is 200 μm, the first electrode layer and the second electrode layer are Au or Pt layers with a thickness of 20 nm, and the dielectric layer is a HfZrO layer with a thickness of 20 nm.

9. The method for preparing a silicon-based capacitor according to claim 6, characterized in that: The designated depth is 8 μm, the designated width is 80 μm, the first electrode layer and the second electrode layer are Ni layers with a thickness of 20 nm, and the dielectric layer is an aluminum oxide layer with a thickness of 25 nm.

10. The method for preparing a silicon-based capacitor according to claim 6, characterized in that: The directionally etched silicon wafer surface is etched using electron beam lithography or semiconductor dry etching; the packaging layer is a ceramic-based packaging layer or a packaging layer for surface mounted devices.

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