EHSOP9L high-power IC plastic packaging structure and corresponding packaging method

Abstract

The invention discloses an eHSOP9L high-power IC (integrated circuit) plastic packaging structure, which solves the problem in the prior art that the product performance is affected due to the connection between a base island and a pin or the problem of the distance between the base island and the pin in the using process of an IC plastic packaging piece, so that the product is ensured to meet the design requirement. The packaging structure comprises a base island frame, a plurality of groups of plastic packaging bodies and plastic packaging chips corresponding to each group of plastic packaging bodies, the base island frame comprises a frame border and an internal area, the internal area is formed by arranging a plurality of base island arrangement units in an array mode, a carrier is arranged in the center area of each base island arrangement unit, each carrier is provided with at least two sets of chips, the chips comprise at least one IC chip and one MOS chip, the carriers and the chips in the base island arrangement units are subjected to plastic package through a plastic package body, and the chips in the base island arrangement units are subjected to plastic package through the plastic package body. Convex pins are respectively arranged on two sides of one pair of side edges of the base island arrangement unit, at least one connecting rib is respectively arranged on two sides of the other pair of end edges of the base island arrangement unit, and the connecting ribs are used for connecting an external frame area.

Description

Technical Field

[0001] The invention relates to the technical field of microelectronic assembly and packaging, in particular to an eHSOP9L high-power IC plastic packaging structure. The invention also provides a packaging method for the eHSOP9L high-power IC plastic packaging component. Background Art

[0002] After the packaging of integrated circuit devices has evolved from the development of a single component to the integration of multiple components, semiconductor packaging has gradually developed and integrated towards high density, high integration, high frequency and high speed, small area, low cost, multi-chip combination, and active electronic components with different functions, and optional passive device combinations. From the perspective of packaging development, under the consideration of various requirements such as volume, processing speed or electrical characteristics of electronic products, multiple components and chips are arranged and assembled, and a planar 2D packaging structure is adopted, combined with multifunctional devices and other integrated components to form a complete system function, thereby achieving product performance requirements. By following up on the long-term application effects of multi-component packaging products, it is found that products with base island and pin connection or increased spacing between pins in the design structure will affect the thermal and electrical performance of the product in long-term use, reduce the application range of the product, or affect the normal operation of the product, which is fatal to the use of the product and seriously affects product safety. Summary of the invention

[0003] In view of the above problems, the present invention provides an eHSOP9L high-power IC plastic packaging structure, which solves the problem in the prior art that IC plastic packages may affect product performance during use due to connection between the base island and the pins or spacing problems, thereby ensuring that the product meets the design requirements.

[0004] An eHSOP9L high-power IC plastic packaging structure, characterized in that it comprises a base island frame, a plurality of groups of plastic packaging bodies, and a plastic packaging chip corresponding to each group of plastic packaging bodies;

[0005] The base island frame includes a frame frame and an internal area, the internal area is composed of a plurality of base island arrangement units arranged in an array, a carrier is arranged in the central area of ​​the base island arrangement unit, at least two groups of chips are arranged on each carrier, the chips include at least one IC chip and one MOS chip, the carrier and the chip in the base island arrangement unit are sealed by a plastic sealing body, and protruding pins are respectively arranged on both sides of one pair of side edges of the base island arrangement unit, and at least one connecting rib is respectively arranged on both sides of another pair of end edges of the base island arrangement unit, and the connecting rib is used to connect the external frame area;

[0006] All narrow pins are arranged on one side of a pair of side edges, and pins with other widths are arranged on the other side of the pair of side edges, and the distances between all adjacent pins are not completely the same.

[0007] The further feature is that after the plastic encapsulation is completed, the pins are processed after the ribs are cut to form the product;

[0008] The base island frame is arranged with M rows and N columns, with a total of M*N base island arrangement units, where M<N;

[0009] The upper and lower sides of the base island arrangement unit are respectively provided with protruding pins, wherein the pins of one group of sides are all narrow pins, and the pins of the other group of sides are wide pins or relatively wide pins, and there is a spacing between adjacently arranged pins;

[0010] The left and right sides of the base island arrangement unit are respectively provided with connecting ribs, and the number of the protruding connecting ribs on the left and right sides is the same, both one or two, and there is a spacing between the adjacently arranged connecting ribs;

[0011] The plastic package body corresponding to the packaged product is provided with a plastic package body ejector hole, and a marking hole is opened on the plastic package body;

[0012] The upper and lower sides of the base island arrangement unit are respectively provided with pins, 6 narrow pins of the same width are distributed on the lower side, 1 wider pin and 2 wide pins are arranged on the upper side, all the pins form an SMT shape, the plastic package body corresponding to the packaged product and the pins form a certain SMT shape, and the exposed part of the base island on the back of the plastic package body is connected to the pins and connected to the ribs of the frame at the same time;

[0013] The upper and lower sides of the base island arrangement unit are respectively provided with pins, 7 narrow pins of the same width are distributed on the lower side, 1 wider pin and 2 wide pins are arranged on the upper side, all the pins form an SMT shape, the plastic package body corresponding to the packaged product and the pins form a certain SMT shape, and the exposed part of the base island on the back of the plastic package body is connected to the pins and connected to the ribs of the frame at the same time;

[0014] Preferably, the chip includes two groups of chips, namely, an IC chip and a MOS chip;

[0015] The IC chip and the MOS chip are installed together in the carrier surface area, the IC chip is stacked on the MOS chip, the IC chip pads are connected to the MOS chip and the corresponding pins through welding wires, and the MOS chip pads are connected to the pins through welding wires;

[0016] The IC chip and the MOS chip are installed together on a carrier, the MOS chip and the IC chip are respectively bonded to the carrier, the IC chip pads are respectively connected to the MOS chip, the pins and the carrier through welding wires, and the MOS chip pads are connected to the pins and the IC chip through welding wires.

[0017] A packaging method for an eHSOP9L high-power IC plastic package, characterized in that it comprises the following steps:

[0018] Step 1, thinning the wafer and then dicing it to form corresponding chips;

[0019] Step 2, the chip is attached to the carrier in the central area of ​​the base island arrangement unit by using die-attachment spraying technology, and the chip is baked and cured;

[0020] Step 3, bonding the wires by bonding low arc control technology;

[0021] Step 4, plastic-sealing the base island arrangement unit to form a whole plastic-sealed product;

[0022] Step 5: Use an automatic electroplating line to tin the lead frame of the package and then perform welding.

[0023] After adopting the above technical scheme, the base island frame is provided with a base island arrangement unit, a carrier is provided on each base island unit, an IC chip and a MOS chip are provided on the carrier, the IC chip and the MOS chip are connected correspondingly through welding wires, the narrow pins are arranged on one side, and the pins of the remaining width are arranged on the other side. The pin arrangement is reasonable and reliable, which solves the problem of transmitting data and electric energy between high-voltage and low-voltage circuits, and meets the market demand for high electrical performance, high reliability, high heat dissipation power management, high voltage resistance, and high safety products. The internal area of ​​the base island frame is composed of a plurality of base island arrangement unit arrays, which can greatly improve material utilization and production efficiency, ensure that the plastic package reaches a high reliability of MSL3 or above, and reduce production costs and packaging and transportation costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A top view of the base island frame corresponding to the present invention;

[0025] Figure 2 A top view of the structure corresponding to the present invention;

[0026] Figure 3 A top view of the packaging structure of the first specific embodiment of the present invention;

[0027] Figure 4 A top view of a packaging structure of a second specific embodiment of the present invention;

[0028] Figure 5 It is a front view of the product structure corresponding to the specific embodiments 1 and 2 of the present invention;

[0029] Figure 6 It is a side view of the product structure corresponding to the specific embodiments 1 and 2 of the present invention;

[0030] Figure 7 It is a top view of the product structure corresponding to the specific embodiments 1 and 2 of the present invention;

[0031] Figure 8 It is a bottom view of the product structure corresponding to the specific embodiments 1 and 2 of the present invention;

[0032] Fig. 9 A top view of a packaging structure according to a third specific embodiment of the present invention;

[0033] Fig.10 It is a front view of the product structure corresponding to the specific embodiment 3 of the present invention;

[0034] Fig.11 It is a side view of the product structure corresponding to the specific embodiment 3 of the present invention;

[0035] Fig.12 It is a top view of the product structure corresponding to the specific embodiment 3 of the present invention;

[0036] Fig.13 It is a bottom view of the product structure corresponding to the specific embodiment 3 of the present invention;

[0037] The names corresponding to the serial numbers in the figure are as follows:

[0038] The base island frame 10, the plastic sealing body 20, the plastic sealing body top rod hole 21, the marking hole 22, the frame frame 30, and the base island arrangement unit 40;

[0039] Carrier 1, connecting rib 2, narrow pin 3, wider pin 4, wide pin 5, IC chip 6, MOS chip 7, base island half-etched groove 8, base island back side locking step 9. DETAILED DESCRIPTION

[0040] An eHSOP9L high-power IC plastic package structure, see Figure 1-Figure 4 , Fig. 9 : It includes a base island frame 10, a plurality of groups of plastic packaging bodies 20, and a plastic packaging chip corresponding to each group of plastic packaging bodies 20;

[0041] The base island frame 10 includes a frame frame 30 and an internal area, the internal area is composed of a plurality of base island arrangement units 40 arranged in an array, a carrier 1 is arranged in the central area of ​​the base island arrangement unit 40, at least two groups of chips are arranged on each carrier 1, and the chips include at least one IC chip and one MOS chip, the carrier 1 and the chip in the base island arrangement unit 40 are plastic-sealed by a plastic package 20, and protruding pins are respectively arranged on both sides of one pair of side edges of the base island arrangement unit 40, and at least one connecting rib 2 is respectively arranged on both sides of the other pair of end edges of the base island arrangement unit 40, and the connecting rib 2 is used to connect the external frame area;

[0042] The pins include narrow pins and other wide pins. All narrow pins 3 are arranged on one side of a pair of sides, and the other wide pins are arranged on the other side of the pair of sides. The distances between all adjacent pins are not exactly the same.

[0043] After the plastic encapsulation is completed, the ribs are cut and the pins are processed to form the corresponding product.

[0044] In specific implementation, the inner area of ​​each base island frame 10 is arranged with 6 rows and 20 columns, with a total of 120 base island arrangement units 40, and the size of the base island frame 10 is length×width: 249×79.5 mm.

[0045] Specific embodiments 1 and 2, the product structure Figure 5-8 Pins are respectively arranged on the upper and lower sides of the plastic package body 20. Six narrow pins 3 of the same width are distributed on the lower side of the plastic package body 20, and one wider pin 4 and two wide pins 5 are arranged on the upper side. All the pins form an SMT shape. The plastic package body 20 corresponding to the product and the pins form a certain SMT shape. The exposed part of the base island on the back side of the plastic package body 20 is connected to the pins and to the connecting ribs of the frame. A plastic package body top rod hole 21 is arranged on the plastic package body 20, and a marking hole 22 is opened on the plastic package body 20.

[0046] Specific embodiment 1, see Figure 3 : The chip includes two groups of chips, an IC chip 6 and a MOS chip 7;

[0047] IC chip 6 and MOS chip 7 are installed together in the surface area of ​​carrier 1, IC chip 6 is superimposed on MOS chip 7, and the pads of IC chip 6 are connected to MOS chip and corresponding pins through welding wires respectively, and the pads of MOS chip 6 are connected to corresponding pins through welding wires.

[0048] Specific embodiment 2, see Figure 4 The chip includes two IC chips 6 and a MOS chip 7, which are mounted together on the upper surface of a carrier 1. The upper surface of the carrier 1 is also provided with corresponding base island half-etched grooves 8, and the chips are connected to each other and to corresponding pins through lead wires.

[0049] Specific embodiment three, its product structure Figure 10-13 Pins are respectively arranged on the upper and lower sides of the plastic package body 20. Seven narrow pins 3 of the same width are distributed on the lower side of the plastic package body 20, and one wider pin 4 and two wide pins 5 are arranged on the upper side. All the pins form an SMT shape. The plastic package body 20 corresponding to the product and the pins form a certain SMT shape. The exposed part of the base island on the back side of the plastic package body 20 is connected to the pins and to the connecting ribs of the frame.

[0050] Specific embodiment three: A base island back locking step 9 is provided at the bottom of the carrier 1, and two groups of connecting ribs are provided on the left and right sides of the carrier respectively. Six narrow pins of the same width are distributed at the bottom of the base island arrangement unit, and one wider pin and two wide pins are arranged at the top of the base island arrangement unit.

[0051] A packaging method for an eHSOP9L high-power IC plastic package, characterized in that it comprises the following steps:

[0052] Step 1, thinning the wafer and then dicing it to form corresponding chips;

[0053] Thinning: Use a thinning machine to thin the wafer to a final thickness of 100μm to 200μm, with the rough grinding speed controlled at ≤35μm / min; the precision speed controlled at ≤10μm / min;

[0054] Slicing: Use a dicing machine to scribing, use double dicing knives to scribing, avoid chip chipping, and control the dicing feed speed to ≤10mm / s, and clean and dry in time;

[0055] Step 2, the chip is attached to the carrier in the central area of ​​the base island arrangement unit by using die-attachment spraying technology, and the chip is baked and cured;

[0056] The integrated chip-on-chip bonding machine with a multifunctional bonding head uses the chip-on-chip bonding spraying technology and the one-time bonding technology for multiple chips. The chip-on-chip bonding machine bonds the chip to the carrier. The bonding material is an environmentally friendly conductive glue (insulating glue) or DAF film (CDAF film). The anti-layering and segmented baking process is adopted. The transformer uses a special chip-on-chip machine to bond the chip to a fixed carrier or a corresponding chip, and then bakes it again to form a solidified chip.

[0057] Step 3, bonding the wires by bonding low arc control technology;

[0058] Use gold wire or palladium copper wire as bonding wire, and implement bonding low arc control technology by pressure welding, using a combination of flat arc and positive and reverse arc, as well as advanced wire arc shapes with sharp corners and advanced wire arc shapes with flat corners, to control the arc height ≤180μm;

[0059] Step 4, plastic-sealing the base island arrangement unit to form a whole plastic-sealed product;

[0060] The CEL-1702HF9TS-G1 series of environmentally friendly plastic packaging materials with high reliability and high temperature and high pressure resistance are selected to use a fully automatic plastic packaging machine to encapsulate the chip, welding wire and base island structure frame in the plastic packaging body package to complete the product plastic packaging; the process adopts a thin anti-warping and reduction and elimination of delamination process to reduce the punching rate to less than 8%, reduce the reverse or back packaging, and the curing time is reduced by 10S to 30S compared to normal; during post-curing, the semi-finished material strips of the IC package frame are aged in an oven at 175℃ for 7.0 hours;

[0061] Step 5, using an automatic electroplating line to tin the lead frame of the package and perform welding;

[0062] The multi-row matrix copper alloy electroplated lead frame of the package is tinned using an automatic electroplating line, so that the surface of the outer pins is plated with 11.43±3.81μm solder, which is convenient for SMT (surface mounting technology) welding.

[0063] When implemented specifically, it may also include the following steps:

[0064] Step 6, printing, using a clamp-type fixation, dual laser heads, and continuous feeding positioning printing method to print the trademark on the surface of the plastic package.

[0065] Step 7, rib cutting and forming are separated. A special rib cutting system and mold are used to cut the middle rib connecting rod connected to the frame. The gap between the rib cutting tool and the plastic package body is greater than 0.05mm to ensure that the plastic package body is not punched and cut. At the same time, the plastic package residue on the mold surface is cleaned to reduce the damage to the colloid.

[0066] The punching separation method is adopted, and the distance between the punching blade and the plastic package body is controlled at 0.05mm. The plastic package body is fixed and compacted up and down, and the punching separation is carried out. The residual glue fragments in the mold are cleaned in time to form a package of a certain shape;

[0067] Step 8, testing and packaging, using a dedicated testing machine and sorting machine to test the appearance and functional parameters of the electromagnetic package to ensure that the product provided to the customer can be used on the machine and meet the use requirements of the package;

[0068] After that, receive the product → taping the product according to the packaging quantity → add foam strips and protective tape according to the specification → the operator checks the warehouse entry form and labels → checks the small traceability label and affixes the reel label → sets vacuum packaging parameters → puts into the packaging box → affixes labels and list quantities according to the specification → checks whether the relevant accessories are complete → packing and warehouse.

[0069] In addition, the present invention also provides a method for producing an EHSOP8L package using the above-mentioned base island frame, which comprises the following steps:

[0070] a. Thin and slice the wafer according to the SOP packaging production process to form individual chips;

[0071] b. Paste the cut chips onto the respective carriers of the base island isolation frame;

[0072] c. Baking. During baking, seven different oxygen-containing zones are used to quickly cure the frame to prevent oxidation. The detailed process of the fast curing and anti-oxidation baking process is as follows: the seven oxygen content zones are arranged up and down, and the frame is transferred to the first oxidation zone after the core is loaded. After the initial curing in the first oxidation zone, it is transferred to the second oxidation zone and so on, until the adhesive material of the out-of-box product has been fully cross-linked. The oxygen content of each curing zone adopts a gradual amount difference, and the oxygen content from the first oxygen content zone to the seventh oxygen content zone is 20000ppm, 18000ppm, 15000ppm, 12000ppm, 6000ppm, 3000ppm, and 1500ppm respectively;

[0073] d. Plasma cleaning after baking;

[0074] e. Press welding: the interconnection between chips adopts right-angle arc multi-layer wire welding. The detailed process is: first plant the ball at the second welding point, then weld the wire from the first welding point, then pull the wire arc at a right angle, then draw the arc horizontally along the direction of the second welding point, and finally bond vertically downward with the solder ball of the second welding point; other wires are press welded according to the existing SOP packaging production process; after press welding, plasma cleaning is performed before plastic sealing to improve silver surface contamination;

[0075] f. Use high-precision automatic encapsulation system and plastic sealing. The process parameters for plastic sealing are: injection pressure 1000-1300Psi, injection time 8-14s, mold temperature 170-180℃, mold clamping pressure 110-130ton, and curing time 100-120s;

[0076] g. After the plastic sealing is completed, post-curing is performed at a temperature of 175°C for 7.0 hours;

[0077] h. Then use heat to soften and remove the overflow, and then tinnize;

[0078] i. Use the entire frame for testing and printing;

[0079] j. One-step molding and cutting to obtain plastic eHSOP package

[0080] Its working principle is as follows: the base island frame is provided with a base island arrangement unit, a carrier is provided on each base island unit, an IC chip and a MOS chip are provided on the carrier, the IC chip and the MOS chip are connected correspondingly through welding wires, and the narrow pins are arranged on one side, and the pins of the remaining width are arranged on the other side. The pin arrangement is reasonable and reliable, which solves the problem of transmitting data and electric energy between high-voltage and low-voltage circuits, and meets the market demand for high electrical performance, high reliability, high heat dissipation power management, high voltage resistance and high safety products. The internal area of ​​the base island frame is composed of a plurality of base island arrangement unit arrays, which can greatly improve material utilization and production efficiency, ensure that the plastic package reaches a high reliability of MSL2 or above, and reduce production costs and packaging and transportation costs.

[0081] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0082] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. An eHSOP9L high-power IC plastic packaging structure, comprising a base island frame, a plurality of groups of plastic packaging bodies, and a plastic packaging chip corresponding to each group of plastic packaging bodies; The base island frame includes a frame frame and an internal area, the internal area is composed of a plurality of base island arrangement units arranged in an array, a carrier is arranged in the central area of ​​the base island arrangement unit, at least two groups of chips are arranged on each carrier, the chips include at least one IC chip and one MOS chip, the carrier and the chip in the base island arrangement unit are sealed by a plastic sealing body, and protruding pins are respectively arranged on both sides of one pair of side edges of the base island arrangement unit, and at least one connecting rib is respectively arranged on both sides of another pair of end edges of the base island arrangement unit, and the connecting rib is used to connect the external frame area; All narrow pins are arranged on one side of a pair of side edges, and pins with other widths are arranged on the other side of the pair of side edges, and the distances between all adjacent pins are not completely the same.

2. The eHSOP9L high-power IC plastic packaging structure according to claim 1, characterized in that: After the plastic encapsulation is completed, the ribs are cut and the pins are processed to form the product.

3. The eHSOP9L high-power IC plastic packaging structure according to claim 1, characterized in that: The base island frame is arranged with M rows and N columns, with a total of M*N base island arrangement units, where M<N.

4. The eHSOP9L high-power IC plastic packaging structure according to claim 1, characterized in that: The upper and lower sides of the base island arrangement unit are respectively provided with protruding pins, wherein the pins of one group of sides are all narrow pins, and the pins of the other group of sides are wide pins or relatively wide pins, and there is a spacing between adjacently arranged pins.

5. The eHSOP9L high-power IC plastic packaging structure according to claim 4, characterized in that: Connecting ribs are arranged on the left and right sides of the base island arrangement unit, respectively. The number of the protruding connecting ribs on the left and right sides is the same, both one or two, and a spacing is left between adjacently arranged connecting ribs.

6. The eHSOP9L high-power IC plastic packaging structure according to claim 2, characterized in that: The plastic sealing body corresponding to the product is provided with a plastic sealing body top rod hole, and a marking hole is opened on the plastic sealing body.

7. The eHSOP9L high-power IC plastic packaging structure according to claim 1, characterized in that: Pins are respectively arranged on the upper and lower sides of the base island arrangement unit, with 6 narrow pins of the same width distributed on the lower side, and 1 wider pin and 2 wide pins distributed on the upper side. All the pins form an SMT shape, and the plastic package body corresponding to the packaged product forms a certain SMT shape with the pins, and the exposed part of the base island on the back side of the plastic package body is connected to the pins and at the same time connected to the connecting ribs of the frame.

8. The eHSOP9L high-power IC plastic packaging structure according to claim 1, characterized in that: Pins are respectively arranged on the upper and lower sides of the base island arrangement unit, with 7 narrow pins of the same width distributed on the lower side, and 1 wider pin and 2 wide pins distributed on the upper side. All the pins form an SMT shape, and the plastic package body corresponding to the packaged product forms a certain SMT shape with the pins, and the exposed part of the base island on the back side of the plastic package body is connected to the pins and at the same time connected to the connecting ribs of the frame.

9. The eHSOP9L high-power IC plastic packaging structure according to claim 1, characterized in that: The chips include two groups of chips, an IC chip and a MOS chip; The IC chip and the MOS chip are installed together in the carrier surface area, the IC chip is stacked on the MOS chip, the IC chip pads are connected to the MOS chip and the corresponding pins through welding wires, and the MOS chip pads are connected to the pins through welding wires; or The IC chip and the MOS chip are installed together on a carrier, the MOS chip and the IC chip are respectively bonded to the carrier, the IC chip pads are respectively connected to the MOS chip, the pins and the carrier through welding wires, and the MOS chip pads are connected to the pins and the IC chip through welding wires.

10. A packaging method using an eHSOP9L high-power IC plastic packaging structure as claimed in any one of claims 1 to 9, characterized in that: It includes the following steps: Step 1, thinning the wafer and then dicing it to form corresponding chips; Step 2, the chip is attached to the carrier in the central area of ​​the base island arrangement unit by using die-attachment spraying technology, and the chip is baked and cured; Step 3, bonding the wires by bonding low arc control technology; Step 4, plastic-sealing the base island arrangement unit to form a whole plastic-sealed product; Step 5: Use an automatic electroplating line to tin the lead frame of the package and then perform welding.

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