Packaging substrate and chip packaging structure
By designing the pad arrangement method of the first and second regions in the packaging substrate, the connection demand of the inner metal layer is reduced, the problem of large thickness of the packaging substrate in the prior art is solved, and the thinner design of the chip packaging structure is realized.
Patent Information
- Application Number
- CN202311127981.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-01
- Publication Date
- 2025-03-04
AI Technical Summary
In the existing chip packaging structure, the number of metal layers in the packaging substrate is large, resulting in a large thickness of the chip packaging structure, making it difficult to achieve a lightweight design of the equipment.
A packaging substrate is designed, including a first area and a second area. The pads of the first area are arranged in a first pitch array. The pads of the second area are larger than the first pitch and are connected to the corresponding surface conductors, reducing the connection demand of the inner metal layer and reducing the number of metal layers.
By reducing the number of metal layers, the thickness and production cost of the packaging substrate are reduced, and the thinner design of the chip packaging structure is realized.
Smart Images
Figure CN119560474A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip packaging technology, and more specifically, to a packaging substrate and a chip packaging structure. Background Art
[0002] With the continuous development of science and technology, more and more electronic devices are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable and important tool for people today.
[0003] The core component of electronic devices to achieve various functions is the chip. In order to protect the chip and facilitate the connection between the chip and the external circuit, the chip needs to be packaged and protected by a packaging substrate. The packaging substrate includes multiple metal layers stacked in sequence, with an insulating layer between adjacent metal layers. In the prior art, the number of metal layers in the packaging substrate is large, resulting in a large thickness of the chip packaging structure, which is not convenient for the lightweight design of the device. Summary of the invention
[0004] In view of this, the present application provides a packaging substrate and a chip packaging structure, and the scheme is as follows:
[0005] On one hand, the present application provides a packaging substrate, the packaging substrate having a first area and a second area surrounding the first area;
[0006] The packaging substrate comprises:
[0007] The first metal layer to the Nth metal layer are stacked in sequence, where N is a positive integer greater than 1; an insulating layer is provided between two adjacent metal layers; the first metal layer includes a plurality of pads and a plurality of surface conductors;
[0008] Both the first area and the second area have a plurality of the pads; in the first area, the pads are arranged in an array with a first spacing; in the second area, the spacing between at least two adjacent pads is greater than the first spacing, so that the pads in the second area are all connected to the corresponding surface conductors.
[0009] Preferably, in the above-mentioned packaging substrate, two adjacent pads with a spacing greater than the first spacing are both target pads;
[0010] In a second region at the same side of the first region, a spacing between target pads close to the first region is smaller than a spacing between target pads far from the first region.
[0011] Preferably, in the above-mentioned packaging substrate, in the second region located on the same side of the first region, in the direction from the first region to the second region, there are solder pads from the first row to the nth row arranged in sequence, where n is a positive integer greater than 1;
[0012] The target pads are arranged in the 2nd row of pads to the nth row of pads, and the difference between the target pad spacings in two adjacent rows of pads is the first spacing.
[0013] Preferably, in the above-mentioned packaging substrate, in the second region located on the same side of the first region, in the direction from the first region to the second region, there are solder pads from the first row to the nth row arranged in sequence, where n is a positive integer greater than 1;
[0014] The target pads are arranged in the 2nd row of pads to the nth row of pads, and the ratio of the distances between the target pads in two adjacent rows of pads is m, where m is a positive integer greater than 1.
[0015] Preferably, in the above-mentioned packaging substrate, in the first row of pads in the second region, the distance between any two adjacent pads is the first distance.
[0016] Preferably, in the above-mentioned packaging substrate, the second region located on the same side of the first region includes: a plurality of sub-regions arranged in sequence around the opposite edges of the first region;
[0017] In the same sub-area, the distance between any two adjacent pads in the jth row of pads is m. j-1 times the first spacing, j is a positive integer not greater than n, and m is a positive integer greater than 1.
[0018] Preferably, in the above-mentioned packaging substrate, in the second region located on the same side as the first region, in the arrangement direction of the plurality of sub-regions, a spacing between two adjacent sub-regions is an integer multiple of the first spacing.
[0019] Preferably, in the above-mentioned packaging substrate, in the same sub-region, the surface conductive line connected to the pad is located in a gap between pads in the sub-region.
[0020] Preferably, in the above-mentioned packaging substrate, for the pads in the first area, the pads are connected to the inner layer wires in the ath metal layer through conductive holes; the inner layer wires extend from the position connected to the conductive holes in the ath metal layer to the second area; a is a positive integer greater than 1 and less than N.
[0021] On the other hand, the present application also provides a chip packaging structure, including:
[0022] The packaging substrate as described in any one of the above items;
[0023] The chip is soldered and fixed on the surface of the first metal layer of the packaging substrate, and the chip bumps are connected to the pads on the packaging substrate in a one-to-one correspondence.
[0024] It can be known from the above description that in the packaging substrate and chip packaging structure provided by the technical solution of the present application, the packaging substrate has a 1st metal layer to an Nth metal layer stacked in sequence, and the 1st metal layer includes a plurality of pads and a plurality of surface conductors. The 1st metal layer is provided with a plurality of pads in both the first region and the second region. In the first region, the pads are arranged in an array with a first spacing, and in the second region, the spacing between at least two adjacent pads is greater than the first spacing, so that the pads in the second region are all connected to the corresponding surface conductors. Therefore, the pads in the second region do not need to be connected to the inner metal layer, which reduces the number of metal layers in the packaging substrate, thereby reducing the thickness of the packaging substrate, and facilitating the thin and light design of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.
[0026] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.
[0027] Figure 1 A schematic diagram of a pad layout method on the first metal surface of a packaging substrate;
[0028] Figure 2 for Figure 1 A schematic diagram of the wiring method of the first metal layer in the package substrate shown;
[0029] Figure 3 A cross-sectional view of a packaging substrate provided in an embodiment of the present application;
[0030] Figure 4 A top view of a first metal layer in a packaging substrate provided in an embodiment of the present application;
[0031] Figure 5 A top view of a first metal layer in another packaging substrate provided in an embodiment of the present application;
[0032] Figure 6 A schematic diagram of a pad layout in a first metal layer of a packaging substrate provided in an embodiment of the present application;
[0033] Figure 7 A schematic diagram of another layout of pads in the first metal layer of a packaging substrate provided in an embodiment of the present application;
[0034] Figure 8 A schematic diagram of a layout of pads in the first metal layer of another packaging substrate provided in an embodiment of the present application;
[0035] Fig. 9 A schematic diagram of a chip packaging structure provided in an embodiment of the present application. DETAILED DESCRIPTION
[0036] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.
[0037] In conventional chip packaging structures, the packaging substrate used is Figure 1 and Figure 2 As shown, Figure 1 This is a schematic diagram of the pad layout of the first metal surface in a packaging substrate. Figure 2 for Figure 1 A schematic diagram of the wiring method of the first metal layer in the package substrate is shown.
[0038] In conventional packaging substrates, such as Figure 1 and Figure 2 As shown, the package substrate has multiple metal layers stacked in sequence, and there is an insulating layer between adjacent metal layers. The first metal layer 11 is used to weld and fix the chip to be packaged. The first metal layer 11 has a plurality of pads 12 arranged in an array, and the pads 12 are used to weld and fix the chip bumps on the back of the chip to be packaged. In order to obtain a smaller package size, the chip bumps on the back of the chip to be packaged are generally arranged in an array with a pitch of 0.4mm.
[0039] Correspondingly, the pads 12 in the first metal layer 11 are also arranged in an array with a spacing of 0.4 mm, that is, the center distance between any two adjacent pads 12 is 0.4 mm. Since the spacing between adjacent pads 12 is small, in the first metal layer 11, only the pads 12 in the first circle (outermost circle) can be connected to the outside of the array area through the external wiring 13 in the first metal layer 11. The other pads 12 need to be connected to the internal metal layer through conductive holes, and extend to the periphery of the array area through the internal wiring 14 in the internal metal layer. For example, the pads 12 in the second circle need to be connected through the internal wiring 14 in the second metal layer, and the pads 12 in the third circle need to be connected through the internal wiring 14 in the third metal layer.
[0040] This method requires more metal layers to be used for setting the internal wiring 14, resulting in a large number of stacked metal layers in the packaging substrate, which not only increases the product thickness but also greatly increases the production cost.
[0041] In order to solve the above problems, the embodiments of the present application provide a packaging substrate and a chip packaging structure, wherein the packaging substrate has a first area and a second area surrounding the first area;
[0042] The package substrate includes:
[0043] The first metal layer to the Nth metal layer are stacked in sequence, where N is a positive integer greater than 1; an insulating layer is provided between two adjacent metal layers; the first metal layer includes a plurality of pads and a plurality of surface conductors;
[0044] Both the first area and the second area have multiple pads; in the first area, the pads are arranged in an array with a first spacing; in the second area, the spacing between at least two adjacent pads is greater than the first spacing, so that the pads in the second area are all connected to corresponding surface wires.
[0045] In the embodiment of the present application, in the second area surrounding the first area, the spacing between at least two adjacent pads is greater than the first spacing, which creatively breaks the conventional arrangement of the same spacing between adjacent pads, so that the pads in the second area are all connected to the corresponding surface wires, reducing the number of metal layers, reducing the thickness of the packaging substrate and the manufacturing cost.
[0046] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.
[0047] refer to Figure 3 and Figure 4 As shown, Figure 3 A cross-sectional view of a packaging substrate provided in an embodiment of the present application, Figure 4This is a top view of a first metal layer in a packaging substrate provided in an embodiment of the present application. The packaging substrate has a first area 201 and a second area 202 surrounding the first area 201 .
[0048] The package substrate includes: a first metal layer L stacked in sequence 1 To the Nth metal layer L N , N is a positive integer greater than 1. The package substrate has N metal layers L, and the N metal layers L are sequentially the first metal layer L in the stacking direction. 1 To the Nth metal layer L N The value of N can be set based on demand, and the embodiment of the present application does not limit the value of N.
[0049] There is an insulating layer 21 between two adjacent metal layers L; the first metal layer L 1 It includes a plurality of pads 22 and a plurality of surface conductors 23; the first area 201 and the second area 202 both have a plurality of pads 22; in the first area 201, the pads 22 are arranged in an array with a first spacing D1; in the second area 202, the spacing between at least two adjacent pads 22 is greater than the first spacing D1, so that the pads 22 in the second area 202 are all connected to the corresponding surface conductors 23, reducing the number of metal layers L, and reducing the thickness of the packaging substrate and the manufacturing cost.
[0050] In the drawings of the embodiments of the present application, the top view of the package substrate is a rectangle as an example for illustration. 1 The top view only shows the first metal layer L 1 The local area of the pad array. Figure 4 As an example, only the local area in the upper left corner of the pad array is shown. Figure 4 The dotted line S is used to indicate the boundary between the first region 201 and the second region 202. As is known, in actual products, the first metal layer L 1 The visible boundary is marked in the figure, or the boundary can be not set.
[0051] In some implementations of the embodiments of the present application, in the direction from the first area 201 to the second area 202, the second area 202 located on the same side of the first area 201 has at least two rows of pads 22. Based on the pad spacing greater than the first spacing D1, the pads in the second area 202 can all be connected based on the surface conductors 23, thereby reducing the number of metal layers L.
[0052] For the pad 22 in the first region 201, the pad is connected to the ath metal layer L through a conductive hole. a The inner conductor 24 is connected to the conductive hole at the a metal layer L aExtending toward the second region 202; a is a positive integer greater than 1 and less than N.
[0053] The pads 22 in the first region 201 may be connected to the inner-layer wires 24 in the same metal layer L through conductive vias, or may be connected to the inner-layer wires 24 in different metal layers L through conductive vias.
[0054] Since the pads 22 in the first area 201 are arranged in an array with a first spacing D, the pad array in the first area 201 can be divided into a plurality of pad groups nested in sequence from outside to inside of the first area 201, and the plurality of pads 22 in the same pad group are evenly distributed on the four sides of the same rectangle, and the rectangles where the pad groups are located are nested in sequence. The inner layer wires 24 connected to the plurality of pads 22 in the same pad group are located in the same metal layer L, so as to facilitate the wiring of the inner layer wires 24.
[0055] The inner layer wires 24 connected to the pads in different pad groups can be arranged to be located in different metal layers L, respectively, so as to facilitate the layout of the inner layer wires 24 connected to the pads 22 in the first area 201. Obviously, the inner layer wires 24 connected to the pads in a plurality of pad groups distributed continuously can also be arranged to be connected to the same metal layer L, and the pads 22 in the first area 201 can be connected to at least two different metal layers L.
[0056] For the pads 22 located in the second region 202, all are based on the first metal layer L 1 Therefore, in the stacking direction of the metal layer L, the a-th metal layer L a The inner conductor 24 in the second region 202 can be routed from below the pad 22 and the outer conductor 23 connected thereto in the second region 202. Therefore, for any metal layer L having an inner conductor 24, a , wiring can be performed in the second area 202 based on demand, with more sufficient wiring space, which is convenient for the a metal layer L a The wiring of the inner layer conductors 24.
[0057] It is set that two adjacent pads with a spacing greater than the first spacing D1 are both target pads; in the second area 202 on the same side of the first area 201, the spacing between the target pads close to the first area 201 is smaller than the spacing between the target pads far from the first area 201. In this way, in the second area 202 on the same side of the first area 201, the spacing between the target pads gradually increases in the direction from the first area 201 to the second area 202, so that the pads 22 in the second area 202 are all wired out through the surface conductors 23.
[0058] In some implementations of the embodiments of the present application, in the second area 202 located on the same side of the first area 201, in the direction from the first area 201 to the second area 202, there are sequentially arranged pads from the 1st row to the nth row, where n is a positive integer greater than 1; target pads are provided in the 2nd row to the nth row, and the difference between the distances between the target pads in two adjacent rows of pads is the first distance D1, that is, the difference between the distance between the two adjacent target pads in the i-th row of pads and the distance between the two adjacent target pads in the i+1th row of pads is the first distance, where i is a positive integer greater than 1 and less than n. In this manner, for the second area 202 located on the same side of the first area 201, the distance between the target pads in the 2nd row to the nth row of pads increases in steps of D1, and the distance between the target pads in the same row of pads remains fixed.
[0059] exist Figure 4 In the illustrated manner, n=3 is used as an example for illustration, and the second area 202 located on the upper side or the lower side of the first area 201 has 3 rows of pads 22. In the direction from the first area 201 to the second area 202, the spacing between two adjacent pads 22 in the first row of pads is D1, the second row of pads is provided with a target pad, and the spacing between two adjacent target pads is 2*D1, and the third row of pads is provided with a target pad, and the spacing between two adjacent target pads is 3*D1.
[0060] refer to Figure 5 As shown, Figure 5 A top view of a first metal layer in another packaging substrate provided in an embodiment of the present application, and Figure 4 The difference between the methods shown is that Figure 5 In the illustrated manner, in the second area 202 located on the same side of the first area 201, in the direction from the first area 201 to the second area 202, there are pads arranged in sequence from the 1st row to the nth row, where n is a positive integer greater than 1. Target pads are set in the pads in the 2nd row to the nth row, and the ratio of the distance between the target pads in two adjacent rows is m. The distance between two adjacent target pads in the jth row is m. j-1 times the first spacing D1, j is a positive integer greater than 1 and not greater than n. In this manner, for the second area 202 located on the same side of the first area 201, the spacing between the target pads in the second row of pads to the target pads in the nth row of pads increases in proportion to m as a multiple, and the spacing between the target pads in the same row of pads remains fixed.
[0061] In the embodiment of the present application, the spacing between two adjacent target pads is preferably set to an integer multiple of the first spacing to facilitate the layout of the pads 22 in the second area 202 .
[0062] exist Figure 5In the illustrated manner, m=2 is used as an example for illustration, that is, in the second area 202 located on the same side of the first area 201, the ratio of the distance between the target pads in two adjacent rows of pads is 2. Figure 5 In the illustrated manner, n=3 is also used as an example for illustration, and the second area 202 located on the upper side or the lower side of the first area 201 has 3 rows of pads 22. The spacing between two adjacent pads 22 in the first row of pads is D1, the second row of pads is provided with a target pad, and the spacing between two adjacent target pads is 2*D1, and the third row of pads is provided with a target pad, and the spacing between two adjacent target pads is 4*D1.
[0063] In the embodiment of the present application, n is not limited to 3 as shown, and the value of n can be set to any positive integer greater than 2 based on demand, and the value of n can be the same or different for the second areas 202 on different sides of the first area 201.
[0064] The value of m can be set based on the demand. For the second area 202 located in the same area as the first area 201, if m=2, the target pad spacing from the second row of pads to the nth row of pads can be 1, 2, 4, 8, ... in sequence; when m=3, the target pad spacing from the second row of pads to the nth row of pads can be 1, 3, 8, 27, ... in sequence. The value of m corresponding to the embodiment of the present application is not limited.
[0065] In the embodiments of the present application, Figure 4 and Figure 5 As shown, for the second area 202 located on the same side of the first area 201, the spacing between any two adjacent pads 22 in the first row of pads in the second area 202 is D1. For the second area 202 located on the same side of the first area 201, based on the pad spacing from the second row of pads to the nth row of pads greater than the first spacing D1, the first row of pads can be connected to the surface wires 23 for wiring, thereby reducing the number of metal layers L.
[0066] refer to Figure 6 As shown, Figure 6 A schematic diagram of a pad layout in the first metal layer of a packaging substrate provided in an embodiment of the present application, in which the first metal layer L 1 In the embodiment, the second region 202 located on the same side of the first region 201 includes: a plurality of sub-regions 31 arranged in sequence around the opposite edges of the first region 201; in the same sub-region, the spacing between any two adjacent pads in the jth row of pads is m j-1times the first spacing D1, j is a positive integer not greater than n, and m is a positive integer greater than 1. A dotted rectangular box represents a sub-area 31. The second area 202 located on the same side of the first area 201 includes a plurality of sub-areas 31 arranged in sequence, and the arrangement direction of the sub-areas 31 is perpendicular to the arrangement direction of a row of pads 22 in the second area 202.
[0067] exist Figure 6 In the illustrated method, n=3, m=2 is used as an example for illustration. For the second area 202 located on the upper side of the first area 201, in any sub-area 31, the distance between two adjacent pads 22 in the first row of pads is 2 1-1 *D1=D1, the distance between two adjacent pads 22 in the second row of pads is 2 2-1 *D1=2*D1, the distance between two adjacent pads 22 in the third row of pads is 2 3-1 *D1=4*D1. At this time, the wiring method of pad 22 can refer to Figure 5 shown.
[0068] In other embodiments, n=3 and m=3 may be set. In this case, in any sub-region 31, the distance between two adjacent pads 22 in the first row of pads is 3. 1-1 *D1=D1, the distance between two adjacent pads 22 in the second row of pads is 3 2-1 *D1=3*D1, the distance between two adjacent pads 22 in the third row of pads is 3 3-1 *D1=9*D1.
[0069] As mentioned above, the values of m and n can be set based on the circuit interconnection requirements of the packaging substrate, and are not limited to n=3, m=2 or 3 in the embodiment of the present application. Both m and n can be any positive integer greater than 1.
[0070] In some implementations of the present application, in the second area 202 located on the same side of the first area 201, in the arrangement direction of the plurality of sub-areas 31, the spacing between two adjacent sub-areas 31 is an integer multiple of the first spacing D1, which facilitates the layout of the pads in the second area 202. Figure 6 As shown, the spacing between two adjacent sub-areas 31 is set to a first spacing D1 (equivalent to 1 times of D1). In other embodiments, the spacing between two adjacent sub-areas 31 can also be set to X*D1, where X is any positive integer greater than 1.
[0071] Combination Figure 5 and Figure 6As shown, in the same sub-region 31, the surface conductors 23 connected to the pads 22 are located in the pad gaps in the sub-region 31. In the direction from the first region 201 to the second region 202, in the same sub-region 31, the pad spacings in each row increase in proportion to m, and the surface conductors 23 connected to the pads in the sub-region 31 can be routed based on the pad gaps in the sub-region 31.
[0072] Based on the packaging substrate provided in the embodiment of the present application, the number of metal layers L can be reduced. Taking n=3 as an example, according to the technical solution of the embodiment of the application, in the direction from the second area 202 to the first area 201, it is only necessary to drill conductive holes starting from the fourth row to connect the inner layer wires 24, thereby effectively reducing the number of holes and the number of metal layers L, and reducing the thickness of the packaging substrate and the production cost.
[0073] In addition, since there are some redundant bumps without connection signals in the chip bump array on the back of the chip in the existing chip manufacturing process, by adjusting the layout of the chip bumps, based on the redundant bumps, the spacing between at least two adjacent pads 22 in the second area 202 is greater than the first spacing D1. In this way, the number of effective chip bumps for connecting signals on the back of the chip can be kept unchanged, and the area corresponding to the redundant bumps (the area is no longer provided with redundant bumps, or even if the bumps are provided, they are not soldered during packaging) is set in the peripheral area of the bottom of the chip, corresponding to the second area 202 in the packaging substrate, so that the thickness of the packaging substrate can be reduced without increasing the area of the packaging substrate, and the layout scheme of the pads 22 and the surface conductors 23 in the embodiment of the present application can be realized.
[0074] refer to Figure 7 , Figure 7 A schematic diagram of another pad layout method in the first metal layer of a package substrate provided in an embodiment of the present application is provided, in which a second area 202 on at least one side of the first area 201 is set, from the first row of pads to the nth row of pads, the pad spacings are D1, 2*D1, 3*D1, ..., in sequence, and at this time, in the second area 202 on this side, the difference between the target pad spacings in the above two adjacent rows of pads is the first spacing D1. The second area 202 on this side is the first peripheral area, such as Figure 7 In the second area 202 located on the upper side of the first area 201, in the first peripheral area, in the same row, the spacing between any two adjacent pads 22 is the same. For the second peripheral area adjacent to the first peripheral area, such as the second area 202 on the left or right side, since the second peripheral area and the first peripheral area have an overlapping portion in the vertex area, the vertex area and the pads in each row of the second peripheral area are arranged based on the first row of pads in the first peripheral area, so that the spacing between pads in each row in the second area 202 on the other side outside the vertex area and the first peripheral area is D1, 2*D1, 3*D1, ... in sequence.
[0075] refer to Figure 8 , Figure 8 A schematic diagram of a pad layout in the first metal layer of another package substrate provided in an embodiment of the present application is provided, in which a second area 202 on at least one side of the first area 201 is set, from the first row of pads to the nth row of pads, the pad spacings are D1, 2*D1, 4*D1, 8*D1, ..., in sequence. At this time, in the second area 202 on this side, the ratio of the target pad spacings between the two adjacent rows of pads is 2, that is, m=2. The second area 202 on this side is the first peripheral area, such as Figure 8 In the second area 202 on the upper middle side, in the first peripheral area, in the same row, the spacing between any two adjacent pads 22 is the same. For the second peripheral area adjacent to the first peripheral area, such as the second area 202 on the left or right side, since the second peripheral area and the first peripheral area have an overlapping portion in the vertex area, the vertex area and each row of pads in the second peripheral area are arranged based on the first row of pads in the first peripheral area, so that the spacing between pads in each row in the second area 202 on the other side outside the vertex area and the first peripheral area is D1, 2*D1, 4*D1, 8*D1, ... in sequence.
[0076] There may be more distribution forms of the pad spacing within the second region 202, which will not be listed one by one here.
[0077] In some embodiments, on the basis that all the pads in the second region 202 can be connected to the surface conductors 23, in order to maximize the distribution density of the pads, only the spacing between the pads in a local area within the second region 202 can be set to meet the spacing setting requirements in the above embodiment, that is, greater than the first spacing D1, so that the spacing between as many pads as possible is configured as the first spacing D1.
[0078] Based on the packaging substrate provided in the above embodiment, another embodiment of the present application further provides a chip packaging structure. The chip packaging structure is as follows Fig. 9 shown.
[0079] refer to Fig. 9 As shown, Fig. 9 A schematic diagram of a chip packaging structure provided in an embodiment of the present application, wherein the chip packaging structure includes:
[0080] The packaging substrate 41 described in any one of the above embodiments;
[0081] The first metal layer L that is soldered and fixed to the package substrate 41 1 The chip 40 on the surface, the chip bumps 42 and the pads 22 on the package substrate 41 are connected one by one.
[0082] In the embodiment of the present application, the chip bumps 42 at the bottom of the chip 40 are welded one-to-one with the pads 22 in the package substrate 41. The layout of the chip bumps 42 at the bottom of the chip 40 is the same as the layout of the pads 22.
[0083] In the embodiment of the present application, the chip packaging structure adopts the packaging substrate 41 in the above embodiment, which can reduce the thickness of the chip packaging structure and reduce the manufacturing cost.
[0084] In this specification, each embodiment is described in a progressive, parallel, or progressive and parallel manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the chip packaging structure disclosed in the embodiment, since it corresponds to the packaging substrate disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the relevant part of the packaging substrate.
[0085] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same reference numerals throughout the embodiments of the specification identify the same structure. In addition, for the sake of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. It is also understood that when an element such as a layer, film, region, or substrate is referred to as "on" another element, the element may be directly on the other element or there may be an intermediate element. In addition, "on" refers to positioning an element on or below another element, but does not essentially refer to positioning on the upper side of another element according to the direction of gravity.
[0086] The terms "upper", "lower", "top", "bottom", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.
[0087] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.
[0088] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A packaging substrate, characterized in that: The packaging substrate has a first area and a second area surrounding the first area; The packaging substrate comprises: The first metal layer to the Nth metal layer are stacked in sequence, where N is a positive integer greater than 1; an insulating layer is provided between two adjacent metal layers; the first metal layer includes a plurality of pads and a plurality of surface conductors; Both the first area and the second area have a plurality of the pads; in the first area, the pads are arranged in an array with a first spacing; in the second area, the spacing between at least two adjacent pads is greater than the first spacing, so that the pads in the second area are all connected to the corresponding surface conductors.
2. The packaging substrate according to claim 1, characterized in that: Two adjacent pads with a spacing greater than the first spacing are both target pads; In a second region at the same side of the first region, a spacing between target pads close to the first region is smaller than a spacing between target pads far from the first region.
3. The packaging substrate according to claim 2, characterized in that: In the second region located on the same side as the first region, there are a first row of pads to an nth row of pads arranged in sequence in a direction from the first region to the second region, where n is a positive integer greater than 1; The target pads are arranged in the 2nd row of pads to the nth row of pads, and the difference between the target pad spacings in two adjacent rows of pads is the first spacing.
4. The packaging substrate according to claim 2, characterized in that: In the second region located on the same side as the first region, there are a first row of pads to an nth row of pads arranged in sequence in a direction from the first region to the second region, where n is a positive integer greater than 1; The target pads are arranged in the 2nd row of pads to the nth row of pads, and the ratio of the distances between the target pads in two adjacent rows of pads is m, where m is a positive integer greater than 1.
5. The packaging substrate according to claim 3 or 4, characterized in that: In the first row of pads in the second region, the distance between any two adjacent pads is the first distance.
6. The packaging substrate according to claim 4, characterized in that: The second area located on the same side of the first area includes: a plurality of sub-areas arranged in sequence around the opposite edges of the first area; In the same sub-area, the distance between any two adjacent pads in the jth row of pads is m. j-1 times the first spacing, j is a positive integer not greater than n, and m is a positive integer greater than 1.
7. The packaging substrate according to claim 6, characterized in that: In the second region located on the same side of the first region, in the arrangement direction of the plurality of sub-regions, a spacing between two adjacent sub-regions is an integer multiple of the first spacing.
8. The packaging substrate according to claim 6, characterized in that: In the same sub-region, the surface conductive line connected to the pad is located in a pad gap in the sub-region.
9. The packaging substrate according to claim 1, characterized in that: For the pad in the first area, the pad is connected to the inner layer wire in the ath metal layer through a conductive hole; the inner layer wire extends from the position connected to the conductive hole in the ath metal layer to the second area; a is a positive integer greater than 1 and less than N.
10. A chip packaging structure, characterized in that: include: The packaging substrate according to any one of claims 1 to 9; The chip is soldered and fixed on the surface of the first metal layer of the packaging substrate, and the chip bumps are connected to the pads on the packaging substrate in a one-to-one correspondence.