Ultra-wideband interconnection structure stray capacitance optimization structure

Abstract

The invention discloses a stray capacitance optimization structure of an ultra-wideband interconnection structure, which is applied to the field of signal transmission and aims to solve the problem of low transmission performance of an existing packaging structure. According to the invention, for interconnection between an external interface and chips, an interconnection structure of an external interface SMA-microstrip line-like coaxial-strip line-like coaxial-BGA solder ball is adopted, for interconnection between chips, an interconnection structure of BGA-like coaxial-strip line-like coaxial-BGA is adopted, and through optimization and adjustment, the number of chips is reduced, and the number of chips is reduced. And excellent interconnection performance between an external interface and a chip and between chips can be realized in an ultra-wideband range of 0-40GHz.

Description

Technical Field

[0001] The invention belongs to the field of signal transmission, and in particular relates to an ultra-wideband device. Background Art

[0002] SiP (System in Package) is an advanced packaging technology that integrates multiple chips or devices with different functions, such as power amplifiers, processors, MEMS filters and other active and passive devices, and other devices into a package through TSV or various three-dimensional packaging technologies to form a module with specific complex functions or even complete system functions.

[0003] With the rapid development of information technology, people's requirements for communication speed, capacity and confidentiality are constantly increasing. Traditional narrowband communication technology is difficult to meet these requirements under the condition of limited spectrum resources. Therefore, ultra-wideband devices have become an important development trend in circuit design today. In order to ensure good signal transmission performance between ultra-wideband chips and between ultra-wideband chips and external interfaces, the design of ultra-wideband packaging interconnection structure has also become an important research direction. Summary of the invention

[0004] In order to achieve ultra-wideband, low-loss, and low-standing-wave-ratio RF interconnect signal transmission, the present invention provides two design schemes of RF interconnect structures based on low-temperature co-fired ceramic technology, in which the substrate material is Hitce, the thickness of the single-layer substrate is 97um, and the conductive material is copper, with a thickness of 10um. The two proposed schemes use the parasitic capacitance introduced by each layer of the coaxial pad and the parasitic inductance introduced by the transmission line to form a multi-order LC matching network, which can achieve high-performance signal transmission between chips and between chips and external interfaces within the ultra-wideband range of 0-40GHz.

[0005] One of the technical solutions adopted by the present invention is: an ultra-wideband packaging interconnection structure between a chip and an external interface, based on a low-temperature co-fired ceramic substrate, adopting an interconnection structure of an external interface SMA-microstrip line-first type coaxial-first stripline-second type coaxial-BGA solder ball; the microstrip line is located on the top layer of the low-temperature co-fired ceramic substrate, the first end of the microstrip line is connected to the external interface SMA, and the second end of the microstrip line is connected to the first end of the first type coaxial line; the second end of the first type coaxial line is connected to the first end of the first stripline, and the first stripline is located on the metal layer of the low-temperature co-fired ceramic substrate; the second end of the first stripline is connected to the first end of the second type coaxial line, the second end of the second type coaxial line is connected to the BGA solder ball, and the BGA solder ball is connected to the chip interface;

[0006] The first type of coaxial and the second type of coaxial are connected to each layer of the occupied low temperature co-fired ceramic substrate through a welding pad;

[0007] The parasitic capacitance introduced by each layer of the pads of the first type coaxial and the second type coaxial and the parasitic inductance introduced by the transmission lines used for the routing of the first type coaxial and the second type coaxial form a multi-stage LC matching network.

[0008] The first type of coaxial and the second type of coaxial are vertically interconnected structures; the first type of coaxial and the second type of coaxial occupy three layers of substrate.

[0009] The distance between the top layer of the low temperature co-fired ceramic substrate and the bottom metal layer is three layers of the substrate height.

[0010] The distance between the ground below the low temperature co-fired ceramic substrate and the metal bottom layer is two substrate heights.

[0011] The microstrip line selects a single-layer substrate height.

[0012] The second technical solution adopted by the present invention is: an ultra-wideband packaging interconnection structure between chips, based on a low-temperature co-fired ceramic substrate, adopting an interconnection structure of a first BGA solder ball-third type coaxial-second stripline-fourth type coaxial-second BGA solder ball, the first BGA solder ball is connected to the first chip interface, the first BGA solder ball is also connected to the first end of the third type coaxial, the second end of the third type coaxial is connected to the first end of the second stripline, the second stripline is located in the metal stratum of the low-temperature co-fired ceramic substrate; the second end of the second stripline is connected to the first end of the fourth type coaxial, the second end of the fourth type coaxial is connected to the second BGA solder ball, and the second BGA solder ball is connected to the second chip interface;

[0013] The third type of coaxial and the fourth type of coaxial are connected to each layer of the occupied low temperature co-fired ceramic substrate through a welding pad;

[0014] The parasitic capacitance introduced by each layer of the pads of the third and fourth coaxial cables and the parasitic inductance introduced by the transmission lines used for the routing of the third and fourth coaxial cables themselves form a multi-order LC matching network.

[0015] The third type coaxial and the fourth type coaxial are vertically interconnected structures; the third type coaxial and the fourth type coaxial occupy three layers of substrates.

[0016] The distance between the top layer of the low temperature co-fired ceramic substrate and the bottom metal layer is three layers of the substrate height.

[0017] The distance between the ground below the low temperature co-fired ceramic substrate and the metal bottom layer is two substrate heights.

[0018] Beneficial effects of the present invention: The substrate material used in the present invention is Hitce, the thickness of the single-layer substrate is 97um, the conductive material is copper, and the thickness of the copper is 10um; the two schemes proposed in the present invention use the parasitic capacitance introduced by each layer of the coaxial pad and the parasitic inductance introduced by the transmission line to form a multi-order LC matching network, which can achieve excellent interconnection performance between the external interface and the chip, and between chips in the ultra-wideband range of 0-40GHz. Specifically, the return loss is better than -20dB, and the insertion loss is better than -1.5dB. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a top view of a quasi-coaxial vertical transmission structure.

[0020] Figure 2 It is a correspondence diagram between equivalent lumped elements and physical structures of coaxial structures.

[0021] Figure 3 This is the interconnection structure diagram of microstrip line-quasi-coaxial-stripline-quasi-coaxial-BGA solder ball.

[0022] Figure 4 This is the interconnection structure diagram of BGA-quasi-coaxial-stripline-quasi-coaxial-BGA.

[0023] Among them, 11 is a quasi-coaxial inner conductor, 12 is a quasi-coaxial outer conductor, 13 is a pad, 14 is a parasitic inductance introduced by a quasi-coaxial trace, 15 is a parasitic capacitance introduced by a pad, 16 is an anti-pad, 17 is a ceramic dielectric, 18 is a planar transmission line, 21 is a microstrip line, 22 is a quasi-coaxial, 23 is a stripline, 24 is a BGA solder ball, 25 is a signal isolation metal column, 26 is a chip model, 27 is an external signal input interface, 31 is a BGA solder ball, 32 is a quasi-coaxial, 33 is a stripline, 34 is a signal isolation metal column, and 35 is a chip model. DETAILED DESCRIPTION

[0024] To facilitate those skilled in the art to understand the technical content of the present invention, the present invention is further explained below with reference to the accompanying drawings. First, the principles of the two interconnect packaging structures are to use the parasitic capacitance introduced by each layer of the coaxial pad and the parasitic inductance introduced by the transmission line to form a multi-order LC matching network to achieve high-order matching. Figure 1 The figure shows a top view of a quasi-coaxial vertical transmission structure, including: a quasi-coaxial inner conductor 11, a quasi-coaxial outer conductor 12 formed by a plurality of circularly distributed grounded metal through holes, a pad 13 for connecting the quasi-coaxial conductor to each layer of the occupied substrate, and an anti-pad 16 for isolating the quasi-coaxial inner conductor and the pad from the surrounding large-area metal ground. The ceramic medium 17 acts as a medium between the inner and outer conductors of the coaxial line. The parasitic effect introduced by the horizontal transmission line 18 such as a microstrip line and a stripline can be equivalent to a parasitic inductance, while the parasitic effect introduced by the vertical transmission line quasi-coaxial is as follows: Figure 2As shown, the quasi-coaxial structure can be regarded as a low-pass LC network. The parasitic inductance 14 introduced by the specific quasi-coaxial routing and the parasitic capacitance 15 introduced by the pad form a multi-order LC matching network. After the approximate size of the quasi-coaxial line is determined by the coaxial line characteristic impedance calculation formula, the value of the parasitic capacitance can be adjusted by adjusting the size of the pad and the anti-pad 16, and then a high-order LC matching network is formed together with the parasitic inductance introduced by the transmission line, thereby playing the role of ultra-wideband matching.

[0025] Example 1

[0026] exist Figure 3 In the figure, for the interconnection between the external interface and the chip, an external interface SMA-microstrip line-quasi-coaxial-stripline-quasi-coaxial-BGA solder ball interconnection structure is adopted, wherein the microstrip line 21 located on the surface is used to receive the surface external signal input from the SMA interface 27. When the received signal frequency is high, the microstrip line 21 can be replaced with a coplanar waveguide (not suitable for ultra-wideband structure). In order to avoid radiation loss of the signal and insufficient routing space of a single-layer substrate, after the microstrip line 21 travels a certain distance, the signal changes layers through the quasi-coaxial 22 to enter the internal layer of the packaging structure, and is changed to be transmitted by stripline 23 between the internal layers (since each layer of metal ground is close to each other, the microstrip line cannot be located in the internal layer). After transmitting the required distance, it changes layers through another section of quasi-coaxial 22. After changing layers, the signal enters the chip internal 26 interface through the BGA solder ball 24 inverted on the surface of the substrate. The microstrip line 21 selects a single-layer substrate height and is routed on the top layer of ground (the metal ground uses copper as the material). The microstrip line 21 is connected to the quasi-coaxial line 22 after traveling an appropriate distance. Both sections of the quasi-coaxial line 22 occupy three layers of substrate height. The stripline 23 is routed on the fourth metal layer and is not connected to the metal ground.

[0027] The height and width of the microstrip line satisfy the impedance matching formula, which is calculated to be 50 ohms to reduce the reflection of external input signals. In this example, the microstrip line occupies one layer of substrate height, the line width is 150um, the distance between the line edge and the surrounding metal ground on the same layer is 155um, and the line length is 2500um. It can be calculated that the characteristic impedance of the microstrip line meets the standard 50 ohms.

[0028] By adjusting the size of the transition pad at the connection between the microstrip line and the quasi-coaxial line, the reflection and loss at the connection between the microstrip line and the quasi-coaxial line can be minimized. In this example, when the radius of the top pad at the connection between the microstrip line and the quasi-coaxial line is 195um and the corresponding anti-pad size is 300um, the transmission loss is the lowest.

[0029] The characteristic impedance of the stripline is adjusted by adjusting the width of the stripline and the height of the upper and lower metal grounds, and the size of the transition pad at the stripline and the quasi-coaxial connection is adjusted to reduce the reflection and loss at the interconnection between the stripline and the BGA. In this example, the distance between the upper ground and the trace of the stripline 23 is 3 layers of substrate height, the distance between the lower ground and the trace is 2 layers of substrate height, the stripline width is 120um, the distance from the edge of the stripline to the metal ground of the same layer is 160um, the stripline length is 250um, and the transition pad radius is 80um.

[0030] The characteristic impedance of the quasi-coaxial line is adjusted by adjusting the ratio of the inner diameter to the outer diameter, and the discontinuity of the connection between the quasi-coaxial line and the microstrip line and the BGA is adjusted by adjusting the size of the transition pad and the anti-pad. At the same time, additional pads are introduced as needed to introduce a certain amount of parasitic capacitance to resonate the high-frequency parasitic inductance introduced by the transmission line (when the transmission line is too long and the quasi-coaxial line crosses too many substrate layers at one time, the parasitic inductance effect is obvious, and the pads between the layers can introduce additional parasitic capacitance to balance the inductance effect), thereby achieving the purpose of broadband matching. In this example, the inner diameter of the quasi-coaxial connected to the microstrip line is 60um, the outer diameter is 680um, the anti-pad size is 305um, and transition pads are provided at the connections with the microstrip line and the stripline respectively. The radius of the microstrip line transition pad is 195um, and the radius of the stripline transition pad is 80um. There are no additional pads; the inner diameter of the quasi-coaxial connected to the BGA is 60um, the outer diameter is 585um, and the anti-pad size is 400um. Transition pads are provided at the connections with the stripline and the BGA respectively. The radius of the stripline transition pad is 80um, and the radius of the BGA transition pad is 140um. There are no additional pads.

[0031] Example 2

[0032] exist Figure 4 In the figure, for the interconnection between chips, the interconnection structure of BGA-quasi-coaxial-stripline-quasi-coaxial-BGA is adopted, that is, the signal is output from the port of a chip, and is vertically input into the quasi-coaxial structure 32 via BGA 31 for layer change to avoid insufficient routing space caused by the routing being concentrated on the surface of the substrate. The quasi-coaxial 32 occupies three layers of substrate height, and the signal is input into the stripline 33 via the quasi-coaxial 32. The stripline 33 routing is located on the fourth metal layer and is not connected to the ground. The signal is input into the quasi-coaxial 22 at the other end via the stripline 33, and is input into the BGA 31 solder ball of another chip via the quasi-coaxial 32, and finally input into the chip 35 at the other end.

[0033] By adjusting the height and width of the stripline, the reflection and transmission loss at the quasi-coaxial connection can be minimized. In this example, the distance between the upper ground and the trace of the stripline 33 is 3 layers of substrate height, the distance between the lower ground and the trace is 2 layers of substrate height, the line width is 120um, the distance between the edge of the stripline and the surrounding metal ground of the same layer is 160um, and the line length is 6150um.

[0034] By adjusting the ratio of the inner diameter to the outer diameter of the quasi-coaxial, the radius of the anti-pad and the radius of the transition pad, the discontinuity of the connection with the stripline and BGA is reduced, and a certain amount of parasitic capacitance is introduced to resonate the parasitic inductance introduced by the transmission line to achieve the purpose of broadband matching. In this example, the inner diameter of the two quasi-coaxial sections is 60um, the outer diameter is 585um, the anti-pad radius is 400um, the stripline transition pad radius is 80um, the BGA transition pad radius is 140um, and there is no additional pad.

[0035] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and should be understood that the scope of protection of the present invention is not limited to such specific statements and embodiments. For those skilled in the art, the present invention may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of the claims of the present invention.

Claims

1. An ultra-wideband package interconnect structure between a chip and an external interface, characterized in that: Based on a low-temperature co-fired ceramic substrate, an interconnection structure of an external interface SMA-microstrip line-first type coaxial-first stripline-second type coaxial-BGA solder ball is adopted; the microstrip line is located on the top layer of the low-temperature co-fired ceramic substrate, the first end of the microstrip line is connected to the external interface SMA, and the second end of the microstrip line is connected to the first end of the first type coaxial line; the second end of the first type coaxial line is connected to the first end of the first stripline, and the first stripline is located on the metal layer of the low-temperature co-fired ceramic substrate; the second end of the first stripline is connected to the first end of the second type coaxial line, the second end of the second type coaxial line is connected to the BGA solder ball, and the BGA solder ball is connected to the chip interface; The first type of coaxial and the second type of coaxial are connected to each layer of the occupied low temperature co-fired ceramic substrate through a welding pad; The parasitic capacitance introduced by each layer of the pads of the first type coaxial and the second type coaxial and the parasitic inductance introduced by the transmission lines used for the routing of the first type coaxial and the second type coaxial form a multi-stage LC matching network.

2. The ultra-wideband package interconnect structure between a chip and an external interface according to claim 1, characterized in that: The material of the low-temperature co-fired ceramic substrate is Hitce.

3. The ultra-wideband package interconnect structure between a chip and an external interface according to claim 2, characterized in that: The first type of coaxial and the second type of coaxial are vertically interconnected structures; the first type of coaxial and the second type of coaxial occupy three layers of substrate.

4. The ultra-wideband package interconnect structure between a chip and an external interface according to claim 3, characterized in that: The height of the microstrip line is the height of a single-layer substrate.

5. The ultra-wideband package interconnect structure between a chip and an external interface according to claim 4, characterized in that: The height and width of the microstrip line satisfy the impedance matching formula and the calculated result is 50 ohms.

6. An ultra-wideband packaging interconnection structure between chips, characterized in that: Based on a low-temperature co-fired ceramic substrate, an interconnection structure of a first BGA solder ball-third type coaxial-second stripline-fourth type coaxial-second BGA solder ball is adopted, the first BGA solder ball is connected to the first chip interface, the first BGA solder ball is also connected to the first end of the third type coaxial, the second end of the third type coaxial is connected to the first end of the second stripline, and the second stripline is located in the metal stratum of the low-temperature co-fired ceramic substrate; the second end of the second stripline is connected to the first end of the fourth type coaxial, the second end of the fourth type coaxial is connected to the second BGA solder ball, and the second BGA solder ball is connected to the second chip interface; The third type of coaxial and the fourth type of coaxial are connected to each layer of the occupied low temperature co-fired ceramic substrate through a welding pad; The parasitic capacitance introduced by each layer of the pads of the third and fourth coaxial cables and the parasitic inductance introduced by the transmission lines used for the routing of the third and fourth coaxial cables themselves form a multi-order LC matching network.

7. The ultra-wideband package interconnect structure between chips according to claim 6, characterized in that: The material of the low-temperature co-fired ceramic substrate is Hitce.

8. The ultra-wideband package interconnect structure between chips according to claim 7, characterized in that: The third type coaxial and the fourth type coaxial are vertically interconnected structures; the third type coaxial and the fourth type coaxial occupy three layers of substrates.

9. The ultra-wideband package interconnect structure between chips according to claim 8, characterized in that: The distance between the ground and the trace above the second stripline is 3 layers of substrate height.

10. The ultra-wideband package interconnect structure between chips according to claim 9, characterized in that: The distance between the ground and the trace under the second stripline is 2 layers of substrate height.

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