Handwriting erasing control circuit for liquid crystal handwriting board

Abstract

The invention relates to the technical field of liquid crystal handwriting board control circuits, in particular to a handwriting erasing control circuit for a liquid crystal handwriting board. The limitation and defects of a handwriting erasing control circuit of a liquid crystal handwriting board in the prior art are overcome. Comprising an input filter capacitor (300) used for filtering input voltage of a button battery or a lithium ion battery; the PCB metal winding parasitic inductor (301) is used for performing energy storage conversion on the input current; the application-specific integrated circuit control chip unit (302) is used for performing boost conversion control on the input battery voltage and outputting high voltage capable of meeting the handwriting erasing function of the liquid crystal handwriting board; the output filter capacitor (303) is used for filtering the high voltage which is output through boost conversion and can meet the handwriting erasing function of the liquid crystal handwriting board; and the touch switch (304) is used for controlling the handwriting erasing control circuit of the liquid crystal handwriting board to start boosting conversion work.

Description

Technical Field

[0001] The invention relates to the technical field of liquid crystal handwriting board control circuits, and in particular to a handwriting erasing control circuit for a liquid crystal handwriting board. Background Art

[0002] Bistable liquid crystal display is a new type of liquid crystal display technology, which mainly realizes image display through the dual stable state of liquid crystal molecules. Without the help of electric field and other external forces, liquid crystal molecules can remain in two stable states, which means that when the power is off, the liquid crystal can still maintain the displayed image. At the same time, liquid crystal is sensitive to pressure and electric field. Under the action of pressure or electric field, the arrangement of liquid crystal molecules will change, which will affect the injection of light and ultimately change the display of the image. This characteristic of bistable liquid crystal makes it widely used in fields such as liquid crystal handwriting tablets.

[0003] When writing on the LCD tablet, the liquid crystal molecules are squeezed and flipped under the force of the pen tip, and arranged in a spiral upward shape. At this time, the liquid crystal molecules are parallel to the screen of the LCD tablet. When natural light shines on the area where the liquid crystal molecules are flipped, the color light with the same wavelength as the liquid crystal thread distance will be reflected, and the color light of other wavelengths will be absorbed, thus forming handwriting of the corresponding color on the LCD tablet.

[0004] When the handwriting on the LCD tablet needs to be erased and restored, press the erase touch switch on the LCD tablet, and the control circuit will generate a voltage, which is loaded on the front and back surfaces of the liquid crystal film. The liquid crystal molecules flip under the action of the electric field and are arranged perpendicular to the screen of the tablet. When natural light shines on the LCD tablet that has been acted on by the electric field, the light can completely pass through the liquid crystal layer and be absorbed by the bottom black plastic film, thus presenting a completely black image on the LCD tablet, realizing the handwriting erasing function of the LCD tablet.

[0005] When the erase touch switch is pressed, the handwriting erase control circuit of the liquid crystal handwriting tablet needs to boost the low voltage of the button battery or lithium-ion battery to a high voltage that can meet the handwriting erase function of the liquid crystal handwriting tablet and load it onto the front and back surfaces of the liquid crystal film. There are two main specific implementation methods of the handwriting erase control circuit of the liquid crystal handwriting tablet in the prior art.

[0006] Figure 1 It is a traditional existing technology handwriting erasing control circuit for liquid crystal handwriting board. It usually includes: single chip control chip U1, input filter capacitor C1, power inductor L1, NMOS power tube NM1, freewheeling diode D1, output filter capacitor C2, PNP transistor Q1, PNP transistor Q2, NPN transistor Q3, NPN transistor Q4, bias resistor R1, bias resistor R2 and touch switch S1. Figure 1 This traditional handwriting erasure control circuit for liquid crystal handwriting tablets has the following limitations: First, the number of components used in the control circuit is large, and the circuit cost is high. The control circuit uses a general-purpose single-chip microcomputer to program and drive an NMOS power tube and four triodes, and also requires discrete power components such as power inductors and freewheeling diodes. This results in a large space occupied by the circuit board, and also increases the complexity of component installation on the circuit board. Second, the consistency of the output voltage after the boost conversion of the control circuit is poor. The single-chip microcomputer control chip U1 does not sample and detect the output voltage, so it cannot adjust the switch duty cycle of the NMOS power tube NM1 in real time to adjust the output voltage, resulting in poor consistency of the output voltage, thereby affecting the quality of the handwriting erasure function of the liquid crystal handwriting tablet and the yield of the finished product.

[0007] Figure 2 This is another traditional handwriting erasing control circuit for a liquid crystal handwriting board. It usually includes: a dedicated integrated circuit control chip U2, an input filter capacitor C2, a power inductor L2, a freewheeling diode D2, an output filter capacitor C4, an output voltage setting resistor R3 and a touch switch S2. This traditional handwriting erasing control circuit for a liquid crystal handwriting board has the following limitations: First, the control circuit adopts a dedicated integrated circuit control chip technical solution, although compared with Figure 1 The technical solution of adopting general single-chip microcomputer control saves a lot of peripheral components; however, power components such as power inductor L2 and freewheeling diode D2 are still needed. The overall solution cost is still high. Second, the output voltage after the boost conversion of the control circuit needs to be set by an external resistor R3, which adds additional peripheral components. Third, the dedicated integrated circuit control chip U2 also needs to define a pin specifically for the function of setting the output voltage. In addition, the dedicated integrated circuit control chip U2 needs to define two output pins, which has great limitations in the application of packaging forms with a small number of pins.

[0008] In summary, the existing technical solutions have technical problems such as a large number of components used, such as expensive power inductors and freewheeling diodes, poor output voltage consistency or the need for additional output voltage setting resistors, and a large number of packaging pins required for the control chip. Summary of the invention

[0009] The object of the present invention is to provide a handwriting erasing control circuit for a liquid crystal handwriting tablet, so as to solve the limitations and shortcomings of the handwriting erasing control circuit of the traditional liquid crystal handwriting tablet in the prior art.

[0010] To achieve the above object, the present invention provides the following technical solutions: A handwriting erasing control circuit for a liquid crystal writing board, comprising an input filter capacitor, a PCB metal winding parasitic inductance, a dedicated integrated circuit control chip unit, an output filter capacitor and a touch switch;

[0011] The input filter capacitor is used to filter the voltage of the input button battery or lithium-ion battery;

[0012] The parasitic inductance of the PCB metal winding is used to convert the input current into energy storage;

[0013] The dedicated integrated circuit control chip unit is used to perform step-up conversion control on the input battery voltage, and output a high voltage that can meet the handwriting erasing function of the liquid crystal handwriting board;

[0014] The output filter capacitor is used to filter the high voltage output by the boost conversion that can meet the handwriting erasing function of the liquid crystal handwriting board;

[0015] The touch switch is used to control the handwriting erasing control circuit of the liquid crystal writing board to start the step-up conversion work.

[0016] Preferably, one end of the PCB metal winding parasitic inductance is connected to the SW input end of the ASIC control chip unit, and the other end is connected to the VIN input end of the ASIC control chip unit, and is also connected to one end of the input filter capacitor and the positive electrode of a button battery or a lithium-ion battery; the other end of the input filter capacitor is connected to the ground; one end of the output filter capacitor is connected to the VH output end of the ASIC control chip unit, and the other end is connected to the ground; one end of the touch switch is connected to the SWT input end of the ASIC control chip unit, and the other end of the touch switch is connected to the ground; the GND input end of the ASIC control chip unit is connected to the ground, and is also connected to an input electrode of the liquid crystal handwriting board and the negative electrode of the button battery or the lithium-ion battery; the OUT output end of the ASIC control chip unit is connected to another input electrode of the liquid crystal handwriting board.

[0017] Preferably, the ASIC control chip unit includes: a key detection unit, a timing control unit, an output voltage constant voltage control unit, a logic control unit, a current zero-crossing detection unit, a gate drive unit, a power management unit, a frequency oscillator unit, a first NMOS power tube, a first PMOS power tube, a second PMOS power tube and a second NMOS power tube; the input end of the key detection unit is connected to the SWT input end of the ASIC control chip unit, and is also connected to the first input end of the output voltage constant voltage control unit; the output end of the key detection unit is connected to the input end of the timing control unit; the output end of the timing control unit is connected to the first input end of the logic control unit; the second input end of the output voltage constant voltage control unit is connected to the OUT output end of the ASIC control chip unit; the output end of the output voltage constant voltage control unit is connected to the second input end of the logic control unit; the first input end of the power management unit is connected to the VIN input end of the ASIC control chip unit; the second input end of the power management unit is connected to the VH output end of the ASIC control chip unit; the first output end of the power management unit is connected to the input end of the frequency oscillator unit; the second output end of the power management unit provides working power to the ASIC control chip unit; The output end of the rate oscillator unit is connected to the third input end of the logic control unit; the output end of the logic control unit is connected to the first input end of the gate driving unit; the input end of the current zero-crossing detection unit is connected to the SW input end of the dedicated integrated circuit control chip unit; the output end of the current zero-crossing detection unit is connected to the second input end of the gate driving unit; the first output end of the gate driving unit is connected to the gate of the first PMOS power tube; the second output end of the gate driving unit is connected to the gate of the second PMOS power tube; the third output end of the gate driving unit is connected to the gate of the second NMOS power tube; the fourth output end of the gate driving unit is connected to the gate of the first NMOS power tube; the drain of the first NMOS power tube is connected to the SW input end of the dedicated integrated circuit control chip unit, and is also connected to the drain of the first PMOS power tube; the source of the first NMOS power tube is connected to the ground; the source of the first PMOS power tube is connected to the VH output end of the dedicated integrated circuit control chip unit, and is also connected to the source of the second PMOS power tube; the drain of the second PMOS power tube is connected to the OUT output end of the dedicated integrated circuit control chip unit, and is also connected to the drain of the second NMOS power tube; the source of the second NMOS power tube is connected to the ground.

[0018] Preferably, the output voltage constant voltage control unit includes: a trimming signal control processing unit, an EFUSE fuse trimming unit, a first switch, a second switch, a third switch, a fourth switch, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a reference voltage generating unit and a voltage comparator unit; a first input end of the trimming signal control processing unit is connected to the SWT input end of the ASIC control chip unit; a second input end of the trimming signal control processing unit is connected to the OUT output end of the ASIC control chip unit and is connected to one end of the first resistor; an output end of the trimming signal control processing unit is connected to the input end of the EFUSE fuse trimming unit; a first output end of the EFUSE fuse trimming unit is connected to the control end of the first switch; a second output end of the EFUSE fuse trimming unit is connected to the control end of the second switch; a third output end of the EFUSE fuse trimming unit is connected to the control end of the third switch; and The fourth output end of the first resistor is connected to the control end of the fourth switch; the other end of the first resistor is connected to one end of the second resistor and is connected to the positive input end of the voltage comparator unit; the other end of the second resistor is connected to one end of the third resistor and is connected to the first output end of the first switch; the other end of the third resistor is connected to one end of the fourth resistor and is connected to the second output end of the first switch and the first output end of the second switch; the other end of the fourth resistor is connected to one end of the fifth resistor and is connected to the second output end of the second switch and the first output end of the third switch; the other end of the fifth resistor is connected to one end of the sixth resistor and is connected to the second output end of the third switch and the first output end of the fourth switch; the other end of the sixth resistor is connected to the second output end of the fourth switch and is connected to ground; the negative input end of the voltage comparator unit is connected to the output end of the reference voltage generating unit; the output end of the voltage comparator unit is connected to the second input end of the logic control unit.

[0019] Preferably, the topology design of the metal winding parasitic inductance of the PCB is performed during the layout and wiring design stage of the PCB circuit board, and is produced together with the PCB circuit board. The topology design of the metal winding parasitic inductance of the PCB is a spiral coil or a regular octagonal coil or a coil of other shapes.

[0020] Compared with the prior art, the beneficial effects of the present invention are: the technical solution of the handwriting erasing control circuit for the liquid crystal handwriting board of the present invention has the following advantages:

[0021] 1. The solution of the present invention only needs a dedicated integrated circuit control chip, two capacitors, a touch switch and a PCB metal winding parasitic inductor and other components, and the solution is highly integrated. It is very suitable for applications such as liquid crystal handwriting tablets that require high space for circuit boards.

[0022] 2. The technical solution of the present invention does not require the use of a special power inductor, but only requires the parasitic inductance generated by the metal winding of the PCB to achieve a step-up conversion from the input low voltage of the battery to the output high voltage that can meet the handwriting erasing function of the liquid crystal handwriting board.

[0023] 3. The technical solution of the present invention can accurately control the size of the output high voltage, and adopts the proprietary EFUSE fuse trimming technology to realize the test trimming of the output high voltage in the FT test stage, which can meet the application requirements of liquid crystal handwriting tablets of different specifications, without the need for additional output voltage setting resistors as in the traditional existing technology, and the product has excellent consistency during mass production.

[0024] 4. The technical solution of the present invention adopts innovative control technology, which effectively saves the use of freewheeling diode components. These are advantages that existing technical solutions, especially traditional single-chip microcomputer control technical solutions, do not have.

[0025] 5. The control chip of the present invention has only six pins in the package, and can adopt a more compact and more cost-effective SOT series package. Therefore, in terms of pursuing high integration, excellent consistency and extremely low cost, the handwriting erasing control circuit for a liquid crystal handwriting board of the present invention has a greater competitive advantage. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is the first conventional prior art handwriting erasing control circuit for a liquid crystal handwriting tablet;

[0027] Figure 2 A second conventional prior art handwriting erasing control circuit for a liquid crystal handwriting tablet;

[0028] Figure 3 A handwriting erasing control circuit for a liquid crystal handwriting board of the present invention;

[0029] Figure 4 It is an embodiment of the dedicated integrated circuit control chip unit of the handwriting erasing control circuit for the liquid crystal handwriting board of the present invention;

[0030] Figure 5 It is a specific embodiment of the output voltage constant voltage control unit of the present invention;

[0031] Figure 6This is the first specific embodiment of the PCB metal winding parasitic inductance unit of the present invention;

[0032] Figure 7 This is the second specific embodiment of the PCB metal winding parasitic inductance unit of the present invention.

[0033] Description of reference numerals: 300, input filter capacitor; 301, parasitic inductance of PCB metal winding; 302, dedicated integrated circuit control chip unit; 303, output filter capacitor; 304, touch switch; 400, key detection unit; 401, timing control unit; 402, output voltage constant voltage control unit; 403, logic control unit; 404, current zero-crossing detection unit; 405, gate drive unit; 406, power management unit; 407, frequency oscillator unit; 408, first NMOS power tube; 409, A first PMOS power tube; 410, a second PMOS power tube; 411, a second NMOS power tube; 500, a trimming signal control processing unit; 501, an EFUSE fuse trimming unit; 502, a first switch; 503, a second switch; 504, a third switch; 505, a fourth switch; 506, a first resistor; 507, a second resistor; 508, a third resistor; 509, a fourth resistor; 510, a fifth resistor; 511, a sixth resistor; 512, a reference voltage generating unit; 513, a voltage comparator unit. DETAILED DESCRIPTION

[0034] The technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0035] The handwriting erasing control circuit for a liquid crystal handwriting board of the present invention realizes the step-up conversion from the input low voltage of the battery to the output high voltage that can meet the handwriting erasing function of the liquid crystal handwriting board through extremely simple components such as a dedicated integrated circuit control chip unit 302, two capacitors, a touch switch 304, and a PCB metal winding parasitic inductance 301, wherein the two capacitors include an input filter capacitor 300 and an output filter capacitor 303. The technical solution of the present invention effectively solves the technical problems of the traditional existing technical solutions, such as a large number of components, the need for expensive power inductors and freewheeling diodes, poor output voltage consistency or the need for additional output voltage setting resistors, and the need for more packaging pins for the control chip.

[0036] Example:

[0037] like Figure 3 The figure shows a handwriting erasing control circuit for a liquid crystal handwriting board of the present invention, the handwriting erasing control circuit comprising: an input filter capacitor 300, used for filtering the voltage of an input button battery or a lithium-ion battery; a PCB metal winding parasitic inductance 301, used for performing energy storage conversion on the input current; a dedicated integrated circuit control chip unit 302, used for performing boost conversion control on the input battery voltage, and outputting a high voltage that can meet the handwriting erasing function of the liquid crystal handwriting board; an output filter capacitor 303, used for filtering the high voltage output by the boost conversion that can meet the handwriting erasing function of the liquid crystal handwriting board; and a touch switch 304, used for controlling the handwriting erasing control circuit of the liquid crystal handwriting board to start the boost conversion operation. One end of the PCB metal winding parasitic inductor 301 is connected to the SW input end of the ASIC control chip unit 302, and the other end is connected to the VIN input end of the ASIC control chip unit 302, and is also connected to one end of the input filter capacitor 300 and the positive electrode of the button battery or lithium-ion battery; the other end of the input filter capacitor 300 is connected to the ground; one end of the output filter capacitor 303 is connected to the VH output end of the ASIC control chip unit 302, and the other end is connected to the ground; one end of the touch switch 304 is connected to the SWT input end of the ASIC control chip unit 302, and the other end of the touch switch 304 is connected to the ground; the GND input end of the ASIC control chip unit 302 is connected to the ground, and is also connected to an input electrode of the liquid crystal handwriting board and the negative electrode of the button battery or lithium-ion battery; the OUT output end of the ASIC control chip unit 302 is connected to another input electrode of the liquid crystal handwriting board.

[0038] like Figure 4As shown, an embodiment of the ASIC control chip unit 302 of the handwriting erasing control circuit for a liquid crystal handwriting board of the present invention is shown. The ASIC control chip unit 302 includes: a key detection unit 400, a timing control unit 401, an output voltage constant voltage control unit 402, a logic control unit 403, a current zero-crossing detection unit 404, a gate drive unit 405, a power management unit 406, a frequency oscillator unit 407, a first NMOS power tube 408, a first PMOS power tube 409, a second PMOS power tube 410 and a second NMOS power tube 411.The input end of the key detection unit 400 is connected to the SWT input end of the ASIC control chip unit 302, and is also connected to the first input end of the output voltage constant voltage control unit 402; the output end of the key detection unit 400 is connected to the input end of the timing control unit 401; the output end of the timing control unit 401 is connected to the first input end of the logic control unit 403; the second input end of the output voltage constant voltage control unit 402 is connected to the OUT output end of the ASIC control chip unit 302; the output end of the output voltage constant voltage control unit 402 is connected to the second input end of the logic control unit 403; the power management unit 40 The first input end of the power management unit 406 is connected to the VIN input end of the ASIC control chip unit 302; the second input end of the power management unit 406 is connected to the VH output end of the ASIC control chip unit 302; the first output end of the power management unit 406 is connected to the input end of the frequency oscillator unit 407; the second output end of the power management unit 406 provides working power to the ASIC control chip unit 302; the output end of the frequency oscillator unit 407 is connected to the third input end of the logic control unit 403; the output end of the logic control unit 403 is connected to the first input end of the gate drive unit 405; the current zero-crossing detection unit 40 The input end of the gate driving unit 405 is connected to the SW input end of the ASIC control chip unit 302; the output end of the current zero-crossing detection unit 404 is connected to the second input end of the gate driving unit 405; the first output end of the gate driving unit 405 is connected to the gate of the first PMOS power tube 409; the second output end of the gate driving unit 405 is connected to the gate of the second PMOS power tube 410; the third output end of the gate driving unit 405 is connected to the gate of the second NMOS power tube 411; the fourth output end of the gate driving unit 405 is connected to the gate of the first NMOS power tube 408; the first NMOS power tube 408 The drain of the first PMOS power tube 409 is connected to the SW input terminal of the dedicated integrated circuit control chip unit 302, and is also connected to the drain of the first PMOS power tube 409; the source of the first NMOS power tube 408 is connected to the ground; the source of the first PMOS power tube 409 is connected to the VH output terminal of the dedicated integrated circuit control chip unit 302, and is also connected to the source of the second PMOS power tube 410; the drain of the second PMOS power tube 410 is connected to the OUT output terminal of the dedicated integrated circuit control chip unit 302, and is also connected to the drain of the second NMOS power tube 411; the source of the second NMOS power tube 411 is connected to the ground.

[0039] When the touch switch 304 is pressed once, the key detection unit 400 starts to detect the input signal of the SWT input terminal of the ASIC control chip unit 302. When the key detection unit 400 detects that the input signal is a valid low-level signal, the key detection unit 400 will output a pulse signal PULSE to the input terminal of the timing control unit 401. At this time, the timing control unit 401 starts to perform timing control, outputs a high-level logic signal TIM to the first input terminal of the logic control unit 403, and controls the ASIC control chip unit 302 to continuously enable and work for one second. During the period when the ASIC control chip unit 302 is enabled to work, the power management unit 406 manages the voltage of the VIN input terminal and the VH output terminal of the ASIC control chip unit 302, and outputs it to the power supply VDDS for powering each unit circuit inside the ASIC control chip unit 302, and also outputs the VDD voltage to the input terminal of the frequency oscillator unit 407. The frequency oscillator unit 407 outputs a clock signal OSC with a frequency of 2MHz to the third input terminal of the logic control unit 403. At this time, the logic control unit 403 will output a logic drive signal DRV with a frequency of 2MHz to the first input terminal of the gate drive unit 405. During the period when the ASIC control chip unit 302 is working, the output voltage constant voltage control unit 402 will sample and detect the voltage of the OUT output terminal of the ASIC control chip unit 302 in real time. When the sampled voltage of the OUT output terminal reaches the reference threshold voltage set inside the output voltage constant voltage control unit 402, the output terminal of the output voltage constant voltage control unit 402 immediately outputs a high-level control signal CTR to the second input terminal of the logic control unit 403, controlling the logic control unit 403 to stop outputting the logic drive signal DRV with a frequency of 2MHz. The DRV logic drive signal becomes a low level at this time.

[0040] The gate drive unit 405 performs gate drive control on the first NMOS power tube 408, the first PMOS power tube 409, the second PMOS power tube 410 and the second NMOS power tube 411 respectively. During the period when the gate drive unit 405 controls the first NMOS power tube 408 to be turned on and the first PMOS power tube 409 to be turned off, the input voltage of the battery is filtered by the input filter capacitor 300, and the input current flows to the ground through the path formed by the PCB metal winding parasitic inductance 301 and the first NMOS power tube 408. At this time, the current of the PCB metal winding parasitic inductance 301 rises in a ramp. Its current satisfies the following relationship in the ramp-up stage:

[0041]

[0042] Wherein, L is the inductance value of the PCB metal winding parasitic inductance 301; T ON is the conduction time of the first NMOS power tube 408; ΔI is the ripple current of the parasitic inductance of the PCB metal winding; V VIN In addition, the conduction time of the first NMOS power tube 408 and the output frequency of the frequency oscillator unit 407 have the following relationship:

[0043]

[0044] Among them, f 407 is the output frequency of the frequency oscillator unit 407; D is the on-time duty cycle of the first NMOS power tube 408. From formula (1) and formula (2), we can get:

[0045]

[0046] It can be seen from formula (3) that when the input voltage V VIN When the on-time duty cycle D of the first NMOS power tube 408 and the ripple current ΔI of the PCB metal winding inductor are all fixed values, the output frequency f of the frequency oscillator unit 407 is 407 The larger the value, the smaller the required inductance value L of the PCB metal winding parasitic inductance 301. Therefore, when the output frequency f of the frequency oscillator unit 407 is 407 When the design is 2MHz, the inductance L of the PCB metal winding parasitic inductance 301 obtained according to formula (3) only needs to be on the order of 1uH. This order of magnitude of inductance can be completely achieved by PCB metal winding. In addition, according to the characteristics of the liquid crystal handwriting board that high voltage and small current are required during operation, the maximum operating current of the PCB metal winding parasitic inductance 301 is usually below 200mA, that is, the saturation current of the PCB metal winding parasitic inductance 301 only needs to meet the level of 200mA. This order of magnitude of saturation current can also be completely achieved by PCB metal winding without the need for expensive power inductors.

[0047] During the period when the gate driving unit 405 controls the first NMOS power tube 408 to be turned off and the first PMOS power tube 409 to be turned on, the input current of the battery flows through the path formed by the PCB metal winding parasitic inductance 301 and the first PMOS power tube 409 to one end of the output filter capacitor 303. Since the current flowing through the PCB metal winding parasitic inductance 301 cannot change suddenly, the current of the PCB metal winding parasitic inductance 301 starts to slope down at this time to charge the output filter capacitor 303. Therefore, the voltage at the VH output end of the ASIC control chip unit 302 will continue to rise. When the current slope of the PCB metal winding parasitic inductance 301 drops to zero, the current zero-crossing detection unit 404 will output a high-level current zero-crossing detection signal ZCD to the second input terminal of the gate drive unit 405, and control the gate drive unit 405 to immediately turn off the first PMOS power tube 409 to prevent the current from flowing back from the VH output terminal of the ASIC control chip unit 302 to the input terminal of the battery, thereby causing the voltage of the VH output terminal of the ASIC control chip unit 302 to rise less than the set voltage value. The second PMOS power tube 410 remains on during the enabled operation period of the ASIC control chip unit 302, and remains off during the disabled operation period of the ASIC control chip unit 302, so that the current path from the battery to the OUT output terminal of the ASIC control chip unit 302 can be effectively cut off during the disabled operation period of the ASIC control chip unit 302. As a result, the handwriting erasing control circuit of the liquid crystal handwriting board of the present invention is always operating in a standby state with a very low working current when there is no need to erase handwriting, which greatly prolongs the battery life of the liquid crystal handwriting board. The second NMOS power tube 411 immediately changes from off to on after the enabling work of the dedicated integrated circuit control chip unit 302 is completed, and the voltage at the OUT output end of the dedicated integrated circuit control chip unit 302 is quickly discharged to zero. As a result, the liquid crystal handwriting board can immediately perform subsequent writing actions after the handwriting erasing action is performed, and the written handwriting will not be erased immediately because the voltage at the OUT output end of the dedicated integrated circuit control chip unit 302 is still a high voltage.

[0048] like Figure 5, which is a specific embodiment of the output voltage constant voltage control unit 402 of the present invention. The output voltage constant voltage control unit 402 is composed of a trimming signal control processing unit 500, an EFUSE fuse trimming unit 501, a first switch 502, a second switch 503, a third switch 504, a fourth switch 505, a first resistor 506, a second resistor 507, a third resistor 508, a fourth resistor 509, a fifth resistor 510, a sixth resistor 511, a reference voltage generating unit 512 and a voltage comparator unit 513. The first input end of the trimming signal control processing unit 500 is connected to the SWT input end of the ASIC control chip unit 302; the second input end of the trimming signal control processing unit 500 is connected to the OUT output end of the ASIC control chip unit 302, and is also connected to one end of the first resistor 506; the output end of the trimming signal control processing unit 500 is connected to the input end of the EFUSE fuse trimming unit 501; the first output end of the EFUSE fuse trimming unit 501 is connected to the control end of the first switch 502; the second output end of the EFUSE fuse trimming unit 501 is connected to the control end of the second switch 503; the third output end of the EFUSE fuse trimming unit 501 is connected to the control end of the third switch 504; the fourth output end of the EFUSE fuse trimming unit 501 is connected to the control end of the fourth switch 505; the other end of the first resistor 506 is connected to one end of the second resistor 507, and is also connected to the positive input of the voltage comparator unit 513. end; the other end of the second resistor 507 is connected to one end of the third resistor 508 and is connected to the first output end of the first switch 502; the other end of the third resistor 508 is connected to one end of the fourth resistor 509 and is connected to the second output end of the first switch 502 and the first output end of the second switch 503; the other end of the fourth resistor 509 is connected to one end of the fifth resistor 510 and is connected to the second output end of the second switch 503 and the first output end of the third switch 504; the other end of the fifth resistor 510 is connected to one end of the sixth resistor 511 and is connected to the second output end of the third switch 504 and the first output end of the fourth switch 505; the other end of the sixth resistor 511 is connected to the second output end of the fourth switch 505 and is connected to ground; the negative input end of the voltage comparator unit 513 is connected to the output end of the reference voltage generating unit 512; the output end of the voltage comparator unit 513 is connected to the second input end of the logic control unit 403.

[0049] According to the requirements of handwriting erasing voltage of liquid crystal handwriting tablets of different specifications, the ASIC control chip unit 302 tests and adjusts the output voltage of the OUT output terminal of the ASIC control chip unit 302 during the FT test phase of chip production. During the FT test phase, the SWT input terminal and the OUT output terminal of the ASIC control chip unit 302 will be multiplexed as the two trimming signal input terminals of the trimming signal control processing unit 500, and a corresponding set of timing combination signals will be input according to the requirements of handwriting erasing voltage of liquid crystal handwriting tablets of different specifications. After the trimming signal control processing unit 500 decodes and controls the input set of timing combination signals, it outputs the corresponding logic signal to the EFUSE fuse trimming unit 501. The EFUSE fuse trimming unit 501 energizes and burns the corresponding EFUSE fuse according to the input logic signal, thereby controlling the opening or closing of the first switch 502, the second switch 503, the third switch 504 and the fourth switch 505, and finally controlling the third resistor 508, the fourth resistor 509, the fifth resistor 510 and the sixth resistor 511 to be normally connected to the resistor string or to work in a short-circuit state. Therefore, different resistance voltage division ratios will be obtained. During the enabling operation of the ASIC control chip unit 302, the resistance voltage division network composed of the first resistor 506, the second resistor 507, the third resistor 508, the fourth resistor 509, the fifth resistor 510 and the sixth resistor 511 samples and detects the output voltage of the OUT output terminal of the ASIC control chip unit 302, and inputs the sampled voltage SENSE to the positive input terminal of the voltage comparator unit 513. The sampled voltage V SENSE and the output voltage V OUT The size relationship is as follows:

[0050]

[0051] The reference voltage generating unit 512 outputs the reference voltage REF1 to the negative input terminal of the voltage comparator unit 513. SENSE is greater than the negative input voltage V of the voltage comparator unit 513 REF1 When, that is, when the voltage at the OUT output terminal of the dedicated integrated circuit control chip unit 302 reaches the voltage threshold value set according to the above formula (4), the output terminal of the voltage comparator unit 513 immediately outputs a high-level control signal CTR to the second input terminal of the logic control unit 403, so that the logic control unit 403 stops outputting the logic drive signal DRV with a frequency of 2MHz, and the DRV logic drive signal becomes a low level at this time.

[0052] like Figure 6 As shown, it is the first specific embodiment of the PCB metal winding parasitic inductance 301 of the present invention. The PCB metal winding parasitic inductance 301 performs the topological design of the metal winding parasitic inductance during the layout and wiring design stage of the PCB circuit board, and is produced together with the PCB circuit board. During this period, no special production process and additional production investment are required, so that the parasitic inductance production is zero cost. Figure 6 The first specific embodiment of the PCB metal winding parasitic inductance 301 adopts a topological design of a spiral coil, and the specific parasitic inductance value is related to the pitch of the spiral coil, the number of windings, the metal trace width and the material of the PCB circuit board.

[0053] Figure 7 This is a second specific embodiment of the PCB metal winding parasitic inductance 301. This specific embodiment adopts a topological design of a regular octagonal coil, and the specific parasitic inductance value is related to the line spacing of the regular octagonal coil, the number of windings, the metal trace width, and the material of the PCB circuit board. The actual specific implementation of the PCB metal winding parasitic inductance 301 of the present invention may have many other topological designs of different shapes, that is, not limited to Figure 6 and Figure 7 The proposed spiral coil and regular octagonal coil, the topological design of the PCB metal winding parasitic inductance 301 can also be coils of other shapes. Figure 6 and Figure 7 It is just a preferred specific embodiment of the PCB metal winding parasitic inductance 301 of the present invention.

[0054] The handwriting erasing control circuit for a liquid crystal handwriting tablet of the present invention, based on the high voltage and low current characteristics of the handwriting erasing voltage of the liquid crystal handwriting tablet, and combined with the 2MHz high operating frequency characteristics of the dedicated integrated circuit control chip unit 302, provides an original technical solution of using the PCB metal winding parasitic inductor 301 to replace the traditional discrete power inductor components of the prior art. The technical solution of using the PCB metal winding parasitic inductor 301 is one of the main differences between the handwriting erasing control circuit for a liquid crystal handwriting tablet of the present invention and the traditional prior art solution.

[0055] This specification describes only the preferred embodiments of the present invention, which are used to illustrate the technical solutions of the present invention, but not to limit the protection scope of the present invention. Without departing from the spirit and essence of the present invention, any technical solution obtained by ordinary technicians in this field through logical analysis, reasoning or limited experiments based on the concept of the present invention is still the essence of the present invention. These adjustments and changes should all fall within the protection scope of the claims attached to the present invention.

[0056] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A handwriting erasing control circuit for a liquid crystal handwriting board, characterized in that: It comprises an input filter capacitor (300), a PCB metal winding parasitic inductance (301), a dedicated integrated circuit control chip unit (302), an output filter capacitor (303) and a touch switch (304); The input filter capacitor (300) is used to filter the voltage of the input button battery or lithium-ion battery; The PCB metal winding parasitic inductance (301) is used to perform energy storage conversion on the input current; The dedicated integrated circuit control chip unit (302) is used to perform voltage step-up conversion control on the input battery voltage, and output a high voltage that can meet the handwriting erasing function of the liquid crystal handwriting board; The output filter capacitor (303) is used to filter the high voltage output by the boost conversion and capable of satisfying the handwriting erasing function of the liquid crystal handwriting board; The light touch switch (304) is used to control the handwriting erasing control circuit of the liquid crystal handwriting board to start the step-up conversion operation.

2. The handwriting erasing control circuit for a liquid crystal writing board according to claim 1 is characterized in that: One end of the PCB metal winding parasitic inductance (301) is connected to the SW input end of the ASIC control chip unit (302), and the other end is connected to the VIN input end of the ASIC control chip unit (302), and is also connected to one end of the input filter capacitor (300) and the positive electrode of a button battery or a lithium-ion battery; the other end of the input filter capacitor (300) is connected to the ground; one end of the output filter capacitor (303) is connected to the VH output end of the ASIC control chip unit (302), and the other end is connected to the ground; one end of the touch switch (304) is connected to the SWT input end of the ASIC control chip unit (302), and the other end of the touch switch (304) is connected to the ground; the GND input end of the ASIC control chip unit (302) is connected to the ground, and is also connected to an input electrode of the liquid crystal handwriting board and the negative electrode of the button battery or the lithium-ion battery; the OUT output end of the ASIC control chip unit (302) is connected to another input electrode of the liquid crystal handwriting board.

3. The handwriting erasing control circuit for a liquid crystal writing board according to claim 2 is characterized in that: The dedicated integrated circuit control chip unit (302) comprises: a key detection unit (400), a timing control unit (401), an output voltage constant voltage control unit (402), a logic control unit (403), a current zero-crossing detection unit (404), a gate drive unit (405), a power management unit (406), a frequency oscillator unit (407), a first NMOS power tube (408), a first PMOS power tube (409), a second PMOS power tube (410) and a second NMOS power tube (411); the input end of the key detection unit (400) is connected to the SWT input end of the dedicated integrated circuit control chip unit (302) and is also connected to the first input end of the output voltage constant voltage control unit (402); the output end of the key detection unit (400) is connected to the input end of the timing control unit (401); the output end of the timing control unit (401) is connected to the first input end of the logic control unit (403); the second input end of the output voltage constant voltage control unit (402) is connected to the OUT output end of the dedicated integrated circuit control chip unit (302); The output end of the output voltage constant voltage control unit (402) is connected to the second input end of the logic control unit (403); the first input end of the power management unit (406) is connected to the VIN input end of the dedicated integrated circuit control chip unit (302); the second input end of the power management unit (406) is connected to the VH output end of the dedicated integrated circuit control chip unit (302); the first output end of the power management unit (406) is connected to the input end of the frequency oscillator unit (407); the second output end of the power management unit (406) is connected to the VH output end of the dedicated integrated circuit control chip unit (302); The chip unit (302) provides working power; the output end of the frequency oscillator unit (407) is connected to the third input end of the logic control unit (403); the output end of the logic control unit (403) is connected to the first input end of the gate drive unit (405); the input end of the current zero-crossing detection unit (404) is connected to the SW input end of the dedicated integrated circuit control chip unit (302); the output end of the current zero-crossing detection unit (404) is connected to the second input end of the gate drive unit (405); the first output end of the gate drive unit (405) is connected to the The gate of the first PMOS power tube (409) is connected; the second output end of the gate driving unit (405) is connected to the gate of the second PMOS power tube (410); the third output end of the gate driving unit (405) is connected to the gate of the second NMOS power tube (411); the fourth output end of the gate driving unit (405) is connected to the gate of the first NMOS power tube (408); the drain of the first NMOS power tube (408) is connected to the SW input end of the dedicated integrated circuit control chip unit (302), and is also connected to the first PMOS power tube ( The drain of the first NMOS power tube (408) is connected to the ground; the source of the first PMOS power tube (409) is connected to the VH output terminal of the dedicated integrated circuit control chip unit (302), and is also connected to the source of the second PMOS power tube (410); the drain of the second PMOS power tube (410) is connected to the OUT output terminal of the dedicated integrated circuit control chip unit (302), and is also connected to the drain of the second NMOS power tube (411); the source of the second NMOS power tube (411) is connected to the ground.

4. The handwriting erasing control circuit for a liquid crystal writing board according to claim 3 is characterized in that: The output voltage constant voltage control unit (402) comprises: a trimming signal control processing unit (500), an EFUSE fuse trimming unit (501), a first switch (502), a second switch (503), a third switch (504), a fourth switch (505), a first resistor (506), a second resistor (507), a third resistor (508), a fourth resistor (509), a fifth resistor (510), a sixth resistor (511), a reference voltage generating unit (512) and a voltage comparator unit (513); a first input end of the trimming signal control processing unit (500) is connected to the SWT input end of the dedicated integrated circuit control chip unit (302); the trimming signal control processing unit (500) is connected to the SWT input end of the dedicated integrated circuit control chip unit (302); The second input end of the control unit (500) is connected to the OUT output end of the dedicated integrated circuit control chip unit (302), and is also connected to one end of the first resistor (506); the output end of the trimming signal control processing unit (500) is connected to the input end of the EFUSE fuse trimming unit (501); the first output end of the EFUSE fuse trimming unit (501) is connected to the control end of the first switch (502); the second output end of the EFUSE fuse trimming unit (501) is connected to the control end of the second switch (503); the third output end of the EFUSE fuse trimming unit (501) is connected to the control end of the third switch (504); The fourth output terminal of the regulating unit (501) is connected to the control terminal of the fourth switch (505); the other end of the first resistor (506) is connected to one end of the second resistor (507) and is also connected to the positive input terminal of the voltage comparator unit (513); the other end of the second resistor (507) is connected to one end of the third resistor (508) and is also connected to the first output terminal of the first switch (502); the other end of the third resistor (508) is connected to one end of the fourth resistor (509) and is also connected to the second output terminal of the first switch (502) and the first output terminal of the second switch (503); the other end of the fourth resistor (509) is connected to the fifth resistor (510 ) is connected to one end of the second switch (503) and the first output end of the third switch (504); the other end of the fifth resistor (510) is connected to one end of the sixth resistor (511) and the second output end of the third switch (504) and the first output end of the fourth switch (505); the other end of the sixth resistor (511) is connected to the second output end of the fourth switch (505) and is connected to ground; the negative input end of the voltage comparator unit (513) is connected to the output end of the reference voltage generating unit (512); the output end of the voltage comparator unit (513) is connected to the second input end of the logic control unit (403).

5. The handwriting erasing control circuit for a liquid crystal writing board according to claim 1 is characterized in that: The topology design of the PCB metal winding parasitic inductance (301) is performed during the layout and wiring design stage of the PCB circuit board, and is produced together with the PCB circuit board. The topology design of the PCB metal winding parasitic inductance (301) is a spiral coil or a regular octagonal coil or a coil of other shapes.

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