Power supply circuit, power supply signal generation method, chip and electronic equipment

Abstract

The invention discloses a power supply circuit, a power supply signal generation method, a chip and electronic equipment, and belongs to the technical field of electronic information. The power supply circuit comprises an oscillation module and a phase dislocation module which are connected with each other; the oscillation module is used for generating a plurality of reference clock signals based on an input signal and a plurality of reference signals and transmitting the plurality of reference clock signals to the phase dislocation module, the amplitudes of the plurality of reference signals are different, and the phase difference among the plurality of reference clock signals is determined based on the amplitude difference among the plurality of reference signals; the phase dislocation module is used for generating a plurality of clock control signals according to the plurality of reference clock signals, the plurality of clock control signals are used for controlling clocks of the plurality of power supply signals, and the phase difference among the plurality of power supply signals is determined based on the phase difference among the plurality of reference clock signals. The phase of the power supply signal can be flexibly adjusted, a plurality of power supply signals with different phases are generated, and electromagnetic interference is reduced.

Description

Technical Field

[0001] The present application relates to the field of electronic information technology, and in particular to a power supply circuit, a method for generating a power supply signal, a chip and an electronic device. Background Art

[0002] The power circuit is a circuit that converts the electrical energy of the power supply and transmits it to the load. It can realize functions such as voltage conversion, rectification, filtering, voltage stabilization or overload protection. The power circuit can usually output different power signals to meet the different requirements of different loads connected to the power circuit for power signals.

[0003] When a power supply circuit outputs multiple power supply signals, the phases of the multiple power supply signals need to be different. Otherwise, when the phases of the multiple power supply signals are the same, when the multiple power supply signals with the same phase charge and discharge the connected loads at the same time, it will cause greater electromagnetic interference, thereby affecting the performance of the power supply circuit. Summary of the invention

[0004] The present application provides a power supply circuit, a power supply signal generation method, a chip and an electronic device, which can be used to reduce electromagnetic interference. The technical solution is as follows:

[0005] On the one hand, the present application provides a power supply circuit, which includes an oscillation module and a phase-shifting module connected to each other; the oscillation module is used to generate multiple reference clock signals based on an input signal and multiple reference signals, and transmit the multiple reference clock signals to the phase-shifting module, the multiple reference signals have different amplitudes, and the phase difference between the multiple reference clock signals is determined based on the amplitude difference between the multiple reference signals; the phase-shifting module is used to generate multiple clock control signals based on the multiple reference clock signals, the multiple clock control signals are used to control the clocks of multiple power supply signals, and the phase difference between the multiple power supply signals is determined based on the phase difference between the multiple reference clock signals.

[0006] In a possible implementation, the oscillation module includes multiple oscillation units and an acquisition unit, the multiple oscillation units are connected in parallel and connected to the acquisition unit, the amplitudes of the reference signals corresponding to the multiple oscillation units are different, and the signal flipping times of the multiple reference clock signals are different; the acquisition unit is used to generate an input signal, and the amplitude of the input signal is determined based on the charging and discharging changes of the capacitor in the acquisition unit; the first oscillation unit is used to compare the amplitude of the reference signal corresponding to the first oscillation unit with the amplitude of the input signal, and obtain the reference clock signal according to the comparison result, and the signal flipping time of the reference clock signal is determined based on the comparison result, and the first oscillation unit is any oscillation unit among the multiple oscillation units.

[0007] In one possible implementation, the reference signal corresponding to the first oscillation unit includes a first reference signal and a second reference signal, and the amplitude of the first reference signal is smaller than the amplitude of the second reference signal; the reference clock signal generated by the first oscillation unit flips when the comparison result indicates that the amplitude of the input signal is greater than or less than the amplitude of the first reference signal and the second reference signal.

[0008] In one possible implementation, the phase-shifting module includes multiple phase-shifting units, and the multiple phase-shifting units correspond one-to-one to multiple oscillation units; the first phase-shifting unit is used to generate a clock control signal according to a reference clock signal generated by a corresponding oscillation unit, and the first phase-shifting unit is any phase-shifting unit among the multiple phase-shifting units.

[0009] In one possible implementation, the power supply circuit also includes a frequency jittering module, which is connected to the oscillation module; the frequency jittering module is used to generate a control signal and transmit the control signal to the oscillation module, and the control signal is used to control the amplitude of the input signal; the oscillation module is also used to generate an input signal according to the control signal.

[0010] In one possible implementation, the frequency jittering module includes a generating unit and a frequency dividing unit connected to each other; the generating unit is used to generate a pre-control signal and transmit the pre-control signal to the frequency dividing unit; the frequency dividing unit is used to divide the pre-control signal to obtain a control signal, and the control signal includes multiple signals with different frequencies.

[0011] In one possible implementation, the frequency division unit includes multiple delay (Delay, D) triggers, the signal output by the previous D trigger of two adjacent D triggers is the signal received by the next D trigger, and the control signal includes the signals output by multiple D triggers; the first D trigger is used to divide the received signal to obtain an output signal, the frequency of the output signal is less than the frequency of the received signal, and the received signal is generated based on the pre-control signal, and the first D trigger is any D trigger among the multiple D triggers.

[0012] On the other hand, the present application provides a method for generating a power supply signal, the method comprising: generating multiple reference clock signals based on an input signal and multiple reference signals, the amplitudes of the multiple reference signals being different, and the phase difference between the multiple reference clock signals being determined based on the amplitude difference between the multiple reference signals; generating multiple clock control signals based on the multiple reference clock signals, the multiple clock control signals being used to control the clocks of multiple power supply signals, and the phase difference between the multiple power supply signals being determined based on the phase difference between the multiple reference clock signals.

[0013] In one possible implementation, the method is applied to a power signal generating device, which includes multiple oscillation units, the amplitudes of reference signals corresponding to the multiple oscillation units are different, and the signal flipping times of the multiple reference clock signals are different; multiple reference clock signals are generated based on an input signal and multiple reference signals, including: generating an input signal, the amplitude of the input signal continuously changes; through a first oscillation unit, comparing the amplitude of the reference signal corresponding to the first oscillation unit with the amplitude of the input signal, obtaining a reference clock signal according to the comparison result, the signal flipping time of the reference clock signal is determined based on the comparison result, and the first oscillation unit is any oscillation unit among the multiple oscillation units.

[0014] In one possible implementation, the reference signal corresponding to the first oscillation unit includes a first reference signal and a second reference signal, and the amplitude of the first reference signal is smaller than the amplitude of the second reference signal; the reference clock signal generated by the first oscillation unit flips when the comparison result indicates that the amplitude of the input signal is greater than or less than the amplitude of the first reference signal and the second reference signal.

[0015] In a possible implementation, the method further includes: generating a control signal, where the control signal is used to control the amplitude of the input signal; generating the input signal includes: generating the input signal according to the control signal.

[0016] In a possible implementation, generating a control signal includes: generating a pre-control signal; dividing the frequency of the pre-control signal to obtain a control signal, wherein the control signal includes a plurality of signals with different frequencies.

[0017] In one possible implementation, a power signal generating device includes multiple D flip-flops, a signal output by a previous D flip-flop of two adjacent D flip-flops is a signal received by a subsequent D flip-flop, and a control signal includes signals output by multiple D flip-flops; the received signal is frequency-divided by a first D flip-flop to obtain an output signal, the frequency of the output signal is less than the frequency of the received signal, the received signal is generated based on a pre-control signal, and the first D flip-flop is any D flip-flop among the multiple D flip-flops.

[0018] On the other hand, the present application provides a chip, which includes any possible power supply circuit mentioned above.

[0019] On the other hand, the present application provides an electronic device, which includes any possible power supply circuit described above.

[0020] The technical solution provided by this application brings at least the following beneficial effects:

[0021] The amplitudes of the multiple reference signals in the present application are different, so the oscillation module performs signal flipping at different times based on the magnitude relationship between the input signal and different reference signals, and the flipping time determines the position of the rising edge and the falling edge of the reference clock signal. The positions of the rising edge and the falling edge of the generated multiple reference clock signals are different, that is, the phases of the multiple reference clock signals are different. Therefore, the phase-shifting module can generate multiple clock control signals with different phases according to multiple reference clock signals with different phases to control the clocks of multiple power supply signals and realize the phase shifting of multiple power supply signals. And by adjusting the amplitude difference between the multiple reference signals, the phase difference between the different power supply signals can be adjusted, so as to realize the flexible adjustment of the power supply signal, avoid the generation of power supply signals with the same phase, and the number of power supply signals with different phases that can be generated is also greater. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 It is a structural schematic diagram of a multi-channel power supply circuit provided by the related technology;

[0024] Figure 2 It is a signal schematic diagram of a multi-channel power supply circuit provided by the related technology;

[0025] Figure 3 is a structural schematic diagram of a power supply circuit provided in an embodiment of the present application;

[0026] Figure 4 is a structural schematic diagram of another power supply circuit provided in an embodiment of the present application;

[0027] Figure 5 is a structural schematic diagram of another power supply circuit provided in an embodiment of the present application;

[0028] Figure 6 is a schematic diagram of a signal provided in an embodiment of the present application;

[0029] Figure 7 is a structural schematic diagram of another power supply circuit provided in an embodiment of the present application;

[0030] Figure 8 is a structural schematic diagram of another power supply circuit provided in an embodiment of the present application;

[0031] Fig. 9 is a structural schematic diagram of a frequency jitter module provided in an embodiment of the present application;

[0032] Fig.10 is a schematic diagram of a frequency relationship of a signal provided in an embodiment of the present application;

[0033] Fig.11 is a schematic diagram of a frequency jitter parameter provided in an embodiment of the present application;

[0034] Fig.12 It is a flow chart of a method for generating a power signal provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0036] In electronic devices, since various circuit modules or devices and other loads have different requirements for power signals, the power chip in the electronic device is required to provide different and stable power signals for each load to meet the requirements of different loads for power signals.

[0037] The power chip usually integrates circuits such as switching power supply circuit, low dropout regulator (LDO), charge pump and gamma (GAMA) circuit. Among them, the switching power supply circuit is, for example, a direct current-direct current (DC-DC) conversion circuit such as buck (BUCK), boost (BOOST) or buck-boost conversion (BUCK-BOOST). The switching power supply circuit usually has the characteristics of high efficiency, low power consumption, high current load capacity, large voltage input and output range and high stability. The switching power supply circuit includes a power tube, which controls the switching action of the power signal. When the power tube controls the switch to be turned on, the switching power supply circuit outputs the power signal corresponding to the switch. When the power tube controls the switch to be turned off, the switching power supply circuit stops outputting the power signal corresponding to the switch.

[0038] During the operation of the switching power supply circuit, an oscillator is needed to control the frequency of the power tube switch, thereby controlling the oscillation frequency of the power signal. For example, a pulse width modulation (PWM) type switching power supply circuit generally operates at a fixed switching frequency, so an oscillator is needed to control the frequency of the power tube switch at a fixed frequency to achieve stable operation of the switching power supply circuit.

[0039] Since the multiple power signals output by the switching power supply circuit are oscillating signals, there is a risk of electromagnetic interference (EMI) when the switching power supply circuit outputs multiple power signals. There are two types of electromagnetic interference: conducted interference and radiated interference. Conducted interference refers to the coupling of a signal on an electrical network to another electrical network through a conductive medium. Radiated interference refers to the coupling of an interference source to another electrical network through space. In the switching power supply circuit, these two types of interference are manifested as: noise is coupled to other circuits through cables in the form of differential mode and common mode noise, and noise is radiated to space in the form of electromagnetic waves through the loop formed by the integrated circuit and the cable. When the switching power supply circuit outputs multiple power signals, the circuits in the switching power supply circuit for outputting multiple power signals will affect each other due to the generation of electromagnetic interference, and the more circuits that output power signals, the greater the risk of electromagnetic interference.

[0040] For example, in a multi-channel switching power supply circuit, if the channels corresponding to multiple power supply signals are charged and discharged at the same time, that is, the power supply signals corresponding to the multiple channels enter the high level state and the low level state at the same time, a very large surge current will be generated, which will burn out the power supply chip. In addition, simultaneous charging and discharging will also aggravate the impact of electromagnetic interference, thereby reducing the performance of the power supply chip. The impact of electromagnetic interference will also increase with the increase in the number of channels charged and discharged at the same time.

[0041] Therefore, in the field of electronic information technology, multiple power signals are usually processed in phase, staggering the time when multiple power signals enter the high level state and the low level state, reducing the generated surge current and thus reducing the impact of electromagnetic interference.

[0042] For example, see Figure 1 , shows a schematic diagram of the structure of a multi-channel power supply circuit provided by the related art. In this circuit, a DC current source provides a stable current I to a capacitor C for charging the capacitor C. After the circuit is powered on, an initial enable voltage ( Figure 1(not shown in the figure). Since CMP outputs a low-level voltage signal (or represented by 0) when the input voltage signal is greater than the reference voltage (Voltage reference, Vref), and outputs a high-level voltage signal (or represented by 1) when the input voltage signal is less than Vref, when the input enable voltage is greater than Vref, CMP outputs a low-level voltage signal. CMP inputs a low-level voltage signal to the not and gate (NAND) 1, that is, the input signal a of NAND1 is a low-level voltage signal. In addition, after power-on, the initial input signal d of NAND2 is a low-level voltage signal, and the voltage signal output by NAND2 is a high-level voltage signal. The voltage signal output by NAND2 is the input signal b of NAND1, the input signal b of NAND1 is a high-level voltage signal, and the input signal a is a low-level voltage signal, so after the not and operation, NAND1 outputs a high-level voltage signal.

[0043] The electrical signal output by NAND1 is the gate input electrical signal of the switch M1. When the gate input electrical signal of the switch M1 is a high-level voltage signal, the switch M1 is turned on, the capacitor C is short-circuited in parallel by the switch M1, the capacitor C is discharged, the charge on the capacitor C is cleared, and the ramp voltage (voltage ramp, Vramp) at the high potential end of the capacitor C is at a low level.

[0044] When the enable signal fails, CMP compares Vramp and Vref. At this time, Vramp is low and less than Vref, so CMP outputs a high voltage signal, and the input signal a of NAND1 is a high voltage signal. At this time, the input signal b of NAND1 is also a high voltage signal. After the AND operation, NAND1 outputs a low voltage signal. The gate of switch M1 inputs a low voltage signal, switch M1 is disconnected, and the current I provided by the DC current source charges the capacitor C. The Vramp at the high potential end of the capacitor C gradually increases. Among them, the charging formula of capacitor C is the following formula (1), where I is the current I provided by the DC current source, C is the size of the capacitor C, V is Vramp, and t is the charging time.

[0045]

[0046] Until Vramp increases to a value greater than Vref, the high-level voltage signal output by CMP is flipped to a low-level voltage signal, and NAND1 outputs a high-level voltage signal again. Switch M1 is turned on again, capacitor C is discharged again, and Vramp gradually decreases until Vramp decreases to a value less than Vref. Figure 2As shown in the signal schematic diagram of the multi-channel power supply circuit provided by the related art, the size of Vramp changes between the two endpoint values ​​greater than or equal to Vref and 0 as the capacitor C is charged and discharged. Among them, the size of Vramp changes to 0 because there is a delay between NAND1 and M1. When it is determined that NAND1 outputs a low level to the time when M1 is disconnected, the capacitor C is still discharging continuously, and the delay time is enough for the capacitor to clear the charge. In this way, NAND1 continuously flips between outputting a high-level voltage signal and a low-level voltage signal.

[0047] The voltage signal output by NAND1 is a pulse signal. However, since the signal in NAND1 may jitter due to instability when flipping, the signal output by NAND1 is not a standard pulse signal. Therefore, the signal output by NAND1 can be input into pulse generator 1, and pulse generator 1 de-jitters the signal output by NAND1 to output a standard pulse signal.

[0048] The signal output by the pulse generator 1 is adjusted by the frequency of the D flip-flop and inverted by the NOT gate to generate the clock signal CLKA. The clock signal CLKA is input into the phase-shifting circuit of the multi-channel power supply circuit. The pulse generator 2 and the pulse generator 3 in the phase-shifting circuit respectively generate the clock signal CLK1 and the clock signal CLK2 based on the clock signal CLKA. The clock signal CLK1 and the clock signal CLK2 are respectively used to generate power supply signals of different channels. Since the pulse generator 2 and the pulse generator 3 can only generate clock signals in the same phase or in the opposite phase to the clock signal CLKA, the clock signal CLK1 and the clock signal CLK2 can only be in phase or out of phase by 180°. Since the phase of the power supply signal generated based on the clock signal CLK1 is the same as the phase of the clock signal CLK1, and the phase of the power supply signal generated based on the clock signal CLK2 is the same as the phase of the clock signal CLK2, the multiple power supply signals generated by the related technology can only be in phase or out of phase by 180°.

[0049] If the related technology generates three or more power signals, there will be power signals with the same phase among the multiple power signals. The power signals with the same phase are in a high level state or a low level state at the same time, which will increase the impact of electromagnetic interference. Therefore, in order to avoid generating greater electromagnetic interference, the related technology usually only generates two or three power signals. It can be seen that the number of power signals generated by the related technology is limited, and the phase difference between each power signal is fixed.

[0050] However, the small amount of power signals generated by the related technology can no longer meet the demand for more and more power signals, so there is an urgent need for a power circuit that can generate more power signals with different phases.

[0051] The embodiment of the present application provides a power supply circuit that can flexibly adjust the phase of a power supply signal, generate multiple power supply signals with different phases, and reduce electromagnetic interference. The power supply circuit can be a multi-channel switching power supply circuit, and the power supply circuit can be located in the power supply chip of various electronic devices. Figure 3 , shows a schematic diagram of the structure of a power supply circuit provided by an embodiment of the present application, the power supply circuit includes an oscillation module 11 and a phase-shifting module 12 connected to each other. The oscillation module 11 is used to generate multiple reference clock signals based on an input signal and multiple reference signals, and transmit the multiple reference clock signals to the phase-shifting module 12; the phase-shifting module 12 is used to generate multiple clock control signals based on the multiple reference clock signals. Among them, the amplitudes of the multiple reference signals are different, the phase difference between the multiple reference clock signals is determined based on the amplitude difference between the multiple reference signals, the multiple clock control signals are used to control the clocks of the multiple power supply signals, and the phase difference between the multiple power supply signals is determined based on the phase difference between the multiple reference clock signals.

[0052] The following describes the oscillation module 11 and the phase shift module 12 to explain the principle that the amplitudes of multiple reference signals affect the phase differences between multiple reference clock signals, and further affect the phase differences between multiple power supply signals.

[0053] See also Figure 4 The structural schematic diagram of another power supply circuit provided by an embodiment of the present application is shown, and the oscillation module 11 includes multiple oscillation units 110 and an acquisition unit 111. The multiple oscillation units 110 are connected in parallel and connected to the acquisition unit 111. The amplitudes of the reference signals corresponding to the multiple oscillation units 110 are different, and the signal flipping times of the multiple reference clock signals are different. The acquisition unit 111 is used to generate an input signal. Among them, the input signal can be a signal at the high potential end of the capacitor in the acquisition unit 111, and the amplitude of the input signal is determined based on the charge and discharge changes of the capacitor in the acquisition unit 111. When the capacitor in the acquisition unit 111 is charged, the amplitude of the input signal continues to rise, and when the capacitor in the acquisition unit 111 is discharged, the amplitude of the input signal continues to decrease.

[0054] The first oscillation unit 110 is used to compare the amplitude of the reference signal corresponding to the first oscillation unit 110 with the amplitude of the input signal, and obtain a reference clock signal according to the comparison result. The signal flip time of the reference clock signal is determined based on the comparison result. The first oscillation unit 110 is any oscillation unit 110 among the multiple oscillation units 110.

[0055] Exemplarily, the reference signal corresponding to the first oscillation unit 110 includes a first reference signal and a second reference signal, and the amplitude of the first reference signal is smaller than the amplitude of the second reference signal; the reference clock signal generated by the first oscillation unit 110 flips when the comparison result indicates that the amplitude of the input signal is greater than or less than the amplitude of the first reference signal and the second reference signal.

[0056] See also Figure 5 , shows a schematic diagram of the structure of another power supply circuit provided by an embodiment of the present application, in which the acquisition unit 111 includes multiple DC power supplies, including a DC power supply connected in series with a capacitor and a DC power supply connected in parallel with the capacitor. The DC power supply connected in series with the capacitor is used to charge the capacitor, and the DC power supply connected in parallel with the capacitor is used to discharge the capacitor. In the process of charging the capacitor, the switch S is closed, the switch SN which is in phase with the switch S is disconnected, the DC power supply connected in series with the capacitor charges the capacitor, and the amplitude of the input signal continues to rise. In the process of discharging the capacitor, the switch S is disconnected, the switch SN is closed, the capacitor is discharged through the grounded wire and the DC power supply connected in parallel with the capacitor, and the amplitude of the input signal continues to decrease. The oscillation unit 110 compares the input signal with the corresponding reference signal, and generates a reference clock signal based on the comparison result.

[0057] For example, see Figure 6 A schematic diagram showing the signals and Figure 5 , CMP1 in the first oscillation unit 110 compares the input signal with the reference signal V1, the input signal is connected to the negative electrode of CMP1, and the reference signal V1 is connected to the positive electrode of CMP1. When the input signal is greater than the reference signal V1, CMP1 outputs a low level, and when the input signal is less than the reference signal V1, CMP1 outputs a high level. CMP2 compares the input signal with the reference signal V2, the input signal is connected to the positive electrode of CMP2, and the reference signal V2 is connected to the negative electrode of CMP2. When the input signal is greater than the reference signal V2, CMP2 outputs a high level, and when the input signal is less than the reference signal V2, CMP2 outputs a low level. The reference signal V2 is the first reference signal corresponding to the first oscillation unit 110, the reference signal V1 is the second reference signal corresponding to the first oscillation unit 110, the comparison result corresponding to the first oscillation unit 110 includes the levels of the signals output by CMP1 and CMP2, and the reference clock signal CLKA is the reference clock signal generated by the first oscillation unit 110.

[0058] During the initial charging of the capacitor, the input signal increases continuously. When the input signal is less than both the reference signal V2 and the reference signal V1, CMP1 outputs a high level, CMP2 outputs a low level, and NAND2 outputs a high level, that is, the reference clock signal CLKA is a high level. The signal b1 is a high level, the signal a1 is a high level, and NAND1 outputs a low level. The signal S is a low level, the switch S is closed and turned on, the signal SN is a high level, the switch SN is disconnected, and the capacitor continues to charge.

[0059] When the input signal increases to be greater than the reference signal V2 and less than the reference signal V1, CPM2 outputs a high level, that is, the signal d1 is a high level, the signal c1 is the same as the output of NAND1, which is a low level, NAND2 maintains the output high level unchanged, and the reference clock signal CLKA maintains the high level unchanged.

[0060] The signal S output by NAND1 is low level, the switch S is still in the closed conduction state, and the capacitor continues to charge. When the input signal is greater than the reference signal V1 and the reference signal V2 at the same time, CMP1 outputs a low level, that is, the signal a1 is low level, so NAND1 outputs a high level, the signal c1 becomes high level, CMP2 continues to output a high level, the signal d1 is high level, NAND2 flips from outputting a high level to outputting a low level, and the reference clock signal CLKA becomes low level. In addition, the signal b1 becomes low level, NAND1 outputs a high level, and the signal c1 remains high level unchanged.

[0061] As the signal S becomes high, the switch S is turned off, the signal SN is low, the switch SN is turned on, the capacitor starts to discharge, and the amplitude of the input signal decreases. When the input signal drops to less than the reference signal V1 and greater than the reference signal V2, the signal a1 output by CPM1 becomes high, and the signal b1 is low at this time, so the signal S output by NAND1 remains high, the signals c1 and d1 are both high, NAND2 continues to output low, and the reference clock signal CLKA remains low.

[0062] The capacitor continues to discharge and the input signal continues to decrease. When the input signal is less than the reference signal V1 and the reference signal V2 at the same time, CMP2 outputs a low level, NAND2 flips from outputting a low level to outputting a high level, and at the same time, the reference clock signal CLKA flips from a low level to a high level.

[0063] It can be seen from this that the reference clock signal generated by the first oscillation unit 110 is flipped when the comparison result indicates that the input signal is simultaneously greater than the two reference signals corresponding to the first oscillation unit 110, and is flipped when the comparison result indicates that the input signal is simultaneously less than the two reference signals corresponding to the first oscillation unit 110.

[0064] CMP3 in the second oscillation unit 110 compares the input signal with the reference signal V3. The input signal is connected to the negative electrode of CMP3, and the reference signal V3 is connected to the positive electrode of CMP3. When the input signal is greater than the reference signal V3, CMP3 outputs a low level. When the input signal is less than the reference signal V3, CMP3 outputs a high level. CMP4 compares the input signal with the reference signal V4. The input signal is connected to the positive electrode of CMP4, and the reference signal V4 is connected to the negative electrode of CMP4. When the input signal is greater than the reference signal V4, CMP4 outputs a high level. When the input signal is less than the reference signal V4, CMP4 outputs a low level. The reference signal V4 is the first reference signal corresponding to the second oscillation unit 110, and the reference signal V3 is the second reference signal corresponding to the second oscillation unit 110. The comparison result corresponding to the second oscillation unit 110 includes the levels of the signals output by CMP3 and CMP4. The reference clock signal CLKC is the reference clock signal generated by the first oscillation unit 110.

[0065] The process of the second oscillation unit 110 generating the reference clock signal CLKC based on the input signal and the first reference signal and the second reference signal can refer to the process of the first oscillation unit generating the reference clock signal CLKA based on the input signal and the first reference signal and the second reference signal. The reference clock signal generated by the second oscillation unit 110 is flipped when the comparison result indicates that the input signal is greater than the two reference signals corresponding to the second oscillation unit 110 at the same time, and is flipped when the comparison result indicates that the input signal is less than the two reference signals corresponding to the 21st oscillation unit 110 at the same time.

[0066] Based on the above examples and Figure 6 It can be known that the phase difference between the two reference clock signals generated by any two oscillation units 110 is approximately the phase difference corresponding to the time when the input signal changes from an amplitude greater than the second reference signal corresponding to one of the oscillation units 110 to an amplitude greater than the second reference signal corresponding to the other oscillation unit 110, or is approximately the phase difference corresponding to the time when the input signal changes from an amplitude less than the first reference signal corresponding to one of the oscillation units 110 to an amplitude less than the first reference signal corresponding to the other oscillation unit 110.

[0067] For example, when the input signal is less than the first reference signal (i.e., reference signal V2) corresponding to the first oscillation unit 110, the reference clock signal CLKA generated by the first oscillation unit 110 flips from a low level to a high level; when the input signal is less than the first reference signal (i.e., reference signal V4) corresponding to the second oscillation unit 110, the reference clock signal CLKC generated by the second oscillation unit 110 flips from a low level to a high level. The time difference between the reference clock signal CLKA and the reference clock signal CLKC flipping in the same direction determines the phase difference between the reference clock signal CLKA and the reference clock signal CLKC.

[0068] Therefore, the embodiment of the present application can flexibly adjust the time difference for flipping the reference clock signals generated by each oscillation unit 110 by controlling the amplitude difference of the reference signals corresponding to each oscillation unit 110, thereby adjusting the phase difference between each reference clock signal. For example, when selecting reference signals V1 to V4, the larger reference signal V1 of reference signal V1 and reference signal V2 needs to be different from the larger reference signal V3 of reference signal V3 and reference signal V4. Similarly, reference signal V2 also needs to be different from reference signal V4, so that the time for flipping the reference clock signals generated by different oscillation units 110 in the same direction is different. For example, reference signal 1 is 5V, reference signal 2 is 2V, reference signal 3 is 4V, reference signal 4 is 3V, reference signal V1 is different from reference signal V3, and reference signal V2 is different from reference signal V4. The size of each reference signal can be set based on actual conditions.

[0069] In one possible implementation, see Figure 4 The phase-shifting module 12 includes multiple phase-shifting units 120, and the multiple phase-shifting units 120 correspond one-to-one to the multiple oscillation units 110; the first phase-shifting unit 120 is used to generate a clock control signal according to a reference clock signal generated by the corresponding oscillation unit 110, and the first phase-shifting unit 120 is any phase-shifting unit 120 among the multiple phase-shifting units 120.

[0070] Further, after receiving the reference clock signal, the first phase-shifting unit 120 may generate one or more clock control signals based on the reference clock signal, and the one or more clock control signals are used to control the clock of the power signal, that is, to control the signal information (or signal parameters) such as the frequency, phase and duty cycle of the power signal. The phases of the multiple clock control signals generated by the first phase-shifting unit 120 based on the reference clock signal are different. For example, the first phase-shifting unit 120 may generate a clock control signal with the same phase as the reference clock signal and a clock control signal with an opposite phase to the reference clock signal through two pulse generators.

[0071] Continue to see Figure 5and Figure 6 The first phase-shifting unit 120 connected to the first oscillation unit 110 includes a pulse generator 1 and a pulse generator 2. The pulse generator 1 generates a clock control signal CKL1 in phase with the reference clock signal CLKA according to the reference clock signal CLKA, and the pulse generator 2 generates a clock control signal CLK2 in phase opposite to the reference clock signal CLKA according to the reference clock signal CLKA. The clock control signal CLK1 controls the switch of the power signal 1 of the channel 1, so that the power signal 1 of the channel 1 has the same frequency and phase as the clock control signal CLK1. The clock control signal CLK2 controls the switch of the power signal 2 of the channel 2, so that the power signal 2 of the channel 2 has the same frequency and phase as the clock control signal CLK2. Since the clock control signal CLK1 and the clock control signal CLK2 are in phase opposite, the power signal 1 and the power signal 2 are in phase opposite.

[0072] The second phase-shifting unit 120 connected to the second oscillation unit 110 includes a pulse generator 3. The pulse generator 3 generates a clock control signal CKL3 in phase or in phase with the reference clock signal CLKC according to the reference clock signal CLKC. The clock control signal CLK3 controls the switch of the power signal 3 of the channel 3, so that the power signal 3 of the channel 3 has the same frequency and phase as the clock control signal CLK3. Since the phases of the clock control signal CLK3, the clock control signal CLK1 and the clock control signal CLK2 are different, the phases of the power signal 3, the power signal 1 and the power signal 2 are all different.

[0073] Above Figure 5 and Figure 6 The principle of the power supply circuit provided in the embodiment of the present application generating multiple power supply signals with different phases is illustrated by taking the generation of three power supply signals with different phases as an example. However, the power supply circuit provided in the embodiment of the present application can generate more power supply signals with different phases by setting more reference signals with different amplitudes.

[0074] In one possible implementation, see Figure 7 The schematic diagram of the structure of another power supply circuit provided by an embodiment of the present application is shown, and the power supply circuit also includes a frequency jittering module 13, and the frequency jittering module 13 is connected to the oscillation module 11. The frequency jittering module 13 is used to generate a control signal and transmit the control signal to the oscillation module 11. The control signal is used to control the amplitude of the input signal; the oscillation module 11 is also used to generate an input signal according to the control signal. Among them, the control signal can control the size of the signal input to the oscillation module 11, thereby controlling the size and change rate of the input signal generated by the oscillation module 11.

[0075] Optionally, the control signal may include one or more signals to achieve different granularity control of the input signal. Figure 5Taking the power supply circuit shown as an example, the control signal may include multiple signals, and the multiple signals in the control signal can respectively control the switches on the circuits of multiple DC power supplies connected in series with capacitors that input signals to the oscillation module 11, thereby fine-grainedly controlling the size of the signal input to the oscillation module 11.

[0076] In the case where the control signal includes multiple signals, the multiple signals included in the control signal may be pulse signals, and the frequencies of the multiple signals may be the same or different. Figure 8 The schematic diagram of the structure of another power supply circuit provided by an embodiment of the present application is shown, and the frequency jitter module 13 includes a generating unit 131 and a frequency dividing unit 132 connected to each other. The generating unit 131 is used to generate a pre-control signal and transmit the pre-control signal to the frequency dividing unit 132; the frequency dividing unit 132 is used to divide the pre-control signal to obtain a control signal, and the control signal includes a plurality of signals with different frequencies.

[0077] The pre-control signal generated by the generating unit 131 may be a pulse signal, and the embodiment of the present application does not limit the frequency of the pre-control signal. After acquiring the pre-control signal, the frequency dividing unit 132 may divide the pre-control signal in different ways, for example, the frequency dividing unit 132 may divide the pre-control signal by a trigger or a counter to obtain a plurality of signals with different frequencies.

[0078] Taking the frequency division unit 132 dividing the pre-control signal by a counter as an example, the counter can receive the pre-control signal and count the number of pulses input to the counter one by one. When the count reaches a specific value, the counter is reset and a pulse signal is output. The frequency of the pulse signal output by the counter is less than the frequency of the pre-control signal. For example, if the specific value is 3, the counter outputs 1 pulse when it receives 3 pulses in the pre-control signal, so the frequency of the signal output by the counter is one third of the pre-control signal.

[0079] The frequency division unit 132 can divide the pre-control signal through multiple counters to output multiple signals with different frequencies. Multiple counters can be connected in parallel or in series. If multiple counters are connected in parallel, the signal input to the multiple counters is the pre-control signal. Different specific values ​​are set for different counters, so that the frequencies of the signals output by different counters can be different. If multiple counters are connected in parallel, the multiple counters successively divide the pre-control signal in multiple stages to output multiple signals with different frequencies.

[0080] Next, the principle of the frequency division of the frequency division unit 132 is explained by taking the frequency division unit 132 dividing the pre-control signal through the trigger as an example. The D flip-flop implements the flipping of the level of the output signal based on the effective trigger edge (rising edge or falling edge). Between two effective trigger edges, the level of the signal output by the D flip-flop does not change. When the D flip-flop receives a valid trigger edge again, the D flip-flop flips the level of the output signal to implement the output of the pulse signal.

[0081] For example, the effective trigger edge of the D flip-flop is the rising edge. When the input D flip-flop receives the first rising edge, the D flip-flop outputs a high-level signal. When the D flip-flop receives a falling edge, the output signal value will not change. Instead, when the D flip-flop receives a rising edge again, the D flip-flop flips the output signal and outputs a low-level signal. When the D flip-flop receives a rising edge for the third time, the D flip-flop flips the output signal again and outputs a high-level signal. It can be seen that after the signal received by the D flip-flop is flipped twice, the signal output by the D flip-flop is flipped once. Therefore, the frequency of the signal output by the D flip-flop is less than the frequency of the received signal, and the frequency of the output signal is half of the frequency of the received signal.

[0082] See also Figure 8 The frequency division unit 132 includes multiple D flip-flops 1320, and the multiple D flip-flops 1320 are used to perform multi-level frequency division on the pre-control signal. The signal output by the previous D flip-flop 1320 of two adjacent D flip-flops 1320 is the signal received by the next D flip-flop 1320, and the control signal includes the signals output by the multiple D flip-flops 1320.

[0083] Taking the first D flip-flop 1320 as an example, the first D flip-flop 1320 is used to divide the frequency of the received signal to obtain an output signal. The frequency of the output signal is less than the frequency of the received signal. The received signal is generated based on the pre-control signal. The first D flip-flop 1320 is any D flip-flop 1320 among multiple D flip-flops 1320.

[0084] For example, the frequency dividing unit 132 includes three D flip-flops 1320 , namely a first D flip-flop 1320 , a second D flip-flop 1320 , and a third D flip-flop 1320 . The signal received by the first D flip-flop 1320 is the pre-control signal, and the first D flip-flop 1320 divides the pre-control signal to obtain the first output signal, and the frequency of the first output signal is half of the frequency of the pre-control signal; the signal received by the second D flip-flop 1320 is the first output signal, and the second D flip-flop 1320 divides the first output signal to obtain the second output signal, and the frequency of the second output signal is half of the frequency of the first output signal, and the frequency of the second output signal is one quarter of the pre-control signal; the signal received by the third D flip-flop 1320 is the second output signal, and the third D flip-flop 1320 divides the second output signal to obtain the third output signal, and the frequency of the third output signal is half of the second output signal, and the frequency of the third output signal is one eighth of the pre-control signal. In this way, three signals with different frequencies are obtained through the three D flip-flops 1320. The principle of frequency division of the received signal by each D flip-flop 1320 can be found above and will not be repeated here.

[0085] The control signal may include a plurality of signals with different frequencies generated by the frequency division unit 132. The plurality of signals with different frequencies jointly control the input signal, thereby achieving frequency jittering of the input signal. Fig. 9 , which shows a schematic diagram of the structure of a frequency jitter module 13 provided in an embodiment of the present application. The process of the generation unit 131 generating the signal output by NAND1 can be referred to Figure 1 The process of generating the signal output by NAND1 is not described here. After generating the signal output by NAND1, the generating unit 131 de-jitters the signal output by NAND1 through the pulse generator, and inverts it to obtain the pre-control signal. The pre-control signal is transmitted to the frequency division unit. Each D flip-flop 1320 in the frequency division unit performs multi-level frequency division on the pre-control signal to realize the division of the pre-control signal into two, four and eight, and obtains the signals Q0, Q1 and Q2 respectively. The frequency relationship of the signals Q0, Q1 and Q2 is as follows: Fig.10 shown.

[0086] See also Fig.11 , shows a schematic diagram of a frequency jitter parameter provided in an embodiment of the present application, Fig.11 It is shown in Fig. 9 The frequency jittering parameters of the control signal generated by the frequency division unit 132, the control signal includes signals Q2, Q1, Q0, the signals Q2, Q1, Q0 are flipped according to their respective frequencies to form a frequency jittering law, so that the control signal is based on the center frequency and realizes frequency jittering within the jittering amplitude and jittering period constrained by the signals Q2, Q1, Q0.

[0087] For example, when signals Q2, Q1, and Q0 are all at high levels, the frequency of the generated control signal is relatively high, which is the frequency indicated by 111. Since signal Q0 is the signal with the highest frequency among signals Q2, Q1, and Q0, the state of signal Q0 changes the fastest, from a high level to a low level, and the frequency of the generated control signal decreases, which is the frequency indicated by 110. The frequency of signal Q1 is half the frequency of signal Q0, so when the state of signal Q0 changes for the second time, the state of signal Q1 changes for the first time, and the frequency of the control signal decreases again, becoming the frequency indicated by 101. By analogy, the frequency of the control signal changes continuously, which forms frequency jitter.

[0088] The control signal can control the current size of the capacitor in the oscillation module 11 to charge and discharge the capacitor, thereby obtaining a frequency jittering frequency that changes within a certain frequency period and frequency amplitude. Figure 5 , signals Q2, Q1, and Q0 respectively control the switches on the circuits of the three DC power supplies connected in series with the capacitor. When the input switch signal is high, the switch is closed and the signal output by the DC power supply can be used to charge the capacitor. When the input switch signal is low, the switch is disconnected and the DC power supply cannot input a signal to the capacitor. Since the signals Q2, Q1, and Q0 in the control signal flip based on different frequencies, the number of closed and turned-on switches keeps changing, and thus the current size for charging the capacitor keeps changing.

[0089] For example, when the signals Q2, Q1, and Q0 in the control signal are all at a high level, the switches on the circuits of the three DC power supplies are all closed and turned on, and the three DC power supplies input signals to the capacitor together, and the current charging the capacitor is relatively large; when the signal Q0 flips to a low level, the switch corresponding to the signal Q0 is disconnected, and the remaining two DC power supplies input signals to the capacitor, and the current charging the capacitor is relatively small; when the signals Q1 and Q0 are both low levels, and the signal Q2 is high, the DC power supply corresponding to the signal Q2 inputs a signal to the power supply, and the current charging the capacitor is even smaller. The current charging the capacitor changes continuously, and the rate of change of the input signal also changes continuously, achieving jitter.

[0090] Based on the following formula (2), it can be seen that the capacitance of the capacitor determines the jitter frequency of the input signal, and the charge and discharge current determines the jitter amplitude of the input signal. Therefore, the frequency of the input signal generated based on the control signal jitters around the center frequency as the capacitor charges and discharges and the current flowing through the capacitor. Among them, F in formula (2) is the frequency of the input signal, I is the current flowing through the capacitor, C is the size of the capacitor, and V is the size of the input signal.

[0091] F=I / CV (2)

[0092] When the frequency jittering technology is used, the discrete frequency spectrum of the generated control signal is distributed within a certain frequency band, so that the frequency spectrum of each reference clock signal generated based on the control signal tends to be continuous within some frequency bands and undergoes pseudo-random changes, thereby reducing the impact of electromagnetic interference between power supply signals corresponding to different reference clock signals.

[0093] In summary, the amplitudes of the multiple reference signals in the present application are different, so the oscillation module performs signal flipping at different times based on the magnitude relationship between the input signal and different reference signals, and the flipping time determines the position of the rising edge and the falling edge of the reference clock signal. The positions of the rising edge and the falling edge of the generated multiple reference clock signals are different, that is, the phases of the multiple reference clock signals are different. Therefore, the phase-shifting module can generate multiple clock control signals with different phases according to multiple reference clock signals with different phases to control the clocks of multiple power supply signals and realize the phase shifting of multiple power supply signals. And by adjusting the amplitude difference between the multiple reference signals, the phase difference between the different power supply signals can be adjusted, so as to realize the flexible adjustment of the power supply signal, avoid the generation of power supply signals with the same phase, and the number of power supply signals with different phases that can be generated is also greater.

[0094] In addition, the present application can also reduce the impact of electromagnetic interference through frequency jittering technology, so that the power signal generated by the power supply circuit can provide stable power supply for multiple loads.

[0095] In an exemplary embodiment, a method for generating a power signal is also provided, the method including but not limited to: Fig.12 S1201 to S1202 shown.

[0096] S1201, generating multiple reference clock signals based on an input signal and multiple reference signals, wherein the multiple reference signals have different amplitudes, and the phase difference between the multiple reference clock signals is determined based on the amplitude difference between the multiple reference signals.

[0097] In one possible implementation, the method is applied to a power signal generating device, which includes multiple oscillation units, the amplitudes of reference signals corresponding to the multiple oscillation units are different, and the signal flipping times of the multiple reference clock signals are different; multiple reference clock signals are generated based on an input signal and multiple reference signals, including: generating an input signal, the amplitude of the input signal continuously changes; through a first oscillation unit, comparing the amplitude of the reference signal corresponding to the first oscillation unit with the amplitude of the input signal, obtaining a reference clock signal according to the comparison result, the signal flipping time of the reference clock signal is determined based on the comparison result, and the first oscillation unit is any oscillation unit among the multiple oscillation units.

[0098] Optionally, the reference signal corresponding to the first oscillation unit includes a first reference signal and a second reference signal, the amplitude of the first reference signal is smaller than the amplitude of the second reference signal; the reference clock signal generated by the first oscillation unit flips when the comparison result indicates that the amplitude of the input signal is greater than or less than the amplitude of the first reference signal and the second reference signal.

[0099] S1202, generating multiple clock control signals according to multiple reference clock signals, wherein the multiple clock control signals are used to control the clocks of multiple power supply signals, and the phase difference between the multiple power supply signals is determined based on the phase difference between the multiple reference clock signals.

[0100] Optionally, the method further includes: generating a control signal, the control signal being used to control the amplitude of the input signal; generating the input signal includes: generating the input signal according to the control signal.

[0101] The generating of the control signal includes: generating a pre-control signal; dividing the frequency of the pre-control signal to obtain the control signal, wherein the control signal includes a plurality of signals with different frequencies.

[0102] In one possible implementation, a power signal generating device includes multiple D flip-flops, a signal output by a previous D flip-flop of two adjacent D flip-flops is a signal received by a subsequent D flip-flop, and a control signal includes signals output by multiple D flip-flops; the received signal is frequency-divided by a first D flip-flop to obtain an output signal, the frequency of the output signal is less than the frequency of the received signal, the received signal is generated based on a pre-control signal, and the first D flip-flop is any D flip-flop among the multiple D flip-flops.

[0103] The implementation process and effect of the method for generating a power signal provided in the embodiment of the present application can refer to the description in the embodiment of the above-mentioned power circuit, and will not be repeated here.

[0104] In an exemplary embodiment, a chip is further provided, the chip comprising any possible power supply circuit provided in the above power supply circuit embodiment. The chip may be a power supply chip.

[0105] In an exemplary embodiment, an electronic device is further provided. The electronic device includes any possible power supply circuit provided in the above power supply circuit embodiments.

[0106] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions. For example, the signals involved in this application are all obtained with full authorization.

[0107] It should be understood that the "plurality" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0108] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A power supply circuit, characterized in that: The power supply circuit comprises an oscillation module (11) and a phase-shifting module (12) which are connected to each other; The oscillation module (11) is used to generate a plurality of reference clock signals based on an input signal and a plurality of reference signals, and transmit the plurality of reference clock signals to the phase shifting module (12), wherein the plurality of reference signals have different amplitudes, and the phase difference between the plurality of reference clock signals is determined based on the amplitude difference between the plurality of reference signals; The phase-shifting module (12) is used to generate a plurality of clock control signals according to the plurality of reference clock signals, wherein the plurality of clock control signals are used to control the clocks of a plurality of power supply signals, and the phase difference between the plurality of power supply signals is determined based on the phase difference between the plurality of reference clock signals.

2. The power supply circuit according to claim 1, characterized in that: The oscillation module (11) comprises a plurality of oscillation units (110) and an acquisition unit (111); the plurality of oscillation units (110) are connected in parallel and connected to the acquisition unit (111); the amplitudes of reference signals corresponding to the plurality of oscillation units (110) are different; and the signal flip times of the plurality of reference clock signals are different; The acquisition unit (111) is used to generate the input signal, wherein the amplitude of the input signal is determined based on the charge and discharge changes of the capacitor in the acquisition unit (111); A first oscillation unit (110) is used to compare the amplitude of a reference signal corresponding to the first oscillation unit (110) with the amplitude of the input signal, and obtain a reference clock signal according to the comparison result, wherein the signal flip time of the reference clock signal is determined based on the comparison result, and the first oscillation unit (110) is any oscillation unit (110) among the multiple oscillation units (110).

3. The power supply circuit according to claim 2, characterized in that: The reference signal corresponding to the first oscillation unit (110) includes a first reference signal and a second reference signal, the amplitude of the first reference signal being smaller than the amplitude of the second reference signal; the reference clock signal generated by the first oscillation unit (110) flips when the comparison result indicates that the amplitudes of the input signals are both greater than or both smaller than the amplitudes of the first reference signal and the second reference signal.

4. The power supply circuit according to claim 2 or 3, characterized in that: The phase-shifting module (12) comprises a plurality of phase-shifting units (120), and the plurality of phase-shifting units (120) correspond one-to-one to the plurality of oscillation units (110); A first phase-shifting unit (120) is used to generate a clock control signal according to a reference clock signal generated by a corresponding oscillating unit (110); the first phase-shifting unit (120) is any phase-shifting unit (120) among the multiple phase-shifting units (120).

5. The power supply circuit according to any one of claims 1 to 4, characterized in that: The power supply circuit further comprises a frequency jittering module (13), wherein the frequency jittering module (13) is connected to the oscillation module (11); The frequency jittering module (13) is used to generate a control signal and transmit the control signal to the oscillation module (11), wherein the control signal is used to control the amplitude of the input signal; The oscillation module (11) is further used to generate the input signal according to the control signal.

6. The power supply circuit according to claim 5, characterized in that: The frequency jittering module (13) comprises a generating unit (131) and a frequency dividing unit (132) which are connected to each other; The generating unit (131) is used to generate a pre-control signal and transmit the pre-control signal to the frequency dividing unit (132); The frequency division unit (132) is used to divide the frequency of the pre-control signal to obtain the control signal, wherein the control signal includes a plurality of signals with different frequencies.

7. The power supply circuit according to claim 6, characterized in that: The frequency division unit (132) includes a plurality of delay triggers (1320), the signal output by the previous delay trigger (1320) of two adjacent delay triggers (1320) is the signal received by the next delay trigger (1320), and the control signal includes the signals output by the plurality of delay triggers (1320); A first delay trigger (1320) is used to divide the frequency of a received signal to obtain an output signal, wherein the frequency of the output signal is less than the frequency of the received signal, and the received signal is generated based on the pre-control signal. The first delay trigger (1320) is any delay trigger (1320) among the multiple delay triggers (1320).

8. A method for generating a power signal, characterized in that: The method comprises: generating a plurality of reference clock signals based on an input signal and a plurality of reference signals, the plurality of reference signals having different amplitudes, and phase differences between the plurality of reference clock signals being determined based on amplitude differences between the plurality of reference signals; A plurality of clock control signals are generated according to the plurality of reference clock signals, the plurality of clock control signals being used to control clocks of a plurality of power supply signals, and phase differences between the plurality of power supply signals are determined based on phase differences between the plurality of reference clock signals.

9. A chip, characterized in that: The chip comprises a power supply circuit as described in any one of claims 1 to 7 above.

10. An electronic device, characterized in that: The electronic device comprises a power supply circuit as described in any one of claims 1 to 7 above.

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