Semiconductor device

Abstract

The invention relates to a semiconductor device. The reliability of a semiconductor device is improved. A resistive element Rg is filled in a trench TR formed in a well region PW of a semiconductor substrate. The resistor element Rg and the trench TR have an endless ring shape in plan view. The resistive element Rg is connected to a first contact member PG electrically connected to the gate pad GP and a second contact member PG electrically connected to the gate wiring GW. Further, a third contact member PG, which electrically connects the emitter electrode EE to the well region PW, is positioned in the Y direction in a region surrounded by the endless ring-shaped resistance element Rg between the first contact member PG and the second contact member PG.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-141068 filed on August 31, 2023, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device, and more particularly, to a semiconductor device provided with a resistance element electrically connected to a gate pad. Background Art

[0004] As a power device, an insulated gate bipolar transistor (IGBT) having a vertical trench gate structure is known. In a semiconductor device (semiconductor chip) equipped with a power device, a resistance element is connected to a gate pad as part of a protection circuit to protect the semiconductor device from a surge voltage applied to the gate pad.

[0005] For example, Japanese Patent Publication No. 2022-82244 (Patent Document 1) discloses a semiconductor device equipped with an IGBT and a resistance element connected to a gate pad. The resistance element is formed on a polysilicon film provided on a semiconductor substrate via an insulating film (silicon oxide film). Summary of the invention

[0006] For example, in a motor control system using a three-phase motor, an IGBT is used as a driver of the motor. The emitter electrode of the high-side IGBT and the collector electrode of the low-side IGBT are connected in series.

[0007] As disclosed in Patent Document 1, defects may occur in the p-type (second conductivity type) collector region formed on the lower surface of the semiconductor substrate of the high-side IGBT due to damage during cutting and other reasons. In this case, when the low-side IGBT switches at high speed, impact ionization occurs in the high-side IGBT, and carriers (holes) are emitted to the surface side of the semiconductor substrate.

[0008] That is, when an emitter potential higher than the collector electrode potential is applied to the emitter electrode, the body diode works and a large number of carriers are generated in the semiconductor substrate. In this state, the potential application is changed, and if a collector potential higher than the emitter electrode potential is applied to the collector region, holes are emitted to the upper surface side of the semiconductor substrate. Due to the remaining carriers, increasing the collector potential makes it difficult for the depletion layer to diffuse in the semiconductor substrate. Further increasing the collector potential makes the inside of the semiconductor substrate a high electric field, resulting in impact ionization. The holes generated by impact ionization are emitted to the surface side of the semiconductor substrate.

[0009] At this time, a high potential rise occurs in the p-type well region near the resistor element for the gate pad. Due to this high potential rise, there is a problem of insulation breakdown occurring in the silicon oxide film formed under the resistor element.

[0010] The inventors of the present application have studied an IGBT in which a groove is formed in a p-type well region, and a resistance element for a gate is formed in the groove with a thin silicon oxide film inserted therein. The thin silicon oxide film has the same film thickness as the gate insulating film of the IGBT. Compared with the technology described in Patent Document 1, the parasitic resistance of the p-type well region in the groove forming portion increases, resulting in a higher potential rise in the p-type well region. In addition, because the film thickness of the silicon oxide film separating the resistance element and the p-type well region is thin, insulation breakdown of the silicon oxide film is more likely to occur. Therefore, there is a problem of reliability degradation of the semiconductor device.

[0011] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0012] An outline of a typical embodiment among the embodiments disclosed in the present application is briefly explained as follows.

[0013] A semiconductor device according to an embodiment includes a semiconductor substrate of a first conductivity type having a first main surface, and a gate pad, a gate wiring, and an emitter electrode are formed on the first main surface, and a well region of a second conductivity type different from the first conductivity type is formed on the first main surface, and a groove is formed in the well region in an endless ring shape in a plan view, and in the groove, a resistance element is formed in an endless ring shape in a plan view and filled with an insulating film. In addition, the semiconductor device includes: a first contact member connected to the resistance element; a second contact member located at a predetermined distance from the first contact member in a first direction, and connected to the resistance element, the first direction being a longitudinal direction of the resistance element; and a third contact member located between the first contact member and the second contact member in a first direction in a plan view, located in a region surrounded by an inner circumference of the resistance element, and connected to the well region. The gate pad is electrically connected to the resistance element via the first contact member, the gate wiring is electrically connected to the resistance element via the second contact member, and the emitter electrode is electrically connected to the well region via the third contact member.

[0014] According to one embodiment, the reliability of a semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a plan view showing the entire semiconductor device in the first embodiment.

[0016] Figure 2 is an equivalent circuit diagram of the semiconductor device in the first embodiment.

[0017] Figure 3 is a main portion plan view showing the semiconductor device in the first embodiment.

[0018] Figure 4 is a main portion plan view showing the semiconductor device in the first embodiment.

[0019] Figure 5 is a cross-sectional view showing the semiconductor device in the first embodiment.

[0020] Figure 6 is a cross-sectional view showing the semiconductor device in the first embodiment.

[0021] Figure 7 is a cross-sectional view showing the semiconductor device in the first embodiment.

[0022] Figure 8 is a cross-sectional view showing the semiconductor device in the first embodiment.

[0023] Fig. 9 is a main portion plan view showing the semiconductor device in the second embodiment.

[0024] Fig.10 is a principal part plan view showing the semiconductor device in the third embodiment.

[0025] Fig.11 is a principal part plan view showing the semiconductor device in the fourth embodiment.

[0026] Fig.12 is a principal part plan view showing the semiconductor device in the fifth embodiment.

[0027] Hereinafter, the embodiments are described in detail with reference to the accompanying drawings. In all the drawings used to explain the embodiments, the same reference numerals represent the same or similar parts, and their repeated description is omitted. In addition, in the following embodiments, the description of the same or similar parts is not repeated unless particularly necessary.

[0028] also, Figure 3 , Figure 4 , Fig. 9 , Fig.10 , Fig.11 ,and Fig.12 In some parts, the vertical relationship between elements is not accurately shown to facilitate understanding of the shapes of the elements.

[0029] In addition, Figure 4 , Fig. 9 , Fig.10 , Fig.11 ,and Fig.12In the figure numerals, for simplicity, CH3 (PG) is represented as CH3, and CH4 (PG) is represented as CH4. DETAILED DESCRIPTION

[0030] (First embodiment)

[0031] <Structure of semiconductor devices>

[0032] The following will use Figures 1 to 8 A semiconductor device 100 in the first embodiment is described.

[0033] Figure 1 1 is a plan view showing a semiconductor chip which is a semiconductor device 100 .

[0034] like Figure 1 As shown, the semiconductor device 100 includes a cell region 1A and a peripheral region 1B. The cell region 1A has a plurality of cells constituting an IGBT formed therein. The plurality of cells are divided into, for example, three cell groups, and a plurality of IGBTs in each cell group are covered by an emitter electrode EE. Figure 1 As shown, three emitter electrodes EE formed on the first main surface SUBa of the semiconductor substrate SUB extend in the X direction and are spaced apart in the Y direction. The X direction and the Y direction are directions intersecting each other.

[0035] In the peripheral region 1B, a gate pad GP, a gate wiring GW, and a resistor element region RGA are provided. The gate wiring GW is positioned to surround the three emitter electrodes EE, the gate pad GP, and the portion around the resistor element region RGA, except for the side opposite to the gate pad GP of the emitter electrode EE. The three emitter electrodes EE are connected to each other on the side opposite to the gate pad GP. In addition, the gate wiring GW crosses in the X direction between adjacent emitter electrodes EE in the Y direction and is connected to the ring-shaped gate wiring GW. Figure 1 As shown, the gate pad GP and the resistance element area RGA are formed in a region surrounded by the gate wiring GW and the emitter electrode EE. The resistance element area RGA has a resistance element Rg formed therein, which will be described later, and the gate pad GP and the gate wiring GW are electrically connected through the resistance element Rg.

[0036] Although not shown, on the first main surface SUBa of the semiconductor substrate SUB, outside the gate wiring GW, an annular field plate is formed in a plurality of layers surrounding the annular gate wiring GW. The emitter electrode EE, the gate pad GP, the gate wiring GW, and the field plate are formed by patterning a metal layer in the same manufacturing process on the interlayer insulating film IL described later. Therefore, in a plan view, each of the emitter electrode EE, the gate pad GP, and the gate wiring GW is separated from each other without overlapping. The field plate located at the innermost circumference among the field plates is integrated with the emitter electrode EE at the portion where the three emitter electrodes EE are connected to each other on the side opposite to the gate pad GP, and is separated from the gate wiring GW without overlapping.

[0037] Although not shown, the emitter electrode EE, the gate pad GP, the gate wiring GW, and the resistance element sub-region RGA are covered by a protective film such as a polyimide film. On a portion of each of the emitter electrode EE and the gate pad GP, openings OPE and OPG are formed in the protective film. External connection terminals are connected to the portions of the emitter electrode EE and the gate pad GP exposed from the openings OPE and OPG, thereby electrically connecting the semiconductor device 100 to a lead frame, another semiconductor chip, or a wiring substrate. The external connection terminals are, for example, bonding wires made of gold, copper, or aluminum, or clips made of a copper plate.

[0038] Figure 2 is an equivalent circuit diagram of the semiconductor device 100. Figure 2 As shown, the IGBT includes a gate electrode GE1, a collector region PC, and an emitter region NE. The collector electrode CE is connected to the collector region PC, and the emitter electrode EE is connected to the emitter region NE. The gate electrode GE1 is electrically connected to the gate pad GP via the resistance element Rg. Specifically, the gate electrode GE1 is connected to the resistance element Rg via the gate wiring GW, and the gate pad GP is connected to the resistance element Rg via the gate pad wiring GPW.

[0039] <IGBT Structure>

[0040] Figure 3 It is a plan view of the main parts of the cell region 1A and the peripheral region 1B. Figure 5 It is along Figure 3 Cross-sectional view along line AA. Figure 6 It is along Figure 3 1A is a cross-sectional view of the semiconductor device 100 along the line BB. The cell region 1A of the semiconductor device 100 has active cells AC for performing the main operation of the IGBT, and passive cells IAC other than the active cells AC. Figure 3, the shapes of multiple trenches TR (gate electrodes GE1, GE2 and resistor element Rg), holes CH1, CH2, CH3 and CH4 (contact structure PG), emitter electrode EE, gate pad GP, gate pad wiring GPW, gate wiring GW, and well region PW are shown.

[0041] like Figure 3 As shown, in the cell area 1A, a plurality of trenches TR extend in the Y direction and are adjacent to each other in the X direction. In the trench TR of the active cell AC, a gate electrode GE1 is formed. In the trench TR of the passive cell IAC, a gate electrode GE2 is formed. The gate trench is composed of the trench TR formed in the active cell AC and the gate electrode GE1 formed therein. The emitter trench is composed of the trench TR formed in the passive cell IAC and the gate electrode GE2 formed therein.

[0042] The pair of adjacent gate electrodes GE1 of the active cell AC extends into the peripheral region 1B in the Y direction and is electrically connected to the gate wiring GW via the contact member PG formed in the hole CH3. During the operation of the IGBT, the gate potential is provided to the pair of gate electrodes GE1. The gate electrode GE2 of the passive cell IAC is electrically connected to the emitter electrode EE via the contact member PG formed in the hole CH2, and the emitter potential is provided during the operation of the IGBT.

[0043] like Figure 5 As shown, the semiconductor device 100 includes a semiconductor substrate SUB having a first main surface (upper surface) SUBa and a second main surface (lower surface) SUBb. The semiconductor substrate SUB is of n-type (first conductivity type). It is composed of silicon and has a drift region NV. Here, the n-type semiconductor substrate SUB itself constitutes the drift region NV. The semiconductor substrate SUB can also be a laminate composed of an n-type silicon substrate and an n-type silicon layer grown on the silicon substrate by an epitaxial growth method while introducing phosphorus (P). In this case, the n-type silicon layer having an impurity concentration lower than that of the n-type silicon substrate constitutes the drift region NV.

[0044] On the second main surface SUBb side of the semiconductor substrate SUB, an n-type field stop region (impurity region) NS is formed in the semiconductor substrate SUB. The impurity concentration of the field stop region NS is higher than the impurity concentration of the drift region NV. The field stop region NS is provided to suppress the extension of the depletion layer from the pn junction on the upper surface side of the semiconductor substrate SUB so as not to reach the p-type collector region PC during the turn-off period of the IGBT.

[0045] On the second main surface SUBb side of the semiconductor substrate SUB, a p-type collector region (impurity region) PC is formed in the semiconductor substrate SUB. The collector region PC is located below the field stop region NS.

[0046] Under the second main surface SUBb of the semiconductor substrate SUB, a collector electrode CE is formed. The collector electrode CE is electrically connected to the collector region PC and provides a collector potential to the collector region PC. The collector electrode CE may be a single metal film such as a gold (Au) film, a nickel (Ni) film, a titanium (Ti) film, or an aluminum silicon (AlSi) film, or a laminated metal film appropriately laminated with these. The field stop region NS, the collector region PC, and the collector electrode CE are formed not only in the cell region 1A but also in the peripheral region 1B, and span the entire semiconductor substrate SUB.

[0047] On the first main surface SUBa side of the semiconductor substrate SUB, a trench TR is formed in the semiconductor substrate SUB. The trench TR penetrates the emitter region NE and the base region PB and reaches the inside of the semiconductor substrate SUB. The depth of the trench TR is, for example, 2 micrometers or more and 5 micrometers or less.

[0048] In the trench TR, a gate insulating film GI is formed. In the trench TR, gate electrodes GE1 and GE2 are filled through the gate insulating film GI. The gate insulating film GI is, for example, a silicon oxide film. The gate electrodes GE1 and GE2 are conductive films, for example, polysilicon films (polycrystalline silicon films) into which n-type impurities are introduced. The thickness of the gate insulating film GI is, for example, 70 nanometers or more and 150 nanometers or less.

[0049] On the first main surface SUBa side of the semiconductor substrate SUB of the active cell AC, a hole barrier region (impurity region) NHB is formed in the semiconductor substrate SUB between the pair of trenches TR (pair of gate electrodes GE1). The impurity concentration of the hole barrier region NHB is higher than that of the drift region NV.

[0050] In the hole barrier region NHB, a p-type base region (impurity region) PB is formed. In the p-type base region PB, an n-type emitter region (impurity region) NE is formed. The impurity concentration of the emitter region NE is higher than the impurity concentration of the drift region NV. The base region PB is formed to be shallower than the depth of the trench TR and the emitter region NE.

[0051] It is formed to be shallower than the depth of the base region PB. Figure 5 As shown, a plurality of emitter regions NE are formed between the pair of trenches TR (the pair of gate electrodes GE1 ), and the base region PB located below the emitter region NE is used as a channel region.

[0052] On the first main surface SUBa of the semiconductor substrate SUB of the passive cell IAC, a hole barrier region NHB is formed in the semiconductor substrate SUB between the paired trenches TR (paired gate electrodes GE2). In addition, in the semiconductor substrate SUB between the gate electrodes GE1 and GE2, a p-type floating region (impurity region) PF is formed. In the passive cell IAC, the floating region PF is formed in the semiconductor substrate SUB of the cell area 1A, not between the paired trenches TR. The p-type base region PB is formed in the hole barrier region NHB and in the floating region PF. The depth of the floating region PF from the first main surface SUBa is slightly deeper than the depth of the trench TR from the first main surface SUBa.

[0053] The floating region PF and the base region PB formed in the floating region PF are not electrically connected to the gate wiring GW and the emitter electrode EE, and are in an electrically floating state.

[0054] In the active cell AC and the passive cell IAC, an interlayer insulating film IL is formed on the first main surface SUBa of the semiconductor substrate SUB so as to cover each trench TR. The interlayer insulating film IL is, for example, a silicon oxide film. The thickness of the interlayer insulating film IL is, for example, 600nm or more and 1500nm or less. In addition, the interlayer insulating film IL is subjected to a planarization process to flatten the upper surface of the interlayer insulating film IL.

[0055] In the active cell AC, the hole CH1 penetrates the interlayer insulating film IL and the emitter region NE and reaches the inside of the base region PB. The hole CH1 is formed to contact the emitter region NE and the base region PB.

[0056] In the passive cell IAC, the hole CH2 penetrates the interlayer insulating film IL and reaches the inside of the base region PB. In addition, the hole CH2 is formed to overlap the gate electrode GE2 in a plan view. Therefore, in the passive cell IAC, the hole CH2 is formed to contact the gate electrode GE2 and the base region PB.

[0057] In the active cell AC and the passive cell IAC, a p-type high concentration diffusion region (impurity region) PR is formed around the bottom of the base region PB of the holes CH1 and CH2. The impurity concentration of the high concentration diffusion region PR is higher than that of the base region PB. The high concentration diffusion region PR is provided mainly to reduce the contact resistance with the contact member PG.

[0058] In each of the holes CH1 and CH2, a contact member PG is filled. The contact member PG includes a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a laminated film of a titanium film and a titanium nitride film formed on the titanium film. The conductive film is, for example, a tungsten film. The emitter electrode EE is formed on the interlayer insulating film IL.

[0059] The emitter electrode EE is electrically connected to the emitter region NE, the base region PB, the high concentration diffusion region PR, and the gate electrode GE2 via the contact member PG, thereby providing an emitter potential to these regions. Although not shown here, the gate wiring GW, the gate pad wiring GPW, and the gate pad GP formed in the same manufacturing process as the emitter electrode EE are also formed on the interlayer insulating film IL. The gate wiring GW is electrically connected to the gate electrode GE1 via the contact member PG filled in the hole CH3, thereby providing a gate potential to the gate electrode GE1.

[0060] The emitter electrode EE, the gate wiring GW, the gate pad wiring GPW, and the gate pad GP include a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a titanium tungsten (TiW) film. The conductive film is, for example, an aluminum alloy film to which copper or silicon is added. The aluminum alloy film is a main conductor film for the emitter electrode EE and the gate wiring GW, and is sufficiently thicker than the titanium tungsten (TiW) film.

[0061] like Figure 3 As explained, the pair of gate electrodes GE1 are interconnected and electrically connected to the gate wiring GW in the peripheral region 1B. Figure 6 As shown, a well region PW is provided in the peripheral region 1B, and the well region PW is a p-type semiconductor region. The gate electrode GE1 formed in the trench TR provided in the well region PW is electrically connected to the gate wiring GW via the contact member PG formed in the hole CH3. The well region PW is formed in the same process as the floating region PF in the cell region 1A, and therefore has the same depth as the floating region PF. However, in a plan view, the well region PW and the floating region PF are physically separated.

[0062] <Resistor element and its surrounding structure>

[0063] Figure 4 yes Figure 3 A plan view of the resistor element area RGA is shown. Figure 7 It is along Figure 4 Cross-sectional view along line CC. Figure 8 It is along Figure 4 A cross-sectional view of line DD in FIG. Figure 3 , Figure 4 , Figure 7 and Figure 8 To describe the resistor element and its surrounding structure.

[0064] like Figure 1 As shown, in the semiconductor device 100, two resistor element regions RGA are formed in the Y direction and are located on the sides of the gate pad GP. Figure 3 FIG. 2 shows the structure of the resistor element region RGA located below the gate pad GP. FIG. 2 shows the structure of the resistor element region RGA located above the gate pad GP. Figure 3The structures shown are the same, and the two resistance element regions RGA are symmetrical in the Y direction about the X axis passing through the center of the gate pad GP.

[0065] like Figure 3 As shown, the semiconductor device 100 includes the above-mentioned cell region 1A and a peripheral region 1B adjacent to the cell region 1A in the X direction. In a plan view, the peripheral region 1B is formed in the well region PW. At the boundary region between the cell region 1A and the peripheral region 1B, the emitter electrode EE formed in the cell region 1A extends into the peripheral region 1B and is electrically connected to the well region PW through the contact member PG formed in the hole CH4. For example, in Figure 3 In the central part of the well region PW, the well region PW is electrically connected to the emitter electrode EE through the contact member PG formed in the elongated hole CH4 in the Y direction. Therefore, the area where the emitter electrode EE is electrically connected to the well region PW through the contact member PG is called a well feed section. In other words, the carriers (holes) generated by the aforementioned impact ionization enter the well region PW and flow to the emitter electrode EE through the well feed section. Therefore, the farther away from the well feed section, the greater the potential rise of the well region PW.

[0066] like Figure 3 As shown, in the Y direction, the peripheral area 1B includes a gate pad GP, a resistor element area RGA located below the gate pad GP, and a gate wiring GW located below the resistor element area RGA. In a plan view, the gate pad GP has a quadrilateral shape (square or rectangular, etc.), and its central portion has an opening OPG. The gate pad wiring GPW is connected to the gate pad GP and extends to the resistor element area RGA. The gate pad wiring GPW is a wiring extending from the gate pad GP, and the width of the gate pad wiring GPW is less than the length of the side of the gate pad GP (for example, the side from which the gate pad wiring GPW extends). The gate wiring GW is located around the gate pad GP and the resistor element area RGA, and extends to the resistor element area RGA.

[0067] In a plan view, the resistance element region RGA is formed in the well region PW. The resistance element region RGA includes a plurality of resistance elements Rg, a plurality of emitter electrodes EE (sometimes referred to as wiring), a gate pad wiring GPW, and a gate wiring GW. As will be described later, the resistance element Rg is filled in the trench TR through the gate insulating film GI. Figure 3 In the description of FIG. 1 , the trench TR filled with the gate electrode GE1 is referred to as a gate trench, but the trench TR filled with the resistance element Rg may be referred to as a resistor trench.

[0068] like Figure 4As shown, in a plan view, the resistor element Rg has an inner circumference and an outer circumference, with the Y direction as the long direction and the X direction as the short direction, thereby forming a ring. It can also be said that the resistor element Rg has an endless ring shape. The resistor element Rg extends in the Y direction and includes two linear portions SP separated in the X direction, and two folding portions WP connecting the two linear portions SP. For example, the two linear portions SP extending in the Y direction are parallel to each other in the X direction, and each of the two folding portions WP has a convex ring shape (arc shape) extending away from the linear portion SP. A plurality of resistor elements Rg are positioned at predetermined intervals in the X direction. Figure 3 and Figure 4 Four resistance elements Rg are shown. Figure 4 As shown, in a plan view, the resistance element Rg and the trench TR have the same shape, and thus the description of the planar shape of the resistance element Rg may be replaced with the description of the planar shape of the trench TR.

[0069] like Figure 4 As shown, in a plan view, the gate pad wiring GPW and the gate wiring GW extend in the X direction and are positioned at predetermined intervals in the Y direction, thereby intersecting with a plurality of resistance elements Rg. Although not limited, the gate pad wiring GPW and the gate wiring GW intersect with the linear portion SP of the resistance element Rg. At the intersection of the gate pad wiring GPW and the resistance element Rg, the resistance element Rg is electrically connected to the gate pad wiring GPW through a contact member PG formed in a hole CH3. Similarly, at the intersection of the gate wiring GW and the resistance element Rg, the resistance element Rg is electrically connected to the gate wiring GW through a contact member PG formed in the hole CH3. The region of the resistance element Rg between the contact member PG connected to the gate pad wiring GPW and the contact member PG connected to the gate wiring GW is a resistance region. As shown in FIG. Figure 8 As shown, in the resistor trench, the resistor element Rg is filled in the trench TR formed in the well region PW through the gate insulating film GI. The thickness of the gate insulating film GI of the resistor trench is equal to the thickness of the gate insulating film GI of the above-mentioned gate trench. In addition, the depth of the trench TR of the resistor trench is equal to the depth of the trench TR of the above-mentioned gate trench. Figure 8 As shown, the gate pad wiring GPW and the gate wiring GW are connected to the resistance element Rg through the contact member PG, respectively. The contact member PG is filled in the hole CH3 that penetrates the interlayer insulating film IL formed on the first main surface SUBa of the semiconductor substrate SUB. Figure 4As shown, two resistance areas are formed in the resistance element Rg, and the two resistance areas are connected in parallel between the gate pad wiring GPW and the gate wiring GW. Since there are four resistance elements Rg located in the resistance element area RGA, eight resistance areas are connected in parallel between the gate pad wiring GPW and the gate wiring GW. However, the number of resistance elements Rg and the number of resistance areas can be freely selected. It should be noted that when a linear resistance element with two ends is used instead of an endless ring resistance element Rg, the inventors of the present application have confirmed that a reduction in breakdown voltage or degradation over time occurs at both ends of the resistance element Rg. Therefore, by using an endless ring-shaped resistance element Rg, a reduction in breakdown voltage and degradation over time between the resistance element Rg and the well region PW can be prevented.

[0070] like Figure 3 and Figure 4 As shown, in the resistor element region RGA, three emitter electrodes EE extend in the X direction and are positioned at predetermined intervals in the Y direction, thereby intersecting with a plurality of resistor elements Rg. For the sake of explanation, the three emitter electrodes EE are referred to as a first emitter electrode EE, a second emitter electrode EE, and a third emitter electrode EE. That is, in the resistor element region RGA, in the Y direction, the first emitter electrode EE, the gate pad wiring GPW, the second emitter electrode EE, the gate wiring GW, and the third emitter electrode EE are positioned in this order from the gate pad GP side. In the Y direction, the first emitter electrode EE is located between the gate pad GP and the gate pad wiring GPW, the second emitter electrode EE is located between the gate pad wiring GPW and the gate wiring GW, and the third emitter electrode EE is located on the opposite side of the second emitter electrode EE relative to the gate wiring GW. That is, in the Y direction, the first emitter electrode EE and the second emitter electrode EE are separated by the gate pad wiring GPW, and the second emitter electrode EE and the third emitter electrode EE are separated by the gate wiring GW. Each of the three emitter electrodes EE is electrically connected to the well region PW through a contact member PG formed in a hole CH4 located in a region surrounded by the inner circumference of the endless ring-shaped resistance element Rg and in a region adjacent to the outer circumference.

[0071] like Figure 7As shown, the resistance element Rg is filled in the trench TR formed in the well region PW through the gate insulating film GI. In the Z direction, a plurality of trenches TR extend from the first main surface SUBa of the semiconductor substrate SUB toward the inside of the semiconductor substrate SUB (in other words, toward the second main surface SUBb). Here, the Z direction is perpendicular to the first main surface SUBa. The depth of the trench TR is shallower than the depth of the well region PW, but there is a thin well region PW below the trench TR. Compared with the thickness of the well region PW in the area without the trench TR, the thickness of the well region PW below the trench TR is very thin. In addition, in the Z direction, the impurity concentration at the bottom of the well region PW is lower than the impurity concentration at the surface or middle of the well region PW. This is because the well region PW is formed from the first main surface SUBa side using ion implantation and thermal diffusion. That is, the parasitic resistance of the well region PW located below the trench TR is higher than the parasitic resistance at the surface or middle of the well region PW. Therefore, in the X direction, there is a possibility of a potential difference between the well regions PW on both sides of the trench TR. In the presented embodiment 1, as Figure 7 As shown, in the X direction, in the regions on both sides of the trench TR, the well region PW is electrically connected to the second emitter electrode EE through the contact member PG filled in the hole CH4. Therefore, the potential difference of the well region PW in the regions on both sides of the trench TR in the X direction is reduced.

[0072] Similarly, in the X direction, in the regions on both sides of the trench TR, the well region PW is electrically connected to the first emitter electrode EE through the contact member PG filled in the hole CH4. In addition, in the X direction, in the regions on both sides of the trench TR, the well region PW is electrically connected to the third emitter electrode EE through the contact member PG filled in the hole CH4. In other words, by placing the contact member PG filled in the hole CH4 in the region surrounded by the inner circumference of the endless ring-shaped resistance element Rg and in the region adjacent to the outer circumference, and connecting the well region PW to the emitter electrode EE, the potential difference in the regions on both sides of the trench TR in the well region PW is reduced. In addition, this prevents the breakdown of the gate insulating film GI in the trench TR filled with the resistance element Rg.

[0073] like Figure 4 As shown, the lengths of the plurality of holes CH4 and the contact members PG formed in the region surrounded by the inner circumference of the endless ring-shaped resistor element Rg in the Y direction are described. In the Y direction, preferably, the lengths of the holes CH4 and the contact members PG located in the center portion are greater than twice the lengths of the holes CH4 and the contact members PG located adjacent to the folded portion WP. Figure 4In the Y direction, the length of the contact member PG (in other words, the hole CH4) connected to the second emitter electrode EE is greater than twice the length of the contact member PG (in other words, the hole CH4) connected to the first emitter electrode EE. The carriers generated by the above-mentioned impact ionization are released to the emitter electrode EE through the contact member PG, but are concentrated in the inner circumference area of ​​the endless ring-shaped resistance element Rg, and the discharge amount in the center part needs to be greater than twice the discharge amount at the turn-back portion WP. In the center part, it is necessary to release the carriers from the top direction and the bottom direction in the Y direction, while at the turn-back portion WP, it is sufficient to release the carriers in the downward direction or the upward direction.

[0074] <Features of the First Embodiment>

[0075] The semiconductor device of the first embodiment has a gate trench in which a gate electrode GE1 constituting an IGBT is embedded, and a resistor trench filled with a resistor element Rg. The depth of the trench TR in the resistor trench is equal to the depth of the trench TR in the gate trench. In addition, the thickness of the gate insulating film GI in the resistor trench is equal to the thickness of the gate insulating film GI in the gate trench. By making the structure of the resistor trench similar to that of the gate trench, and forming the gate electrode GE1 and the resistor element Rg in the same manufacturing process, the manufacturing cost is reduced.

[0076] By forming the resistance element Rg and the trench TR into an endless ring shape (eg, a ring shape) in a plan view, a decrease in breakdown voltage and aging degradation between the resistance element Rg and the well region PW are prevented.

[0077] In a region surrounded by the inner circumference of the endless ring-shaped resistance element Rg formed in the well region PW, the well region PW is electrically connected to the emitter electrode EE through the contact member PG formed in the hole CH4 .

[0078] Therefore, the potential fluctuation of the well region PW in the area surrounded by the inner circumference of the endless ring-shaped resistor element Rg is suppressed, and the breakdown of the gate insulating film GI provided in the trench TR in which the resistor element Rg is formed is prevented. Similarly, in the area adjacent to the outer circumference of the endless ring-shaped resistor element Rg formed in the well region PW, the well region PW is electrically connected to the emitter electrode EE through the contact member PG formed in the hole CH4. Therefore, the potential fluctuation of the well region PW in the area adjacent to the outer circumference of the endless ring-shaped resistor element Rg is suppressed, and the breakdown of the gate insulating film GI provided in the trench TR in which the resistor element Rg is formed is prevented. Here, the area adjacent to the outer circumference includes the area sandwiched between two adjacent endless ring-shaped resistor elements Rg.

[0079] In the area surrounded by the inner circumference of the endless ring-shaped resistor element Rg formed in the well region PW, the contact part PG formed in the hole CH4 is positioned in the area adjacent to the linear portion SP of the resistor element Rg and the area adjacent to the turn-back portion WP, respectively. Figure 4 As shown, in the Y direction, the length of the hole CH4 and the contact member PG located in the area (central part) adjacent to the linear portion SP is greater than twice the length of the hole CH4 and the contact member PG adjacent to the turn portion WP. In the central part, by increasing the amount of carrier discharge due to the above-mentioned impact ionization as compared to the turn portion WP, the potential fluctuation of the well region PW in the area surrounded by the inner circumference of the endless ring-shaped resistance element Rg can be further suppressed.

[0080] (Second embodiment)

[0081] The second embodiment is a modified example of the first embodiment, relating to the arrangement of the hole CH4 and the contact member PG provided in the above-mentioned first emitter electrode EE. In the following description, the difference from the first embodiment is mainly explained, and the overlapping points with the first embodiment are omitted. Fig. 9 is a plan view of a main portion of the semiconductor device 100 of the second embodiment, showing the resistance element area RGA.

[0082] like Fig. 9 As shown, the width of the first emitter electrode EE (the width in the Y direction) is greater than the width of the first emitter electrode EE in the above-mentioned first embodiment. Then, in the Y direction, the hole CH4 and the contact member PG are positioned between the folded portion WP of the resistor element Rg and the gate pad GP, thereby connecting the well region PW to the first emitter electrode EE. The gate pad GP has a wider area, so there is a region away from the well feed part under the gate pad GP in the well region PW. In the case of the above-mentioned impact ionization, a potential rise occurs in the well region PW in the region away from the well feed part. In the Y direction, the hole CH4 and the contact member PG are positioned between the folded portion WP of the resistor element Rg and the gate pad GP, thereby fixing the potential of the well region PW between the folded portion WP and the gate pad GP to the emitter potential. Then, the gate insulating film GI present in the folded portion WP prevents insulation breakdown due to the potential rise.

[0083] (Third Embodiment)

[0084] The third embodiment is a modified example of the first embodiment, omitting the above-described first emitter electrode EE and third emitter electrode EE. In the following description, focus will be mainly on differences from the first embodiment, and explanation of aspects overlapping with the first embodiment will be omitted. Fig.10 is a plan view of a main portion of the semiconductor device 100 of the third embodiment, showing the resistance element area RGA.

[0085] like Fig.10 As shown, in the Y direction, the gate pad GP, the gate pad wiring GPW, the second emitter electrode EE, the extension GWE, and the gate wiring GW are positioned in this order. In the Y direction, the gate pad wiring GPW extends from the gate pad GP to the resistor element area RGA, thereby covering a portion of one of the folded portion WP and the linear portion SP of the resistor element Rg. In the Y direction, from the gate wiring GW extending in the X direction, the extension GWE extends into the resistor element area RGA, thereby covering a portion of the other of the folded portion WP and the linear portion SP of the resistor element Rg. In the Y direction, between the gate pad wiring GPW and the extension GWE of the gate wiring GW, the second emitter electrode EE extends in the X direction. The second emitter electrode EE is electrically connected to the well region PW through a contact component PG formed in a hole CH4, which is located in a region surrounded by the resistor element Rg in an endless ring shape and adjacent to the outer circumference. The gate pad wiring GPW is electrically connected to the resistor element Rg through a contact member PG formed in a hole CH3. The gate pad wiring GPW is electrically connected to the gate pad GP. Similarly, the extension portion GWE of the gate wiring GW is electrically connected to the resistance element Rg through the contact member PG formed in the hole CH3. The extension portion GWE of the gate wiring GW is electrically connected to the gate wiring GW.

[0086] By omitting the first emitter electrode EE and the third emitter electrode EE described above, the wiring width of the gate pad wiring GPW and the gate wiring GW (including the extension portion GWE) can be widened in the Y direction compared to the first embodiment. Therefore, the variable range of the length of the resistance element region RGA of the resistance element Rg in the Y direction can be increased.

[0087] In addition, in the resistor element region RGA where the plurality of resistor elements Rg are located, the second emitter electrode EE includes a first portion intersecting the central portion of the resistor element Rg in the long direction (Y direction) in the short direction (X direction), and a second portion extending along the long direction of the resistor element Rg in the peripheral portion of the resistor element region RGA. The second portion branches from the first portion and extends in the Y direction beyond the position where the gate pad wiring GPW and the resistor element Rg are connected, and the position where the extension portion GWE of the gate wiring GW and the resistor element Rg are connected. The wiring width of the second portion in the Y direction is greater than the wiring width of the first portion in the Y direction. In the X direction, a plurality of holes CH4 and a plurality of contact members PG are positioned in the first portion of the second emitter electrode EE. The first portion of the second emitter electrode EE is electrically connected to the well region PW through the plurality of contact members PG formed in the plurality of holes CH4. Similarly, a plurality of holes CH4 and a plurality of contact members PG extending in the Y direction are positioned in the second portion of the second emitter electrode EE. And, the second portion of the second emitter electrode EE is electrically connected to the well region PW through the plurality of contact members PG formed in the plurality of holes CH4. Therefore, by providing the second portion extending in the Y direction on the second emitter electrode EE and bringing the well feeding section closer to the turned-back portion WP of the resistance element Rg, insulation breakdown of the gate insulation film GI in the resistance trench can be prevented.

[0088] (Fourth embodiment)

[0089] The fourth embodiment is a modified example of the first embodiment, omitting the above-described first emitter electrode EE and gate pad wiring GPW. In the following description, differences from the first embodiment will be mainly explained, and points overlapping with the first embodiment will be omitted. Fig.11 is a plan view of a main portion of the semiconductor device 100 of the fourth embodiment, showing the resistance element area RGA.

[0090] like Fig.11 As shown, in the Y direction, the gate pad GP, the second emitter electrode EE, the gate wiring GW, and the third emitter electrode EE are positioned in this order. In the Y direction, the gate pad GP covers a part of the folded portion WP and the linear portion SP of the resistance element Rg. The gate pad GP is electrically connected to the resistance element Rg through a contact member PG formed in the hole CH3. In a plan view, a part of the folded portion WP and the linear portion SP of the resistance element Rg can be located within the opening OPG.

[0091] By omitting the above-mentioned first emitter electrode EE and gate pad wiring GPW, the width of the second emitter electrode EE in the Y direction can be increased compared with the first embodiment. Also, in the Y direction, the length of the contact member PG formed in the hole CH4 electrically connected to the second emitter electrode EE and the well region PW is increased. Therefore, the ability of the second emitter electrode EE to release carriers in the above-mentioned impact ionization can be improved, and insulation breakdown of the gate insulating film GI at the folded portion WP of the resistance element Rg under the gate pad GP can be prevented.

[0092] However, in the well region PW under the gate pad GP, there is an area far from the well feed section (in other words, an area where the potential rises significantly). Therefore, in the Y direction, preferably, the folded portion WP of the resistance element Rg is placed in an area less than 300 microns from the contact member PG connected to the second emitter electrode EE. Considering the parasitic resistance of the well region PW, the insulation breakdown of the gate insulating film GI can be prevented in an area less than 300 microns from the well feed section.

[0093] Furthermore, by extending the resistance element Rg under the gate pad GP to the end portion, the linear portion SP of the resistance element Rg can be made longer in the Y direction, and the variable range of the resistance region can be increased.

[0094] (Fifth Embodiment)

[0095] The fifth embodiment is a modified example of the first embodiment, concerning the shape of the resistance element Rg. In the following description, the difference from the first embodiment will be mainly explained, and the points overlapping with the first embodiment will be omitted. Fig.12 is a plan view of a main portion of the semiconductor device 100 of the fifth embodiment, showing the resistance element area RGA.

[0096] Similar to the first embodiment, in the resistor element region RGA, in the Y direction, from the gate pad GP side, the first emitter electrode EE, the gate pad wiring GPW, the second emitter electrode EE, the gate wiring GW, and the third emitter electrode EE are positioned in order. Fig.12 As shown, the resistance element Rg includes a first linear portion SP and a second linear portion SP continuously extending from the first emitter electrode EE to the third emitter electrode EE in the Y direction. In addition, the first linear portion SP and the second linear portion SP are parallel to each other and spaced apart by a predetermined distance in the X direction.

[0097] In addition, the resistance element Rg includes a third linear portion SP and a fourth linear portion SP, which are parallel to and adjacent to each other between the first linear portion SP and the second linear portion SP. The third linear portion SP and the fourth linear portion SP extend continuously from the first emitter electrode EE to the second emitter electrode EE in the Y direction. Additionally, the resistance element Rg includes a fifth linear portion SP and a sixth linear portion SP, which are parallel to and adjacent to each other between the first linear portion SP and the second linear portion SP. The fifth linear portion SP and the sixth linear portion SP extend continuously from the second emitter electrode EE to the third emitter electrode EE in the Y direction. In the Y direction, the third linear portion SP and the fifth linear portion SP are linearly positioned, and so are the fourth linear portion SP and the sixth linear portion SP.

[0098] In addition, the resistance element Rg includes a first folding portion WP, a second folding portion WP, a third folding portion WP, a fourth folding portion WP, a fifth folding portion WP, and a sixth folding portion WP. The first folding portion WP connects the first linear portion SP and the third linear portion SP. The second folding portion WP connects the third linear portion SP and the fourth linear portion SP in an area overlapping with the second emitter electrode EE. The third folding portion WP connects the fourth linear portion SP and the second linear portion SP. The fourth folding portion WP connects the first linear portion SP and the fifth linear portion SP. The fifth folding portion WP connects the fifth linear portion SP and the sixth linear portion SP in an area overlapping with the second emitter electrode EE. The sixth folding portion WP connects the sixth linear portion SP and the second linear portion SP. The first folding portion WP and the third folding portion WP are both positioned in an area overlapping or adjacent to the first emitter electrode EE. The first folding portion WP and the third folding portion WP may also span from overlapping with the first emitter electrode EE to an adjacent area. The fourth folding portion WP and the sixth folding portion WP are both positioned in an area overlapping with or adjacent to the third emitter electrode EE. The fourth turned portion WP and the sixth turned portion WP may also span from the region overlapping with the third emitter electrode EE to the adjacent region.

[0099] In the area formed by the inner circumference of the resistor element Rg and the area adjacent to the outer circumference thereof, the well region PW is electrically connected to the first emitter electrode EE adjacent to the first turn-back portion WP and the third turn-back portion WP through the contact member PG formed in the hole CH4. In the area formed by the inner circumference of the resistor element Rg and the area adjacent to the outer circumference thereof, the well region PW is electrically connected to the second emitter electrode EE adjacent to the second turn-back portion WP and the fifth turn-back portion WP through the contact member PG formed in the hole CH4. In the area formed by the inner circumference of the resistor element Rg and the area adjacent to the outer circumference thereof, the well region PW is electrically connected to the third emitter electrode EE adjacent to the fourth turn-back portion WP and the sixth turn-back portion WP through the contact member PG formed in the hole CH4. Therefore, the well region PW is electrically connected to the third emitter electrode EE.

[0100] The resistance element Rg is in an area overlapping with the gate pad wiring GPW at the first linear portion SP or the third linear portion SP electrically connected to the gate pad wiring GPW through the contact member PG formed in the hole CH3. In addition, in an area overlapping with the gate wiring GW, the resistance element Rg is electrically connected to the gate wiring GW through the contact member PG formed in the hole CH3 at the first linear portion SP or the fifth linear portion SP. Fig.12 An example is shown in which the gate pad wiring GPW is electrically connected to the third linear portion SP and the gate wiring GW is connected to the fifth linear portion SP. In the resistance element Rg, the region where the gate pad wiring GPW and the gate wiring GW are electrically connected can vary, allowing the variability range in the resistance region to increase.

[0101] As described above, the present invention has been explained based on the embodiment, but the present invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the present invention.

[0102] For example, in the above-described embodiments, the IGBT is exemplified as a device formed in the cell region 1A, but the technology disclosed in the embodiments is not limited to the IGBT and can also be applied to a power MOSFET having a vertical trench gate structure.

[0103] Furthermore, the material for the semiconductor substrate SUB is not limited to silicon (Si), and may be silicon carbide (SiC), gallium nitride (GaN), or gallium oxide (Ga 2 O 3 ).

[0104] [Description of Reference Numerals]

[0105] 100: Semiconductor devices

[0106] 1A: Unit area

[0107] 1B: Outer Zone

[0108] AC: Active Unit

[0109] CE: Collector Electrode

[0110] CH1, CH2, CH3, CH4: hole

[0111] EE: emitter electrode (first emitter electrode, second emitter electrode, third emitter electrode)

[0112] GE1, GE2: Gate electrodes

[0113] GI: Gate Insulation Film

[0114] GP: Gate pad

[0115] GPW: Gate Pad Wiring

[0116] GW: Gate wiring

[0117] GWE: Extension

[0118] IAC: Passive Unit

[0119] IL: Interlayer insulation film

[0120] NE: emitter region

[0121] NHB: Hole Barrier Region

[0122] NS: Field Stop Zone

[0123] NV: Drift Zone

[0124] OPE, OPG: Open

[0125] PB: Base region

[0126] PC: Collector region

[0127] PF: Floating Field

[0128] PG: Contact member

[0129] PR: High concentration diffusion region

[0130] PW: Well region

[0131] RGA: Resistor Component Area

[0132] Rg: resistance element

[0133] SP: Linear

[0134] SUB: semiconductor substrate

[0135] SUBa: First main surface

[0136] SUBb: Second major surface

[0137] TR: Groove

[0138] WP: Turnback

Claims

1. A semiconductor device, comprising: A semiconductor substrate of a first conductivity type having a first main surface; A gate pad, a gate wiring, and an emitter electrode are formed on the first main surface; A well region of a second conductivity type opposite to the first conductivity type is formed on the first main surface; a first trench formed in an endless ring shape on the well region in a plan view; a first resistance element formed in an endless ring shape in a plan view so that the first resistance element is filled in the first trench via a first insulating film; a first contact member connected to the first resistive element; a second contact member spaced apart from the first contact member in a first direction and connected to the first resistance element, the first direction being a long direction of the first resistance element; as well as a third contact member located between the first contact member and the second contact member in the first direction and positioned within a region surrounded by an inner circumference of the first resistance element and connected to the well region, wherein the gate pad is electrically connected to the first resistance element via the first contact member, The gate wiring is electrically connected to the first resistance element via the second contact member, and The emitter electrode is electrically connected to the well region via the third contact member.

2. The semiconductor device according to claim 1, further comprising: A fourth contact member is located between the first contact member and the second contact member in the first direction and is positioned in a region adjacent to an outer circumference of the first resistance element and is connected to the well region.

3. The semiconductor device according to claim 2, further comprising: a fifth contact member electrically connected to the gate pad and the first resistance element, and a sixth contact member electrically connected to the gate wiring and the first resistance element and located at a predetermined interval from the fifth contact member in the first direction, wherein The first resistance element comprises: a first linear portion and a second linear portion extending in the first direction and adjacent to each other in a second direction, the second direction being a short direction of the first resistance element; and A first folded portion and a second folded portion are spaced apart from each other in the first direction and connected to the first linear portion and the second linear portion, The first contact member is connected to the first folded portion or the first linear portion, the second contact member is connected to the second folded portion or the first linear portion, the fifth contact member is connected to the first folded portion or the second linear portion, and The sixth contact member is connected to the second turning portion or the second linear portion.

4. The semiconductor device according to claim 3, wherein The third contact member and the fourth contact member are adjacent to the first linear portion of the first resistance element in the first direction.

5. The semiconductor device according to claim 3, wherein The first resistance element has a ring-like shape in a plan view.

6. The semiconductor device according to claim 3, wherein The first resistance element comprises: a first resistance region located between the first contact member and the second contact member, and a second resistance region located between the fifth contact member and the sixth contact member, and The first resistance region and the second resistance region are electrically connected in parallel between the gate pad and the gate wiring.

7. The semiconductor device according to claim 3, further comprising: a first wiring extending along the second direction and connected to the first contact member and the fifth contact member, a second wiring extending along the second direction and connected to the second contact member and the sixth contact member, and a third wiring extending along the second direction and connected to the third contact member and the fourth contact member, wherein the first wiring is electrically connected to the gate pad, the second wiring is electrically connected to the gate wiring, The third wiring is electrically connected to the emitter electrode, and The third wiring is located between the first wiring and the second wiring, and does not overlap with the first wiring and the second wiring in the first direction.

8. The semiconductor device according to claim 7, further comprising: a fourth wiring located between the first wiring and the gate pad in the first direction, extending in the second direction, and electrically connected to the emitter electrode; a plurality of seventh contact members electrically connecting the fourth wiring to the well region; a fifth wiring located on an opposite side of the third wiring relative to the second wiring in the first direction, extending in the second direction, and electrically connected to the emitter electrode; as well as A plurality of eighth contact members electrically connect the fifth wiring to the well region.

9. The semiconductor device according to claim 8, wherein The plurality of seventh contact members contact the first folded portion and are located in the region surrounded by the inner circumference of the first resistor element and in the region adjacent to the outer circumference of the first resistor element, and The plurality of eighth contact members contact the second folded-back portion and are located in the region surrounded by the inner circumference of the first resistance element and in the region adjacent to the outer circumference of the first resistance element.

10. The semiconductor device according to claim 9, wherein A portion of the plurality of seventh contact members is located between the first turning portion and the gate pad.

11. The semiconductor device according to claim 9, wherein in the second direction, a length of the third contact member is greater than twice a length of the seventh contact member adjacent to the first turned-back portion in the region surrounded by the inner circumference of the first resistance element.

12. The semiconductor device according to claim 7, wherein the first wiring continuously extending from the gate pad in the first direction, The first turning portion, a portion of the first linear portion, and a portion of the second linear portion overlap with the first wiring in a plan view, and The first contact member and the fifth contact member overlap the first wiring in a plan view.

13. The semiconductor device according to claim 3, wherein The first turning portion, a portion of the first linear portion, and a portion of the second linear portion overlap with the first wiring in a plan view, and The first contact member and the fifth contact member overlap the first wiring in a plan view.

14. The semiconductor device according to claim 3, further comprising: A second trench and a third trench formed outside the well region in a plan view; a first gate electrode formed in the second trench via a second insulating film; a second gate electrode formed in the third trench via a third insulating film; The emitter region of the first conductivity type is formed on the first main surface in a region between the second trench and the third trench; The base region of the second conductivity type is formed in the semiconductor substrate and contacts the emitter region in the region between the second trench and the third trench; The drift region of the first conductivity type is formed in the semiconductor substrate and contacts the base region; The collector region of the second conductivity type is formed on a second main surface of the semiconductor substrate opposite to the first main surface; A ninth contact member electrically connects the first gate electrode and the second gate electrode to the gate wiring.

15. The semiconductor device according to claim 14, wherein A depth of the first trench from the first main surface is equal to a depth of the second trench or the third trench from the first main surface.

16. The semiconductor device according to claim 15, wherein The thickness of the first insulating film is equal to the thickness of the second insulating film and the third insulating film.

17. The semiconductor device according to claim 14, wherein The first resistance element, the first gate electrode, and the second gate electrode include a polysilicon film.

18. The semiconductor device according to claim 14, further comprising: an interlayer insulating film formed on the first main surface to cover the well region, the first resistance element, the first gate electrode, and the second gate electrode, wherein the first contact member, the second contact member, the fifth contact member, and the sixth contact member penetrate the interlayer insulating film and are connected to the first resistance element, The third contact member and the fourth contact member penetrate the interlayer insulating film and are connected to the well region, and The ninth contact member penetrates the interlayer insulating film and is connected to the first gate electrode and the second gate electrode.

19. The semiconductor device according to claim 3, further comprising: a fourth trench formed in an endless ring shape on the well region in a plan view; a second resistance element formed in an endless ring shape in a plan view so that the second resistance element is filled in the second trench via a fourth insulating film, wherein The fourth groove is adjacent to the first groove in the second direction, The first resistance element and the second resistance element are electrically connected in parallel between the gate pad and the gate wiring.

20. A semiconductor device comprising: A semiconductor substrate of a first conductivity type having a main surface; A gate pad, a gate wiring, and an emitter electrode are formed on the main surface; A well region of a second conductivity type opposite to the first conductivity type is formed on the main surface; a first trench formed in an endless ring shape on the well region in a plan view; a first resistance element formed in an endless ring shape in a plan view so that the first resistance element is filled in the first trench via a first insulating film; a first contact member connected to the first resistive element; a second contact member spaced apart from the first contact member in a first direction and connected to the first resistance element, the first direction being a long direction of the first resistance element; as well as a third contact member located between the first contact member and the second contact member in the first direction and positioned within a region surrounded by an inner circumference of the first resistance element and connected to the well region, wherein the gate pad is electrically connected to the first resistance element via the first contact member, The gate wiring is electrically connected to the first resistance element via the second contact member, The emitter electrode is electrically connected to the well region via the third contact member, The first resistance element comprises: a first linear portion and a second linear portion extending in the first direction and adjacent to each other in a second direction, the second direction being a short direction of the first resistor element; a third linear portion, a fourth linear portion, a fifth linear portion, and a sixth linear portion extending in the first direction in a region between the first linear portion and the second linear portion and spaced apart from each other in the second direction; a first folding portion connecting the first linear portion and the third linear portion; a second folding portion connecting the third linear portion and the fourth linear portion; a third folding portion connecting the fourth linear portion and the second linear portion; a fourth folding portion connecting the first linear portion and the fifth linear portion; a fifth folding portion connecting the fifth linear portion and the sixth linear portion; and a sixth folding portion connecting the sixth linear portion and the second linear portion, The lengths of the third linear portion, the fourth linear portion, the fifth linear portion, and the sixth linear portion are shorter than those of the first linear portion and the second linear portion, the third linear portion and the fifth linear portion are linearly located in the first direction, and The fourth linear portion and the sixth linear portion are linearly located in the first direction.

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