Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the structure comprises a substrate which comprises a first device region; the channel layer structure is suspended above the substrate, and the channel layer structure comprises one or more channel layers which are arranged at intervals; the gate structures are located on the substrate, the gate structures stretch across the channel layer structures and surround the channel layers, and the gate structures and the channel layer structures located between the adjacent channel layers and between the channel layers and the substrate form a device laminated structure; the growth layer covers the side wall of the device laminated structure of the first device region; and the source-drain doped layer is located on the substrate at two sides of the gate structure, and in the first device region, the source-drain doped layer covers the growth layer at the end part of the device lamination structure. The working performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In semiconductor manufacturing, with the development trend of ultra-large-scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to smaller feature sizes, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also shortened accordingly. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens, so the control ability of the gate structure over the channel becomes worse, and the difficulty of pinching off the channel by the gate voltage becomes increasingly greater, making subthreshold leakage, the so-called short-channel effects (SCE), more likely to occur.

[0003] Therefore, in order to better adapt to the requirements of device size reduction, semiconductor processes have gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as gate-all-around (GAA) transistors. In a metal-all-around transistor, the gate surrounds the channel area from all sides. Compared with planar transistors, the gate of a metal-all-around transistor has a stronger control ability over the channel and can better suppress the short channel effect. Summary of the invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a forming method thereof, so as to improve the working performance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a first device region; a channel layer structure, suspended above the substrate, the channel layer structure including one or more channel layers spaced apart; a gate structure, located on the substrate, the gate structure spanning the channel layer structure and surrounding the channel layer, wherein the gate structure and the channel layer structure located between adjacent channel layers and between the channel layer and the substrate constitute a device stack structure; a growth layer, covering the side walls of the device stack structure in the first device region; a source-drain doping layer, located on the substrate on both sides of the gate structure, and in the first device region, the source-drain doping layer covers the growth layer at the end of the device stack structure.

[0006] Optionally, the growth layer also extends onto the substrate on both sides of the device stack structure in the first device region; in the first device region, the source-drain doping layer also covers the growth layer on the substrate.

[0007] Optionally, the thickness of the growth layer is 1 nm to 5 nm.

[0008] Optionally, the material of the growth layer includes SiB.

[0009] Optionally, in the material SiB of the growth layer, the B element volume density is 10 18 Pieces / cm 3 Up to 10 21 Pieces / cm 3 .

[0010] Optionally, the semiconductor structure further includes: a gate sidewall covering an outer sidewall of the gate structure; in the first device region, the device stack structure is recessed relative to the gate sidewall.

[0011] Optionally, sidewalls of the device stack structure in the first device region are flush.

[0012] Optionally, in the first device region, a distance between a sidewall of the device stack structure and an outer sidewall of the gate spacer on the same side is less than or equal to 5 nm.

[0013] Optionally, the substrate also includes a second device region, and the device types of the first device region and the second device region are different; the semiconductor structure also includes: an inner side wall, located between adjacent channel layers in the second device region, and between the channel layer and the substrate, and in the extension direction of the channel layer structure, the inner side wall is located between the gate structure and the source and drain doping layer.

[0014] Optionally, the first device region is a PMOS region, and the second device region is an NMOS region.

[0015] Optionally, the material of the channel layer includes silicon, silicon germanium or Group III-V semiconductor material.

[0016] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a first device region, a stacked structure formed on the substrate, the stacked structure comprising one or more stacked channel stacks, the channel stack comprising a sacrificial layer and a channel layer located on the sacrificial layer, a dummy gate structure spanning the stacked structure is also formed on the substrate, the dummy gate structure covers part of the sidewalls and part of the top of the stacked structure, and exposes both ends of the stacked structure; forming a growth layer covering the sidewalls of the stacked structure in the first device region; in the first device region, on the substrate on both sides of the dummy gate structure, forming a first source-drain doping layer of the growth layer covering the ends of the stacked structure; after forming the first source-drain doping layer, removing the dummy gate structure and the sacrificial layer, and forming a gate structure.

[0017] Optionally, in the step of forming the growth layer, the growth layer also extends onto the substrate on both sides of the stacked structure in the first device region; in the step of forming the source-drain doped layer, the source-drain doped layer also covers the growth layer on the substrate.

[0018] Optionally, an epitaxial growth process is used to form a growth layer covering the sidewalls of the stacked structure of the first device region.

[0019] Optionally, the first source-drain doped layer is formed by an epitaxial growth process.

[0020] Optionally, in the step of providing a substrate, the sidewalls of the pseudo gate structure are also formed with gate sidewalls, and the gate sidewalls are flush with the ends of the stacked structure; before forming the growth layer, the formation method also includes: using the gate sidewalls as a mask to remove part of the width of the stacked structure in a direction perpendicular to the sidewalls of the pseudo gate structure.

[0021] Optionally, an etching process is used to remove a portion of the width of the stacked structure along the extension direction of the channel layer, and the etching selectivity ratio of the etching process to the channel layer and the sacrificial layer is 1:2 to 2:1.

[0022] Optionally, in the step of removing a portion of the width of the stacked structure along a direction perpendicular to the sidewall of the dummy gate structure, the width of the removed stacked structure is less than or equal to 5 nm.

[0023] Optionally, in the step of providing a substrate, the substrate also includes a second device region adjacent to the first device region, and the device types of the first device region and the second device region are different; the formation method also includes: in the second device region, removing a portion of the width of the sacrificial layer along a direction perpendicular to the side wall of the pseudo gate structure to form a groove surrounded by the channel layer and the remaining sacrificial layer; forming an inner side wall in the groove; in the second device region, on the substrate on both sides of the pseudo gate structure, forming a second source and drain doping layer in contact with the end of the channel layer, and the second source and drain doping layer is isolated from the sacrificial layer by the inner side wall.

[0024] Optionally, the step of forming an inner sidewall in the groove includes: forming an inner sidewall material layer covering the top of the substrate, the sidewalls of the stacked structure, the sidewalls and the top of the pseudo gate structure, and filling the groove; removing the inner sidewall material layer covering the top of the substrate, the sidewalls of the stacked structure, the sidewalls and the top of the pseudo gate structure, and retaining the inner sidewall material layer filling the groove as the inner sidewall.

[0025] Optionally, before forming the groove, the formation method also includes: forming a first protective layer covering the side walls of the stacked structure and the side walls and top of the pseudo gate structure of the first device area; in the step of forming the groove, using the first protective layer as a mask to remove a portion of the width of the sacrificial layer in the second device area; in the step of forming the inner sidewall material layer, the inner sidewall material layer also covers the first protective layer; in the step of removing the inner sidewall material layer covering the top of the substrate, the side walls of the stacked structure and the side walls and top of the pseudo gate structure, the inner sidewall material layer covering the first protective layer is also removed; after forming the second source and drain doping layer, it also includes: removing the first protective layer.

[0026] Optionally, after forming the second source-drain doping layer, a growth layer is formed to cover the sidewalls of the stacked structure of the first device region.

[0027] Optionally, after forming the second source-drain doping layer and before forming the growth layer covering the side walls of the stacked structure of the first device region, the method further includes: forming a second protective layer covering the side walls and top of the pseudo-gate structure of the second device region and the second source-drain doping layer; in the step of forming the growth layer covering the side walls of the stacked structure of the first device region, the second protective layer is used as a mask; after forming the first source-drain doping layer, the method further includes: removing the second protective layer.

[0028] Optionally, the first device region is a PMOS region, and the second device region is an NMOS region.

[0029] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0030] In the structure provided by the embodiment of the present invention, the growth layer covers the side walls of the device stack structure in the first device area, the source-drain doping layer is located on the substrate on both sides of the gate structure, and in the first device area, the source-drain doping layer covers the growth layer at the end of the device stack structure; in the embodiment of the present invention, the growth layer covers the side walls of the device stack structure in the first device area, then in the step of forming the source-drain doping layer, it can grow uniformly along the growth layer from the side walls of the device stack structure, which is beneficial to reducing the crystal plane dislocation in the source-drain doping layer due to uneven growth, and is also beneficial to reducing the defects of holes formed in the source-drain doping layer due to inconsistent growth rates, thereby helping to increase the stress of the source-drain doping layer, and further helping to improve the working performance of the semiconductor structure.

[0031] In the formation method provided in the embodiment of the present invention, a growth layer covering the side walls of the stacked structure in the first device area is formed, and in the first device area, on the substrate on both sides of the pseudo-gate structure, a first source-drain doping layer covering the growth layer at the end of the stacked structure is formed; in the embodiment of the present invention, the growth layer covers the side walls of the stacked structure in the first device area, and in the step of forming the first source-drain doping layer, it can grow uniformly along the growth layer from the side walls of the device stacked structure, which is beneficial to reducing the crystal plane dislocation in the first source-drain doping layer due to uneven growth, and is also beneficial to reducing the defects of holes formed in the first source-drain doping layer due to inconsistent growth rates, thereby facilitating the improvement of the stress of the first source-drain doping layer, and further facilitating the improvement of the working performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figures 1 to 3 It is a structural schematic diagram corresponding to each step of a method for forming a semiconductor structure;

[0033] Figure 4 is a structural schematic diagram corresponding to an embodiment of a semiconductor structure of the present invention;

[0034] Figures 5 to 19 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0035] The performance of current semiconductor structures needs to be improved. The reasons why the performance needs to be improved are analyzed in combination with a semiconductor structure.

[0036] Figures 1 to 3 The present invention is a schematic structural diagram corresponding to each step of a method for forming a semiconductor structure.

[0037] refer to Figure 1 A substrate 10 is provided, on which a stacked structure 20 is formed, the stacked structure 20 includes one or more stacked channel stacks, the channel stack includes a sacrificial layer 21 and a channel layer 22 located on the sacrificial layer 21, a dummy gate structure 30 spanning the stacked structure 20 is also formed on the substrate 10, the dummy gate structure 30 covers part of the sidewalls and part of the top of the stacked structure 20, and exposes both ends of the stacked structure 20, and an inner sidewall 51 located on the sidewall of the sacrificial layer 21 is formed between adjacent channel layers 22 and between the channel layer 22 and the substrate 10.

[0038] Combined with reference Figure 2 and Figure 3 , a source-drain doped layer 62 is formed on the substrate 10 at both sides of the dummy gate structure 30 , and the source-drain doped layer 62 is in contact with the end of the stacked structure 20 .

[0039] Since the surface exposed at the end of the stacked structure 20 includes both the surface of the channel layer 22 and the surface of the inner sidewall 51, when the source-drain doped layer 62 is grown at the end of the stacked structure 20, it can grow on the surface of the channel layer 22 but not on the surface of the inner sidewall 51. Therefore, the source-drain doped layer 62 grows unevenly at the end of the stacked structure 20, and the growth rate at the end of the stacked structure 20 and the top of the substrate 10 is uneven (for example, Figure 2 As shown in the figure, it is easy to cause the problem of crystal plane dislocation when the crystal planes contact each other during the growth of the source-drain doping layer 62, which affects the quality and performance of the source-drain doping layer 62. It is also easy to cause defects such as holes in the source-drain doping layer 62 due to inconsistent growth rates (for example, Figure 3 As shown), thus affecting the working performance of the semiconductor structure.

[0040] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a first device region; a channel layer structure, suspended above the substrate, the channel layer structure including one or more layers of spaced channel layers; a gate structure, located on the substrate, the gate structure spans the channel layer structure and surrounds the channel layer, wherein the gate structure and the channel layer structure located between adjacent channel layers and between the channel layer and the substrate constitute a device stack structure; a growth layer, covering the side walls of the device stack structure in the first device region; a source-drain doping layer, located on the substrate on both sides of the gate structure, and in the first device region, the source-drain doping layer covers the growth layer at the end of the device stack structure.

[0041] In the semiconductor structure provided by the embodiment of the present invention, the growth layer covers the side walls of the device stack structure in the first device area. In the step of forming the source-drain doping layer, it can grow uniformly along the growth layer from the side walls of the device stack structure, which is beneficial to reducing the crystal plane dislocation in the source-drain doping layer due to uneven growth, and is also beneficial to reducing the defects of holes formed in the source-drain doping layer due to inconsistent growth rates, thereby helping to increase the stress of the source-drain doping layer, and further helping to improve the working performance of the semiconductor structure.

[0042] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0043] Figure 4 It is a structural schematic diagram corresponding to an embodiment of a semiconductor structure of the present invention.

[0044] In this embodiment, the semiconductor structure includes: a substrate 100, including a first device region 100P; a channel layer structure suspended above the substrate 100, the channel layer structure including one or more layers of spaced channel layers 220; a gate structure 700 located on the substrate 100, the gate structure 700 spanning the channel layer structure and surrounding the channel layer 220, wherein the gate structure 700 and the channel layer structure located between adjacent channel layers 220 and between the channel layer 220 and the substrate 100 constitute a device stack structure 201; a growth layer 600 covering the sidewalls of the device stack structure 201 of the first device region 100P; a source-drain doped layer 610 located on the substrate 100 on both sides of the gate structure 700, and in the first device region 100P, the source-drain doped layer 610 covers the growth layer 600 at the end of the device stack structure 201.

[0045] In this embodiment, the substrate 100 provides a process operation basis for the formation process of the semiconductor structure, wherein the semiconductor structure includes a gate-all-around (GAA) transistor and a forksheet transistor.

[0046] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0047] In this embodiment, the substrate 100 includes a first device region 100P.

[0048] The first device region 100P is used to form a first device.

[0049] In this embodiment, the substrate 100 further includes a second device region 100N, and the first device region 100P and the second device region 100N have different device types.

[0050] The second device region 100N is used to form a second device, and the first device and the second device are of different device types.

[0051] Specifically, in this embodiment, the first device region 100P is a PMOS region, and the second device region 100N is an NMOS region. Accordingly, the first device is a PMOS transistor, and the second device is an NMOS transistor.

[0052] In this embodiment, the channel layer structure includes one or more channel layers 220 arranged at intervals, and the channel layer 220 is used as a channel of a transistor.

[0053] In this embodiment, the material of the channel layer 220 includes silicon, silicon germanium or III-V semiconductor material. As an example, the material of the channel layer 220 is silicon. In other embodiments, the material of the channel layer is determined according to the type and performance of the transistor.

[0054] It should be noted that, in this embodiment, the channel layer 220 and the substrate 100 are made of the same material. In other embodiments, the channel layer and the substrate may be made of different materials.

[0055] In this embodiment, the gate structure 700 is used to control the opening and closing of the channel of the transistor.

[0056] In the above embodiment, the gate structure 700 surrounds and covers the channel layer 220. Therefore, the top, bottom and sidewalls of the channel layer 220 can all serve as channels, thereby increasing the area of ​​the channel layer 220 used as a channel, thereby increasing the operating current of the semiconductor structure.

[0057] In this embodiment, the gate structure 700 includes a gate dielectric layer surrounding the channel layer 220 along the extension direction of the gate structure 700 , and a gate electrode layer located on the gate dielectric layer.

[0058] In this embodiment, the gate dielectric layer is used to isolate the gate electrode layer from the channel layer 220 , and the gate electrode layer from the substrate 100 .

[0059] Specifically, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. Among them, the high-k dielectric material refers to a dielectric material whose relative dielectric constant is greater than the relative dielectric constant of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3, etc.

[0060] It should be noted that the gate dielectric layer may further include a gate oxide layer, and the gate oxide layer is located between the high-k gate dielectric layer and the channel layer 220. Specifically, the material of the gate oxide layer may be silicon oxide.

[0061] In this embodiment, the gate structure 700 is a metal gate structure, and therefore the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0062] Specifically, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer, wherein the work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to lead out the electrical properties of the metal gate structure.

[0063] In some other embodiments, the gate electrode layer may also only include a work function layer.

[0064] In other embodiments, according to process requirements, the gate structure may also be a polysilicon gate structure.

[0065] In this embodiment, the semiconductor structure further includes: a gate spacer 310 covering the outer sidewall of the gate structure 700 .

[0066] The outer sidewall of the gate structure 700 refers to the sidewall of the gate structure 700 that crosses the channel layer structure.

[0067] In the present embodiment, the gate spacer 310 may be a single-layer structure or a stacked structure, and the material of the gate spacer 310 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride. In the present embodiment, the gate spacer 310 is a single-layer structure, and the material of the gate spacer 310 is silicon nitride.

[0068] In this embodiment, in the first device region 100P, the device stack structure 201 is recessed relative to the gate spacer 310 .

[0069] In the semiconductor manufacturing process, in the first device region 100P, the sidewalls of the channel layer 220 are etched using the gate sidewall 310 as a mask to adjust the channel length, thereby adjusting the length of the gate structure 700 surrounding the channel layer 220. The channel length and the gate length are adjusted simultaneously to obtain a semiconductor structure that meets the performance requirements. Therefore, in this embodiment, in the first device region 100P, the device stack structure 201 is recessed relative to the gate sidewall 310.

[0070] In the present embodiment, a sacrificial layer is formed between the gate structures 700, between the channel layers 220, and between the channel layer 220 and the substrate 100. In the semiconductor process, in the step of etching the sidewall of the channel layer 220 using the gate sidewall 310 as a mask in the first device area 100P, the channel layer 220 and the sacrificial layer are etched at the same time, and the etching rates of the channel layer 220 and the sacrificial layer are similar, so that the etched channel layer 220 is flush with the sidewall of the sacrificial layer, and the sacrificial layer is subsequently replaced with the gate structure 700 to obtain the device stack structure 201. Therefore, in the present embodiment, the sidewalls of the device stack structure 201 in the first device area 100P are flush.

[0071] It should be noted that, in the present embodiment, in the first device region 100P, the distance between the sidewall of the device stack structure 201 and the outer sidewall of the gate spacer 310 on the same side should not be too large. If the distance between the sidewall of the device stack structure 201 and the outer sidewall of the gate spacer 310 on the same side is too large, in the semiconductor manufacturing process, in the step of etching the sidewall of the channel layer 220 using the gate spacer 310 as a mask in the first device region 100P, too much channel layer 220 is removed, and the sacrificial layer across the channel layer 220 is easily exposed. When the sacrificial layer is subsequently replaced with the gate structure 700, the gate structure 700 above the device stack structure 201 is easily exposed at the side of the channel layer 220, thereby easily causing leakage between the gate structure 700 and the source-drain doping layer 610, affecting the performance of the semiconductor structure. To this end, in the present embodiment, in the first device region 100P, the distance between the sidewall of the device stack structure 201 and the outer sidewall of the gate spacer 310 on the same side is less than or equal to 5 nm.

[0072] The growth layer 600 is used to provide a growth basis for the formation of the source-drain doping layer 610 , and is also used to isolate the source-drain doping layer 610 from the gate structure 700 .

[0073] In this embodiment, the growth layer 600 covers the side walls of the device stack structure 201 of the first device area 100P. In the step of forming the source-drain doping layer 610, it can grow uniformly along the growth layer 600 from the side walls of the device stack structure 201, which is beneficial to reduce the crystal plane dislocation in the source-drain doping layer 610 due to uneven growth, and is also beneficial to reduce the defects of holes formed in the source-drain doping layer 610 due to inconsistent growth rates, thereby helping to increase the stress of the source-drain doping layer 610, and further helping to improve the working performance of the semiconductor structure.

[0074] In this embodiment, the growth layer 600 also extends onto the substrate 100 on both sides of the device stack structure 201 in the first device region 100P.

[0075] The growth layer 600 also extends onto the substrate 100 on both sides of the device stack structure 201 in the first device region 100P. In the step of forming the source-drain doping layer 610, the side walls of the device stack structure 201 and the top of the substrate 100 can be uniformly grown along the growth layer 600, so that the growth of the source-drain doping layer 610 in all directions is more uniform, which is beneficial to further reduce the crystal plane dislocation in the source-drain doping layer 610 caused by uneven growth, and is also beneficial to further reduce the defects of holes formed in the source-drain doping layer 610 due to inconsistent growth rates, thereby helping to further increase the stress of the source-drain doping layer 610, and further helping to further improve the working performance of the semiconductor structure.

[0076] Correspondingly, in this embodiment, in the first device region 100P, the source-drain doped layer 610 also covers the growth layer 600 on the substrate 100 .

[0077] In this embodiment, the thickness of the growth layer 600 should not be too large or too small. If the thickness of the growth layer 600 is too large, it is easy to occupy too much space of the source-drain doping layer 610, affecting the formation quality and performance of the source-drain doping layer 610; if the thickness of the growth layer 600 is too small, it is easy to affect the growth of the growth layer 600 and the isolation performance between the gate structure 700 and the source-drain doping layer 610. For this reason, in this embodiment, the thickness of the growth layer 600 is 1nm to 5nm.

[0078] In this embodiment, the material of the growth layer 600 includes SiB.

[0079] SiB can be used as a basic material for the growth of the source-drain doping layer 610, so that the source-drain doping layer 610 can grow well. In addition, using SiB material as the growth layer 600 can reduce the additional introduction of elements and reduce the impact of the additional introduction of other elements on the semiconductor structure.

[0080] It should be noted that in this embodiment, the B element density in the SiB material of the growth layer should not be too large or too small. If the B element density is too large, it is easy to cause excessive diffusion of the B element into the channel, resulting in leakage, affecting the performance of the semiconductor structure; if the B element density is too small, it is easy to cause the resistance of the growth layer 600 to be too large, affecting the performance of the semiconductor structure. For this reason, in this embodiment, the B element density in the SiB material of the growth layer 600 is 10 18 Pieces / cm 3 Up to 10 21 Pieces / cm 3 .

[0081] The source-drain doped layer 610 is used as a source region or a drain region of a transistor. Specifically, the doping type of the source-drain doped layer 610 is the same as the channel conductivity type of the corresponding transistor.

[0082] In this embodiment, the doping type of the source-drain doping layer 610 is the same as the channel conductivity type of the corresponding transistor. Specifically, when the substrate 100 is used to form an NMOS transistor, the doping ions in the source-drain doping layer 610 are N-type ions, and the N-type ions include P ions, As ions, or Sb ions; when the substrate 100 is used to form a PMOS transistor, the doping ions in the source-drain doping layer 610 are P-type ions, and the P-type ions include B ions, Ga ions, or In ions.

[0083] In this embodiment, the semiconductor structure also includes: an inner sidewall 510, which is located between adjacent channel layers 220 in the second device area 100N, and between the channel layer 220 and the substrate 100. In the extension direction of the channel layer structure, the inner sidewall 510 is located between the gate structure 700 and the source-drain doping layer 610.

[0084] The inner spacer 510 serves to isolate the gate structure 700 and the source-drain doped layer 610 of the second device region 100N, so as to reduce the parasitic capacitance between the gate structure 700 and the source-drain doped layer 610 .

[0085] In this embodiment, the material of the inner sidewall 510 is an insulating material. Specifically, in this embodiment, the material of the inner sidewall 510 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

[0086] Figures 5 to 19 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0087] refer to Figure 5A substrate 100 is provided, including a first device region 100P, a stacked structure 200 is formed on the substrate 100, the stacked structure 200 includes one or more stacked channel stacks, the channel stack includes a sacrificial layer 210 and a channel layer 220 located on the sacrificial layer 210, and a pseudo gate structure 300 spanning the stacked structure 200 is also formed on the substrate 100, the pseudo gate structure 300 covers part of the sidewalls and part of the top of the stacked structure 200, and exposes both ends of the stacked structure 200.

[0088] In this embodiment, the substrate 100 provides a process operation basis for the formation process of the semiconductor structure, wherein the semiconductor structure includes a gate-all-around (GAA) transistor and a forksheet transistor.

[0089] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0090] In this embodiment, the substrate 100 includes a first device region 100P.

[0091] The first device region 100P is used to form a first device.

[0092] In this embodiment, in the step of providing the substrate 100 , the substrate 100 further includes a second device region 100N, and the first device region 100P and the second device region 100N have different device types.

[0093] The second device region 100N is used to form a second device, and the first device and the second device are of different device types.

[0094] Specifically, in this embodiment, the first device region 100P is a PMOS region, and the second device region 100N is an NMOS region. Accordingly, the first device is a PMOS transistor, and the second device is an NMOS transistor.

[0095] In this embodiment, the channel layer 220 in the stacked structure 200 is used as a channel of the semiconductor structure, and the sacrificial layer 210 is used to provide a process basis for the subsequent suspended arrangement of the channel layer 220, and is also used to occupy a space position for the gate structure formed subsequently. In the subsequent process, the sacrificial layer 210 is removed, so that the channel layer 220 is suspended, and a gate structure is formed between the channel layer 220 and the substrate 100, and between adjacent channel layers 220.

[0096] In this embodiment, the surface of the channel layer 220 covered by the gate structure is used as a channel, and the top, bottom and sidewalls of the channel layer 220 can all be used as channels, increasing the area of ​​the channel layer 220 used as a channel, thereby increasing the operating current of the semiconductor structure.

[0097] In this embodiment, the material of the channel layer 220 includes silicon, germanium, silicon germanium or III-V semiconductor materials. As an example, the material of the channel layer 220 is silicon. In other embodiments, the material of the channel layer is determined according to the type and performance of the transistor.

[0098] It should be noted that, in this embodiment, the channel layer 220 and the substrate 100 are made of the same material. In other embodiments, the channel layer and the substrate may be made of different materials.

[0099] In this embodiment, the material of the sacrificial layer 210 includes silicon germanium.

[0100] Silicon germanium and silicon can form a larger etching selectivity ratio, which is beneficial to the subsequent removal of the sacrificial layer 210 and reduces damage to the channel layer 220 .

[0101] In other embodiments, the sacrificial layer may be made of a suitable material having an etching selectivity ratio with the channel layer according to the material of the channel layer, so as to reduce damage to the channel layer when the sacrificial layer is subsequently removed.

[0102] In this embodiment, the dummy gate structure 300 is used to occupy a space for the subsequent formation of a gate structure.

[0103] Specifically, the dummy gate structure 300 is a stacked structure, including a dummy gate oxide layer (not shown) and a dummy gate layer (not shown) covering the dummy gate oxide layer.

[0104] As an example, the material of the dummy gate oxide layer is silicon oxide, and the material of the dummy gate layer is polysilicon.

[0105] In this embodiment, in the step of providing the substrate 100 , a gate spacer 310 is formed on the sidewall of the dummy gate structure 300 , and the gate spacer 310 is flush with the end of the stacked structure 200 .

[0106] After the gate structure is subsequently formed, the gate sidewall 310 is used to protect the sidewall of the gate structure. In the step of forming the stacked structure 200 , the stacked structure 200 is obtained by etching along the gate sidewall 310 , and the gate sidewall 310 is flush with the end of the stacked structure 200 .

[0107] In the present embodiment, the gate spacer 310 may be a single-layer structure or a stacked structure, and the material of the gate spacer 310 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride. In the present embodiment, the gate spacer 310 is a single-layer structure, and the material of the gate spacer 310 is silicon nitride.

[0108] In this embodiment, a mask layer is formed on the top of the dummy gate structure 300 .

[0109] In this embodiment, the mask layer is used as an etching mask for forming the dummy gate structure 300 and is also used to protect the top of the dummy gate structure.

[0110] In this embodiment, the material of the mask layer includes one or more of silicon oxide and silicon nitride. As an example, the material of the mask layer is silicon nitride.

[0111] Combined with reference Figures 6 to 11 The formation method further includes: in the second device area 100N, removing a portion of the width of the sacrificial layer 210 along a direction perpendicular to the sidewall of the dummy gate structure 300 to form a trench 230 surrounded by the channel layer 220 and the remaining sacrificial layer 210; and forming an inner sidewall 510 in the trench 230.

[0112] The groove 230 is used to provide a space for forming the inner sidewall 510 .

[0113] In this embodiment, an isotropic etching process is used to remove a portion of the width of the sacrificial layer 210 to form the trench 230 .

[0114] In this embodiment, the isotropic etching process includes a wet etching process, and the etching solution includes one or more of a H2O2 solution, a HNO3 solution, a CH3COOH solution and a HF solution.

[0115] In this embodiment, the isotropic etching process also includes a dry etching process, including HCl gas etching and ICP etching (etching gas includes H / F / Cl / N-based gas).

[0116] The inner sidewall 510 serves to isolate the gate structure and the source-drain doped layer to be subsequently formed in the second device region 100N, so as to reduce the parasitic capacitance between the gate structure and the source-drain doped layer.

[0117] In this embodiment, the material of the inner sidewall 510 is an insulating material. Specifically, in this embodiment, the material of the inner sidewall 510 includes silicon nitride.

[0118] Combined with reference Figure 6 and Figure 7Before forming the trench 230 , the forming method further includes: forming a first protection layer 410 covering the sidewalls of the stacked structure 200 and the sidewalls and top of the dummy gate structure 300 of the first device region 100P.

[0119] The first protection layer 410 is used to cover the first device region 100P and protect the structure of the first device region 100P in the subsequent step of forming the trench 230 and the inner sidewall 510 in the second device region 100N.

[0120] In this embodiment, the material of the first protection layer 410 includes silicon oxide.

[0121] refer to Figure 6 In this embodiment, the step of forming the first protection layer 410 includes: forming a first protection material layer 400 covering the top of the substrate 100, the sidewalls of the stacked structure 200, and the sidewalls and top of the dummy gate structure 300.

[0122] The first protective material layer 400 is used to form a first protective layer 410 .

[0123] Correspondingly, in this embodiment, the material of the first protective material layer 400 is silicon oxide.

[0124] refer to Figure 7 , forming a first mask layer 420 of the first protection material layer 400 covering the first device area 100P; patterning the first protection material layer 400 using the first mask layer 420 as a mask, retaining the first protection material layer 400 located in the first device area 100P as the first protection layer 410.

[0125] refer to Figure 8 After forming the first protection layer 410 , the first mask layer 420 is removed.

[0126] refer to Fig. 9 In the step of forming the trench 230 , the first protection layer 410 is used as a mask to remove a portion of the width of the sacrificial layer 210 in the second device region 100N.

[0127] Specifically, in the step of removing a portion of the sacrificial layer 210 in the second device region 100N, the first protection layer 410 protects the structure of the first device region 100P, and the gate spacer 310 protects the dummy gate structure 300 .

[0128] refer to Fig.10 The step of forming the inner spacer 510 in the trench 230 includes: forming an inner spacer material layer 500 covering the top of the substrate 100 , the sidewalls of the stacked structure 200 , and the sidewalls and top of the dummy gate structure 300 , and filling the trench 230 .

[0129] The inner sidewall material layer 500 is used to form an inner sidewall 510 .

[0130] Accordingly, in the present embodiment, the material of the inner spacer material layer 500 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

[0131] In this embodiment, the inner sidewall material layer 500 is formed by an atomic layer deposition process.

[0132] The inner sidewall material layer 500 formed by the atomic layer deposition process has good thickness uniformity and good step coverage capability, so that the inner sidewall material layer 500 can conformally cover the top of the substrate 100, the sidewalls of the stacked structure 200 and the sidewalls and top of the pseudo gate structure 300, fill the groove 230, and is conducive to making the thickness uniformity of the inner sidewall 510 better.

[0133] Correspondingly, in this embodiment, in the step of forming the inner sidewall material layer 500 , the inner sidewall material layer 500 also covers the first protection layer 410 .

[0134] refer to Fig.11 , the inner sidewall material layer 500 covering the top of the substrate 100 , the sidewalls of the stacked structure 200 , and the sidewalls and top of the dummy gate structure 300 is removed, and the inner sidewall material layer 500 filling the trench 230 is retained as the inner sidewall 510 .

[0135] Accordingly, in this embodiment, in the step of removing the inner spacer material layer 500 covering the top of the substrate 100 , the sidewalls of the stacked structure 200 , and the sidewalls and top of the dummy gate structure 300 , the inner spacer material layer 500 covering the first protection layer 410 is also removed.

[0136] refer to Fig.12 In the second device region 100N, a second source / drain doped layer 620 in contact with the end of the channel layer 220 is formed on the substrate 100 on both sides of the dummy gate structure 300 , and the second source / drain doped layer 620 is isolated from the sacrificial layer 210 by the inner sidewall 510 .

[0137] The second source-drain doped layer 620 is used as a source region or a drain region of a transistor. Specifically, the doping type of the second source-drain doped layer 620 is the same as the channel conductivity type of the corresponding transistor.

[0138] In this embodiment, the doping type of the second source-drain doping layer 620 is the same as the channel conductivity type of the corresponding transistor. Specifically, the substrate 100 of the second device region 100N is used to form an NMOS transistor, and the doping ions in the second source-drain doping layer 620 are N-type ions, including P ions, As ions or Sb ions.

[0139] Continue to refer Fig.12In this embodiment, after forming the second source-drain doping layer 620 , the process further includes: removing the first protective layer 410 .

[0140] The first protection layer 410 is removed to prepare for the subsequent formation of a growth layer in the first device region 100P.

[0141] In this embodiment, after the second source-drain doping layer 620 is formed, a growth layer is formed to cover the sidewalls of the stacked structure 200 of the first device region 100P.

[0142] In other embodiments, the first source-drain doping layer of the first device region may be formed first, and then the inner sidewall and the second source-drain doping layer of the second device region may be formed.

[0143] Combined with reference Fig.13 and Fig.14 After forming the second source-drain doped layer 620 , before subsequently forming a growth layer covering the sidewalls of the stacked structure 200 of the first device region 100P, it also includes: forming a second protective layer 450 covering the sidewalls and top of the dummy gate structure 300 of the second device region 100N, and the second source-drain doped layer 620 .

[0144] The second protection layer 450 is used to cover the second device region 100N and protect the structure of the second device region 100N in the subsequent step of forming a growth layer in the first device region 100P.

[0145] In this embodiment, the material of the second protection layer 450 includes silicon oxide.

[0146] refer to Fig.13 In this embodiment, the step of forming the second protective layer 450 includes: forming a second protective material layer 430 covering the top of the substrate 100, the sidewalls of the stacked structure 200, the sidewalls and top of the dummy gate structure 300, and the second source and drain doping layer 620.

[0147] The second protection material layer 430 is used to form a second protection layer 450 .

[0148] Correspondingly, in this embodiment, the material of the second protective material layer 430 is silicon oxide.

[0149] refer to Fig.14 , forming a second mask layer 440 covering the second protection material layer 430 in the second device area 100N; patterning the second protection material layer 430 using the second mask layer 440 as a mask, retaining the second protection material layer 430 located in the second device area 100N as the second protection layer 450 .

[0150] refer to Fig.15 After forming the second protection layer 450 , the second mask layer 440 is removed.

[0151] refer to Fig.16 Before subsequently forming the growth layer 600 , the formation method further includes: using the gate sidewall 310 as a mask to remove a portion of the width of the stacked structure 200 in a direction perpendicular to the sidewall of the dummy gate structure 300 .

[0152] The sidewalls of the channel layer 220 are etched using the gate spacer 310 as a mask to adjust the channel length, thereby adjusting the length of the gate structure 700 surrounding the channel layer 220, and accordingly obtaining a semiconductor structure that meets performance requirements.

[0153] It should be noted that, in the present embodiment, in the step of removing a portion of the width of the stacked structure 200 along the direction perpendicular to the sidewall of the pseudo gate structure 300, the width of the removed stacked structure 200 should not be too large. If the width of the removed stacked structure 200 is too large, the sacrificial layer across the channel layer 220 is easily exposed. When the sacrificial layer is subsequently replaced with a gate structure, the gate structure above the stacked structure 200 is easily exposed on the side of the channel layer 220, which can easily lead to leakage between the gate structure and the first source-drain doped layer, affecting the performance of the semiconductor structure. For this reason, in the present embodiment, in the step of removing a portion of the width of the stacked structure 200 along the direction perpendicular to the sidewall of the pseudo gate structure 300, the width of the removed stacked structure 200 is less than or equal to 5nm.

[0154] In this embodiment, an etching process is used to remove a portion of the width of the stacked structure 200 along the extension direction of the channel layer 220 , and the etching selectivity ratio of the etching process to the channel layer 220 and the sacrificial layer 210 is 1:2 to 2:1.

[0155] The etching process has an etching selectivity ratio of 1:2 to 2:1 for the channel layer 220 and the sacrificial layer 210, so that the etching rates of the channel layer 220 and the sacrificial layer 210 are similar, so that the side walls of the channel layer 220 and the sacrificial layer 210 after etching are flush, providing a better process platform for the subsequent formation of a growth layer.

[0156] In this embodiment, an anisotropic etching process is used to remove a portion of the width of the stacked structure 200 along the extension direction of the channel layer 220 .

[0157] The anisotropic etching process is easy to control the process parameters, which is beneficial to control the size of the stacked structure 200 with a partial width to be removed, and is easy to obtain similar etching rates for the channel layer 220 and the sacrificial layer 210 .

[0158] refer to Fig.17 , forming a growth layer 600 covering the sidewalls of the stacked structure 200 of the first device region 100P.

[0159] The growth layer 600 is used to provide a growth basis for the subsequent formation of the first source / drain doped layer, and is also used to protect the sidewalls of the first source / drain doped layer to reduce damage when replacing the sacrificial layer 210 with a gate structure after the first source / drain doped layer is formed.

[0160] In this embodiment, the growth layer 600 covers the side walls of the stacked structure 200 of the first device area 100P. In the subsequent step of forming the first source-drain doping layer, it can grow uniformly along the growth layer 600 from the side walls of the stacked structure 200, which is beneficial to reduce the crystal plane dislocation in the first source-drain doping layer due to uneven growth, and is also beneficial to reduce the defects of holes formed in the first source-drain doping layer due to inconsistent growth rates, thereby helping to increase the stress of the first source-drain doping layer, and further helping to improve the working performance of the semiconductor structure.

[0161] Accordingly, in this embodiment, in the step of forming the growth layer 600 covering the sidewalls of the stacked structure 200 of the first device region 100P, the second protection layer 450 is used as a mask.

[0162] In this embodiment, in the step of forming the growth layer 600 , the growth layer 600 also extends onto the substrate 100 on both sides of the stacked structure 200 in the first device region 100P.

[0163] The growth layer 600 also extends onto the substrate 100 on both sides of the stacked structure 200 in the first device region 100P. In the subsequent step of forming the first source-drain doping layer, it can grow uniformly along the growth layer 600 from the side walls of the stacked structure 200 and the top of the substrate 100, so that the growth of the first source-drain doping layer in all directions is more uniform, which is beneficial to further reduce the crystal plane dislocation in the first source-drain doping layer due to uneven growth, and is also beneficial to further reduce the defects of holes formed in the first source-drain doping layer due to inconsistent growth rates, thereby helping to further increase the stress of the first source-drain doping layer, and further helping to further improve the working performance of the semiconductor structure.

[0164] In this embodiment, an epitaxial growth process is used to form the growth layer 600 covering the sidewalls of the stacked structure 200 of the first device region 100P.

[0165] The growth layer 600 is formed by an epitaxial growth process, so that the growth layer 600 is formed on the side walls of the stacked structure 200 and the top of the substrate, but not in other positions. The epitaxial growth process can better control the process parameters, the process controllability is high, and it is easy to obtain a more precise film thickness size. The epitaxial growth process can easily form a film layer with less impurities, so that the quality of the growth layer 600 is higher.

[0166] In the present embodiment, in the step of forming the growth layer 600, the thickness of the growth layer 600 should not be too large or too small. If the thickness of the growth layer 600 is too large, it is easy to occupy too much space of the first source-drain doping layer formed subsequently, affecting the formation quality and performance of the first source-drain doping layer; if the thickness of the growth layer 600 is too small, it is easy to affect the growth of the growth layer 600, and also easy to affect the isolation performance between the gate structure formed subsequently and the first source-drain doping layer. For this reason, in the present embodiment, in the step of forming the growth layer 600, the thickness of the growth layer 600 is 1nm to 5nm.

[0167] In this embodiment, in the step of forming the growth layer 600 , the material of the growth layer 600 includes SiB.

[0168] SiB can be used as a base material for the growth of the first source-drain doped layer, so that the first source-drain doped layer can grow well. Moreover, using SiB material as the growth layer 600 can reduce the additional elements introduced, thereby reducing the impact on the semiconductor structure caused by the additional introduction of other elements.

[0169] It should be noted that in this embodiment, the B element density in the SiB material of the growth layer should not be too large or too small. If the B element density is too large, it is easy to cause excessive diffusion of the B element into the channel, resulting in leakage, affecting the performance of the semiconductor structure; if the B element density is too small, it is easy to cause the resistance of the growth layer 600 to be too large, affecting the performance of the semiconductor structure. For this reason, in this embodiment, the B element density in the SiB material of the growth layer 600 is 10 18 Pieces / cm 3 Up to 10 21 Pieces / cm 3 .

[0170] refer to Fig.18 In the first device region 100P, a first source-drain doped layer 610 of the growth layer 600 covering the end of the stacked structure 200 is formed on the substrate 100 at both sides of the dummy gate structure 300 .

[0171] The first source-drain doped layer 610 is used as a source region or a drain region of a transistor. Specifically, the doping type of the first source-drain doped layer 610 is the same as the channel conductivity type of the corresponding transistor.

[0172] In this embodiment, the doping type of the first source-drain doping layer 610 is the same as the channel conductivity type of the corresponding transistor. Specifically, the substrate 100 of the first device region 100P is used to form a PMOS transistor, and the doping ions in the first source-drain doping layer 610 are P-type ions, and the P-type ions include B ions, Ga ions or In ions.

[0173] Correspondingly, in the present embodiment, in the step of forming the first source-drain doped layer 610 , the first source-drain doped layer 610 also covers the growth layer 600 on the substrate 100 .

[0174] In this embodiment, the first source / drain doping layer 610 is formed by an epitaxial growth process.

[0175] The epitaxial growth process can be used to uniformly grow the first source-drain doped layer 610 on the growth layer 610, forming the first source-drain doped layer 610 with higher film quality. The epitaxial growth process can better control the process parameters, and the process controllability is high, so it is easy to obtain a more precise film thickness. The epitaxial growth process can easily form a film with less impurities, so that the quality of the first source-drain doped layer 610 is higher.

[0176] refer to Fig.19 After forming the first source-drain doping layer 610 , the method further includes: removing the second protective layer 450 .

[0177] The second protection layer 450 is removed to prepare for the subsequent formation of a gate structure.

[0178] Continue to refer Fig.19 After forming the first source-drain doped layer 610 , the dummy gate structure 300 and the sacrificial layer 210 are removed, and a gate structure 700 is formed.

[0179] In this embodiment, after the first source-drain doped layer 610 is formed, the dummy gate structure 300 and the sacrificial layer 210 are removed to form a gate opening (not shown) exposing the channel layer 220 .

[0180] In this embodiment, the gate opening provides a space for subsequently forming a gate structure.

[0181] Specifically, the dummy gate structure 300 is removed to form an initial gate opening (not shown), wherein the initial gate opening exposes the sacrificial layer 210 .

[0182] The initial gate opening provides a space for the subsequent formation of a gate structure and prepares for removing the sacrificial layer 210 .

[0183] In this embodiment, the sacrificial layer 210 is removed through the initial gate opening to form a through groove (not shown), which is surrounded by the adjacent channel layer 220 , or by the adjacent channel layer 220 and the substrate 100 .

[0184] The sacrificial layer 210 is removed through the initial gate opening to expose various surfaces of the channel layer 220 , so that the subsequently formed gate structure surrounds and covers the channel layer 220 .

[0185] In this embodiment, a gate structure 700 is formed in the gate opening to cross over and surround the channel layer 220 .

[0186] In this embodiment, the gate structure 700 is used to control the opening or closing of the channel of the transistor.

[0187] The gate structure 700 covers the channel layer 220 , so the top, bottom and sidewalls of the channel layer 220 can all serve as channels, increasing the area of ​​the channel layer 220 used as a channel, thereby increasing the operating current of the semiconductor structure.

[0188] In this embodiment, the gate structure 700 includes a gate dielectric layer surrounding the channel layer 220 along the extension direction of the gate structure 700 , and a gate electrode layer located on the gate dielectric layer.

[0189] The gate dielectric layer is used to isolate the gate electrode layer from the channel layer 220 , and the gate electrode layer from the substrate 100 .

[0190] Specifically, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. Among them, the high-k dielectric material refers to a dielectric material whose relative dielectric constant is greater than the relative dielectric constant of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3, etc.

[0191] It should be noted that the gate dielectric layer may further include a gate oxide layer, and the gate oxide layer is located between the high-k gate dielectric layer and the channel layer 220. Specifically, the material of the gate oxide layer may be silicon oxide.

[0192] In this embodiment, the gate structure 700 is a metal gate structure, and therefore the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0193] Specifically, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer, wherein the work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to lead out the electrical properties of the metal gate structure.

[0194] In some other embodiments, the gate electrode layer may also only include a work function layer.

[0195] In other embodiments, according to process requirements, the gate structure may also be a polysilicon gate structure.

[0196] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate including a first device region; A channel layer structure is suspended above the substrate, wherein the channel layer structure comprises one or more channel layers arranged at intervals; A gate structure, located on the substrate, the gate structure spans the channel layer structure and surrounds the channel layer, wherein the gate structure located between adjacent channel layers and between the channel layer and the substrate and the channel layer structure constitute a device stacked structure; A growth layer covering the sidewalls of the device stack structure in the first device region; The source-drain doped layers are located on the substrate at both sides of the gate structure, and in the first device region, the source-drain doped layers cover the growth layer at the end of the device stacked structure.

2. The semiconductor structure according to claim 1, wherein: The growth layer also extends onto the substrate on both sides of the device stack structure in the first device region; In the first device region, the source-drain doping layer also covers the growth layer on the substrate.

3. The semiconductor structure according to claim 1, wherein: The thickness of the growth layer is 1 nm to 5 nm.

4. The semiconductor structure according to claim 1, wherein: The material of the growth layer includes SiB.

5. The semiconductor structure according to claim 4, characterized in that The material SiB of the growth layer has a B element volume density of 10 18 Pieces / cm 3 Up to 10 21 Pieces / cm 3 .

6. The semiconductor structure according to claim 1, wherein: The semiconductor structure further comprises: a gate sidewall, covering an outer sidewall of the gate structure; In the first device region, the device stack structure is recessed relative to the gate sidewall.

7. The semiconductor structure according to claim 6, wherein: The sidewalls of the device stack structure in the first device region are flush.

8. The semiconductor structure according to claim 7, wherein: In the first device region, a distance between a sidewall of the device stack structure and an outer sidewall of the gate spacer on the same side is less than or equal to 5 nm.

9. The semiconductor structure according to claim 1, wherein: The substrate further includes a second device region, and the device types of the first device region and the second device region are different; The semiconductor structure further includes: an inner sidewall located between adjacent channel layers in the second device region and between the channel layer and the substrate. In the extension direction of the channel layer structure, the inner sidewall is located between the gate structure and the source-drain doping layer.

10. The semiconductor structure according to claim 9, wherein: The first device region is a PMOS region, and the second device region is an NMOS region.

11. The semiconductor structure according to claim 1, wherein: The material of the channel layer includes silicon, silicon germanium or III-V group semiconductor material.

12. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, including a first device region, a stacked structure formed on the substrate, the stacked structure including one or more stacked channel stacks, the channel stack including a sacrificial layer and a channel layer located on the sacrificial layer, and a dummy gate structure spanning the stacked structure is also formed on the substrate, the dummy gate structure covers a portion of the sidewall and a portion of the top of the stacked structure, and exposes both ends of the stacked structure; forming a growth layer covering the sidewalls of the stacked structure in the first device region; In the first device region, on the substrate at both sides of the dummy gate structure, a first source-drain doped layer covering the growth layer at the end of the stacked structure is formed; After forming the first source-drain doped layer, the dummy gate structure and the sacrificial layer are removed, and a gate structure is formed.

13. The method for forming a semiconductor structure according to claim 12, wherein: In the step of forming the growth layer, the growth layer also extends onto the substrate on both sides of the stacked structure in the first device region; In the step of forming the first source-drain doped layer, the first source-drain doped layer also covers the growth layer on the substrate.

14. The method for forming a semiconductor structure according to claim 12, wherein: An epitaxial growth process is adopted to form a growth layer covering the sidewalls of the stacked structure of the first device region.

15. The method for forming a semiconductor structure according to claim 12, wherein: The first source-drain doped layer is formed by an epitaxial growth process.

16. The method for forming a semiconductor structure according to claim 12, wherein: In the step of providing the substrate, the sidewalls of the dummy gate structure are further formed with gate sidewalls, and the gate sidewalls are flush with the ends of the stacked structure; Before forming the growth layer, the forming method further comprises: using the gate sidewall as a mask to remove a portion of the width of the stacked structure in a direction perpendicular to the sidewall of the dummy gate structure.

17. The method for forming a semiconductor structure according to claim 16, wherein: An etching process is used to remove a portion of the width of the stacked structure along the extension direction of the channel layer, and the etching selection ratio of the etching process to the channel layer and the sacrificial layer is 1:2 to 2:

1.

18. The method for forming a semiconductor structure according to claim 16, wherein: In the step of removing a portion of the width of the stacked structure along a direction perpendicular to the sidewall of the dummy gate structure, the width of the removed stacked structure is less than or equal to 5 nm.

19. The method for forming a semiconductor structure according to claim 12, wherein: In the step of providing the substrate, the substrate further comprises a second device region, and the device types of the first device region and the second device region are different; The formation method further comprises: in the second device region, removing a portion of the sacrificial layer along a direction perpendicular to the sidewall of the dummy gate structure to form a trench surrounded by the channel layer and the remaining sacrificial layer; and forming an inner sidewall in the trench; In the second device region, a second source-drain doped layer in contact with the end of the channel layer is formed on the substrate at both sides of the dummy gate structure, and the second source-drain doped layer is isolated from the sacrificial layer by the inner sidewall.

20. The method for forming a semiconductor structure according to claim 19, wherein: The step of forming an inner sidewall in the trench comprises: forming an inner sidewall material layer covering the top of the substrate, the sidewall of the stacked structure, and the sidewall and top of the dummy gate structure, and filling the trench; The inner sidewall material layer covering the top of the substrate, the sidewalls of the stacked structure, and the sidewalls and top of the dummy gate structure is removed, and the inner sidewall material layer filling the trench is retained as the inner sidewall.

21. The method for forming a semiconductor structure according to claim 20, wherein: Before forming the trench, the forming method further comprises: forming a first protection layer covering the sidewalls of the stacked structure and the sidewalls and top of the dummy gate structure of the first device region; In the step of forming the trench, the first protection layer is used as a mask to remove a portion of the width of the sacrificial layer in the second device region; In the step of forming the inner sidewall material layer, the inner sidewall material layer also covers the first protective layer; In the step of removing the inner sidewall material layer covering the top of the substrate, the sidewalls of the stacked structure, and the sidewalls and top of the dummy gate structure, the inner sidewall material layer covering the first protective layer is also removed; After forming the second source-drain doped layer, the method further includes: removing the first protective layer.

22. The method for forming a semiconductor structure according to claim 19, wherein: After forming the second source-drain doping layer, a growth layer is formed to cover the sidewalls of the stacked structure of the first device region.

23. The method for forming a semiconductor structure according to claim 22, wherein: After forming the second source-drain doped layer and before forming the growth layer covering the sidewalls of the stacked structure of the first device region, the method further includes: forming a second protective layer covering the sidewalls and top of the dummy gate structure of the second device region and the second source-drain doped layer; In the step of forming a growth layer covering the sidewalls of the stacked structure of the first device region, the second protective layer is used as a mask; After forming the first source-drain doped layer, the method further includes: removing the second protective layer.

24. The method for forming a semiconductor structure according to claim 19, wherein: The first device region is a PMOS region, and the second device region is an NMOS region.

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