Formation method of semiconductor structure

Abstract

A method for forming a semiconductor structure comprises the following steps: providing a wafer which comprises a functional surface and a non-functional surface; forming a functional layer structure on the surface of the functional surface; obtaining the warping condition of the wafer; according to the warping condition, at least one time of stress neutralization treatment is carried out on the surface of the non-functional surface to form a stress neutralization structure, the stress neutralization structure comprises at least one stress layer, and the stress neutralization treatment comprises the steps that an initial stress layer is formed on the surface of the non-functional surface; and performing stress enhancement processing on the initial stress layer to form the stress layer. The warping condition of the wafer is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure. Background Art

[0002] As technology development follows Moore's Law, three-dimensional integrated circuits (3D ICs) are attracting more and more attention from researchers. The development direction of existing 3D integrated circuits has shifted from horizontal to vertical planes, such as 3D memory, 3D through-silicon vias, and monolithic 3D.

[0003] Due to the mismatch in the coefficient of thermal expansion (CTE) between different stacked materials deposited on the wafer, as the temperature decreases, the film and the wafer shrink at different rates, and the residual stress generated in the wafer causes the wafer to bend up or down, resulting in wafer warpage.

[0004] If the curvature or warping of the wafer is too large or the warping is different in different directions, the wafer processing will be restricted or even the wafer cannot be processed on the same machine, thereby increasing the device manufacturing cost.

[0005] Therefore, improving the warpage of wafers is an ongoing issue that needs to be addressed. Summary of the invention

[0006] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the warping of a wafer.

[0007] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a wafer, the wafer comprising a functional surface and a non-functional surface; forming a functional layer structure on the surface of the functional surface; obtaining the warping condition of the wafer; according to the warping condition, performing at least one stress neutralization treatment on the surface of the non-functional surface to form a stress neutralization structure, the stress neutralization structure comprising at least one stress layer, and the stress neutralization treatment comprising: forming an initial stress layer on the surface of the non-functional surface; performing stress enhancement treatment on the initial stress layer to form the stress layer.

[0008] Optionally, the warping of the wafer includes: the wafer is bent toward a non-functional surface, or the wafer is bent toward a functional surface.

[0009] Optionally, when the wafer is bent toward the functional surface, the initial stress layer has an initial compressive stress; and the compressive stress of the stress layer is greater than the initial compressive stress of the initial stress layer.

[0010] Optionally, the process of performing stress enhancement treatment on the initial stress layer includes: ion implantation process.

[0011] Optionally, the material of the initial stress layer includes silicon oxide or silicon carbide.

[0012] Optionally, the implanted ions in the ion implantation process include nitrogen ions.

[0013] Optionally, when the wafer is bent toward the non-functional surface, the initial stress layer has an initial tensile stress; and the tensile stress of the stress layer is greater than the initial tensile stress of the initial stress layer.

[0014] Optionally, the process of performing stress enhancement treatment on the initial stress layer includes: a plasma treatment process, wherein the gas of the plasma treatment process is the same as at least one of the reaction gases used to form the initial stress layer.

[0015] Optionally, the material of the initial stress layer includes silicon nitride or silicon oxynitride, and the silicon oxynitride includes silicon oxynitride.

[0016] Optionally, when the material of the initial stress layer includes silicon nitride, the gas used in the plasma treatment process for performing stress enhancement treatment on the initial stress layer includes nitrogen.

[0017] Optionally, the reaction time of the plasma treatment process includes: 40 seconds to 80 seconds.

[0018] Optionally, the process of forming the initial stress layer includes a plasma enhanced chemical vapor deposition process.

[0019] Optionally, when the material of the initial stress layer includes silicon nitride, the process parameters of the plasma enhanced chemical vapor deposition process include: the reaction gases include silane, ammonia and nitrogen, the flow rate of the silane accounts for 15% to 25% of the total flow rate, the flow rate of the ammonia accounts for 25% to 35% of the total flow rate, and the flow rate of the nitrogen accounts for 45% to 55% of the total flow rate; the temperature range is 375 degrees Celsius to 425 degrees Celsius; the pressure range is 6 Torr to 8 Torr; and the power range is 200 watts to 300 watts.

[0020] Optionally, when the wafer warpage is within a first preset range, the initial stress layer has a first thickness; when the wafer warpage is within a second preset range, the initial stress layer has a second thickness, the first preset range is smaller than the second preset range, and the first thickness is smaller than the second thickness.

[0021] Optionally, the first preset range is 50 microns to 100 microns, and the first thickness is 15 angstroms to 25 angstroms; the first preset range is greater than 100 microns, and the second thickness is 25 angstroms to 35 angstroms.

[0022] Optionally, the materials of the multiple stress layers are the same.

[0023] Optionally, the materials of the multiple stress layers are not completely the same.

[0024] Optionally, the thicknesses of the multiple stress layers are the same.

[0025] Optionally, the thicknesses of the multiple stress layers are not completely the same.

[0026] Optionally, before forming the stress neutralization structure on the surface of the non-functional surface, the method further includes: forming a protective layer on the surface of the functional layer structure.

[0027] Optionally, forming a stress neutralization structure further includes: obtaining a warping condition of the wafer, wherein the warping degree of the wafer is within a preset range.

[0028] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0029] The formation method of the present invention performs at least one stress neutralization treatment on the surface of the non-functional surface, and the stress neutralization treatment includes: forming an initial stress layer on the surface of the non-functional surface; performing stress enhancement treatment on the initial stress layer to form the stress layer. The multiple stress layers are stress enhanced in sequence, so that the stress of the formed stress neutralization structure is enhanced as a whole, the warping of the wafer is improved, and the warping degree of the wafer meets the preset range.

[0030] Furthermore, the process of performing stress enhancement treatment on the initial stress layer includes: a plasma treatment process, wherein the gas of the plasma treatment process is the same as at least one of the reaction gases used to form the initial stress layer, so that other types of gas impurities are not introduced during the process of performing stress enhancement treatment on the initial stress layer, which is beneficial to improving the stress of the formed stress layer.

[0031] Furthermore, the gas used in the plasma treatment process for stress enhancement treatment of the initial stress layer includes nitrogen. The plasma containing nitrogen provides sufficient energy to open the Si-H bonds and NH bonds in the silicon nitride film. This process allows hydrogen elements to be removed, and the generated Si-N bonds can enhance the stress of silicon nitride.

[0032] Furthermore, when the wafer warpage is within a first preset range, the initial stress layer has a first thickness; when the wafer warpage is within a second preset range, the initial stress layer has a second thickness, the first preset range is smaller than the second preset range, and the first thickness is smaller than the second thickness. The thickness range of the single-layer initial stress layer is set according to the wafer warpage, and the film thickness of the initial stress layer is relatively thin, so the use of plasma treatment can have a significant effect on the stress enhancement of the thin initial stress layer film, thereby increasing the stress of the stress layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a schematic flow chart of a method for forming a semiconductor structure in an embodiment of the present invention;

[0034] Figures 2 to 5 is a structural schematic diagram of a formation process of a semiconductor structure in one embodiment of the present invention;

[0035] Figure 6 It is a structural schematic diagram of a formation process of a semiconductor structure in another embodiment of the present invention. DETAILED DESCRIPTION

[0036] As described in the background art, improving the warpage of wafers is a problem that needs to be solved continuously.

[0037] Specifically, methods for improving the wafer warpage problem generally include: (1) thermal annealing: usually used to solve isotropic wafer warpage, with the property of heating the whole wafer, so that the speed of rapid heating of different areas of the wafer is inconsistent, resulting in uneven temperature field distribution, which leads to uneven thermal deformation of the wafer; (2) ion implantation: by doping ions to generate stress opposite to the warpage, the degree of warpage is reduced, but at the same time, it is necessary to add a back mask and implantation process, which is complicated; (3) thin film deposition: an auxiliary film with the opposite stress type to the wafer is formed on the back to offset the stress of the wafer. Conventional PECVD can prepare thin films through a high-frequency power source, but the stress of the obtained thin film is low and cannot effectively improve the warpage of the wafer.

[0038] In order to solve the above problems, the technical solution of the present invention provides a method for forming a semiconductor structure, by performing at least one stress neutralization treatment on the surface of the non-functional surface, the stress neutralization treatment includes: forming an initial stress layer on the surface of the non-functional surface; performing stress enhancement treatment on the initial stress layer to form the stress layer. The multiple stress layers are stress enhanced in sequence, so that the stress of the formed stress neutralization structure is enhanced as a whole, the warping of the wafer is improved, and the warping degree of the wafer meets the preset range.

[0039] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0040] Figure 1 It is a schematic flow chart of a method for forming a semiconductor structure in an embodiment of the present invention.

[0041] Please refer to Figure 1 , the process of the method for forming the semiconductor structure includes:

[0042] Step S10: providing a wafer, wherein the wafer includes a functional surface and a non-functional surface;

[0043] Step S20: forming a functional layer structure on the surface of the functional surface;

[0044] Step S30: obtaining the warpage condition of the wafer;

[0045] Step S40: According to the warping condition, the non-functional surface is subjected to at least one stress neutralization treatment to form a stress neutralization structure, wherein the stress neutralization structure includes at least one stress layer, and the stress neutralization treatment includes: forming an initial stress layer on the non-functional surface; and performing stress enhancement treatment on the initial stress layer to form the stress layer.

[0046] The formation method performs at least one stress neutralization treatment on the surface of the non-functional surface, and the stress neutralization treatment includes: forming an initial stress layer on the surface of the non-functional surface; performing stress enhancement treatment on the initial stress layer to form the stress layer. Multiple stress layers are stress enhanced in sequence, so that the stress of the formed stress neutralization structure is enhanced as a whole, the warping of the wafer is improved, and the warping degree of the wafer meets the preset range.

[0047] The warping of the wafer includes: the wafer is bent toward the non-functional surface, or the wafer is bent toward the functional surface.

[0048] In one embodiment, when the wafer is bent toward the functional surface, the initial stress layer has an initial compressive stress; and the compressive stress of the stress layer is greater than the initial compressive stress of the initial stress layer.

[0049] In this embodiment, when the wafer is bent toward the non-functional surface, the initial stress layer has an initial tensile stress; and the tensile stress of the stress layer is greater than the initial tensile stress of the initial stress layer.

[0050] Next, combine Figures 2 to 5 Each step is analyzed and explained. Figures 2 to 5 It is a structural schematic diagram of a formation process of a semiconductor structure in one embodiment of the present invention.

[0051] Please combine Figure 2 Execute step S10: provide a wafer 100, wherein the wafer 100 includes a functional surface S1 and a non-functional surface S2; execute step S20: form a functional layer structure on the surface of the functional surface S1.

[0052] The functional layer structure includes a stack of multiple thin films, the stresses between the multiple thin films are mismatched, and the stresses between the functional layer structure and the wafer 100 are mismatched.

[0053] Please continue to refer to Figure 2 , further comprising: forming a protective layer 101 on the surface of the functional layer structure.

[0054] The protective layer 101 is used to protect the surface of the functional layer structure.

[0055] In this embodiment, the material of the protection layer 101 includes silicon oxide.

[0056] Please continue to combine Figure 2 Execute step S30: obtain the warping condition of the wafer 100, where the warping condition of the wafer 100 includes: the wafer 100 is bent toward the non-functional surface S2.

[0057] In this embodiment, the warping condition of the wafer 100 also includes: the warping degree of the wafer 100 toward the non-functional surface S2 is greater than a preset value.

[0058] The preset value is a standard value for determining whether wafer warpage will affect production and yield. Wafers with a warpage within the preset range meet production and yield requirements.

[0059] In this embodiment, the wafer 100 is bent toward the non-functional surface S2 , and compressive stress is generated on the surface of the non-functional surface S2 of the wafer 100 .

[0060] Next, please combine Figure 3 and Figure 4 Execute step S40: according to the warping condition, perform at least one stress neutralization treatment on the surface of the non-functional surface to form a stress neutralization structure, wherein the stress neutralization structure includes at least one stress layer, and the stress neutralization treatment includes: forming an initial stress layer on the surface of the non-functional surface; performing stress enhancement treatment on the initial stress layer to form the stress layer.

[0061] The stress of the stress layer is greater than the stress of the initial stress layer.

[0062] When the initial stress layer has an initial tensile stress, the material of the initial stress layer includes silicon nitride or silicon oxynitride, and the silicon oxynitride includes silicon nitride oxide.

[0063] When the initial stress layer has initial compressive stress, the material of the initial stress layer includes silicon oxide or silicon carbide.

[0064] In this embodiment, the materials of the multiple stress layers are the same, so that the stress of each stress layer can be well controlled and the number of stress layers to be formed can be calculated.

[0065] In other embodiments, the materials of the multiple stress layers may not be completely the same, so that the material selection freedom of the stress neutralization structure is higher.

[0066] In this embodiment, the thickness of the multiple stress layers is the same, so that the stress of each stress layer can be well controlled and the number of stress layers to be formed can be calculated.

[0067] In other embodiments, the thicknesses of the multiple stress layers are not completely the same, so that the process window of the formation process of the stress neutralization structure is large, and it is not necessary to require that the thickness of each stress layer be the same.

[0068] Please refer to Figure 3 , performing a first stress neutralization treatment on the surface of the non-functional surface S2, and forming a first stress layer 102 on the surface of the non-functional surface S2.

[0069] The method for forming the first stress layer 102 includes: forming an initial stress layer on the surface of the non-functional surface S2 ; and performing stress enhancement treatment on the initial stress layer to form the first stress layer 102 .

[0070] The material of the initial stress layer includes silicon nitride or silicon oxynitride.

[0071] In this embodiment, the material of the initial stress layer includes silicon nitride. The material of the initial stress layer has initial tensile stress, which can neutralize the compressive stress on the surface of the non-functional surface S2 and improve the warpage of the wafer.

[0072] The initial stress layer has an initial tensile stress, and the process of performing stress enhancement treatment on the initial stress layer includes: a plasma treatment process, wherein the gas of the plasma treatment process is the same as at least one of the reaction gases forming the initial stress layer.

[0073] The gas of the plasma treatment process is of the same type as at least one of the reaction gases used to form the initial stress layer, so that other types of gas impurities are not introduced during the stress enhancement treatment of the initial stress layer, which is beneficial to enhancing the stress of the formed stress layer, and the stress of the stress layer is greater than the stress of the initial stress layer.

[0074] In this embodiment, the gas used in the plasma treatment process for performing stress enhancement treatment on the initial stress layer includes nitrogen.

[0075] The gas used in the plasma treatment process for stress enhancement treatment of the initial stress layer includes nitrogen. The plasma containing nitrogen provides sufficient energy to open the Si-H bonds and NH bonds in the silicon nitride film. This process allows hydrogen elements to be removed, and the generated Si-N bonds can enhance the stress of silicon nitride.

[0076] In this embodiment, the process of forming the initial stress layer includes a plasma enhanced chemical vapor deposition (PECVD) process.

[0077] The process parameters of the plasma enhanced chemical vapor deposition process include: the reaction gases include silane, ammonia and nitrogen, the flow rate of the silane accounts for 15% to 25% of the total flow rate, the flow rate of the ammonia accounts for 25% to 35% of the total flow rate, and the flow rate of the nitrogen accounts for 45% to 55% of the total flow rate; the temperature range is 375 degrees Celsius to 425 degrees Celsius; the pressure range is 6 Torr to 8 Torr; and the power range is 200 watts to 300 watts.

[0078] The nitrogen gas used in the plasma treatment process is of the same type as the nitrogen gas used as the reaction gas in the plasma enhanced chemical vapor deposition process, so that no new impurities are introduced when the initial stress layer is enhanced by the plasma treatment process.

[0079] In this embodiment, the reaction time of the plasma treatment process ranges from 40 seconds to 80 seconds.

[0080] When the wafer warpage is within a first preset range, the initial stress layer has a first thickness; when the wafer warpage is within a second preset range, the initial stress layer has a second thickness, the first preset range is smaller than the second preset range, and the first thickness is smaller than the second thickness.

[0081] In this embodiment, the first preset range is 50 micrometers to 100 micrometers, and the first thickness is 15 angstroms to 25 angstroms; the first preset range is greater than 100 micrometers, and the second thickness is 25 angstroms to 35 angstroms.

[0082] The thickness range of the single initial stress layer is set according to the warpage of the wafer. The film thickness of the initial stress layer is relatively thin, so plasma treatment can significantly affect the stress enhancement of the thinner initial stress layer film, thereby increasing the stress of the first stress layer 102 .

[0083] Please refer to Figure 4 , performing a second stress neutralization treatment on the surface of the non-functional surface S2 to form a second stress layer 103 on the surface of the first stress layer 102 .

[0084] The method for forming the second stress layer 103 includes: forming an initial stress layer on the surface of the first stress layer 102 ; and performing stress enhancement treatment on the initial stress layer to form the second stress layer 103 .

[0085] The process of performing stress enhancement treatment on the initial stress layer includes: a plasma treatment process, wherein the gas of the plasma treatment process is the same as at least one of the reaction gases used to form the initial stress layer.

[0086] The gas used in the plasma treatment process is of the same type as at least one of the reaction gases used to form the initial stress layer, so that other types of gas impurities will not be introduced during the stress enhancement treatment of the initial stress layer, which is beneficial to enhancing the stress of the formed stress layer.

[0087] In this embodiment, the material of the initial stress layer includes silicon nitride. The silicon nitride material has an initial tensile stress, which can neutralize the compressive stress on the surface of the non-functional surface S2 and improve the warping of the wafer. The gas in the plasma treatment process for stress enhancement treatment of the initial stress layer includes nitrogen. The nitrogen-containing plasma provides sufficient energy to open the Si-H bonds and NH bonds in the silicon nitride film. This process allows the hydrogen element to be removed, and the generated Si-N bonds can enhance the stress of silicon nitride.

[0088] In this embodiment, the process of forming the initial stress layer includes a plasma enhanced chemical vapor deposition (PECVD) process.

[0089] The process parameters of the plasma enhanced chemical vapor deposition process include: the reaction gases include silane, ammonia and nitrogen, the flow rate of the silane accounts for 15% to 25% of the total flow rate, the flow rate of the ammonia accounts for 25% to 35% of the total flow rate, and the flow rate of the nitrogen accounts for 45% to 55% of the total flow rate; the temperature range is 375 degrees Celsius to 425 degrees Celsius; the pressure range is 6 Torr to 8 Torr; and the power range is 200 watts to 300 watts.

[0090] The nitrogen gas used in the plasma treatment process is of the same type as the nitrogen gas used as the reaction gas in the plasma enhanced chemical vapor deposition process, so that no new impurities are introduced when the initial stress layer is enhanced by the plasma treatment process.

[0091] In this embodiment, the reaction time of the plasma treatment process ranges from 40 seconds to 80 seconds.

[0092] In this embodiment, only two stress neutralization processes are illustrated. The stress neutralization structure includes a first stress layer 102 and a second stress layer 103 on the surface of the first stress layer 102 .

[0093] In other embodiments, the stress neutralization treatment process further includes one or more times until the formed stress neutralization structure makes the warpage of the wafer within a preset range.

[0094] In this embodiment, the materials of the first stress layer 102 and the second stress layer 103 are the same. In other embodiments, the materials of the first stress layer and the second stress layer may be different.

[0095] In this embodiment, the first stress layer 102 and the second stress layer 103 have the same thickness.

[0096] In other embodiments, the thicknesses of the first stress layer and the second stress layer may be different.

[0097] When the wafer warpage is within a first preset range, the initial stress layer has a first thickness; when the wafer warpage is within a second preset range, the initial stress layer has a second thickness, the first preset range is smaller than the second preset range, and the first thickness is smaller than the second thickness.

[0098] In this embodiment, the first preset range is 50 micrometers to 100 micrometers, and the first thickness is 15 angstroms to 25 angstroms; the first preset range is greater than 100 micrometers, and the second thickness is 25 angstroms to 35 angstroms.

[0099] The thickness range of the single initial stress layer is set according to the warpage of the wafer. The film thickness of the initial stress layer is relatively thin, so plasma treatment can have a significant effect on the stress enhancement of the thinner initial stress layer film, thereby increasing the stress of the second stress layer 103 .

[0100] Please refer to Figure 5 After the stress neutralization structure is formed, the warping condition of the wafer 100 is obtained, and the warping degree of the wafer is within a preset range.

[0101] In this embodiment, the preset range includes: less than or equal to 20 micrometers.

[0102] Figure 6 It is a structural schematic diagram of a formation process of a semiconductor structure in another embodiment of the present invention.

[0103] Please refer to Figure 6 , Figure 6 The semiconductor structure and Figure 3 The difference between the semiconductor structure in the embodiment is that: in the embodiment, the wafer is bent toward the functional surface, the initial stress layer has an initial compressive stress; the compressive stress of the stress layer is greater than the initial compressive stress of the initial stress layer.

[0104] According to the warping condition, the non-functional surface is subjected to at least one stress neutralization treatment to form a stress neutralization structure, wherein the stress neutralization structure includes at least one stress layer, and the stress neutralization treatment includes: forming an initial stress layer on the non-functional surface; and performing stress enhancement treatment on the initial stress layer to form the stress layer.

[0105] In this embodiment, it is schematically shown that a stress neutralization treatment is performed on the surface of the non-functional surface S2 to form a stress layer 202 on the surface of the non-functional surface S2.

[0106] The method for forming the stress layer 202 includes: forming an initial stress layer on the surface of the non-functional surface S2 ; and performing stress enhancement treatment on the initial stress layer to form the stress layer 202 .

[0107] The material of the initial stress layer includes silicon oxide or silicon carbide.

[0108] In this embodiment, the material of the initial stress layer includes silicon oxide. The material of the initial stress layer has initial compressive stress, which can neutralize the tensile stress on the surface of the non-functional surface S2 and improve the warping of the wafer.

[0109] The process of performing stress enhancement treatment on the initial stress layer includes: ion implantation process.

[0110] In this embodiment, the implanted ions of the ion implantation process include nitrogen ions. Doping nitrogen into silicon oxide (forming SiOxNγ silicon oxynitride) can effectively increase compressive stress because the Si-O bond in silicon oxide is relatively long and has a lower bond energy. When nitrogen is doped into silicon oxide, the Si-N bond is shorter and stronger than the Si-O bond. This change in chemical bonds makes the network structure of the entire material denser and increases the shrinkage of the material, thereby introducing higher intrinsic compressive stress. The bond length of the Si-N bond is shorter than that of the Si-O bond, which makes the lattice structure tend to compress during deposition or growth. This compressibility naturally causes the silicon oxynitride film to exhibit intrinsic compressive stress.

[0111] In this embodiment, the process of forming the initial stress layer includes a plasma enhanced chemical vapor deposition (PECVD) process.

[0112] In this embodiment, Figure 6 Only one stress neutralization process is illustrated. The stress neutralization structure includes a stress layer 202 .

[0113] In other embodiments, the stress neutralization treatment process is performed multiple times, and the stress neutralization structure includes multiple stress layers, until the formed stress neutralization structure makes the warpage of the wafer within a preset range.

[0114] In one embodiment, the materials of the multiple stress layers are the same, so that the stress of each stress layer can be well controlled and the number of stress layers to be formed can be calculated.

[0115] In other embodiments, the materials of the multiple stress layers may not be completely the same, so that the material selection freedom of the stress neutralization structure is higher.

[0116] In one embodiment, the thickness of the multiple stress layers is the same, so that the stress of each stress layer can be well controlled and the number of stress layers to be formed can be calculated.

[0117] In other embodiments, the thicknesses of the multiple stress layers are not completely the same, so that the process window of the formation process of the stress neutralization structure is large, and it is not necessary to require that the thickness of each stress layer be the same.

[0118] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a wafer, wherein the wafer comprises a functional surface and a non-functional surface; forming a functional layer structure on the surface of the functional surface; Obtaining a warpage condition of the wafer; According to the warping condition, the surface of the non-functional surface is subjected to at least one stress neutralization treatment to form a stress neutralization structure, wherein the stress neutralization structure includes at least one stress layer, and the stress neutralization treatment includes: forming an initial stress layer on the surface of the non-functional surface; The initial stress layer is subjected to stress enhancement treatment to form the stress layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The warping of the wafer includes: the wafer is bent toward the non-functional surface, or the wafer is bent toward the functional surface.

3. The method for forming a semiconductor structure according to claim 2, wherein: When the wafer is bent toward the functional surface, the initial stress layer has an initial compressive stress; and the compressive stress of the stress layer is greater than the initial compressive stress of the initial stress layer.

4. The method for forming a semiconductor structure according to claim 3, wherein: The process of performing stress enhancement treatment on the initial stress layer includes: ion implantation process.

5. The method for forming a semiconductor structure according to claim 3, wherein: The material of the initial stress layer includes silicon oxide or silicon carbide.

6. The method for forming a semiconductor structure according to claim 4, wherein: The implanted ions in the ion implantation process include nitrogen ions.

7. The method for forming a semiconductor structure according to claim 2, wherein: When the wafer is bent toward the non-functional surface, the initial stress layer has an initial tensile stress; and the tensile stress of the stress layer is greater than the initial tensile stress of the initial stress layer.

8. The method for forming a semiconductor structure according to claim 7, wherein: The process of performing stress enhancement treatment on the initial stress layer includes: a plasma treatment process, wherein the gas of the plasma treatment process is the same as at least one of the reaction gases used to form the initial stress layer.

9. The method for forming a semiconductor structure according to claim 7, wherein: The material of the initial stress layer includes silicon nitride or silicon oxynitride, and the silicon oxynitride includes silicon nitride oxide.

10. The method for forming a semiconductor structure according to claim 8, wherein: The gas used in the plasma treatment process for performing stress enhancement treatment on the initial stress layer includes nitrogen.

11. The method for forming a semiconductor structure according to claim 8, wherein: The reaction time of the plasma treatment process ranges from 40 seconds to 80 seconds.

12. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the initial stress layer includes a plasma enhanced chemical vapor deposition process.

13. The method for forming a semiconductor structure according to claim 12, wherein: When the material of the initial stress layer includes silicon nitride, the process parameters of the plasma enhanced chemical vapor deposition process include: the reaction gases include silane, ammonia and nitrogen, the flow rate of the silane accounts for 15% to 25% of the total flow rate, the flow rate of the ammonia accounts for 25% to 35% of the total flow rate, and the flow rate of the nitrogen accounts for 45% to 55% of the total flow rate; the temperature range is 375 degrees Celsius to 425 degrees Celsius; the pressure range is 6 Torr to 8 Torr; and the power range is 200 watts to 300 watts.

14. The method for forming a semiconductor structure according to claim 1, wherein: When the wafer warpage is within a first preset range, the initial stress layer has a first thickness; when the wafer warpage is within a second preset range, the initial stress layer has a second thickness, the first preset range is smaller than the second preset range, and the first thickness is smaller than the second thickness.

15. The method for forming a semiconductor structure according to claim 14, wherein: The first preset range is 50 micrometers to 100 micrometers, and the first thickness is 15 angstroms to 25 angstroms; the first preset range is greater than 100 micrometers, and the second thickness is 25 angstroms to 35 angstroms.

16. The method for forming a semiconductor structure according to claim 1, wherein: The materials of the multiple stress layers are the same.

17. The method for forming a semiconductor structure according to claim 1, wherein: The materials of the multiple stress layers are not exactly the same.

18. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the multiple stress layers is the same.

19. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the multiple stress layers is not exactly the same.

20. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the stress neutralization structure on the surface of the non-functional surface, the method further includes: forming a protective layer on the surface of the functional layer structure.

21. The method for forming a semiconductor structure according to claim 1, wherein: Forming a stress neutralization structure also includes: obtaining a warpage condition of the wafer, wherein the warpage degree of the wafer is within a preset range.

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