Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a substrate which comprises a first region and a second region; the channel structure is suspended on the substrate, and the channel structure comprises one or more channel layers which are sequentially arranged at intervals from bottom to top; the gate structure stretches across the channel structure and surrounds the channel layer, and the gate structure comprises a work function layer surrounding the channel layer, a work function layer located between the channel layer and the substrate or located between the adjacent channel layers, a work function layer serving as a first work function layer, a work function layer located at the top of the topmost channel layer and a second work function layer; wherein the sum of the thickness of the first work function layer and the thickness of the second work function layer in the first area is larger than the sum of the thickness of the first work function layer and the thickness of the second work function layer in the second area. According to the embodiment of the invention, under the condition that the threshold voltage of the semiconductor device in the second region meets the requirement, the threshold voltage of the semiconductor device in the first region is improved, so that the semiconductor device can meet different functional requirements.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration, and semiconductor process nodes are continuously decreasing in accordance with Moore's Law. Transistor size is getting smaller and smaller, and Fin-type field-effect transistor (FinFET) came into being. However, to maintain the original driving current performance, this structure is no longer suitable for smaller nodes. So the all-around gate transistor (Gate-All-Around, GAAFET) appeared. Its control of short channel effects and superior electrical performance make it replace FinFET and become the mainstream at smaller process nodes.

[0003] The threshold voltage is an important parameter of the transistor and has a significant impact on the performance of the transistor. Transistors with different functions often have different requirements for the threshold voltage. In the process of forming different transistors, the threshold voltage of different transistors needs to be adjusted.

[0004] However, the performance of current all-around gate transistors still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, the substrate including a first region and a second region; a channel structure, suspended on the substrate, the channel structure including one or more channel layers spaced in sequence from bottom to top; a gate structure, spanning the channel structure and surrounding the channel layer, the gate structure including a work function layer surrounding the channel layer, a work function layer located between the channel layer and the substrate or between adjacent channel layers, serving as a first work function layer, and a work function layer located on top of the topmost channel layer, serving as a second work function layer; wherein the sum of the thicknesses of the first work function layer and the second work function layer in the first region is greater than the sum of the thicknesses of the first work function layer and the second work function layer in the second region.

[0007] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region and a second region; forming one or more channel stacks stacked in sequence on the substrate, each of the channel stacks comprising a sacrificial layer and a channel layer located on the sacrificial layer; forming a dummy gate structure spanning the channel stack, the dummy gate structure covering part of the top and part of the sidewalls of the channel stack; removing the dummy gate structure, forming an opening at the position of the dummy gate structure, the opening exposing the top and sidewalls of the channel stack; removing the sacrificial layer through the opening to form a through groove between the substrate and the channel layer, or between adjacent channel layers; forming a gate structure in the opening and the through groove, the gate structure comprising a work function layer surrounding the channel layer, the work function layer located in the through groove serving as the first work function layer, and the work function layer located on the top of the topmost channel layer serving as the second work function layer; wherein the sum of the thicknesses of the first work function layer and the second work function layer in the first region is greater than the sum of the thicknesses of the first work function layer and the second work function layer in the second region.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] The semiconductor structure provided by an embodiment of the present invention includes a gate structure that spans the channel structure and surrounds the channel layer, the gate structure includes a work function layer surrounding the channel layer, a work function layer located between the channel layer and the substrate or between adjacent channel layers, serving as a first work function layer, and a work function layer located on top of the topmost channel layer, serving as a second work function layer; wherein the sum of the thicknesses of the first work function layer and the second work function layer in the first region is greater than the sum of the thicknesses of the first work function layer and the second work function layer in the second region, that is, the sum of the thicknesses of the work function layers at the bottom and top of the channel layer in the first region is greater than the sum of the thicknesses of the work function layers at the bottom and top of the channel layer in the second region, which is beneficial to improve the threshold voltage of the semiconductor devices in the first region when the threshold voltage of the semiconductor devices in the second region meets the requirements, so that the semiconductor devices in the first region and the semiconductor devices in the second region can meet different functional requirements, thereby improving the performance of the semiconductor structure.

[0010] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a gate structure is formed in the opening and the through groove, and the gate structure includes a work function layer surrounding the channel layer, the work function layer located in the through groove serves as the first work function layer, and the work function layer located on the top of the topmost channel layer serves as the second work function layer; wherein the sum of the thicknesses of the first work function layer and the second work function layer in the first region is greater than the sum of the thicknesses of the first work function layer and the second work function layer in the second region, that is, the sum of the thicknesses of the work function layers at the bottom and top of the channel layer in the first region is greater than the sum of the thicknesses of the work function layers at the bottom and top of the channel layer in the second region, which is beneficial to improving the threshold voltage of the semiconductor device in the first region when the threshold voltage of the semiconductor device in the second region meets the requirements, so that the semiconductor device in the first region and the semiconductor device in the second region can meet different functional requirements, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a schematic diagram of the structure of a semiconductor structure;

[0012] Figure 2 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0013] Figures 3 to 9 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0014] At present, the performance of semiconductor structures still needs to be improved. Now, combining a semiconductor structure, we analyze the reasons why the performance of semiconductor structures needs to be improved. Figure 1 It is a structural diagram of a semiconductor structure.

[0015] refer to Figure 1 The semiconductor structure includes: a substrate 10, the substrate including an NMOS region i′ and a PMOS region ii′; a channel structure 20, suspended on the substrate 10, the channel structure 20 including one or more channel layers 21 arranged in sequence from bottom to top; a gate structure 30, spanning the channel structure 20 and surrounding the channel layer 21, the gate structure 30 including a work function layer 31 surrounding the channel layer.

[0016] Research has found that the threshold voltage of the MOS transistor is mainly determined by the thickness of the work function layer 31. When the work function layer material of the NMOS region i′ is consistent with the work function layer material of the PMOS region ii′ (for example, both are titanium nitride), if the threshold voltage of the NMOS region i′ is proportional to the thickness of the work function layer 31, then the threshold voltage of the PMOS region ii′ is inversely proportional to the thickness of the work function layer 31, so it is difficult to simultaneously meet the threshold voltage requirements of the NMOS region i′ and the PMOS region ii′, which limits the electrical performance of the MOS transistor.

[0017] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, the substrate including a first region and a second region; a channel structure, suspended on the substrate, the channel structure including one or more channel layers arranged in sequence from bottom to top; a gate structure, spanning the channel structure and surrounding the channel layer, the gate structure including a work function layer surrounding the channel layer, a work function layer located between the channel layer and the substrate, or between adjacent channel layers, serving as a first work function layer, and a work function layer located on top of the topmost channel layer, serving as a second work function layer; wherein the sum of the thicknesses of the first work function layer and the second work function layer in the first region is greater than the sum of the thicknesses of the first work function layer and the second work function layer in the second region.

[0018] The semiconductor structure provided by an embodiment of the present invention includes a gate structure that spans the channel structure and surrounds the channel layer, the gate structure includes a work function layer surrounding the channel layer, a work function layer located between the channel layer and the substrate or between adjacent channel layers, serving as a first work function layer, and a work function layer located on top of the topmost channel layer, serving as a second work function layer; wherein the sum of the thicknesses of the first work function layer and the second work function layer in the first region is greater than the sum of the thicknesses of the first work function layer and the second work function layer in the second region, that is, the sum of the thicknesses of the work function layers at the bottom and top of the channel layer in the first region is greater than the sum of the thicknesses of the work function layers at the bottom and top of the channel layer in the second region, which is beneficial to improve the threshold voltage of the semiconductor devices in the first region when the threshold voltage of the semiconductor devices in the second region meets the requirements, so that the semiconductor devices in the first region and the semiconductor devices in the second region can meet different functional requirements, thereby improving the performance of the semiconductor structure.

[0019] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0020] Figure 2 It is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

[0021] refer to Figure 2 In this embodiment, the semiconductor structure includes: a substrate 100, the substrate 100 includes a first region i and a second region ii; a channel structure 115, suspended on the substrate 100, the channel structure 115 includes one or more channel layers 112 arranged in sequence from bottom to top; a gate structure 150, spanning the channel structure 115 and surrounding the channel layer 112, the gate structure 150 includes a work function layer 151 surrounding the channel layer 112, the work function layer 151 located between the channel layer 112 and the substrate 100 or between adjacent channel layers 112, serving as a first work function layer 1511, and the work function layer 151 located on top of the topmost channel layer 112, serving as a second work function layer 1512; wherein the sum of the thicknesses of the first work function layer 1511 and the second work function layer 1512 of the first region i is greater than the sum of the thicknesses of the first work function layer 1511 and the second work function layer 1512 of the second region ii.

[0022] The substrate 100 provides a process platform for forming a semiconductor structure.

[0023] In this embodiment, the substrate 100 is used to form a fully surrounded gate transistor.

[0024] In this embodiment, the base 100 includes a substrate (not shown), which is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator.

[0025] In this embodiment, the first region i and the second region ii are used to form different types of MOS devices. Specifically, the first region i is used to form an NMOS device, and the second region ii is used to form a PMOS device.

[0026] In this embodiment, a groove (not shown) is formed in the substrate 100, and the groove is used to define an isolation region between adjacent devices so as to provide a spatial position for forming an isolation layer in the groove. The substrate 100 at the bottom of the groove serves as a substrate.

[0027] In this embodiment, the semiconductor structure further includes: an isolation layer 120, which is located in the trench. The isolation layer 120 is used to achieve isolation between adjacent devices. In this embodiment, the isolation layer 120 is a shallow trench isolation structure (STI). Specifically, the material of the isolation layer 120 may include one or more of silicon oxide, silicon oxynitride and silicon nitride.

[0028] In this embodiment, the channel structure 115 includes a plurality of channel layers 112 as an example for explanation, and the direction in which the plurality of channel layers 112 are stacked and arranged on the substrate 100 is perpendicular to the top surface of the substrate 100. Specifically, the number of the channel layers 112 is three. In other embodiments, the number of the channel layers may also be two, four, etc. In other embodiments, based on actual process requirements, the number of the channel layers may also be only one.

[0029] The channel layer 112 is used to form a conductive channel of a MOS transistor.

[0030] In this embodiment, the top of the substrate 100 in the first region i is lower than the top of the substrate 100 in the second region ii, or the top of any channel layer 112 in the first region i is lower than the top of the channel layer 112 in the second region ii located in the same layer.

[0031] Here, the channel structure 115 includes one or more channel layers 112 arranged in sequence from bottom to top, therefore, being located in the same layer means: along the normal direction of the top surface of the substrate 100, the channel layer 112 has the same layer number as the channel layer 112 of the first region i, that is, the channel layer 112 whose bottom surface is flush.

[0032] Typically, one or more channel stacks (not shown) stacked in sequence are first formed on the substrate 100, each channel stack including a sacrificial layer (not shown) and a channel layer 112 located on the sacrificial layer; the sacrificial layer is removed to form a through groove (not shown) between the substrate 100 and the channel layer 112, or between adjacent channel layers 112, and then a gate structure 150 is formed in the through groove, the gate structure 150 including a first work function layer 1511 located in the through groove.

[0033] The top of the substrate 100 in the first region i is lower than the top of the substrate 100 in the second region ii, or the top of any channel layer 112 in the first region i is lower than the top of the channel layer 112 in the second region ii located in the same layer, which makes it easy for the height of the through groove (not marked) between the substrate 100 and the channel layer 112 in the first region i to be greater than the height of the through groove between the substrate 100 and the channel layer 112 in the second region ii, or the height of the through groove between adjacent channel layers 112 in the first region i is greater than the height of the through groove between adjacent channel layers 112 in the second region ii located in the same layer, which makes it easy for the sum of the through groove heights in the first region i to be greater than the sum of the through groove heights in the second region ii, thereby making it easier for the sum of the thicknesses of the first work function layers 1511 in the first region i to be greater than the sum of the thicknesses of the first work function layers 1511 in the second region ii.

[0034] It should be noted that, during the formation of the semiconductor structure, it is easy to process the top of the substrate 100 or the top of a certain channel layer 112 (for example, back etching) to lower its top surface, thereby making the top of the substrate 100 in the first region i lower than the top of the substrate 100 in the second region ii, or making the top of any channel layer 112 in the first region i lower than the top of the channel layer 112 in the second region ii located on the same layer, thereby reducing the manufacturing complexity of forming the semiconductor structure.

[0035] In this embodiment, the material of the channel layer 112 includes one or more of silicon, silicon germanium, germanium and III-V semiconductor materials.

[0036] In a specific embodiment, the material of the channel layer 112 is silicon. Usually, before forming the gate structure 150, one or more sequentially stacked channel stacks (not shown) are first formed on the substrate 100, each channel stack including a sacrificial layer (not shown) and a channel layer 112 located on the sacrificial layer, and then the dummy gate structure is removed, an opening (not shown) is formed at the position of the dummy gate structure, and the sacrificial layer is removed through the opening to form a through groove (not shown) located between the substrate 100 and the channel layer 112, or between adjacent channel layers 112; therefore, setting the material of the channel layer 112 to silicon and setting the material of the sacrificial layer to silicon germanium is conducive to reducing the influence of the sacrificial layer removal process on the channel layer 112, thereby making it easy to make the quality of the channel layer 112 better, and further conducive to improving the performance of the semiconductor device.

[0037] In this embodiment, the material of the substrate 100 is silicon, and the material of the channel layer 112 is silicon, that is, the material of the substrate 100 is the same as the material of the channel layer 112; since the etching selectivity of silicon germanium and silicon is relatively high, during the process of removing the sacrificial layer, it is also beneficial to reduce the effect of the sacrificial layer removal process on the substrate 100.

[0038] In other embodiments, the material of the channel layer may be different from the material of the substrate. As an example, the material of the substrate is silicon, and the material of the channel layer is a III-V semiconductor material.

[0039] The material of the channel layer is different from that of the substrate, which is beneficial for back-etching the currently exposed substrate in the first region after removing the sacrificial layer through the opening, so that the vertical distance between the substrate and the channel layer in the first region (i.e., the through-groove height) is greater than the vertical height between the substrate and the channel layer in the second region ii, thereby making it easy to make the thickness of the first work function layer between the substrate and the channel layer in the first region greater than the thickness of the first work function layer between the substrate and the channel layer in the second region; and, during the back-etching process, the probability of damage to the channel layer is reduced.

[0040] In the present embodiment, the top of the substrate 100 in the first region i is lower than the top of the substrate 100 in the second region ii, which makes it easy for the vertical distance between the substrate 100 and the channel layer 112 in the first region i (i.e., the through groove height) to be greater than the vertical distance between the substrate 100 and the channel layer 112 in the second region ii, thereby making it easy for the thickness of the first work function layer 1511 between the substrate 100 and the channel layer 112 in the first region i to be greater than the thickness of the first work function layer 1511 between the substrate 100 and the channel layer 112 in the second region ii.

[0041] In this embodiment, the semiconductor structure further includes: source-drain doped layers (not shown), which are located on the substrate 100 on both sides of the gate structure 150 and connected to the ends of the channel layer 112. When the device is working, the source-drain doped layers are used as source or drain to provide carrier sources.

[0042] In this embodiment, the semiconductor structure further includes: an interlayer dielectric layer (not shown), which covers the source-drain doped layer and exposes the top of the gate structure 150. The interlayer dielectric layer covers the source-drain doped layer and is used to protect the source-drain doped layer during the formation of the gate structure 150. The interlayer dielectric layer is also used to achieve electrical isolation between adjacent devices.

[0043] Specifically, the interlayer dielectric layer is formed on the isolation layer 120 and covers the source and drain doping layers.

[0044] It should be noted that the material of the interlayer dielectric layer includes one or more of silicon oxide and silicon nitride. As an example, the material of the interlayer dielectric layer is silicon nitride.

[0045] The gate structure 150 is a device gate structure. When the device is working, the gate structure 150 is used to control the opening and closing of the conductive channel.

[0046] The work function layer 151 is used to adjust the threshold voltage of the field effect transistor.

[0047] The sum of the thickness of the first work function layer 1511 and the second work function layer 1512 in the first region i is greater than the sum of the thickness of the first work function layer 1511 and the second work function layer 1512 in the second region ii, that is, the sum of the thickness of the work function layer 151 at the bottom and top of the channel layer 112 in the first region i is greater than the sum of the thickness of the work function layer 151 at the bottom and top of the channel layer 112 in the second region ii, which is beneficial to improve the threshold voltage of the semiconductor device in the first region i when the threshold voltage of the semiconductor device in the second region ii meets the requirements, so that the semiconductor device in the first region i and the semiconductor device in the second region ii can meet different functional requirements, thereby improving the performance of the semiconductor structure. Among them, the thickness of the first work function layer 1511 and the second work function layer 1512 both refer to: the thickness of the first work function layer 5511 and the second work function layer 1512 along the normal direction of the top surface of the substrate 100.

[0048] In this embodiment, along the normal direction of the top surface of the substrate 100 , the first work function layers 1511 located on the surfaces of adjacent channel layers 112 are in contact with each other, or the first work function layers located on the surfaces of adjacent channel layers 112 and the substrate 100 are in contact with each other.

[0049] Along the normal direction of the top surface of the substrate 100, the first work function layers 1511 located on the surfaces of adjacent channel layers 112 are in contact with each other, or the first work function layers located on the surfaces of adjacent channel layers 112 and the substrate 100 are in contact with each other, that is, the first work function layer 1511 fills up the longitudinal space between adjacent channel layers 112, or the first work function layer 1511 fills up the longitudinal space between adjacent channel layers 112 and the substrate 100, that is, the first work function layer 1511 fills up the through groove, which is conducive to reducing the difficulty of forming the first work function layer 1511, and is also conducive to reducing the difficulty of forming the work function layer 151. In other embodiments, along the normal direction of the top surface of the substrate, the first work function layers located on the surfaces of adjacent channel layers are isolated, or the first work function layers located on the surfaces of adjacent channel layers and the substrate are isolated, that is, the first work function layer does not fill up the through groove, and the gate electrode layer fills the remaining space of the through groove.

[0050] It should be noted that the difference between the sum of the thickness of the first work function layer 1511 and the second work function layer 1512 of the first region i and the sum of the thickness of the first work function layer 1511 and the second work function layer 1512 of the second region ii should not be too small or too large. If the difference between the sum of the thickness of the first work function layer 1511 and the second work function layer 1512 of the first region i and the sum of the thickness of the first work function layer 1511 and the second work function layer 1512 of the second region ii is too small, it is easy to make the effect of improving the threshold voltage of the semiconductor device in the first region ii poor, thereby making the effect of improving the performance of the semiconductor structure unsatisfactory; if the difference between the sum of the thickness of the first work function layer 1511 and the second work function layer 1512 of the first region i and the sum of the thickness of the first work function layer 1511 and the second work function layer 1512 of the second region II is too large, it is easy to increase the difficulty of forming the work function layer 151. Therefore, in this embodiment, the difference between the sum of the thickness of the first work function layer 1511 and the second work function layer 1512 in the first region i and the sum of the thickness of the first work function layer 1511 and the second work function layer 1512 in the second region ii is 3 nm to 10 nm.

[0051] In this embodiment, the sum of the thicknesses of the first work function layers 1511 in the first region i is greater than the sum of the thicknesses of the first work function layers 1511 in the second region ii, which facilitates the sum of the thicknesses of the first work function layer and the second work function layer in the first region I to be greater than the sum of the thicknesses of the first work function layer and the second work function layer in the second region II, which is beneficial to reducing the difficulty of forming work function layers 151 with different thickness requirements, and the changes to the process are also relatively small, which is beneficial to combining with the existing process.

[0052] Specifically, the top of the first work function layer 1511 in the first region i is flush with the top of the first work function layer 1511 in the second region ii located in the same layer.

[0053] Typically, one or more sequentially stacked channel stacks are formed on a substrate 100, each channel stack including a sacrificial layer and a channel layer 112 located on the sacrificial layer. The steps include: alternatingly performing a first film forming process for forming a sacrificial material layer (not shown) and a second film forming process for forming a channel material layer (not shown) to form one or more sequentially stacked channel stacks; wherein the step method for forming the channel stack also includes: in a first region i, before any first film forming process, performing a back etching process on the currently exposed substrate 100 or the channel material layer to remove a portion of the thickness of the material.

[0054] The top of the first work function layer 1511 in the first region i is flush with the top of the first work function layer 1511 in the second region ii located in the same layer. That is to say, in the first film forming step carried out successively after the back etching treatment, the top of the sacrificial material layer in the first region i is flush with the top of the sacrificial material layer in the second region ii, that is, the top of the sacrificial material layer in the first region i is flush with the top of the sacrificial material layer in the second region ii located in the same layer. Accordingly, the second film forming treatment after the back etching treatment is not easily affected by the back etching treatment, so that the back etching treatment causes less change to the existing process flow, which is conducive to combination with the existing process flow.

[0055] In a specific embodiment, the thickness of the first work function layer 1511 between the substrate 100 and the channel layer 112 in the first region i is greater than the thickness of the first work function layer 1511 between the substrate 100 and the channel layer 112 in the second region ii.

[0056] Since the gate structure 150 generally has a weaker control capability over the substrate 100, and the first region i and the second region ii are used to form different types of MOS devices, the thickness of the first work function layer 1511 located between the substrate 100 and the channel layer 112 in the first region i is greater than the thickness of the first work function layer 1511 located between the substrate 100 and the channel layer 112 in the second region ii. That is, the thickness of the first work function layer 1511 covering the substrate 100 in the first region i is larger, and the thickness of the first work function layer 1511 covering the substrate 100 in the second region ii is smaller, which is beneficial for increasing the threshold voltage of the semiconductor device in the first region i while reducing the leakage current (Ioff) of the semiconductor device in the first region i, thereby reducing the static power consumption of the semiconductor device.

[0057] In this embodiment, the gate structure 150 is a metal gate structure. Therefore, the material of the work function layer 151 includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, tantalum carbide, titanium aluminide, tantalum carbide, aluminum and titanium carbide.

[0058] As an example, the material of the work function layer 151 is titanium nitride. Titanium nitride is relatively stable, which is beneficial to reducing the probability of diffusion of doped ions in the semiconductor structure when the device is working, and correspondingly reducing the probability of leakage, and is also beneficial to improving the adhesion between the work function layer 151 and the gate dielectric layer 160, and is also beneficial to improving the reliability of the semiconductor device and reducing the probability of breakdown.

[0059] In this embodiment, the gate structure 150 further includes a gate electrode layer 152 covering the work function layer 151. The gate electrode layer 152 is used as an external electrode for electrically connecting the gate structure 550 to an external circuit. The material of the gate electrode layer 152 is a conductive material, such as titanium aluminide, tungsten, aluminum, copper, silver, gold, platinum, nickel or titanium.

[0060] In this embodiment, the semiconductor structure further includes: a gate dielectric layer 160 located between the substrate 100 and the gate structure 150 , and between the channel layer 112 and the gate structure 150 .

[0061] The gate dielectric layer 160 is used to achieve electrical isolation between the gate structure 150 and the conductive channel. The material of the gate dielectric layer 160 includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3 and Al2O3.

[0062] In this embodiment, the gate dielectric layer 160 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3. In other embodiments, the gate dielectric layer may also include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer.

[0063] In this embodiment, the semiconductor structure further includes: a gate spacer (not shown) located on the sidewall of the gate structure 150. The gate spacer is used as an etching mask during the process of forming the source and drain doping layers, and is also used to protect the sidewall of the gate structure 150.

[0064] Specifically, the gate spacer may be a single-layer structure or a stacked structure, and the material of the gate spacer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

[0065] In this embodiment, the semiconductor structure further includes: an inner sidewall (not shown), which is located between the source-drain doped layer and the channel layer 112 along a direction parallel to the top surface of the substrate 100 and perpendicular to the extension direction of the gate structure 150. The inner sidewall is used to achieve isolation between the source-drain doped layer and the gate structure 150, and is also used to increase the distance between the source-drain doped layer and the gate structure 150, which is beneficial to reduce the parasitic capacitance between the source-drain doped layer and the gate structure 150.

[0066] More specifically, the material of the inner sidewall is an insulating material to achieve isolation between the source-drain doping layer and the gate structure 150. As an example, the material of the inner sidewall includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material. Among them, the low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9, and the ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6.

[0067] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 3 to 9 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0068] refer to Figure 3 , providing a substrate 500, the substrate 500 includes a first region I and a second region II.

[0069] The substrate 500 provides a process platform for subsequent process steps. In this embodiment, the substrate 500 is used to form a full-surround gate transistor.

[0070] In this embodiment, the base 500 includes a substrate (not shown), which is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator.

[0071] In this embodiment, the first region I and the second region II are used to form different types of MOS devices. Specifically, the first region I is used to form an NMOS device, and the second region II is used to form a PMOS device.

[0072] Continue to refer Figure 3 , and combined with reference Figures 4 to 6 , one or more sequentially stacked channel stacks 510 are formed on a substrate 500 , and each channel stack 510 includes a sacrificial layer 511 and a channel layer 512 located on the sacrificial layer 511 .

[0073] The channel stack 510 provides a process basis for subsequently forming a channel layer 512 with a suspended spacing arrangement.

[0074] The channel layer 512 is used to form a conductive channel of the MOS transistor, and the sacrificial layer 511 is used to support the channel layer 512, thereby providing a process basis for the subsequent realization of the spaced-apart suspended arrangement of the channel layer 512. The sacrificial layer 511 is also used to occupy a spatial position for the subsequent formation of a device gate structure.

[0075] In this embodiment, the number of the channel stacks 510 is multiple as an example for description, and the stacking direction of the multiple channel stacks 510 on the substrate 500 is perpendicular to the top surface of the substrate 500. Specifically, the number of the channel stacks 510 is three. In other embodiments, the number of the channel stacks can also be two, four, etc. In other embodiments, based on actual process requirements, the number of the channel stacks can also be only one.

[0076] In this embodiment, the material of the channel layer 512 includes one or more of silicon, silicon germanium, germanium and III-V semiconductor materials.

[0077] In a specific embodiment, the material of the channel layer 512 is silicon, and the material of the sacrificial layer 511 is silicon germanium. In the subsequent process of removing the sacrificial layer 511, the etching selectivity of silicon germanium and silicon is relatively high, so by setting the material of the sacrificial layer 511 to silicon germanium and the material of the channel layer 512 to silicon, it is beneficial to reduce the impact of the sacrificial layer 511 removal process on the channel layer 512, so that the quality of the channel layer 512 is easy to be better, which is beneficial to improve the performance of the semiconductor device.

[0078] In this embodiment, the material of the substrate 500 is silicon, and the material of the channel layer 512 is silicon, that is, the material of the substrate 500 is the same as the material of the channel layer 512; since the etching selectivity of silicon germanium and silicon is relatively high, in the subsequent process of removing the sacrificial layer 511, it is also beneficial to reduce the impact of the sacrificial layer 511 removal process on the substrate 500.

[0079] In other embodiments, the material of the channel layer may be different from that of the substrate. The material of the channel layer is different from that of the substrate, which is conducive to performing a back-etching process on the currently exposed substrate in the first region after the sacrificial layer is subsequently removed through the opening, so that the height of the through groove between the substrate and the channel layer in the first region is greater than the height of the through groove between the substrate and the channel layer in the second region ii, thereby making it easy to make the thickness of the first work function layer between the substrate and the channel layer in the first region greater than the thickness of the first work function layer between the substrate and the channel layer in the second region; and in the process of back-etching, the probability of the channel layer being damaged is reduced.

[0080] As an example, the material of the substrate is silicon, and the material of the channel layer is a III-V semiconductor material.

[0081] In this embodiment, in the step of forming the channel stack 510 , along the normal direction of the top surface of the substrate 500 , the sum of the thicknesses of the sacrificial layer 511 in the first region I is greater than the sum of the thicknesses of the sacrificial layer 511 in the second region II.

[0082] The sacrificial layer 511 is subsequently removed to form a through groove at the position where the sacrificial layer 511 is located, and the through groove is used to provide a spatial position for forming a work function layer. The sum of the thicknesses of the sacrificial layer 511 in the first region I is greater than the sum of the thicknesses of the sacrificial layer 511 in the second region II, which is beneficial for the sum of the heights of the through grooves in the first region I formed subsequently to be greater than the sum of the heights of the through grooves in the second region II, thereby facilitating the sum of the thicknesses of the first work function layer in the first region I formed subsequently to be greater than the sum of the thicknesses of the first work function layer in the second region II.

[0083] It should be noted that the steps of forming one or more sequentially stacked channel stacks 510 on the substrate 500, each channel stack 510 including a sacrificial layer 511 and a channel layer 512 located on the sacrificial layer 511, include: Figures 3 to 5 As shown, the first film forming process (such as Figure 4 ), and a second film forming process for forming a channel material layer 512′ (as shown Figure 5 As shown), to form one or more channel stacks 510 stacked in sequence; wherein, the step of forming the channel stack 510 also includes: in the first region I, before any first film forming process, back-etching the currently exposed substrate 500 or the channel layer material layer 512′ to remove a portion of the thickness of the material.

[0084] Before any first film forming treatment, the currently exposed first region I substrate 500 or the first region I channel layer material layer 512′ is etched back to remove part of the thickness of the material so that the recess in the first region I can be used to accommodate more sacrificial material layers, which makes it easy for the thickness of the sacrificial material layer 511′ formed in the first region I to be larger in the first film forming step performed successively after the back etching treatment, thereby making it easy to make the sum of the thickness of the sacrificial layer 511 of the first region I greater than the sum of the thickness of the sacrificial layer 511 of the second region II, and correspondingly making it easy to make the sum of the height of the through groove 536 of the first region I greater than the sum of the height of the through groove 536 of the second region II.

[0085] like Figure 3 As shown, in a specific embodiment, in the first region I, before the first film forming process, the currently exposed substrate 500 is etched back to remove a portion of the thickness of the substrate 500 material; Figure 4 As shown, in the first film forming step performed successively after the back etching process, along the normal direction of the top surface of the substrate 500, the thickness of the sacrificial material layer 511′ covering the first region I substrate 500 is greater than the thickness of the sacrificial material layer 511′ covering the second region II substrate 500.

[0086] Before the first first film-forming treatment, part of the thickness of the substrate 500 material in the first region I is removed. That is, before the first first film-forming treatment, the top of the substrate 500 in the first region I is lower than the top of the substrate 500 in the second region II, so that in the first first film-forming treatment step, the thickness of the sacrificial material layer 511′ covering the substrate 500 in the first region I is greater than the thickness of the sacrificial material layer 511′ covering the substrate 500 in the second region II. Correspondingly, after the sacrificial material layer 511′ and the channel material layer 512′ are patterned, the thickness of the sacrificial layer 511 covering the substrate 500 in the first region I is greater than the thickness of the sacrificial layer 511 covering the substrate 500 in the second region II, so that the height of the through groove between the substrate 500 and the channel layer 512 in the first region I is greater than the height of the through groove between the substrate 500 and the channel layer 512 in the second region II, and further, the sum of the through groove heights in the first region I is greater than the sum of the through groove heights in the second region II.

[0087] As an example, before the currently exposed substrate 500 is subjected to the back etching process, the forming method further includes: forming a patterned hard mask structure 505 on the substrate 500 in the second region II; in the step of performing the back etching process on the currently exposed substrate 500, performing the back etching process (such as Figure 3 shown).

[0088] Before etching back the currently exposed substrate 500, a patterned hard mask structure 505 is formed on the substrate 500 in the second region II. During the etching back process, the hard mask structure 505 protects the substrate 500 in the second region II and reduces the probability of damage to the substrate 500 in the second region II.

[0089] In this embodiment, in the step of the first film forming process performed successively after the etch-back process, the top of the sacrificial material layer 511 ′ in the first region I is flush with the top of the sacrificial material layer 511 ′ in the second region II.

[0090] In the step of the first film forming treatment carried out successively after the back etching treatment, the top of the sacrificial material layer 511′ in the first region I is flush with the top of the sacrificial material layer 511′ in the second region II, that is, the top of the sacrificial material layer 511′ in the first region I is flush with the top of the sacrificial material layer 511′ in the second region II located on the same layer. Accordingly, the second film forming treatment after the back etching treatment is not easily affected by the back etching treatment, so that the back etching treatment causes less change to the existing process flow, which is conducive to combination with the existing process flow.

[0091] Specifically, the first film forming step performed successively after the back etching treatment includes forming an initial sacrificial material layer (not shown) on the exposed substrate 500 or the channel layer 512; planarizing the initial sacrificial material layer so that the top of the initial sacrificial material layer in the first region I is flush with the top of the initial sacrificial material layer in the second region II, and the remaining initial sacrificial material layer serves as the sacrificial material layer 511′.

[0092] Firstly forming an initial sacrificial material layer on the exposed substrate 500 or the channel layer 512 and then planarizing the initial sacrificial material layer can help reduce the difficulty of making the top of the sacrificial material layer 511' in the first region I flush with the top of the sacrificial material layer 511' in the second region II.

[0093] In a specific embodiment, an initial sacrificial material layer is formed on the exposed substrate 500; the initial sacrificial material layer covering the substrate 500 is planarized, and the remaining initial sacrificial material layer covering the substrate 500 serves as a sacrificial material layer.

[0094] Specifically, in the step of patterning the sacrificial material layer 511′ and the channel material layer 512′, a partial thickness of the substrate 500 may also be patterned to form a groove (not shown) in the substrate 500. The groove is used to define an isolation region between adjacent devices so as to provide a spatial position for forming an isolation layer in the groove. The unpatterned substrate 500 serves as a substrate.

[0095] In a specific embodiment, along the normal direction of the top surface of the substrate 500 , the thickness of the sacrificial layer 511 covering the first region I of the substrate 500 is greater than the thickness of the sacrificial layer 511 covering the second region II of the substrate 500 .

[0096] In this embodiment, the formation method further includes: forming an isolation layer 520 in the trench. The isolation layer 520 is used to achieve isolation between adjacent devices. In this embodiment, the isolation layer 520 is a shallow trench isolation structure. Specifically, the material of the isolation layer 520 may include one or more of silicon oxide, silicon oxynitride and silicon nitride.

[0097] Continue to refer Figure 6 , a dummy gate structure 530 is formed across the channel stack 510 , and the dummy gate structure 530 covers a portion of the top and a portion of the sidewall of the channel stack 510 .

[0098] The dummy gate structure 530 is used to pre-occupy a space position for the subsequent formation of a gate structure. In this embodiment, the dummy gate structure 530 is formed on the isolation layer and crosses the channel stack 510. Specifically, the dummy gate structure 530 includes a dummy gate oxide layer 531 and a dummy gate layer 532 located on the dummy gate oxide layer 531.

[0099] More specifically, the material of the dummy gate oxide layer 531 includes one or more of silicon oxide and silicon oxynitride. The material of the dummy gate layer 532 includes polysilicon or amorphous silicon.

[0100] In a specific embodiment, a dummy gate mask structure 540 is further formed on the top of the dummy gate layer 532 . The dummy gate mask structure 540 is used as an etching mask for patterning the dummy gate material layer to form the dummy gate structure 530 .

[0101] In this embodiment, after forming the dummy gate structure 530, the method for forming the semiconductor structure further includes: forming a gate sidewall (not shown) on the sidewall of the dummy gate structure 530. The gate sidewall is used together with the dummy gate layer 532 and the dummy gate mask structure 540 as an etching mask for the subsequent formation of source and drain grooves to define the formation position of the source and drain doping layer, and the gate sidewall is also used to protect the dummy gate layer 532 and the sidewall of the gate structure formed subsequently. Specifically, the gate sidewall can be a single-layer structure or a stacked structure, and the material of the gate sidewall includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride and boron carbonitride.

[0102] In this embodiment, after forming the dummy gate structure 530 and before removing the dummy gate structure 530, the formation method also includes: forming source and drain grooves (not shown) in the channel stack 510 on both sides of the dummy gate structure 530; and forming source and drain doping layers (not shown) in the source and drain grooves.

[0103] The source-drain grooves are used to provide a spatial position for forming a source-drain doped layer. When the device is working, the source-drain doped layer is used as a source or a drain to provide a carrier source.

[0104] Specifically, after forming the source-drain grooves and before forming the source-drain doped layers, the forming method further includes: in a direction parallel to the top surface of the substrate 500 and perpendicular to the extension direction of the dummy gate structure 530, laterally etching the sacrificial layer 511 with a thickness of a portion of the exposed sidewall of the source-drain groove to form an inner groove (not shown), wherein the inner groove is surrounded by the adjacent channel layer 512 and the remaining sacrificial layer 511, or the inner groove is surrounded by the substrate 500, the channel layer 512 adjacent to the substrate 500, and the remaining sacrificial layer 511; forming an inner sidewall (not shown) in the inner groove

[0105] The inner trench provides a space for forming an inner sidewall, which is used to isolate the source-drain doped layer from the gate structure to be formed later, and to increase the distance between the source-drain doped layer and the gate structure, which is beneficial to reduce the parasitic capacitance between the source-drain doped layer and the gate structure.

[0106] More specifically, the material of the inner sidewall is an insulating material to achieve isolation between the source and drain doping layers and the gate structure. As an example, the material of the inner sidewall includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material.

[0107] It should be noted that the process of forming the source-drain doping layer includes an epitaxial growth process.

[0108] In this embodiment, after forming the source and drain doped layers and before forming the opening, the formation method also includes: forming an interlayer dielectric layer (not shown) on the substrate 500 on the side of the dummy gate structure 530, the interlayer dielectric layer covering the source and drain doped layers and exposing the top of the dummy gate structure 530.

[0109] The interlayer dielectric layer covers the source-drain doped layer and is used to protect the source-drain doped layer in the subsequent process of forming the opening. The interlayer dielectric layer is also used to achieve electrical isolation between adjacent devices.

[0110] Specifically, the interlayer dielectric layer is formed on the isolation layer 520 and covers the source and drain doping layers.

[0111] It should be noted that the material of the interlayer dielectric layer includes one or more of silicon oxide and silicon nitride. As an example, the material of the interlayer dielectric layer is silicon nitride.

[0112] refer to Figure 7 , the dummy gate structure 530 is removed, and an opening 535 is formed at the location of the dummy gate structure 530 , wherein the opening 535 exposes the top and sidewalls of the channel stack 510 .

[0113] The opening 535 is used to reserve space for the subsequent formation of a gate structure. Moreover, after removing the dummy gate structure 530 , the opening exposes the top and sidewalls of the channel stack 510 , so that the sacrificial layer 511 can be removed through the channel stack 510 exposed by the opening 535 .

[0114] Specifically, the process of removing the dummy gate structure 530 includes one or both of a dry etching process and a wet etching process.

[0115] Continue to refer Figure 7 The sacrificial layer 511 is removed through the opening 535 to form a through groove 536 between the substrate 500 and the channel layer 512 , or between adjacent channel layers 512 .

[0116] The through groove 536 is also used to reserve space for the subsequent formation of a gate structure.

[0117] After removing the sacrificial layer 511, one or more channel layers 512 are suspended in space, so that the subsequent work function layer of the gate structure can surround the channel layer 512. The one or more channel layers 512 that are suspended in space in sequence are used to form a channel structure 515.

[0118] Specifically, the process of removing the sacrificial layer 511 includes an isotropic etching process. As an example, the isotropic etching process includes an isotropic wet etching process. The isotropic etching process has the characteristic of isotropic etching, which is conducive to quickly removing the sacrificial layer 511. In addition, the isotropic wet etching process can easily achieve a high etching selectivity between the etched object (that is, the sacrificial layer 511) and other film layers (such as the channel layer 512), thereby reducing damage to other film layers.

[0119] As an example, the etching selectivity ratio between the sacrificial layer 511 and the channel layer 512 is greater than 10.

[0120] In this embodiment, in the step of forming the through grooves 536 , along the normal direction of the top surface of the substrate 500 , the sum of the heights of the through grooves 536 in the first region I is greater than the sum of the heights of the through grooves 536 in the second region II.

[0121] Subsequently, a work function layer is formed in the through groove 536 . Therefore, by adjusting the height of the through groove 536 , after the work function layer is formed in the through groove 536 , the requirements of the first region I and the second region II on the total thickness of the work function layer can be met, and the process is simpler.

[0122] Specifically, the sum of the heights of the through grooves 536 in the first region I is greater than the sum of the heights of the through grooves 536 in the second region II, which is beneficial for making the sum of the thicknesses of the first work function layers of the first region I formed subsequently greater than the sum of the thicknesses of the first work function layers of the second region II, thereby making the sum of the thicknesses of the first work function layer and the second work function layer of the first region I greater than the sum of the thicknesses of the first work function layer and the second work function layer of the second region II, which is beneficial for reducing the difficulty of forming work function layers with different thickness requirements, and the changes to the process are also relatively small, which is conducive to combination with existing process.

[0123] In a specific embodiment, in the step of forming the through groove 536, along the normal direction of the top surface of the substrate 500, the height of the through groove 536 between the substrate 500 and the channel layer 512 in the first region I is greater than the height of the through groove 536 between the substrate 500 and the channel layer 512 in the second region II.

[0124] Because before the first film forming process, the currently exposed substrate 100 in the first region I is etched back to remove a portion of the thickness of the substrate 100 material, that is, the top of the substrate 100 in the first region I is lower than the top of the substrate in the second region II, so that in the step of forming the sacrificial material layer 511′, the thickness of the sacrificial material layer 511′ covering the substrate 500 in the first region I is greater than the thickness of the sacrificial material layer 511′ covering the substrate 500 in the second region II. Accordingly, in the step of forming the sacrificial layer, the thickness of the sacrificial layer 511′ covering the substrate 500 in the first region I is greater than the thickness of the sacrificial material layer 511′ covering the substrate 500 in the second region II. , which is greater than the thickness of the sacrificial layer 511 covering the substrate 500 in the second region II. Therefore, in the step of removing the sacrificial layer 511 and forming the through groove 536, the height of the through groove 536 between the substrate 500 and the channel layer 512 in the first region I is greater than the height of the through groove 536 between the substrate 500 and the channel layer 512 in the second region II, thereby facilitating the thickness of the first work function layer subsequently formed between the substrate 500 and the channel layer 512 in the first region I to be greater than the thickness of the first work function layer formed between the substrate 500 and the channel layer 512 in the second region II.

[0125] In other embodiments, the step of forming the through groove includes: removing the sacrificial layer through the opening; after removing the sacrificial layer, in the first area, etching back the currently exposed substrate to remove a portion of the thickness of the substrate material to form a through groove located between the substrate and the channel layer, or between adjacent channel layers.

[0126] In the step of forming the through groove, in the first region, the currently exposed substrate is etched back to remove part of the thickness of the substrate material, which makes little change to the existing process flow; moreover, it is also easy to make the height of the through groove between the substrate and the channel layer in the first region greater than the height of the through groove between the substrate and the channel layer in the second region, thereby making it easier to make the height of the first work function layer between the substrate and the channel layer in the first region greater than the height of the first work function layer between the substrate and the channel layer in the second region, and correspondingly, it is also easy to make the sum of the thickness of the first work function layer and the second work function layer in the first region greater than the sum of the thickness of the first work function layer and the second work function layer in the second region.

[0127] refer to Figure 8 After forming the opening 535 and the through-groove 536 , and before forming the gate structure, the forming method further includes: forming a gate dielectric layer 560 on inner walls of the opening 535 and the through-groove 536 .

[0128] The gate dielectric layer 560 is used to achieve electrical isolation between the subsequently formed gate structure and the conductive channel. The material of the gate dielectric layer 560 includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3 and Al2O3.

[0129] In this embodiment, the gate dielectric layer 560 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3. In other embodiments, the gate dielectric layer may also include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer.

[0130] refer to Fig. 9 , a gate structure 550 is formed in the opening 535 and the through groove 536, the gate structure 550 includes a work function layer 551 surrounding the channel layer 512, the work function layer 551 located in the through groove 536 serves as a first work function layer 5511, and the work function layer 551 located on the top of the topmost channel layer 512 serves as a second work function layer 5512; wherein the sum of the thicknesses of the first work function layer 5511 and the second work function layer 5512 in the first region I is greater than the sum of the thicknesses of the first work function layer 5511 and the second work function layer 5512 in the second region II.

[0131] The thickness of the first work function layer 5511 and the second work function layer 5512 both refer to the thickness of the first work function layer 5511 and the second work function layer 5512 along the normal direction of the top surface of the substrate 500 .

[0132] The gate structure 550 is a device gate structure. When the device is working, the gate structure 550 is used to control the opening and closing of the conductive channel.

[0133] The work function layer 551 is used to adjust the threshold voltage of the field effect transistor.

[0134] The sum of the thicknesses of the first work function layer 5511 and the second work function layer 5512 in the first region I is greater than the sum of the thicknesses of the first work function layer 5511 and the second work function layer 5512 in the second region II, that is, the sum of the thicknesses of the work function layer 551 at the bottom and top of the channel layer 512 in the first region I is greater than the sum of the thicknesses of the work function layer 551 at the bottom and top of the channel layer 512 in the second region II. This is beneficial for improving the threshold voltage of the semiconductor device in the first region II when the threshold voltage of the semiconductor device in the second region II meets the requirements, so that the semiconductor devices in the first region I and the semiconductor devices in the second region II can meet different functional requirements, thereby improving the performance of the semiconductor structure.

[0135] In this embodiment, in the step of forming the gate structure 550 , the first work function layer 5511 completely fills the through groove 536 .

[0136] The first work function layer 5511 fills the through groove 536, that is, along the normal direction of the top surface of the substrate 100, the first work function layer 5511 located on the surface of the adjacent channel layer 512 is in contact with each other, or the first work function layer 5511 located on the surface of the adjacent channel layer 512 and the substrate 500 is in contact with each other, which is conducive to reducing the difficulty of forming the first work function layer 5511 and also conducive to reducing the difficulty of forming the work function layer 551. In other embodiments, the first work function layer does not fill the through groove, and the gate electrode layer fills the remaining space of the through groove.

[0137] It should be noted that the difference between the sum of the thickness of the first work function layer 5511 and the second work function layer 5512 of the first region I and the sum of the thickness of the first work function layer 5511 and the second work function layer 5512 of the second region II should not be too small or too large. If the difference between the sum of the thickness of the first work function layer 5511 and the second work function layer 5512 of the first region I and the sum of the thickness of the first work function layer 5511 and the second work function layer 5512 of the second region II is too small, it is easy to make the effect of improving the threshold voltage of the semiconductor device in the first region II poor, thereby making the effect of improving the performance of the semiconductor structure unsatisfactory; if the difference between the sum of the thickness of the first work function layer 5511 and the second work function layer 5512 of the first region I and the sum of the thickness of the first work function layer 5511 and the second work function layer 5512 of the second region II is too large, it is easy to increase the difficulty of forming the work function layer 551. Therefore, in this embodiment, the difference between the sum of the thickness of the first work function layer 5511 and the second work function layer 5512 along the first region I and the sum of the thickness of the first work function layer 5511 and the second work function layer 5512 in the second region II is 3 nanometers to 10 nanometers.

[0138] In this embodiment, in the step of forming the through grooves 536, along the normal direction of the top surface of the substrate 500, the sum of the heights of the through grooves 536 in the first region I is greater than the sum of the heights of the through grooves 536 in the second region II. Accordingly, in the step of forming the gate structure 550, along the normal direction of the top surface of the substrate 500, the sum of the thicknesses of the first work function layers 5511 in the first region I is greater than the sum of the thicknesses of the first work function layers 5511 in the second region II.

[0139] In a specific embodiment, accordingly, in the step of forming the gate structure 550, along the normal direction of the top surface of the substrate 500, the thickness of the first work function layer 5511 located between the substrate 500 and the channel layer 512 in the first region I is greater than the thickness of the first work function layer 5511 located between the substrate 500 and the channel layer 512 in the second region II.

[0140] Since the gate structure 550 generally has a weaker control capability over the substrate 500, and since the first region I and the second region II form different types of MOS devices, the thickness of the first work function layer 5511 between the substrate 500 and the channel layer 512 in the first region I is greater than the thickness of the first work function layer 5511 between the substrate 500 and the channel layer 512 in the second region II. That is, the thickness of the first work function layer 5511 covering the substrate 500 in the first region I is greater, and the thickness of the first work function layer 5511 covering the substrate 500 in the second region II is less, which is beneficial to reducing the leakage current (I ) of the semiconductor device in the first region I while increasing the threshold voltage of the semiconductor device in the first region I. off ), thereby reducing the static power consumption of semiconductor devices.

[0141] In this embodiment, the gate structure 550 is a metal gate structure. Therefore, the material of the work function layer 551 includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, tantalum carbide, titanium aluminide, tantalum carbide, aluminum and titanium carbide.

[0142] As an example, the material of the work function layer 551 includes titanium nitride. Titanium nitride is relatively stable, which is beneficial to reducing the probability of diffusion of doped ions in the semiconductor structure when the device is working, and correspondingly reducing the probability of leakage, and is also beneficial to improving the adhesion between the work function layer 551 and the gate dielectric layer 560, and is also beneficial to improving the reliability of the semiconductor device and reducing the probability of breakdown.

[0143] In this embodiment, in the step of forming the gate structure 550, the gate structure 550 further includes a gate electrode layer 552 covering the work function layer 551. The gate electrode layer 552 is used as an external electrode for electrically connecting the gate structure 550 to an external circuit. The material of the gate electrode layer 552 is a conductive material, such as titanium aluminide, tungsten, aluminum, copper, silver, gold, platinum, nickel or titanium.

[0144] It should be noted that the semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0145] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: a substrate comprising a first region and a second region; A channel structure is suspended on the substrate, wherein the channel structure comprises one or more channel layers sequentially arranged from bottom to top; a gate structure spanning the channel structure and surrounding the channel layer, the gate structure comprising a work function layer surrounding the channel layer, a work function layer located between the channel layer and the substrate or between adjacent channel layers as a first work function layer, and a work function layer located on top of the topmost channel layer as a second work function layer; The sum of the thicknesses of the first work function layer and the second work function layer in the first region is greater than the sum of the thicknesses of the first work function layer and the second work function layer in the second region.

2. The semiconductor structure according to claim 1, wherein: The sum of thicknesses of the first work function layers in the first region is greater than the sum of thicknesses of the first work function layers in the second region.

3. The semiconductor structure according to claim 2, wherein: The top of the substrate of the first region is lower than the top of the substrate of the second region, or the top of any channel layer of the first region is lower than the top of the channel layer of the second region located in the same layer.

4. The semiconductor structure according to claim 3, characterized in that The top of the first work function layer in the first region is flush with the top of the first work function layer in the second region located in the same layer.

5. The semiconductor structure according to claim 3, wherein: The thickness of the first work function layer located between the substrate and the channel layer in the first region is greater than the thickness of the first work function layer located between the substrate and the channel layer in the second region.

6. The semiconductor structure according to claim 1, wherein: The gate structure further includes a gate electrode layer covering the work function layer.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that: Along the normal direction of the top surface of the substrate, the first work function layers located on the surfaces of adjacent channel layers are in contact with each other, or the first work function layers located on the surfaces of adjacent channel layers and the substrate are in contact with each other.

8. The semiconductor structure according to claim 1, wherein: The material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, tantalum carbide, titanium aluminide, tantalum carbide, aluminum and titanium carbide.

9. The semiconductor structure according to claim 1, wherein: The difference between the sum of the thickness of the first work function layer and the second work function layer in the first region and the sum of the thickness of the first work function layer and the second work function layer in the second region is 3 nanometers to 10 nanometers.

10. The semiconductor structure according to claim 1, wherein: The material of the channel layer includes one or more of silicon, silicon germanium, germanium and III-V semiconductor materials.

11. The semiconductor structure according to claim 1 or 10, characterized in that: A material of the channel layer is different from a material of the substrate.

12. A method for forming a semiconductor structure, characterized in that: include: providing a substrate comprising a first region and a second region; Forming one or more sequentially stacked channel stacks on the substrate, each of the channel stacks comprising a sacrificial layer and a channel layer located on the sacrificial layer; forming a dummy gate structure across the channel stack, wherein the dummy gate structure covers a portion of the top and a portion of the sidewall of the channel stack; removing the dummy gate structure and forming an opening at the location of the dummy gate structure, wherein the opening exposes the top and sidewalls of the channel stack; removing the sacrificial layer through the opening to form a through groove between the substrate and the channel layer, or between adjacent channel layers; forming a gate structure in the opening and the through groove, the gate structure comprising a work function layer surrounding the channel layer, the work function layer in the through groove being a first work function layer, and the work function layer on top of the topmost channel layer being a second work function layer; The sum of the thicknesses of the first work function layer and the second work function layer in the first region is greater than the sum of the thicknesses of the first work function layer and the second work function layer in the second region.

13. The method for forming a semiconductor structure according to claim 12, wherein: In the step of forming the through grooves, along the normal direction of the top surface of the substrate, the sum of the through groove heights in the first region is greater than the sum of the through groove heights in the second region; In the step of forming the gate structure, along a normal direction of the top surface of the substrate, the sum of the thicknesses of the first work function layers in the first region is greater than the sum of the thicknesses of the first work function layers in the second region.

14. The method for forming a semiconductor structure according to claim 13, wherein: In the step of forming the channel stack, along a normal direction of the top surface of the substrate, the sum of the thickness of the sacrificial layers in the first region is greater than the sum of the thickness of the sacrificial layers in the second region.

15. The method for forming a semiconductor structure according to claim 14, wherein: The step of forming one or more sequentially stacked channel stacks on the substrate, each of the channel stacks comprising a sacrificial layer and a channel layer located on the sacrificial layer, comprises: alternately performing a first film forming process for forming a sacrificial material layer and a second film forming process for forming a channel material layer to form one or more sequentially stacked channel stacks; The step of forming the channel stack further includes: in the first region, before any first film forming process, performing a back etching process on the currently exposed substrate or channel material layer to remove a portion of the thickness of the material.

16. The method for forming a semiconductor structure according to claim 15, wherein: In the step of the first film forming process performed successively after the etch-back process, the top of the sacrificial material layer in the first region is flush with the top of the sacrificial material layer in the second region.

17. The method for forming a semiconductor structure according to claim 16, wherein: The first film forming process performed successively after the etch-back process includes forming an initial sacrificial material layer on the exposed substrate or channel layer; The initial sacrificial material layer is planarized so that the top of the initial sacrificial material layer in the first region is flush with the top of the initial sacrificial material layer in the second region, and the remaining initial sacrificial material layer serves as a sacrificial material layer.

18. The method for forming a semiconductor structure according to claim 15, wherein: In the first region, before the first film forming process, the currently exposed substrate is etched back to remove a portion of the thickness of the substrate material; In the first film forming step performed after the etch-back process, along the normal direction of the top surface of the substrate, the thickness of the sacrificial material layer covering the first area substrate is greater than the thickness of the sacrificial material layer covering the second area substrate.

19. The method for forming a semiconductor structure according to claim 12, wherein: The steps of forming the through groove include: removing the sacrificial layer through the opening; After removing the sacrificial layer, the currently exposed substrate is etched back in the first region to remove a portion of the substrate material to form a through groove between the substrate and the channel layer, or between adjacent channel layers.

20. The method for forming a semiconductor structure according to any one of claims 12 to 19, wherein: In the step of forming the gate structure, the first work function layer completely fills the through groove.

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