Substrate and manufacturing method thereof, semiconductor device, circuit module and electronic equipment

Abstract

The invention provides a substrate and a manufacturing method thereof, a semiconductor device, a circuit module and electronic equipment. Wherein the substrate comprises a first substrate layer, a second substrate layer and a first doped region, the second substrate layer and the first doped region are stacked on the first substrate layer, a hollow region is formed on the second substrate layer, the first doped region is arranged in the hollow region, and the thickness of the first doped region is the same as that of the second substrate layer. The manufacturing precision and the doping depth of the doped region can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a substrate and a manufacturing method thereof, a semiconductor device, a circuit module and an electronic device. Background Art

[0002] Substrates with different doping types and doping concentrations have different thermal expansion coefficients. For semiconductor devices, the difference in thermal expansion coefficients of different doped substrates leads to differences in the performance of semiconductor devices. Therefore, in order to improve the performance of semiconductor devices, a doping region can usually be set on the substrate to achieve this.

[0003] In the related art, the doping region is usually made by diffusion or ion implantation, but these two doping methods result in low manufacturing precision and low doping depth of the doping region. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides a substrate and a manufacturing method thereof, a semiconductor device, a circuit module and an electronic device, which can improve the manufacturing accuracy and doping depth of the doped region.

[0005] In a first aspect of the present application, a substrate is provided, comprising: a first substrate layer, and a second substrate layer and a first doped region stacked on the first substrate layer. A hollow region is formed on the second substrate layer, the first doped region is arranged in the hollow region, and the thickness of the first doped region is the same as the thickness of the second substrate layer.

[0006] Since the doping region is made by diffusion or ion implantation in the related art, the depth of the doping region is shallow and is much smaller than the thickness of the substrate. In the present application, the thickness of the first doping region is the same as the thickness of the second substrate layer. When the thickness of the second substrate layer is greater than 5 μm, the depth of the first doping region is also greater than 5 μm. Therefore, the doping depth of the present application is deeper.

[0007] Moreover, in the present application, a hollow region is formed on the second substrate layer, and the first doped region is arranged in the hollow region. Therefore, when making the first doped region, a blind hole that can accommodate the first doped region can be formed on the first surface of the second substrate layer by etching, and then the first doped region is formed in the blind hole by growth or deposition; the second surface of the second substrate layer opposite to the first surface is ground to expose the first doped region, thereby completing the production of the first doped region. Since the first doped region in the present application can be formed by etching first and then growing or depositing, the dimensional accuracy of the first doped region is higher and more uniform, that is, the production accuracy of the first doped region is higher.

[0008] The second substrate layer may be a doped substrate. Furthermore, the first doping region and the second substrate layer may have different doping types and / or doping concentrations.

[0009] In some embodiments, the number of the first doping region may be one. The substrate may be applied to a MEMS device, and when an oscillating body of the MEMS device is manufactured on the substrate, oscillating bodies with different doping types and / or doping concentrations may be manufactured based on the first doping region and the second substrate layer, respectively, thereby manufacturing oscillating bodies with different temperature characteristics.

[0010] In other embodiments, the number of first doping regions may be multiple, the doping types of the multiple first doping regions are the same, and the doping concentrations of the multiple first doping regions are also the same. The multiple first doping regions may be arranged along a first direction and spaced apart. The first direction is perpendicular to the thickness direction of the substrate. When the number and doping concentration of the first doping regions are different, the temperature expansion coefficient of the substrate is different. Therefore, the number and doping concentration of the first doping regions can be determined according to the requirements of the temperature expansion coefficient of the substrate, thereby making it possible to produce substrates with multiple different temperature expansion coefficients. In addition, the thicknesses of the multiple first doping regions are also the same, so that when making the substrate, multiple first doping regions can be made in the same process. Therefore, the present application can also simplify the manufacturing process of the substrate.

[0011] On this basis, the second substrate layer includes a plurality of sub-substrate layers that are spaced apart and arranged along the first direction, and a hollow area is formed between every two adjacent sub-substrate layers. A first doping area is provided in each hollow area. The sub-substrate layer may also be a doped substrate, and the doping type of the sub-substrate layer may be different from the doping type of the first doping area. For example, the sub-substrate layer is a P-type substrate, and the first doping area is an N-type doping area. Or, the sub-substrate layer is an N-type substrate, and the first doping area is a P-type doping area. In this way, the substrate may form an NPN structural layer or a PNP structural layer on the first substrate layer. The substrate of the present application may be applied to a gas sensor. In the process of manufacturing a gas sensor, the substrate of the present application may be manufactured first, and then a passivation layer, a metal layer, and a sensing layer may be manufactured on the substrate in sequence. Since the substrate includes a structural layer, the structural layer may be manufactured in the process of manufacturing the substrate, so that there is no need to manufacture the structural layer in the subsequent processing technology, and there is no need to perform doping in the subsequent processing technology, thereby reducing the subsequent process flow and reducing the wafer production cost.

[0012] In some embodiments, the substrate further includes a second doping region, and the second doping region and the first doping region are disposed on the same side of the first substrate layer. In one possible implementation, the doping type of the second doping region is the same as the doping type of the first doping region, and the doping concentration of the second doping region is different from the doping concentration of the first doping region. In this case, the region on the substrate where the first doping region is disposed has a different temperature expansion coefficient from the region where the second doping region is disposed, and the frequency stability under temperature drift is also different, and therefore, the substrate can be applied to a dual sensor.

[0013] In another possible implementation, the doping concentration of the second doping region is the same as the doping concentration of the first doping region, and the doping type of the second doping region is different from the doping type of the first doping region. In this way, the first doping region and the second doping region can form an NPN structure layer, or form a PNP structure layer.

[0014] In another possible implementation, the doping concentration of the second doping region is different from the doping concentration of the first doping region, and the doping type of the second doping region is different from the doping type of the first doping region. Similarly, the first doping region and the second doping region may also form an NPN structure layer, or a PNP structure layer.

[0015] Regarding the location of the second doping region, in a possible implementation, the second doping region is located in the hollow region, and the second doping region has the same thickness as the second substrate layer. In this way, when manufacturing the second doping region, after forming a blind hole on the first surface of the second substrate layer, the first doping region can be formed in the blind hole by growth or deposition, and the second doping region can also be formed in the blind hole by growth or deposition. When the second surface of the second substrate layer is ground to expose the first doping region, the second doping region can also be exposed. Therefore, the manufacturing process of the second doping region can be simplified.

[0016] Moreover, in this case, the second substrate layer may include a plurality of spaced sub-substrate layers, and a hollow region is formed between each two adjacent sub-substrate layers, and a first doping region and a second doping region are provided in each hollow region. The first doping region, the second doping region and the sub-substrate layer form a PIN structure, so that the substrate can be applied to a phase-shifting switch diode. When the phase-shifting switch diode is a table-top phase-shifting switch diode, the P-type electrode, the I-type electrode and the N-type electrode of the phase-shifting switch diode of the related art are stacked along the thickness direction of the phase-shifting switch diode, which is not conducive to subsequent electrical extraction, packaging and detection, and the table height is relatively high. In the present application, the plurality of sub-substrate layers, the first doping region and the second doping region of the second substrate layer are all arranged on the surface of the first substrate layer, so the sub-substrate layer, the first doping region and the second doping region are arranged along the surface of the first substrate layer, that is, the PIN structure is arranged along the surface of the first substrate layer, thereby making the electrode design planar and reducing the table height. In addition, the cross-sectional area of ​​the PIN structure can be adjusted by the length or width of the substrate, which can reduce the process difficulty of passivation slot filling, making the manufacturing process of the substrate of the present application simpler.

[0017] Regarding the location of the second doping region, in another possible implementation, a second blind hole is provided on the first surface of the second substrate layer, and the second doping region is provided in the second blind hole. That is, the thickness of the second doping region is less than the thickness of the second substrate layer.

[0018] Moreover, the first surface of the second substrate layer is the surface of the second substrate layer facing the first substrate layer. The substrate also includes a third doping region, which is arranged on the second surface of the second substrate layer away from the first substrate layer. The third doping region and the second doping region have different doping types and / or doping concentrations. The projection of the third doping region on the first surface overlaps with the second doping region, and the third doping region and the second doping region have a spacing in the thickness direction of the substrate. For the overlapping area, the third doping region and the second doping region are arranged at different thicknesses of the overlapping area, thereby, the present application can achieve different doping at different heights in a certain area of ​​the second substrate layer, thereby forming a three-dimensional doping structure in the substrate.

[0019] On this basis, the number of first doping regions is at least two, at least two first doping regions are arranged at intervals along the first direction, the second doping region and the third doping region are located between two adjacent first doping regions, the second doping region is in contact with one of the two adjacent first doping regions, and the third doping region is in contact with the other first doping region of the two adjacent first doping regions. In this way, the substrate can be used to manufacture a double-sided pressure sensor based on piezoresistance, which may include two piezoresistors, one of which is arranged on the second doping region, and the other piezoresistors is arranged on the third doping region, thereby improving the sensitivity of the double-sided pressure sensor based on piezoresistance. Moreover, electrical connection channels can be formed on the two adjacent first doping regions respectively by heavy doping, so as to perform metal interconnection on the surface of the double-sided pressure sensor based on piezoresistance, thereby simplifying the manufacturing process of the double-sided pressure sensor based on piezoresistance.

[0020] In some embodiments, the first doping region includes a first sub-doping region and a second sub-doping region, the first sub-doping region and the second sub-doping region are stacked along the thickness direction of the substrate, and the first sub-doping region and the second sub-doping region have different doping concentrations and / or doping types. Therefore, the present application can achieve different doping at different depths in the same area on the first surface of the substrate to form a three-dimensional doping structure.

[0021] Moreover, the size of the first sub-doping region along the first direction is greater than the size of the second sub-doping region along the first direction; the first doping region also includes a third sub-doping region, the third sub-doping region and the second sub-doping region are arranged along the first direction, and the first sub-doping region covers the second sub-doping region and the third sub-doping region. In this way, the first sub-doping region, the second sub-doping region and the third sub-doping region can form a three-dimensional doping structure. The first sub-doping region, the second sub-doping region and the third sub-doping region can form a PIN structure, so that the substrate can be applied to a phase-shifting switching diode. When the phase-shifting switching diode is a mesa phase-shifting switching diode, the present application can reduce the mesa height, and since the second sub-doping region and the third sub-doping region are arranged on the first sub-doping region, the lateral size of the phase-shifting switching diode can also be reduced.

[0022] In some embodiments, a fourth blind hole is provided on the surface of the first substrate layer facing the second substrate layer; the substrate further includes a fourth doping region provided in the fourth blind hole, and the fourth doping region is different from the first doping region in doping type and / or doping concentration, thereby forming a substrate with different temperature expansion coefficients. In addition, the fourth doping region can also be manufactured by etching first and then growing or depositing, thereby making the fourth doping region more precise.

[0023] Furthermore, the first doping region is in contact with and overlaps the fourth doping region, thereby achieving electrical interconnection between the first doping region and the fourth doping region.

[0024] In some embodiments, the substrate further includes a first dielectric layer located between the first substrate layer and the second substrate layer. A cavity is formed on the first dielectric layer, or a connected cavity is formed on the first dielectric layer and the first substrate layer. The cavity overlaps with the first doping region. When manufacturing the substrate, a first substrate layer and a second substrate layer may be provided first; a first dielectric layer may be manufactured on the first substrate layer; a cavity may be etched on the first dielectric layer, or a cavity may be etched on the first dielectric layer and the first substrate layer; a first doping region may be manufactured on the second substrate layer; the second substrate layer may be bonded to the first dielectric layer; and the surface of the second substrate layer facing away from the first substrate layer may be ground to complete the manufacturing of the substrate. The provision of the first dielectric layer may make the bonding process of the first substrate layer and the second substrate layer easier, that is, a better bonding effect may be achieved by using a lower bonding temperature. When the substrate is applied to a MEMS device, an oscillating body may be formed in the first doping region, and the cavity overlapping with the first doping region may provide sufficient resonance space for the resonance of the oscillating body.

[0025] In a second aspect of the present application, a method for manufacturing a substrate is further provided, the method comprising: providing a first substrate layer. providing a second substrate layer. etching a first blind hole on a first surface of the second substrate layer. forming a first doped region in the first blind hole. bonding the first substrate layer and the second substrate layer having the first doped region formed thereon, wherein the first surface faces the first substrate layer. grinding a second surface of the second substrate layer opposite to the first surface to expose the first doped region, wherein the thickness of the first doped region after grinding is the same as the thickness of the second substrate layer.

[0026] Since the doping region is made by diffusion or ion implantation in the related art, the depth of the doping region is shallow and is much smaller than the thickness of the substrate. In the present application, the thickness of the first doping region is the same as the thickness of the second substrate layer. When the thickness of the second substrate layer is greater than 5 μm, the depth of the first doping region is also greater than 5 μm. Therefore, the doping depth of the present application is deeper.

[0027] Furthermore, since the first doped region is formed by etching first and then growing or depositing, the manufacturing accuracy of the first doped region is higher.

[0028] In some embodiments, after the step of providing a second substrate layer, the manufacturing method further includes: etching a second blind hole on the first surface of the second substrate layer, the second blind hole is connected to the first blind hole, and the depth of the second blind hole is less than the depth of the first blind hole. A second doping region is formed in the second blind hole. After the step of grinding the second surface of the second substrate layer opposite to the first surface to expose the first doping region, the manufacturing method further includes: etching a third blind hole on the second surface of the second substrate layer, forming a third doping region in the third blind hole, and the projection of the third doping region on the first surface overlaps with the second doping region. For the overlapping area, the third doping region and the second doping region are arranged at different thicknesses in the overlapping area, thereby, the present application can achieve different doping at different heights in a certain area of ​​the second substrate layer, thereby forming a three-dimensional doping structure in the substrate.

[0029] In some embodiments, the step of forming the first doping region in the first blind hole includes: forming a second sub-doping region and a third sub-doping region arranged along the first direction in the first blind hole, the depths of the second sub-doping region and the third sub-doping region are both less than the depth of the first blind hole, and the first direction is perpendicular to the thickness direction of the substrate; forming the first sub-doping region in the first blind hole, and the first sub-doping region is stacked on the second sub-doping region and the third sub-doping region. The first sub-doping region, the second sub-doping region, and the third sub-doping region can form a three-dimensional doping structure. Therefore, the present application can realize different doping at different depths in the same area on the first surface of the substrate to form a three-dimensional doping structure. Moreover, the first sub-doping region, the second sub-doping region, and the third sub-doping region can form a PIN structure, so that the substrate can be applied to a phase-shifting switching diode. When the phase-shifting switching diode is a mesa phase-shifting switching diode, the present application can reduce the mesa height, and since the second sub-doping region and the third sub-doping region are arranged on the first sub-doping region, the lateral size of the phase-shifting switching diode can also be reduced.

[0030] In some embodiments, after the step of providing the first substrate layer, the manufacturing method further includes: etching a fourth blind hole on the first substrate layer. Forming a fourth doping region in the fourth blind hole. The step of bonding the first substrate layer and the second substrate layer having the first doping region formed thereon includes: bonding the first substrate layer having the fourth doping region formed thereon and the second substrate layer having the first doping region formed thereon, the fourth doping region being located on the surface of the first substrate layer facing the second substrate layer. The fourth doping region can also be manufactured by etching first and then growing or depositing, thereby making the manufacturing accuracy of the fourth doping region also high.

[0031] The third aspect of the present application further provides a semiconductor device, comprising an electrode and a substrate according to any one of the embodiments of the first aspect, wherein the electrode is disposed on the substrate. The semiconductor device can achieve all the effects of the substrate.

[0032] In a fourth aspect of the present application, a circuit module is provided, comprising a controller and the semiconductor device of the third aspect, wherein the controller is electrically connected to the semiconductor device. The circuit module can achieve all the effects of the semiconductor device.

[0033] In a fifth aspect of the present application, an electronic device is provided, comprising a circuit board and the circuit module of the fourth aspect, wherein the circuit module is electrically connected to the circuit board. The electronic device can achieve all the effects of the circuit module. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0035] Figure 1a It is a schematic structural diagram of a substrate in the first related technology;

[0036] Figure 1b is a schematic structural diagram of a substrate in a second related art;

[0037] Figure 2 This is a schematic structural diagram of a substrate in the first embodiment of the present application;

[0038] Figure 3 This is a schematic structural diagram of a substrate in a second embodiment of the present application;

[0039] Figure 4a Based on Figure 2 The schematic diagram of the structure of the first step in the process of manufacturing a MEMS device on a substrate;

[0040] Figure 4b Based on Figure 2 The schematic diagram of the structure of the second step in the process of manufacturing a MEMS device on a substrate;

[0041] Figure 4c Based on Figure 2 The schematic diagram of the structure of the third step in the process of manufacturing a MEMS device using a substrate;

[0042] Figure 4d Based on Figure 2 The schematic diagram of the structure of the fourth step in the process of manufacturing a MEMS device using a substrate;

[0043] Figure 4e Based on Figure 2 The schematic diagram of the structure of the fifth step in the process of manufacturing a MEMS device using a substrate;

[0044] Figure 5 This is a schematic structural diagram of a substrate in a third embodiment of the present application;

[0045] Figure 6 This is a schematic structural diagram of a substrate in a fourth embodiment of the present application;

[0046] Figure 7 This is a schematic structural diagram of a substrate in a fifth embodiment of the present application;

[0047] Figure 8 This is a schematic structural diagram of a substrate in a sixth embodiment of the present application;

[0048] Figure 9a Based on Figure 8 The schematic diagram of the first step in the process of manufacturing a gas sensor on a substrate;

[0049] Figure 9b Based on Figure 8 The schematic diagram of the structure of the second step in the process of manufacturing a gas sensor on a substrate;

[0050] Fig.9c Based on Figure 8 The schematic diagram of the structure of the third step in the process of manufacturing a gas sensor on a substrate;

[0051] Fig.10 This is a schematic structural diagram of a substrate in the seventh embodiment of the present application;

[0052] Fig.11a Based on Fig.10 The structural diagram of the first step in the process of manufacturing a phase-shift switch diode using a substrate;

[0053] Fig.11b Based on Fig.10 The schematic diagram of the structure of the second step in the process of manufacturing a phase-shift switch diode using a substrate;

[0054] Fig.11c Based on Fig.10 The schematic diagram of the structure of the third step in the process of manufacturing a phase-shift switch diode using a substrate;

[0055] Fig.11d Based on Fig.10 The schematic diagram of the structure of the fourth step in the process of manufacturing a phase-shift switch diode using a substrate;

[0056] Fig.11e Based on Fig.10 The schematic diagram of the structure of the fifth step in the process of manufacturing a phase-shift switch diode using a substrate;

[0057] Fig.12 This is a schematic structural diagram of a substrate in an eighth embodiment of the present application;

[0058] Fig.13 This is a schematic structural diagram of a substrate in a ninth embodiment of the present application;

[0059] Fig.14 This is a schematic structural diagram of a substrate in a tenth embodiment of the present application;

[0060] Fig.15 This is a schematic structural diagram of a substrate in the eleventh embodiment of the present application;

[0061] Fig.16a Based on Fig.15 The schematic diagram of the first step in the process of manufacturing a double-sided pressure sensor based on piezoresistive substrate;

[0062] Fig.16b Based on Fig.15 The schematic diagram of the structure of the second step in the process of manufacturing a double-sided pressure sensor based on piezoresistor on a substrate;

[0063] Fig.16c Based on Fig.15 A schematic diagram of the structure of the third step in the process of manufacturing a double-sided pressure sensor based on piezoresistor on a substrate;

[0064] Fig.16d Based on Fig.15 A schematic diagram of the structure of the fourth step in the process of manufacturing a double-sided pressure sensor based on piezoresistor on a substrate;

[0065] Fig.16e Based on Fig.15 The schematic diagram of the structure of the fifth step in the process of manufacturing a double-sided pressure sensor based on piezoresistor on a substrate;

[0066] Fig.16f Based on Fig.15 The schematic diagram of the sixth step in the process of manufacturing a double-sided pressure sensor based on piezoresistive substrate;

[0067] Fig.17 This is a schematic structural diagram of a substrate in the twelfth embodiment of the present application;

[0068] Fig.18 This is a schematic structural diagram of a substrate in the thirteenth embodiment of the present application;

[0069] Fig.19a Based on Fig.18 The structural diagram of the first step in the process of manufacturing a phase-shift switch diode using a substrate;

[0070] Fig.19b Based on Fig.18 The schematic diagram of the structure of the second step in the process of manufacturing a phase-shift switch diode using a substrate;

[0071] Fig.19c Based on Fig.18 The schematic diagram of the structure of the third step in the process of manufacturing a phase-shift switch diode using a substrate;

[0072] Fig.19d Based on Fig.18 The schematic diagram of the structure of the fourth step in the process of manufacturing a phase-shift switch diode using a substrate;

[0073] Fig.19e Based on Fig.18 The schematic diagram of the structure of the fifth step in the process of manufacturing a phase-shift switch diode using a substrate;

[0074] Fig. 20 for Figure 2 A schematic diagram of a process for manufacturing a substrate shown;

[0075] Fig.21 for Fig. 20 A schematic diagram of the specific process of the manufacturing method shown;

[0076] Fig. 22 for Figure 7 A schematic diagram of a process for manufacturing a substrate shown;

[0077] Fig.23 for Fig. 22 A schematic diagram of the specific process of the manufacturing method shown;

[0078] Fig.24 for Fig.17 A schematic diagram of a process for manufacturing a substrate shown;

[0079] Fig.25 for Fig.24 A schematic diagram of the specific process of the manufacturing method shown;

[0080] Fig.26 for Fig.18 A schematic diagram of a process for manufacturing a substrate shown;

[0081] Fig. 27 for Fig.26 Schematic diagram of the specific process of the production method shown.

[0082] Icons: 10-substrate; 11-substrate layer; 12-doping region; 31-first substrate layer; 32-second substrate layer; 321-hollow region; 322-first surface; 323-second surface; 324-sub-substrate layer; 325-N-type electrode; 33-first dielectric layer; 331-cavity; 34-isolation layer; 41-first doping region; 411-first sub-doping region; 412-second sub-doping region; 413-third sub-doping region; 42-second doping region; 43-third doped region; 44-fourth doped region; 451-second dielectric layer; 452-metal layer; 4521-electrode; 4531-first oscillator; 4532-second oscillator; 454-first passivation layer; 455-sensing layer; 456-second passivation layer; 457-third dielectric layer; 51-first blind hole; 511-first sub-blind hole; 512-second sub-blind hole; 52-second blind hole; 53-third blind hole; 54-fourth blind hole. DETAILED DESCRIPTION

[0083] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0084] The term "and / or" herein is merely a description of the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone, wherein A and B may be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one (item)" refers to one or more, and "plurality" refers to two or more. "At least one of the following (items)" or similar expressions refers to any combination of these items, including any combination of single (items) or plural (items). For example, at least one (item) of a, b or c may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or multiple.

[0085] The terms "first" and "second" in the description and claims of the embodiments of the present application are used to distinguish different objects rather than to describe a specific order of objects. For example, a first target object and a second target object are used to distinguish different target objects rather than to describe a specific order of target objects.

[0086] "Connected", "connected" and similar words are used to express the intercommunication or interaction between different components, which may include direct connection or indirect connection through other components. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, inclusion of a series of steps or units. Methods, systems, products or devices are not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right" and the like are only used relative to the orientation of the components in the drawings. These directional terms are relative concepts. They are used for description and clarification relative to the description, which may change accordingly according to the change of the orientation of the components in the drawings.

[0087] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0088] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" refers to two or more than two. For example, multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.

[0089] An electronic device may generally include a circuit module and a circuit board, and the circuit module is electrically connected to the circuit board. The circuit module may be a power distribution unit (PDU). The circuit module may include a semiconductor device, a drive circuit, a controller, and the like. The semiconductor device is electrically connected to the drive circuit, and the semiconductor device is also electrically connected to the controller. The drive circuit may provide a drive signal to the semiconductor device, and the controller may provide a control signal to the semiconductor device. Here, the semiconductor device may be a micro-electro-mechanical system (MEMS) device. Specifically, the semiconductor device may be a resonator, a micro-vibration mirror, an optical image stabilization device, a speaker, a switching diode, an oscillator, a gas sensor, a piezoresistive sensor, an accelerometer, a gyroscope, and the like. The semiconductor device may include a substrate and an electrode disposed on the substrate.

[0090] In order to realize the basic functions of the substrate, a doping region is usually provided on the substrate. In the related art, the doping region is usually made by diffusion or ion implantation. For example, Figure 1a and Figure 1b As shown, the substrate 10 includes a substrate layer 11 and a doped region 12 disposed on the substrate layer 11 . Figure 1a The doping region 12 in the embodiment is made by diffusion. Figure 1a It can be seen that, on the one hand, the depth of the doped region 12 made by diffusion is relatively shallow, and its depth is much smaller than the thickness of the substrate layer 11. Moreover, during diffusion, it is necessary to plate a doped seed layer on the surface of the substrate layer 11, and then the seed layer needs to be placed in a high temperature environment for a long time so that it can diffuse from the surface of the substrate layer 11 to the inside of the substrate layer 11. On the other hand, the width of the doped region 12 is greater than the gap width of the dielectric layer above the substrate layer 11. It can be seen that the diffusion manufacturing process has the problem of lateral diffusion. On the other hand, the diffusion concentration on the surface of the substrate layer 11 is prone to saturation, and it is difficult to ensure uniform diffusion inside the substrate layer 11. In other words, the manufacturing accuracy of the doped region 12 is low.

[0091] Figure 1b The doping region 12 is made by ion implantation. Figure 1b It can be seen that the doping region 12 made by ion implantation also has the problem of shallow depth. Moreover, when the substrate layer 11 is a silicon substrate layer, the damage to the silicon lattice is large during the ion implantation process, and even adding an annealing process after the ion implantation cannot eliminate the damage.

[0092] Based on this, the embodiment of the present application provides a substrate 10 that can increase the depth of the doping region, improve the manufacturing accuracy of the doping region, and is not prone to damage to the silicon lattice.

[0093] For the convenience of description, two directions can be defined, namely a first direction (X direction) and a second direction (Z direction). The X direction represents the length direction of the semiconductor device, and the Z direction represents the thickness direction of the semiconductor device. The X direction and the Z direction are perpendicular.

[0094] like Figure 2 As shown, in this embodiment, the substrate 10 may include a first substrate layer 31, a first dielectric layer 33, and a second substrate layer 32 which are stacked in sequence. The materials of the first substrate layer 31 and the second substrate layer 32 may both be single crystal silicon. The first dielectric layer 33 may be an oxide layer. Moreover, the provision of the first dielectric layer 33 may make the bonding process of the first substrate layer 31 and the second substrate layer 32 easier. That is, a lower bonding temperature may be used to achieve a better bonding effect. In other embodiments, such as Figure 3 As shown, the substrate 10 may include a stacked first substrate layer 31 and a second substrate layer 32 , but does not include a first dielectric layer 33 .

[0095] like Figure 2 and Figure 3As shown, a hollow region 321 is formed on the second substrate layer 32. The substrate 10 may further include a first doping region 41. The first doping region 41 is disposed in the hollow region 321, and the thickness of the first doping region 41 is the same as the thickness of the second substrate layer 32.

[0096] Since the doping region 12 is made by diffusion or ion implantation in the related art, the depth of the doping region 12 is relatively shallow, and the depth of the doping region 12 is much smaller than the thickness of the substrate layer 11. In the present embodiment, the thickness of the first doping region 41 is the same as the thickness of the second substrate layer 32. When the thickness of the second substrate layer 32 is greater than 5 μm, the depth of the first doping region 41 is also greater than 5 μm. Therefore, the doping depth of the present embodiment is deeper.

[0097] Moreover, in the present embodiment, a hollow region 321 is formed on the second substrate layer 32, and the first doping region 41 is arranged in the hollow region 321. Therefore, when making the first doping region 41, a blind hole can be formed on the first surface of the second substrate layer 32 by etching, and then the first doping region 41 is formed in the blind hole by growth or deposition. The first doping region 41 can be made by growing single crystal silicon or polycrystalline silicon in the first blind hole, and passing gas in the process of growing single crystal silicon or polycrystalline silicon. Moreover, passing different gases can achieve different types and / or different concentrations of doping. The second surface of the second substrate layer 32 opposite to the first surface is ground to expose the first doping region 41, thereby completing the production of the first doping region 41. Since the first doping region 41 in the present embodiment can be produced by etching first and then growing or depositing, the size accuracy of the first doping region 41 is higher and more uniform, that is, the production accuracy of the first doping region 41 is higher.

[0098] like Figure 2 As shown, the number of the first doping region 41 can be one. The second substrate layer 32 can be a doped substrate. Moreover, the doping type and / or doping concentration of the first doping region 41 and the second substrate layer 32 are different. In one example, the doping type of the first doping region 41 is the same as the doping type of the second substrate layer 32, and the doping concentration of the first doping region 41 is different from the doping concentration of the second substrate layer 32. In another example, the doping type of the first doping region 41 is different from the doping type of the second substrate layer 32, and the doping concentration of the first doping region 41 is the same as the doping concentration of the second substrate layer 32. In yet another example, the doping type of the first doping region 41 is different from the doping type of the second substrate layer 32, and the doping concentration of the first doping region 41 is different from the doping concentration of the second substrate layer 32.

[0099] The substrate 10 of this embodiment can be used to manufacture MEMS devices. Figure 4a , Figure 4b , Figure 4c Figure 4d and Figure 4e MEMS devices are made in the following order. Figure 4a As shown, a second dielectric layer 451 is formed on the substrate 10. The second dielectric layer 451 can be formed by first depositing and then etching. The second dielectric layer 451 can cover a portion of the second substrate layer 32 and a portion of the first doped region 41. Figure 4b As shown, a metal layer 452 is formed on the substrate 10, and the metal layer 452 includes four electrodes 4521, wherein the bottoms of two electrodes 4521 are in contact with the second substrate layer 32, and the bottoms of the other two electrodes 4521 are in contact with the first doping region 41. Figure 4c As shown, a portion of the second substrate layer 32 and a portion of the first doping region 41 are etched respectively to form a first oscillating body 4531 and a second oscillating body 4532. The first oscillating body 4531 is formed by etching the second substrate layer 32, and the second oscillating body 4532 is formed by etching the first doping region 41. Since the first doping region 41 and the second substrate layer 32 have different doping types and / or doping concentrations, the first oscillating body 4531 and the second oscillating body 4532 have different doping types and / or doping concentrations, thereby making the first oscillating body 4531 and the second oscillating body 4532 have different temperature characteristics, where the temperature characteristic may be a temperature expansion coefficient. Figure 4d As shown, the partial area on the first substrate layer 31 corresponding to the first oscillating body 4531 and the second oscillating body 4532 is etched. Figure 4e As shown, the partial regions corresponding to the first oscillating body 4531 and the second oscillating body 4532 on the first dielectric layer 33 are etched to obtain a MEMS device. This allows different regions in the same MEMS device to have different temperature expansion coefficients. Alternatively, the doping type and doping concentration of the first oscillating body 4531 and the second oscillating body 4532 in the same MEMS device are the same, and the doping type and doping concentration of the first oscillating body 4531 and the second oscillating body 4532 in different MEMS devices are different, so that different MEMS devices can have different temperature expansion coefficients.

[0100] In order to form isolation between the first doping region 41 and the second substrate layer 32, in other embodiments of the present application, such as Figure 5 As shown, the substrate 10 may further include an isolation layer 34, which is located between the first doping region 41 and the second substrate layer 32. There may be two isolation layers 34, which are respectively located on two opposite sides of the first doping region 41 and arranged along the X direction.

[0101] In other embodiments of the present application, Figure 6 As shown, Figure 2 The difference between the illustrated embodiments lies in the structure of the first dielectric layer 33. When the substrate 10 is applied to a MEMS device, as shown in FIG. Figure 6As shown, two cavities 331 can be formed on the first dielectric layer 33, the first doped region 41 covers one of the cavities 331, and the second substrate layer 32 covers the other cavity 331. When manufacturing the substrate 10, the first substrate layer 31 and the second substrate layer 32 can be provided first; the first dielectric layer 33 is manufactured on the first substrate layer 31; the cavity 331 is etched on the first dielectric layer 33; the first doped region 41 is manufactured on the second substrate layer 32; the second substrate layer 32 is bonded to the first dielectric layer 33; the surface of the second substrate layer 32 facing away from the first substrate layer 31 is ground, and the manufacturing of the substrate 10 is completed. Figure 6 When the substrate 10 shown is applied to a MEMS device, Figure 4e The first oscillating body 4531 and the second oscillating body 4532 shown can cover two cavities 331 respectively, so that the cavities 331 can provide sufficient resonance space for the resonance of the corresponding oscillating bodies. Figure 6 When the substrate 10 shown in the figure is used to manufacture a MEMS device, the following method can be used: Figure 4a , Figure 4b , Figure 4c and Figure 4d The order of production is not required. Figure 4e As shown, the first dielectric layer 33 is etched, thereby saving subsequent processing steps.

[0102] In other embodiments of the present application, Figure 7 As shown, Figure 2 The difference between the illustrated embodiments lies in the structure of the first substrate layer 31 . Figure 2 No doping region is provided on the first substrate layer 31. In this embodiment, Figure 7 As shown, a fourth doping region 44 may be provided on the first substrate layer 31. Specifically, the substrate 10 is provided with a fourth blind hole 54 on the first substrate layer 31 and the first dielectric layer 33, a portion of the fourth blind hole 54 is located on the first dielectric layer 33, and the remaining portion of the fourth blind hole 54 is located on the first substrate layer 31. The substrate 10 further includes a fourth doping region 44, which is provided in the fourth blind hole 54. The fourth doping region 44 has a different doping type and / or doping concentration from the first doping region 41. Moreover, in this embodiment, there is no overlap between the fourth doping region 44 and the first doping region 41. The fourth doping region 44 may also be manufactured by etching first and then growing or depositing, thereby making the doping accuracy of the fourth doping region 44 higher. Moreover, in this embodiment, the substrate 10 with different temperature expansion coefficients may be formed by adjusting the doping type and / or doping concentration of the first doping region 41, or adjusting the doping type and / or doping concentration of the fourth doping region 44.

[0103] In other embodiments of the present application, Figure 8 As shown, Figure 2The difference between the illustrated embodiments lies in the number of first doping regions 41. Figure 8 As shown, in this embodiment, the number of the first doping regions 41 can be multiple, the doping types of the multiple first doping regions 41 are the same, and the doping concentrations of the multiple first doping regions 41 are also the same. The multiple first doping regions 41 can be arranged along the X direction and spaced apart. When the number and / or doping concentration of the first doping regions 41 in different substrates 10 are different, the temperature expansion coefficients of the different substrates 10 are different. Therefore, the number and / or doping concentration of the first doping regions 41 can be determined according to the requirements of the temperature expansion coefficient of the substrate 10, thereby, substrates 10 with multiple different temperature expansion coefficients can be manufactured. In addition, the thicknesses of the multiple first doping regions 41 are also the same. In this way, when manufacturing the substrate 10, multiple first doping regions 41 can be manufactured in the same process. Therefore, this embodiment can also simplify the manufacturing process of the substrate 10.

[0104] On this basis, if Figure 8 As shown, the second substrate layer 32 includes a plurality of sub-substrate layers 324 that are spaced apart and arranged along the X direction, and a hollow area 321 is formed between every two adjacent sub-substrate layers 324. A first doping area 41 is provided in each hollow area 321. The sub-substrate layer 324 may also be a doped substrate, and the doping type of the sub-substrate layer 324 may be different from the doping type of the first doping area 41. For example, the sub-substrate layer 324 is a P-type substrate, and the first doping area 41 is an N-type doping area. Or, the sub-substrate layer 324 is an N-type substrate, and the first doping area 41 is a P-type doping area. In this way, the substrate 10 may form an NPN structural layer or a PNP structural layer on the first substrate layer 31. The substrate 10 of this embodiment may be applied to a gas sensor, and exemplarily, may be configured as follows. Figure 9a , Figure 9b of Fig.9c The gas sensor is made in the following order. Figure 9a As shown, a first passivation layer 454 is formed on the second substrate layer 32 of the substrate 10. Figure 9b As shown, a metal layer 452 is formed on the second substrate layer 32 of the substrate 10. The metal layer 452 includes a plurality of electrodes 4521. The number of electrodes 4521 is the same as the number of first doping regions 41. A portion of each electrode 4521 is disposed in the first passivation layer 454 and contacts the first doping region 41. Another portion of each electrode 4521 extends out of the first passivation layer 454. Fig.9c As shown, the sensing layer 455 is formed on the first passivation layer 454. Since the substrate 10 includes an NPN structure layer or a PNP structure layer, the structure layer can be formed in the process of forming the substrate 10. In this way, there is no need to form the structure layer in the subsequent processing technology, and there is no need to perform doping in the subsequent processing technology, thereby reducing the subsequent process flow and reducing the wafer production cost.

[0105] In other embodiments of the present application, Fig.10 As shown, Figure 2 The difference between the embodiment shown in the figure is that the number of the first doping regions 41 and the Figure 2 On the basis of the embodiment shown in FIG. 4 , a second doping region 42 is added. Specifically, in this embodiment, as shown in FIG. Fig.10 As shown, the substrate 10 may further include a second doping region 42, and the second doping region 42 and the first doping region 41 are arranged on the same side of the first substrate layer 31. The second doping region 42 has a different doping type and / or doping concentration from the first doping region 41. In a possible implementation, the doping type of the second doping region 42 is the same as the doping type of the first doping region 41, and the doping concentration of the second doping region 42 is different from the doping concentration of the first doping region 41. In this case, the region on the substrate 10 where the first doping region 41 is arranged has a different temperature expansion coefficient from the region where the second doping region 42 is arranged, and the frequency stability under temperature drift is also different, so the substrate 10 can be applied to a dual sensor.

[0106] In another possible implementation, the doping concentration of the second doping region 42 is the same as the doping concentration of the first doping region 41, and the doping type of the second doping region 42 is different from the doping type of the first doping region 41. In this way, the first doping region 41 and the second doping region 42 can form an NPN structure layer, or a PNP structure layer.

[0107] In another possible implementation, the doping concentration of the second doping region 42 is different from the doping concentration of the first doping region 41, and the doping type of the second doping region 42 is different from the doping type of the first doping region 41. Similarly, the first doping region 41 and the second doping region 42 may also form an NPN structure layer, or a PNP structure layer.

[0108] like Fig.10 As shown, the second substrate layer 32 may include a plurality of spaced sub-substrate layers 324, and a hollow region 321 is formed between every two adjacent sub-substrate layers 324. A first doping region 41 and a second doping region 42 are provided in each hollow region 321. Moreover, the number of the first doping regions 41 is the same as the number of the second doping regions 42. The thicknesses of the first doping region 41, the second doping region 42 and the second substrate layer 32 are the same. In this way, when manufacturing the second doping region 42, after a blind hole is formed on the first surface of the second substrate layer 32, the first doping region 41 can be formed in the blind hole by growth or deposition, and the second doping region 42 can also be formed in the blind hole by growth or deposition. When the second surface of the second substrate layer 32 is ground to expose the first doping region 41, the second doping region 42 can also be exposed, thereby improving and simplifying the manufacturing process of the second doping region 42.

[0109] In addition, the first doping region 41, the second doping region 42 and the sub-substrate layer 324 may form a PIN structure. For example, the first doping region 41 is a P-type doping region, the second doping region 42 is an I-type doping region, and the sub-substrate layer 324 may be an N-type substrate. Therefore, a plurality of PIN structures may be formed in the substrate 10, and thus the substrate 10 may be applied to a phase-shift switch diode.

[0110] According to Fig.11a , Fig.11b , Fig.11c , Fig.11d and Fig.11e The phase shift switch diode is made in the order of Fig.11a As shown, a first passivation layer 454 is formed on the second substrate layer 32 of the substrate 10. The first passivation layer 454 covers the first doping region 41, the second doping region 42 and a portion of the sub-substrate layer 324. Fig.11b As shown, a portion of the second substrate layer 32 is etched to form a plurality of N-type electrodes 325. Fig.11c As shown, a second passivation layer 456 is formed on the first dielectric layer 33. The upper surface of the second passivation layer 456 is flush with the upper surface of the first passivation layer 454. Fig.11d As shown, a portion of the first passivation layer 454 is etched to expose the first doped region 41 and the sub-substrate layer 324. The first doped region 41 can be used as a P-type electrode, the second doped region 42 can be used as an I-type electrode, and the sub-substrate layer 324 can be used as an N-type electrode. Fig.11e As shown, a metal layer 452 is manufactured. The metal layer 452 includes a plurality of groups of electrodes 4521, and a portion of one electrode 4521 in each group of electrodes 4521 is disposed between the first passivation layer 454 and the second passivation layer 456, and contacts the first doped region 41. A portion of another electrode 4521 in each group of electrodes 4521 is disposed between the first passivation layer 454 and the second passivation layer 456, and contacts the sub-substrate layer 324.

[0111] When the phase-shifting switch diode is a mesa phase-shifting switch diode, the P-type electrode, I-type electrode and N-type electrode of the phase-shifting switch diode of the related art are stacked along the Z direction of the phase-shifting switch diode, which is not conducive to the subsequent electrical extraction, packaging and detection, and the mesa height is relatively high. In this embodiment, the multiple sub-substrate layers 324, the first doping region 41 and the second doping region 42 of the second substrate layer 32 are all arranged on the surface of the first substrate layer 31, so the sub-substrate layer 324, the first doping region 41 and the second doping region 42 are arranged along the surface of the first substrate layer 31. The sub-substrate layer 324, the first doping region 41 and the second doping region 42 form a PIN structure, so the P-type electrode, the I-type electrode and the N-type electrode are arranged along the surface of the first substrate layer 31, that is, arranged along the length direction of the phase-shifting switch diode. In this way, the electrode design can be planarized and the mesa height can be reduced. In addition, the cross-sectional area of ​​the PIN structure can be adjusted by the length or width of the substrate 10, which can reduce the process difficulty of passivation slot filling, making the manufacturing process of the substrate 10 of this embodiment simpler.

[0112] In other embodiments of the present application, Fig.12 As shown, Fig.10 The difference between the embodiments shown is that in this embodiment Fig.10 In the embodiment shown in FIG. 1 , a cavity 331 is formed on the first dielectric layer 33 and the first substrate layer 31. The cavity 331 overlaps with both the first doping region 41 and the second doping region 42. When the substrate 10 is applied to a MEMS device, the first doping region 41 and the second doping region 42 can be etched to form an oscillating body, and the cavity 331 overlapping with the first doping region 41 and the second doping region 42 can provide sufficient resonance space for the resonance of the oscillating body.

[0113] In other embodiments of the present application, Fig.13 As shown, Fig.12 The difference between the embodiments shown is that in this embodiment Fig.12 A fourth doping region 44 is added on the basis of the embodiment shown. In this embodiment, Fig.13 As shown, a fourth doping region 44 may be provided in the cavity 331. The fourth doping region 44 has a different doping type and / or doping concentration from the first doping region 41. Moreover, in the present embodiment, the fourth doping region 44 is in contact with the first doping region 41, thereby enabling electrical interconnection between the fourth doping region 44 and the first doping region 41. The fourth doping region 44 is also in contact with the second doping region 42, thereby enabling electrical interconnection between the fourth doping region 44 and the second doping region 42. The fourth doping region 44 may also be fabricated by etching first and then growing or depositing, thereby enabling the fabrication accuracy of the fourth doping region 44 to be higher.

[0114] In other embodiments of the present application, Fig.14 As shown, Fig.13The difference between the embodiments shown is the number of the first doping region 41, the second doping region 42, the position of the fourth doping region 44 and the Fig.13 An isolation layer 34 is added on the basis of Fig.14 As shown, there are two first doping regions 41, one second doping region 42, and the second doping region 42 is located between the two first doping regions 41. An isolation layer 34 is provided between the first doping region 41 and the sub-substrate layer 324 and between the first doping region 41 and the second doping region 42.

[0115] In other embodiments of the present application, Fig.15 As shown, Fig.10 The difference between the two is the number and location of the second doping regions 42. Fig.15 As shown, in this embodiment, the number of the second doping regions 42 is less than the number of the first doping regions 41, and the number of the first doping regions 41 may be twice the number of the second doping regions 42. Fig.15 In the embodiment, the number of the first doping regions 41 is four, and the number of the second doping regions 42 is two. One of the second doping regions 42 may be located between two of the first doping regions 41 , and another second doping region 42 may be located between the other two first doping regions 41 .

[0116] The first surface 322 of the second substrate layer 32 is provided with a second blind hole 52, and the second doping region 42 is provided in the second blind hole 52. That is, the thickness of the second doping region 42 is less than the thickness of the second substrate layer 32.

[0117] The substrate 10 of this embodiment can be applied to a double-sided pressure sensor based on piezoresistance. Fig.16a , Fig.16b , Fig.16c , Fig.16d , Fig.16e and Fig.16f The double-sided pressure sensor based on piezoresistance is fabricated in the following order. Fig.16a As shown, a first passivation layer 454 may be formed on the second substrate layer 32 of the substrate 10. Fig.16bAs shown, a third doping region 43 is formed on the second surface 323 of the second substrate layer 32 by, for example, ion implantation. The third doping region 43 and the second doping region 42 have different doping types and / or doping concentrations. The projection of the third doping region 43 on the first surface 322 overlaps with the second doping region 42. The third doping region 43 and the second doping region 42 have a spacing in the thickness direction of the substrate 10. For the overlapping area between the projection of the third doping region 43 on the first surface 322 and the second doping region 42, the third doping region 43 and the second doping region 42 are arranged at different thicknesses in the overlapping area. Moreover, the number of the first doping regions 41 is at least two, at least two first doping regions 41 are arranged along the X direction and are arranged at intervals, the second doping region 42 and the third doping region 43 are located between two adjacent first doping regions 41, the second doping region 42 is in contact with one of the two adjacent first doping regions 41, and the third doping region 43 is in contact with the other of the two adjacent first doping regions 41.

[0118] Remove the first passivation layer 454, such as Fig.16c As shown, the second substrate layer 32 and the first doping region 41 are exposed. Fig.16d As shown, a second passivation layer 456 is formed on the second substrate layer 32. Fig.16e As shown, a metal layer 452 is formed on the second passivation layer 456, and the metal layer 452 includes a plurality of electrodes 4521, and a portion of each electrode 4521 is disposed in the second passivation layer 456 and contacts the first doped region 41. Thus, the electrical connection of the double-sided pressure sensor based on piezoresistance can be realized. Fig.16f As shown, the regions on the first substrate layer 31 and the first dielectric layer 33 corresponding to the two first doping regions 41 farthest apart, and the regions on the first substrate layer 31 and the first dielectric layer 33 corresponding to the region between the two first doping regions 41 are etched.

[0119] A piezoresistance-based double-sided pressure sensor may include two piezoresistors, one of which is located at Fig.16f The second doping region 42 is provided with a piezoresistance resistor, and the other piezoresistance resistor is provided with a third doping region 43, thereby improving the sensitivity of the double-sided pressure sensor based on piezoresistance. Moreover, electrical connection channels can be formed on two adjacent first doping regions 41 by heavy doping, that is, Fig.16e The electrodes shown are used to make metal interconnections on the surface of the piezoresistive-based double-sided pressure sensor, thereby simplifying the manufacturing process of the piezoresistive-based double-sided pressure sensor.

[0120] In other embodiments of the present application, Fig.16b The third doping region 43 in the substrate 10 can be formed during the manufacturing process, and does not need to be manufactured in a subsequent process after obtaining the substrate 10. For example, Fig.17As shown, in this embodiment, the substrate 10 includes a third doping region 43. In addition, the third doping region 43 is disposed at a position similar to Fig.16b The third doping region 43 is arranged at the same position, which will not be described again. For the overlapping area between the projection of the third doping region 43 on the first surface 322 and the second doping region 42, the third doping region 43 and the second doping region 42 are arranged at different thicknesses in the overlapping area, so that the present embodiment can achieve different doping at different heights in a certain area of ​​the second substrate layer 32, thereby forming a three-dimensional doping structure in the substrate 10.

[0121] In other embodiments of the present application, Fig.18 As shown, Figure 2 The difference between the illustrated embodiments lies in the number and structure of the first doping regions 41. Fig.18 As shown, in this embodiment, the number of the first doping region 41 may be plural. Moreover, the first doping region 41 may include a first sub-doping region 411 , a second sub-doping region 412 and a third sub-doping region 413 .

[0122] The first sub-doping region 411 and the second sub-doping region 412 are stacked along the Z direction, the first sub-doping region 411 and the third sub-doping region 413 are stacked along the Z direction, and the third sub-doping region 413 and the second sub-doping region 412 are arranged along the X direction. The third sub-doping region 413 and the second sub-doping region 412 have the same size along the Z direction. Moreover, the first sub-doping region 411 covers the second sub-doping region 412 and the third sub-doping region 413, that is, the size of the first sub-doping region 411 along the X direction is greater than the sum of the sizes of the second sub-doping region 412 and the third sub-doping region 413 along the X direction. The doping concentration and / or doping type of the first sub-doping region 411, the second sub-doping region 412 and the third sub-doping region 413 are different. In this way, the first sub-doping region 411, the second sub-doping region 412 and the third sub-doping region 413 can form a three-dimensional doping structure. The first sub-doping region 411, the second sub-doping region 412, and the third sub-doping region 413 may form a PIN structure, so that the substrate 10 may be applied to a phase-shifting switching diode. When the phase-shifting switching diode is a mesa phase-shifting switching diode, the mesa height may be reduced, and since the second sub-doping region 412 and the third sub-doping region 413 are disposed on the first sub-doping region 411, the size of the phase-shifting switching diode along the X direction may also be reduced.

[0123] In this embodiment, the Fig.19a , Fig.19b , Fig.19c , Fig.19d and Fig.19e The phase shift switch diode is made in the order of Fig.19aAs shown, a second dielectric layer 451 is formed on the second substrate layer 32 of the substrate 10. The second dielectric layer 451 covers the first doped region 41, the second doped region 42 and part of the sub-substrate layer 324. Fig.19b As shown, part of the second substrate layer 32 is etched, and part of the second substrate layer 32 covered by the second dielectric layer 451 is retained. Fig.19c As shown, a third dielectric layer 457 is formed on the first dielectric layer 33. The upper surface of the third dielectric layer 457 is flush with the upper surface of the second dielectric layer 451. Fig.19d As shown, a portion of the second dielectric layer 451 is etched to expose a portion of the first doped region 41 and a portion of the sub-substrate layer 324. Fig.19e As shown, a metal layer 452 is manufactured. The metal layer 452 includes a plurality of electrodes 4521, wherein a portion of one electrode 4521 is disposed between the third dielectric layer 457 and the second dielectric layer 451 and contacts the first doped region 41, and the remaining portion of the electrode 4521 is located above the third dielectric layer 457 and the second dielectric layer 451. A portion of one electrode 4521 is disposed between the third dielectric layer 457 and the second dielectric layer 451 and contacts the second doped region 42, and the remaining portion of the electrode 4521 is located above the third dielectric layer 457 and the second dielectric layer 451.

[0124] When the phase-shifting switching diode is a table-type phase-shifting switching diode, in this embodiment, Fig.19e As shown, the first doping region 41, the second doping region 42 and the sub-substrate layer 324 can form a PIN structure. The sub-substrate layer 324, the first doping region 41 and the second doping region 42 are all arranged on the surface of the first substrate layer 31, so the sub-substrate layer 324, the first doping region 41 and the second doping region 42 are arranged along the surface of the first substrate layer 31. In this way, the electrode design can be planarized and the table height can be reduced. In addition, the cross-sectional area of ​​the PIN structure can be adjusted by the length or width of the substrate 10, which can reduce the process difficulty of passivation slot filling, making the manufacturing process of the substrate 10 of this embodiment simpler.

[0125] The present application also provides a method for manufacturing a substrate, which can be applied to Figure 2 The substrate 10 shown. Fig. 20 As shown, the production method includes:

[0126] like Fig.21 As shown, S201, providing a first substrate layer 31.

[0127] S202 , manufacturing a first dielectric layer 33 on the first substrate layer 31 .

[0128] like Fig.21 As shown, the first dielectric layer 33 may be an oxide layer.

[0129] S203, providing a second substrate layer 32.

[0130] exist Fig.21 In the embodiment, the second substrate layer 32 may be a doped substrate. For example, the second substrate layer 32 is a P-type substrate or an N-type substrate.

[0131] S204 , etching a first blind hole 51 on the first surface 322 of the second substrate layer 32 .

[0132] like Fig.21 As shown, the cross-sectional area of ​​the first blind hole 51 is smaller than the surface of the first surface 322 of the second substrate layer 32 , that is, the first blind hole 51 is arranged on a partial region of the first surface 322 .

[0133] S205 , forming a first doped region 41 in the first blind hole 51 .

[0134] Single crystal silicon or polycrystalline silicon can be grown in the first blind hole 51, and gas can be introduced during the growth of single crystal silicon or polycrystalline silicon. Different types of doping can be achieved by introducing different types of gas. Different total amounts of gas introduced into the first blind hole 51 can achieve different concentrations of doping. Fig.21 In the embodiment, the doping type and / or doping concentration of the first doping region 41 is different from the doping type and / or doping concentration of the second substrate layer 32. Moreover, after forming the first doping region 41, the first doping region 41 may be ground so that the first doping region 41 is flush with the first surface 322.

[0135] S206 , bonding the second substrate layer 32 formed with the first doping region 41 to the first dielectric layer 33 .

[0136] like Fig.21 As shown, the first surface 322 of the second substrate layer 32 faces the first dielectric layer 33 . That is, the first doped region 41 faces the first substrate layer 31 .

[0137] S207 , grinding the second surface 323 of the second substrate layer 32 opposite to the first surface 322 to expose the first doping region 41 .

[0138] like Fig.21 As shown, the thickness of the first doped region 41 after grinding is the same as the thickness of the second substrate layer 32 .

[0139] Since the doping region is made by diffusion or ion implantation in the related art, the depth of the doping region is shallow, and the depth of the doping region is much smaller than the thickness of the substrate. In this embodiment, the thickness of the first doping region 41 is the same as the thickness of the second substrate layer 32. When the thickness of the second substrate layer 32 is greater than 5 μm, the depth of the first doping region 41 is also greater than 5 μm. Therefore, the doping depth of this embodiment is deeper. Moreover, since the first doping region 41 is formed by etching first and then growing or depositing, the manufacturing accuracy of the first doping region 41 is higher.

[0140] The present application also provides a method for manufacturing a substrate, which can be applied to Figure 7 The substrate 10 shown. Fig. 22 As shown, Fig. 20 The difference between the embodiments shown is that Fig. 20 Steps S263 and S264 are added on the basis of the illustrated embodiment.

[0141] like Fig. 22 As shown, the method for manufacturing the substrate 10 includes:

[0142] S221 , providing a first substrate layer 31 .

[0143] Reference Fig. 20 Step S201 is shown.

[0144] S222 , manufacturing a first dielectric layer 33 on the first substrate layer 31 .

[0145] Reference Fig. 20 Step S202 is shown.

[0146] S223 , etching a fourth blind hole 54 on the first dielectric layer 33 and the first substrate layer 31 .

[0147] like Fig.23 As shown, the depth of the fourth blind hole 54 is greater than the thickness of the first dielectric layer 33. That is, part of the fourth blind hole 54 is disposed on the first dielectric layer 33, and the rest of the fourth blind hole 54 is disposed on the first substrate layer 31.

[0148] like Fig.23 As shown, S224 , a fourth doped region 44 is formed in the fourth blind hole 54 .

[0149] Single crystal silicon or polycrystalline silicon may be grown in the fourth blind hole 54 , and gas may be introduced during the process of growing the single crystal silicon or polycrystalline silicon to form the fourth doping region 44 .

[0150] S225 , providing a second substrate layer 32 .

[0151] Reference Fig. 20 Step S203 shown.

[0152] S226 , etching a first blind hole 51 on the first surface 322 of the second substrate layer 32 .

[0153] Reference Fig. 20 Step S204 is shown.

[0154] S227 , forming a first doped region 41 in the first blind hole 51 .

[0155] Reference Fig. 20 Step S205 shown.

[0156] S228 , bonding the second substrate layer 32 formed with the first doping region 41 to the first dielectric layer 33 .

[0157] Reference Fig. 20 Step S206 is shown.

[0158] S229 , grinding the second surface 323 of the second substrate layer 32 opposite to the first surface 322 to expose the first doping region 41 .

[0159] Reference Fig. 20 Step S207 shown.

[0160] The present application also provides a method for manufacturing a substrate, which can be applied to Fig.17 The embodiment shown. Fig.24 As shown, the production method includes:

[0161] like Fig.25 As shown, S241, a first substrate layer 31 is provided.

[0162] S242 , manufacturing a first dielectric layer 33 on the first substrate layer 31 .

[0163] Reference Fig. 20 Step S201 in .

[0164] S243, providing a second substrate layer 32.

[0165] exist Fig.25 In the embodiment, the second substrate layer 32 may be a doped substrate. For example, the second substrate layer 32 is a P-type substrate or an N-type substrate.

[0166] S244 , etching a first blind hole 51 on the first surface 322 of the second substrate layer 32 .

[0167] like Fig.25As shown, the cross-sectional area of ​​the first blind hole 51 is smaller than the surface of the first surface 322 of the second substrate layer 32, that is, the first blind hole 51 is arranged on a partial area of ​​the first surface 322. The number of the first blind holes 51 can be multiple, and the number is an even number. The multiple first blind holes 51 are arranged along the X direction and are arranged at intervals. Exemplarily, in this embodiment, the number of the first blind holes 51 can be four.

[0168] S245 , forming a first doped region 41 in the first blind hole 51 .

[0169] exist Fig.25 In the embodiment, the number of the first doping regions 41 may be multiple and an even number. Exemplarily, in this embodiment, the number of the first doping regions 41 may be four. The multiple first doping regions 41 are arranged along the X direction and are arranged at intervals. The doping type and doping concentration of each first doping region 41 may be the same.

[0170] S246 , etching a second blind hole 52 on the first surface 322 of the second substrate layer 32 .

[0171] like Fig.25 As shown, the second blind hole 52 is connected to the first blind hole 51, and the depth of the second blind hole 52 is less than the depth of the first blind hole 51. The number of the second blind holes 52 may be less than the number of the first blind holes 51. For example, the number of the first blind holes 51 is twice the number of the second blind holes 52.

[0172] S247 , forming a second doped region 42 in the second blind hole 52 .

[0173] Single crystal silicon or polycrystalline silicon can be grown in the second blind hole 52, and gas can be introduced during the growth of single crystal silicon or polycrystalline silicon to form the second doping region 42. The second doping region 42 and the first doping region 41 have different doping types and / or doping concentrations.

[0174] It can be understood that, in this embodiment, Fig.23 As shown, when manufacturing the substrate 10, the first blind hole 51 is first etched and the first doped region 41 is manufactured, and then the second blind hole 52 is etched and the second doped region 42 is manufactured. In other embodiments, the second blind hole 52 may be first etched and the second doped region 42 may be manufactured, and then the first blind hole 51 may be etched and the first doped region 41 may be manufactured.

[0175] S248 , bonding the second substrate layer 32 formed with the first doping region 41 and the second doping region 42 to the first dielectric layer 33 .

[0176] like Fig.25 As shown, the first surface 322 of the second substrate layer 32 faces the first substrate layer 31 .

[0177] S249 , grinding the second surface 323 of the second substrate layer 32 opposite to the first surface 322 to expose the first doping region 41 .

[0178] like Fig.25 As shown, the thickness of the first doping region 41 after grinding is the same as the thickness of the second substrate layer 32 , and the thickness of the second doping region 42 is less than the thickness of the second substrate layer 32 .

[0179] S2410 , etching a third blind hole 53 on the second surface 323 of the second substrate layer 32 .

[0180] like Fig.23 As shown, the depth of the third blind hole 53 is less than the depth of the first doping region 41. The projection of the third blind hole 53 on the first surface 322 overlaps with the second doping region 42. The third blind hole 53 is also located between two adjacent first doping regions 41.

[0181] S2411 , forming a third doped region 43 in the third blind hole 53 .

[0182] Single crystal silicon or polycrystalline silicon can be grown in the third blind hole 53, and gas can be introduced during the process of growing single crystal silicon or polycrystalline silicon to form the third doped region 43. Fig.25 As shown, the projection of the third doping region 43 on the first surface 322 overlaps with the second doping region 42. The third doping region 43 and the second doping region 42 may be located between two adjacent first doping regions 41, the second doping region 42 contacts one of the first doping regions 41, and the third doping region 43 contacts the other first doping region 41.

[0183] For the overlapping area between the projection of the third doping region 43 on the first surface 322 and the second doping region 42, the third doping region 43 and the second doping region 42 are arranged at different thicknesses in the overlapping area. Therefore, this embodiment can achieve different doping at different heights in a certain area of ​​the second substrate layer 32, thereby forming a three-dimensional doping structure in the substrate 10.

[0184] It is understandable that Fig.15 The substrate 10 shown in FIG. 1 does not include the third doping region 43. Therefore, when manufacturing the substrate 10, the following steps are performed: Fig.24 Just follow the steps S241-S249 shown.

[0185] The present application also provides a method for manufacturing a substrate, which can be applied to Fig.18 The embodiment shown. Fig.26 As shown, the production method includes:

[0186] like Fig. 27 As shown, S261, a first substrate layer 31 is provided.

[0187] S262 , manufacturing a first dielectric layer 33 on the first substrate layer 31 .

[0188] like Fig. 27 As shown, the first dielectric layer 33 may be an oxide layer.

[0189] S263, provide a second substrate layer 32.

[0190] exist Fig. 27 In the embodiment, the second substrate layer 32 may be a doped substrate. For example, the second substrate layer 32 is a P-type substrate or an N-type substrate.

[0191] S264 , etching a first blind hole 51 on the first surface 322 of the second substrate layer 32 .

[0192] like Fig. 27 As shown, the first blind hole 51 includes a first sub-blind hole 511 and a second sub-blind hole 512 arranged along the Z direction. The first sub-blind hole 511 is closer to the first surface 322 than the second sub-blind hole 512. The size of the first sub-blind hole 511 along the X direction is greater than the size of the second sub-blind hole 512 along the X direction.

[0193] S265 , forming a second sub-doping region 412 and a third sub-doping region 413 in the first blind hole 51 .

[0194] like Fig. 27 As shown, a second sub-doping region 412 and a third sub-doping region 413 may be formed in the second sub-blind hole 512 of the first blind hole 51. The second sub-doping region 412 and the third sub-doping region 413 are arranged along the X direction and contact each other. Since the second sub-doping region 412 and the third sub-doping region 413 are located in the second sub-blind hole 512, the depths of the second sub-doping region 412 and the third sub-doping region 413 are both less than the depth of the first blind hole 51.

[0195] S266 , forming a first sub-doped region 411 in the first blind hole 51 .

[0196] like Fig. 27 As shown, a first sub-doping region 411 may be formed in a first sub-blind hole 511 in the first blind hole 51. The first sub-doping region 411 is stacked on the second sub-doping region 412 and the third sub-doping region 413. The first sub-doping region 411, the second sub-doping region 412, and the third sub-doping region 413 may form a three-dimensional doping structure. Therefore, the present application can achieve different doping at different depths in the same area on the surface of the substrate 10 to form a three-dimensional doping structure.

[0197] exist Fig. 27 In the embodiment, the first sub-doping region 411, the second sub-doping region 412 and the third sub-doping region 413 have different doping types and / or doping concentrations.

[0198] S267 , bonding the second substrate layer 32 formed with the first sub-doping region 411 , the second sub-doping region 412 and the third sub-doping region 413 to the first dielectric layer 33 .

[0199] like Fig. 27 As shown, the first surface 322 of the second substrate layer 32 faces the first substrate layer 31 . Then, the first sub-doping region 411 faces the first substrate layer 31 .

[0200] S268 , grinding the second surface 323 of the second substrate layer 32 opposite to the first surface 322 to expose the second sub-doping region 412 and the third sub-doping region 413 .

[0201] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A substrate, characterized in that: include: A first substrate layer and a second substrate layer and a first doping region stacked on the first substrate layer, a hollow region is formed on the second substrate layer, the first doping region is arranged in the hollow region, and the thickness of the first doping region is the same as the thickness of the second substrate layer.

2. The substrate according to claim 1, characterized in that The second substrate layer is a doped substrate, and the second substrate layer and the first doping region have different doping types and / or doping concentrations.

3. The substrate according to claim 1 or 2, characterized in that The second substrate layer comprises a plurality of sub-substrate layers which are spaced apart and arranged along a first direction, and the hollow area is formed between every two adjacent sub-substrate layers; the first direction is perpendicular to the thickness direction of the substrate; There are a plurality of first doped regions, and each of the hollow regions is provided with the first doped region.

4. The substrate according to any one of claims 1 to 3, characterized in that The substrate further includes a second doping region, which is disposed on the same side of the first substrate layer as the first doping region, and has a different doping concentration and / or doping type from the first doping region.

5. The substrate according to claim 4, characterized in that The second doping region is disposed in the hollow region, and the second doping region has the same thickness as the second substrate layer.

6. The substrate according to claim 5, characterized in that The second substrate layer includes a plurality of sub-substrate layers that are spaced apart and arranged along the first direction, the hollow region is formed between every two adjacent sub-substrate layers, and the first doped region and the second doped region are disposed in each of the hollow regions; The first doping region, the second doping region and the sub-substrate layer form a PIN structure.

7. The substrate according to claim 4, characterized in that A second blind hole is disposed on the first surface of the second substrate layer, and the second doped region is disposed in the second blind hole.

8. The substrate according to claim 7, characterized in that The first surface of the second substrate layer is a surface of the second substrate layer facing the first substrate layer; The substrate also includes a third doping region, which is arranged on a second surface of the second substrate layer away from the first substrate layer. The third doping region is different from the second doping region in doping type and / or doping concentration. The projection of the third doping region on the first surface overlaps with the second doping region, and the third doping region and the second doping region have a spacing in the thickness direction of the substrate.

9. The substrate according to claim 8, characterized in that The number of the first doping regions is at least two, at least two of the first doping regions are arranged at intervals along the first direction, the second doping region and the third doping region are located between two adjacent first doping regions, the second doping region is in contact with one of the two adjacent first doping regions, and the third doping region is in contact with the other of the two adjacent first doping regions.

10. The substrate according to claim 1 or 2, characterized in that The first doping region includes a first sub-doping region and a second sub-doping region, the first sub-doping region and the second sub-doping region are stacked along the thickness direction of the substrate, and the first sub-doping region and the second sub-doping region have different doping concentrations and / or doping types.

11. The substrate according to claim 10, characterized in that The size of the first sub-doping region along the first direction is greater than the size of the second sub-doping region along the first direction; The first doping region further includes a third sub-doping region, the third sub-doping region and the second sub-doping region are arranged along the first direction, and the first sub-doping region covers the second sub-doping region and the third sub-doping region.

12. The substrate according to any one of claims 1 to 11, characterized in that A third blind hole is provided on the surface of the first substrate layer facing the second substrate layer; the substrate further comprises a fourth doping region provided in the third blind hole, and the fourth doping region has a different doping type and / or doping concentration from the first doping region.

13. The substrate according to claim 12, characterized in that The first doping region contacts and overlaps with the fourth doping region.

14. The substrate according to any one of claims 1 to 13, characterized in that The substrate further includes a first dielectric layer located between the first substrate layer and the second substrate layer; a cavity is formed on the first dielectric layer, or a connected cavity is formed on the first dielectric layer and the first substrate layer, and the cavity overlaps with the first doping region.

15. A method for manufacturing a substrate, characterized in that: The production method comprises: providing a first substrate layer; providing a second substrate layer; Etching a first blind hole on the first surface of the second substrate layer; forming a first doped region in the first blind hole; Bonding the first substrate layer and the second substrate layer having the first doped region formed thereon, with the first surface facing the first substrate layer; A second surface of the second substrate layer opposite to the first surface is ground to expose the first doped region, wherein the thickness of the ground first doped region is the same as the thickness of the second substrate layer.

16. The manufacturing method according to claim 15, characterized in that: After the step of providing the second substrate layer, the manufacturing method further comprises: Etching a second blind hole on the first surface of the second substrate layer, wherein the second blind hole is connected to the first blind hole, and the depth of the second blind hole is less than the depth of the first blind hole; forming a second doped region in the second blind hole; After the step of grinding the second surface of the second substrate layer opposite to the first surface to expose the first doped region, the manufacturing method further includes: Etching a third blind hole on the second surface of the second substrate layer; A third doping region is formed in the third blind hole, and a projection of the third doping region on the first surface overlaps with the second doping region.

17. The manufacturing method according to claim 15, characterized in that: The step of forming the first doped region in the first blind hole comprises: forming a second sub-doping region and a third sub-doping region arranged along a first direction in the first blind hole, wherein the depths of the second sub-doping region and the third sub-doping region are both less than the depth of the first blind hole, and the first direction is perpendicular to the thickness direction of the substrate; A first sub-doping region is formed in the first blind hole, and the first sub-doping region is stacked on the second sub-doping region and the third sub-doping region.

18. The production method according to any one of claims 15 to 17, characterized in that: After the step of providing the first substrate layer, the manufacturing method further comprises: Etching a fourth blind hole on the first substrate layer; forming a fourth doped region in the fourth blind hole; The step of bonding the first substrate layer and the second substrate layer having the first doped region formed thereon comprises: The first substrate layer formed with the fourth doping region and the second substrate layer formed with the first doping region are bonded, and the fourth doping region is located on a surface of the first substrate layer facing the second substrate layer.

19. A semiconductor device, characterized in that: It comprises an electrode and the substrate according to any one of claims 1 to 14, wherein the electrode is arranged on the substrate.

20. A circuit module, characterized in that: The invention comprises a controller and the semiconductor device according to claim 19, wherein the controller is electrically connected to the semiconductor device.

21. An electronic device, characterized in that: It comprises a circuit board and the circuit module as claimed in claim 20, wherein the circuit module is electrically connected to the circuit board.

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