IGBT device and manufacturing method thereof

Abstract

The invention provides an IGBT device and a manufacturing method thereof. The IGBT device comprises an N-type semiconductor layer and a plurality of grooves located in the N-type semiconductor layer, the width of the upper portion of each groove is larger than that of the lower portion of each groove, shielding electrodes are located in the grooves, and gate electrodes are located on the two sides of the shielding electrodes and located on the upper portions of the grooves. The P-type body region is located between the adjacent grooves, and an N-type emitter region is arranged in the P-type body region; the N-type carrier storage layer is positioned below the P-type body region and is positioned between the adjacent grooves; and the P-type protection layer is positioned below the N-type carrier storage layer. The P-type protection layer is introduced below the N-type carrier storage layer, charge compensation can be performed on the N-type carrier storage layer, and local charge balance is formed, so that the electric field on the surface of the groove is reduced, and the withstand voltage of the IGBT device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor devices, and in particular to an IGBT device and a manufacturing method thereof. Background Art

[0002] Insulated Gate Bipolar Transistor (IGBT) is a composite fully controlled voltage-driven power semiconductor device composed of bipolar transistors and MOS (Metal-Oxide-Semiconductor) transistors. It has the advantages of low driving power and fast switching speed of MOS transistors, as well as low saturation voltage drop and large capacity of bipolar transistors. It is very suitable for use in converter systems with DC voltages of 600V and above, such as AC motors, inverters, switching power supplies, lighting circuits, traction drives, and other fields. Setting up a carrier storage layer can effectively improve the carrier concentration distribution in the drift region, so that the IGBT obtains a lower forward conduction voltage drop and improves the trade-off relationship between the forward voltage drop and the turn-off loss. However, the concentration window of the carrier storage layer is small, and the concentration increase caused by process fluctuations will cause the device's voltage resistance to decrease. Summary of the invention

[0003] In view of this, an object of the present invention is to provide an IGBT device and a method for manufacturing the same, which can improve the withstand voltage of the IGBT while increasing the doping concentration of the carrier storage layer.

[0004] The present invention provides an IGBT device, comprising:

[0005] An N-type semiconductor layer, and located in the N-type semiconductor layer:

[0006] A plurality of grooves, wherein the width of the upper portion of the groove is greater than the width of the lower portion;

[0007] a shielding electrode located in the trench, the shielding electrode being located in a lower portion of the trench and extending upwardly into an upper portion of the trench;

[0008] A gate electrode located in the upper portion of the trench, the gate electrode being located at both sides of the shielding electrode, the gate electrode, the shielding electrode and the N-type semiconductor layer being insulated and isolated from each other;

[0009] A P-type body region located between adjacent grooves, wherein an N-type emitter region is provided in the P-type body region;

[0010] An N-type carrier storage layer located below the P-type body region and between adjacent trenches;

[0011] A P-type protection layer is located below the N-type carrier storage layer, and the P-type protection layer surrounds the bottom of the gate electrode.

[0012] Furthermore, the P-type protection layer is located on both sides of the trench.

[0013] Furthermore, the P-type protection layer surrounds the sidewall and bottom of the lower portion of the trench.

[0014] Furthermore, at least one floating doping region is provided below the trench.

[0015] Furthermore, it also includes an N-type field stop region and a P-type collector region located at the bottom of the N-type semiconductor layer, and the N-type field stop region is located above the P-type collector region.

[0016] The present invention provides a method for manufacturing an IGBT device, comprising:

[0017] S1: forming a mask layer on the provided N-type semiconductor layer, and then forming a mask layer opening in the mask layer by photolithography and etching processes;

[0018] S2: performing anisotropic etching and isotropic etching on the N-type semiconductor layer to form a plurality of first trenches arranged in sequence in the N-type semiconductor layer, wherein the width of the first trench is greater than the width of the opening of the mask layer;

[0019] S3: performing inclined N-type ion implantation in the N-type semiconductor layer to form an N-type carrier storage layer located at the bottom of the first trench;

[0020] S4: performing P-type ion implantation in the N-type semiconductor layer to form a P-type protective layer located at the bottom of the first trench, wherein a lower surface of the P-type protective layer is lower than a lower surface of the N-type carrier storage layer;

[0021] S5: forming a gate dielectric layer on the surface of the first trench, then depositing a polysilicon layer and etching back to form a gate electrode in the first trench, wherein the gate electrode is located at a sidewall position of the first trench;

[0022] S6: etching the N-type semiconductor layer using the mask layer as a mask to form a second trench below the first trench, wherein the width of the second trench is smaller than the width of the first trench, and the first trench and the second trench form a trench;

[0023] S7: forming an insulating dielectric layer on the surface of the second trench and the exposed surface of the gate electrode, and then depositing a polysilicon layer and etching back to form a shielding electrode in the first trench and the second trench;

[0024] S8: removing the mask layer, and then performing P-type ion implantation to form a P-type body region in the N-type semiconductor layer, wherein the P-type body region is located between adjacent first trenches;

[0025] S9: performing N-type ion implantation to form an N-type emitter region in the P-type body region;

[0026] S10: performing high temperature annealing to diffuse the N-type carrier storage layer and the P-type protection layer to predetermined positions, wherein the N-type carrier storage layer is located below the P-type body region, and the P-type protection layer is located below the N-type carrier storage layer and surrounds the bottom of the gate electrode.

[0027] Further, the S6 includes:

[0028] S61: etching the N-type semiconductor layer using the mask layer as a mask to form a second trench below the first trench, wherein the width of the second trench is smaller than the width of the first trench, and the first trench and the second trench form a trench;

[0029] S62: performing inclined P-type ion implantation, so that the formed P-type protection layer surrounds the sidewall and bottom of the second trench.

[0030] Further, the S62 includes:

[0031] S621: performing inclined P-type ion implantation so that the formed P-type protection layer surrounds the sidewall and bottom of the second trench;

[0032] S622: Perform vertical P-type ion implantation to form at least one floating doping region below the second trench.

[0033] The IGBT device provided by the present invention introduces a P-type protective layer under the N-type carrier storage layer, which can compensate the charge of the N-type carrier storage layer to form a local charge balance, thereby reducing the electric field on the groove surface and improving the withstand voltage of the IGBT device. The introduction of the P-type protective layer also reduces the conduction width of the carriers in the on-state and improves the short-circuit current capability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the following is a brief introduction to the drawings required for describing the embodiments. It should be noted that in the drawings, for the convenience of explanation, the thickness of the layers and regions are exaggerated, and the sizes shown do not represent the actual sizes. The drawings are schematic diagrams of idealized embodiments of the present invention, and the embodiments shown in the present invention should not be considered to be limited to the specific shapes of the regions shown in the drawings, but include the resulting shapes, such as deviations caused by manufacturing.

[0035] Figure 1 It is a schematic cross-sectional structure diagram of a first embodiment of an IGBT device provided by the present invention;

[0036] Figure 2 is a schematic cross-sectional structural diagram of a second embodiment of an IGBT device provided by the present invention;

[0037] Figures 3 to 11 It is a schematic cross-sectional structure diagram of main process nodes of an embodiment of a method for manufacturing an IGBT device of the present invention. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0039] Figure 1 FIG. 1 is a schematic cross-sectional view of a first embodiment of an IGBT device provided by the present invention. Figure 1 As shown, an IGBT device of the present invention comprises: an N-type semiconductor layer 101, and a plurality of trenches 102 located in the N-type semiconductor layer, wherein the width of the upper portion of the trench 102 is greater than the width of the lower portion thereof, and only two trenches 102 are exemplarily shown in the embodiment of the present invention. A shielding electrode 103 and gate electrodes 104a and 104b are provided in the trench 102, wherein the shielding electrode 103 is located in the lower portion of the trench 102 and extends upward to the upper portion of the trench 102, and the gate electrodes 104a and 104b are located in the upper portion of the trench 102 and located on both sides of the shielding electrode 103, and the gate electrodes 104a and 104b are insulated and isolated from the N-type semiconductor layer 101 by a gate dielectric layer 105, and the shielding electrode 103 is insulated and isolated from the N-type semiconductor layer 101 and the gate electrodes 104a and 104b by an insulating dielectric layer 106. The material of the N-type semiconductor layer 101 is generally silicon, and the materials of the gate electrodes 104 a , 104 b and the shielding electrode 103 may be polysilicon or metal.

[0040] A P-type body region 107 is disposed between adjacent trenches 102 , and an N-type emitter region 108 is disposed within the P-type body region 107 .

[0041] The N-type carrier storage layer 109 is located below the P-type body region 107 and between adjacent trenches 102. A P-type protective layer 110 is provided below the N-type carrier storage layer 109. The P-type protective layer 110 is located on both sides of the trench 102 and surrounds the bottom of the gate electrode 104a and the gate electrode 104b. The P-type protective layer 110 and the N-type carrier storage layer 109 can form a local charge balance, which can effectively improve the withstand voltage of the IGBT device.

[0042] The IGBT device of the present invention further includes an N-type field stop region 111 and a P-type collector region 112 located at the bottom of the N-type semiconductor layer 101 . The N-type field stop region 111 is located above the P-type collector region 112 .

[0043] Figure 2 is a schematic cross-sectional structure diagram of a second embodiment of an IGBT device provided by the present invention, such as Figure 2 As shown, the P-type protection layer 113 of the IGBT device of the present invention surrounds the bottom of the gate electrode 104a and the gate electrode 104b and surrounds the sidewall and bottom of the lower part of the trench 102; at least one floating doping region 114 is also provided below the trench 102. The floating doping region 114 can absorb the electric lines of force in the drift region below, reduce the electric field at the bottom of the trench 102, and further improve the withstand voltage of the IGBT device. It should be noted that Figure 2 Taking the case where multiple floating doping regions 114 are disposed under the trench 102 as an example, when multiple floating doping regions 114 are disposed under the trench 102 , the multiple floating doping regions 114 are disposed vertically, that is, the multiple floating doping regions 114 are arranged in sequence along the depth direction of the trench 102 .

[0044] Figures 3 to 10 FIG. 1 is a schematic cross-sectional structure diagram of the main process nodes of an embodiment of the method for manufacturing an IGBT device of the present invention. Figures 3 to 10 As shown, the manufacturing method of the IGBT device of the present invention comprises:

[0045] First, if Figure 3 As shown, a mask layer 202 is formed on the provided N-type semiconductor layer 201 , and then the position of the mask layer opening is defined by photolithography, and then the mask layer 202 is etched to form a mask opening 214 in the mask layer 202 .

[0046] Next, if Figure 4 As shown, the N-type semiconductor layer 201 is etched using the mask layer 202 as a mask to form a plurality of first trenches 203 arranged in sequence, and then isotropic etching is performed to increase the width of the formed trenches, so that the width of the formed first trenches 203 is greater than the width of the mask layer opening 214.

[0047] Next, if Figure 5As shown, an inclined N-type ion implantation is performed to form an N-type carrier storage layer 204 located at the bottom of the first trench 203 in the N-type semiconductor layer 201, and the N-type carrier storage layer 204 surrounds the bottom of the first trench 203; next, a P-type ion implantation is performed to form a P-type protective layer 205 located at the bottom of the first trench 203 in the N-type semiconductor layer 201, and the lower surface of the P-type protective layer 205 is lower than the lower surface of the N-type carrier storage layer 204.

[0048] Next, if Figure 6 As shown, a gate dielectric layer 206 is formed on the surface of the first trench 203 , and then a polysilicon layer is deposited and etched back to form a gate electrode 207 a and a gate electrode 207 b in the first trench 203 . The gate electrodes 207 a and 207 b are located at the sidewalls of the first trench 203 .

[0049] Next, if Figure 7 As shown, the N-type semiconductor layer 201 is etched using the mask layer 202 as a mask to form a second trench below the first trench 203. The width of the formed second trench is smaller than the width of the first trench 203. The first trench 203 and the formed second trench form a trench 215. The first trench 203 is the upper part of the trench 215, and the formed second trench is the lower part of the trench 215.

[0050] In a preferred embodiment, after forming the second trench, an inclined P-type ion implantation may be performed so that the formed P-type protection layer 212 surrounds the sidewalls and the bottom of the formed second trench; and then a vertical P-type ion implantation may be performed to form at least one floating doping region 213 below the formed second trench. Figure 8 It should be noted that Figure 8 The following description is only given by taking the case where the P-type protection layer 212 surrounds the sidewall and bottom of the formed second trench, and at least one floating doping region 213 is disposed below the second trench. Figure 7 As shown, when the P-type protection layer 205 is formed at the bottom of the first trench 203, at least one floating doping region (not shown in the figure) can also be provided below the second trench by vertical P-type ion implantation. In other words, the provision of the floating doping region is independent of the specific provision method of the P-type protection layer 205. By providing the floating doping region, it is ensured that the electric lines of the drift region below can be absorbed, the electric field at the bottom of the trench can be reduced, and the withstand voltage of the IGBT device can be improved.

[0051] Next, Figure 7 The structure shown in the figure continues to describe the manufacturing method of the IGBT device of the present invention, as shown in the figure. Fig. 9As shown, an insulating dielectric layer 208 is formed covering the exposed surfaces of the gate electrode 207a, the gate electrode 207b and the surface of the second trench, and then a polysilicon layer is deposited and etched back to form a shielding electrode 209 in the trench 215. The shielding electrode 209 is located in the second trench and extends upward into the first trench. The shielding electrode 209 is insulated and isolated from the gate electrode 207a, the gate electrode 207b and the N-type semiconductor layer 201 by the insulating dielectric layer 208. Then, the mask layer 202 is removed.

[0052] Next, if Fig.10 As shown, P-type ion implantation is performed to form a P-type body region 210 in the N-type semiconductor layer 201, and the P-type body region 210 is located between adjacent trenches 215; then N-type ion implantation is performed to form an N-type emitter region 211 in the P-type body region 210. Finally, high-temperature annealing is performed to diffuse the N-type carrier storage layer 204 and the P-type protective layer 205 to a predetermined position, the N-type carrier storage layer 204 is located below the P-type body region 210, and the P-type protective layer 205 is located on both sides of the trench 215 and below the N-type carrier storage layer 204 and surrounds the bottom of the gate electrode 207a and the gate electrode 207b.

[0053] based on Figure 8 The structure shown can form an IGBT device in a preferred embodiment, such as Fig.11 As shown, the N-type carrier storage layer 204 is located below the P-type body region 210 , the P-type protective layer 205 surrounds part of the sidewalls and the bottom of the trench 215 and surrounds the bottom of the gate electrode 207 a and the gate electrode 207 b , and at least one floating doped region 213 is located below the trench 215 .

[0054] Finally, a conventional process is used to form an N-type field stop region and a P-type collector region, and to form a passivation layer and a metal electrode layer. This process is a conventional process in the industry and will not be specifically demonstrated in the embodiments of the present invention.

[0055] The invention provides a method for manufacturing an IGBT device, wherein ion implantation of an N-type carrier storage layer, a P-type protection layer and a floating doping region at the bottom of a groove is performed in a self-aligned manner, and the process consistency is good, which can further improve the manufacturing yield of the IGBT device.

[0056] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and the implementation modes, and they can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.

Claims

1. An IGBT device, characterized in that: include: An N-type semiconductor layer, and located in the N-type semiconductor layer: A plurality of grooves, wherein the width of the upper portion of the groove is greater than the width of the lower portion; a shielding electrode located in the trench, the shielding electrode being located in a lower portion of the trench and extending upwardly into an upper portion of the trench; A gate electrode located in the upper portion of the trench, the gate electrode being located at both sides of the shielding electrode, the gate electrode, the shielding electrode and the N-type semiconductor layer being insulated and isolated from each other; A P-type body region located between adjacent grooves, wherein an N-type emitter region is provided in the P-type body region; An N-type carrier storage layer located below the P-type body region and between adjacent trenches; A P-type protection layer is located below the N-type carrier storage layer, and the P-type protection layer surrounds the bottom of the gate electrode.

2. An IGBT device as claimed in claim 1, characterized in that: The P-type protection layer is located on both sides of the trench.

3. An IGBT device according to claim 1, characterized in that: The P-type protection layer surrounds the sidewall and the bottom of the lower portion of the trench.

4. An IGBT device according to claim 1, characterized in that: At least one floating doping region is disposed below the trench.

5. An IGBT device according to claim 1, characterized in that: It also includes an N-type field stop region and a P-type collector region located at the bottom of the N-type semiconductor layer, and the N-type field stop region is located above the P-type collector region.

6. A method for manufacturing an IGBT device, characterized in that: include: S1: forming a mask layer on the provided N-type semiconductor layer, and then forming a mask layer opening in the mask layer by photolithography and etching processes; S2: performing anisotropic etching and isotropic etching on the N-type semiconductor layer to form a plurality of first trenches arranged in sequence in the N-type semiconductor layer, wherein the width of the first trench is greater than the width of the opening of the mask layer; S3: performing inclined N-type ion implantation in the N-type semiconductor layer to form an N-type carrier storage layer located at the bottom of the first trench; S4: performing P-type ion implantation in the N-type semiconductor layer to form a P-type protective layer located at the bottom of the first trench, wherein a lower surface of the P-type protective layer is lower than a lower surface of the N-type carrier storage layer; S5: forming a gate dielectric layer on the surface of the first trench, then depositing a polysilicon layer and etching back to form a gate electrode in the first trench, wherein the gate electrode is located at a sidewall position of the first trench; S6: etching the N-type semiconductor layer using the mask layer as a mask to form a second trench below the first trench, wherein the width of the second trench is smaller than the width of the first trench, and the first trench and the second trench form a trench; S7: forming an insulating dielectric layer on the surface of the second trench and the exposed surface of the gate electrode, and then depositing a polysilicon layer and etching back to form a shielding electrode in the first trench and the second trench; S8: removing the mask layer, and then performing P-type ion implantation to form a P-type body region in the N-type semiconductor layer, wherein the P-type body region is located between adjacent first trenches; S9: performing N-type ion implantation to form an N-type emitter region in the P-type body region; S10: performing high temperature annealing to diffuse the N-type carrier storage layer and the P-type protection layer to predetermined positions, wherein the N-type carrier storage layer is located below the P-type body region, and the P-type protection layer is located below the N-type carrier storage layer and surrounds the bottom of the gate electrode.

7. The method for manufacturing an IGBT device according to claim 6, characterized in that: The S6 includes: S61: etching the N-type semiconductor layer using the mask layer as a mask to form a second trench below the first trench, wherein the width of the second trench is smaller than the width of the first trench, and the first trench and the second trench form a trench; S62: performing inclined P-type ion implantation, so that the formed P-type protection layer surrounds the sidewall and bottom of the second trench.

8. The method for manufacturing an IGBT device according to claim 7, characterized in that: The S62 includes: S621: performing inclined P-type ion implantation so that the formed P-type protection layer surrounds the sidewall and bottom of the second trench; S622: Perform vertical P-type ion implantation to form at least one floating doping region below the second trench.

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