Diamond and gallium nitride heterogeneous integrated complementary field effect transistor device

Abstract

The invention relates to the technical field of semiconductor devices, in particular to a diamond and gallium nitride heterogeneous integrated complementary field effect transistor device. The device comprises an n-type GaN-based transistor unit (001), a p-type diamond-based transistor unit (002), an electrode connecting unit (003) and a diamond substrate (1), and the n-type GaN-based transistor unit (001) and the p-type diamond-based transistor unit (002) are both arranged on the diamond substrate (1). The first electrode connection metal (15a) is connected to the n-type GaN transistor gate electrode (8) and the p-type diamond transistor gate electrode (13), respectively, and the second electrode connection metal (15b) is connected to the n-type GaN transistor drain electrode (9) and the p-type diamond transistor source electrode (12), respectively. The complementary field effect transistor has the advantages of being wide in forbidden band width and low in inter-band tunneling probability, and the formed complementary field effect transistor has the advantages of being high in switching speed and low in power consumption.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular, to a complementary field effect transistor device heterogeneously integrated with diamond and gallium nitride. Background Art

[0002] As semiconductor chips continue to develop in the direction of multifunctionality, existing silicon-based CMOS (Complementary Metal Oxide Semiconductor) devices are difficult to meet the design requirements of high-frequency and high-power chips. Existing high-electron mobility transistors, namely GaN HEMTs, are usually made of gallium nitride materials, which can operate at high frequencies and high powers to achieve high-performance n-channel transistors; but the main disadvantage of such existing transistor devices is that they hinder their ability to replace silicon in many applications. At the same performance level, it is difficult to realize p-type GaN transistors, and they cannot form a collaborative working type similar to silicon-based CMOS by themselves, so the design of logic circuit functions is limited. Summary of the invention

[0003] The present application provides a diamond and gallium nitride heterogeneously integrated complementary field effect transistor device, which can be heterogeneously integrated by diamond material and gallium nitride, wherein gallium nitride is used to form an n-channel transistor, and diamond is used to form a p-type channel transistor, which forms a complementary field effect between each other, and can form a collaborative working logic similar to silicon-based CMOS, further solving the problem of limited design functions of logic circuits. The material structure of heterogeneously integrated diamond material and gallium nitride is compatible with gallium nitride radio frequency devices, which can provide a material structure basis for realizing a multifunctional gallium nitride radio frequency chip for monolithic integrated analog drive, power management and digital processing; the n-type transistor uses a gallium nitride-based structure, with a high two-dimensional electron gas concentration, high mobility, and low resistance, and the gallium nitride-based channel material has a wide bandgap width, a low probability of inter-band tunneling, a high on-state current, and a small off-state leakage; the p-type transistor uses a diamond-based semiconductor structure, with a high two-dimensional hole gas concentration, high mobility, and a high device on-state current, and the combined complementary field effect transistor device has the characteristics of fast switching speed and low power consumption.

[0004] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0005] According to one aspect of an embodiment of the present application, a diamond and gallium nitride heterogeneously integrated complementary field effect transistor device is provided, comprising: an n-type GaN-based transistor unit (001), a p-type diamond-based transistor unit (002), an electrode connection unit (003) and a diamond substrate (1), wherein the n-type GaN-based transistor unit (001) and the p-type diamond-based transistor unit (002) are both arranged on the diamond substrate (1), the n-type GaN-based transistor unit (001) comprises an n-type GaN transistor gate electrode (8) and an n-type GaN transistor drain electrode (9); the p-type diamond-based transistor unit (002) comprises a p-type diamond transistor source electrode (12) and p-type diamond transistor gate electrode (13); the electrode connection unit (003) comprises a first electrode connection metal (15a) and a second electrode connection metal (15b) which are spatially staggered, the first electrode connection metal (15a) being used to connect to an interface of an input signal, and the second electrode connection metal (15b) being used to connect to an interface of an output signal; the first electrode connection metal (15a) being respectively connected to the n-type GaN transistor gate electrode (8) and the p-type diamond transistor gate electrode (13), and the second electrode connection metal (15b) being respectively connected to the n-type GaN transistor drain electrode (9) and the p-type diamond transistor source electrode (12).

[0006] In one embodiment of the present application, based on the above-mentioned solution, the n-type GaN transistor unit (001) and the p-type diamond transistor unit (002) are arranged on the upper surface of the diamond substrate (1) at intervals, and the interval distance between the n-type GaN transistor unit (001) and the p-type diamond transistor unit (002) is not less than a preset distance threshold.

[0007] In one embodiment of the present application, based on the above-mentioned solution, the n-type GaN-based transistor unit (001) further comprises an n-type GaN transistor transition layer (2), an n-type GaN transistor buffer layer (3), an n-type GaN transistor channel layer (4), and an n-type GaN transistor barrier layer (5); the n-type GaN transistor transition layer (2), the n-type GaN transistor buffer layer (3), the n-type GaN transistor channel layer (4), and the n-type GaN transistor barrier layer (5) are arranged in sequence from bottom to top, and the n-type GaN transistor transition layer (2) is arranged on the diamond substrate (1).

[0008] In one embodiment of the present application, based on the above scheme, the n-type GaN-based transistor unit (001) further includes a first SiN passivation layer (6a), a second SiN passivation layer (6b) and an n-type GaN transistor source electrode (7), wherein the n-type GaN transistor source electrode (7), the first SiN passivation layer (6a), the n-type GaN transistor gate electrode (8), the second SiN passivation layer (6b) and the n-type GaN transistor drain electrode (9) are sequentially arranged from left to right above the surface of the n-type GaN transistor barrier layer (5), and the n-type GaN The transistor source electrode (7) and the n-type GaN transistor drain electrode (9) are respectively arranged at two ends of the n-type GaN transistor barrier layer (5); the n-type GaN transistor source electrode (7) and the n-type GaN transistor gate electrode (8) are connected via the first SiN passivation layer (6a), and the n-type GaN transistor gate electrode (8) and the n-type GaN transistor drain electrode (9) are connected via the second SiN passivation layer (6b), and the length ratio of the first SiN passivation layer (6a) to the second SiN passivation layer (6b) is in the range of 1.5-2.

[0009] In one embodiment of the present application, based on the above scheme, the n-type GaN transistor channel layer (4) and the n-type GaN transistor barrier layer (5) are both group III nitrides, and the group III nitrides are one or more of gallium nitride, aluminum nitride and indium nitride; a two-dimensional electron gas is formed between the n-type GaN transistor channel layer (4) and the n-type GaN transistor barrier layer (5) to form a conductive channel of the n-type GaN-based transistor unit (001).

[0010] In one embodiment of the present application, based on the above scheme, the material of the n-type GaN transistor transition layer (2) is aluminum nitride, the thickness of the n-type GaN transistor transition layer is 50nm-300nm, and the n-type GaN transistor transition layer (2) is used to release the lattice mismatch stress and thermal stress between the n-type GaN transistor buffer layer (3) and the diamond substrate (1); the material of the n-type GaN transistor buffer layer (3) is undoped gallium nitride or aluminum gallium nitride, with a thickness of 200nm-5μm; the material of the n-type GaN transistor channel layer (4) is a ternary compound semiconductor formed by gallium nitride, indium nitride and gallium nitride or aluminum gallium nitride, with a thickness of 50nm-500nm; the material of the n-type GaN transistor barrier layer (5) is a ternary compound semiconductor formed by aluminum gallium nitride, indium nitride and gallium nitride or aluminum nitride, with a thickness of 5nm to 50nm.

[0011] In one embodiment of the present application, based on the above scheme, the n-type GaN transistor source electrode (7) and the n-type GaN transistor drain electrode (9) are both stacked structures of titanium, aluminum, nickel and gold stacked from bottom to top; the n-type GaN transistor gate electrode (8) is a stacked structure of nickel and gold stacked from bottom to top; the electrode connection metal (003) material is one or more of titanium, aluminum, nickel, gold, copper, titanium nitride, and tantalum.

[0012] In one embodiment of the present application, based on the above scheme, the p-type diamond-based transistor unit (002) further comprises a p-type diamond layer (10), a p-type diamond transistor gate dielectric layer (11) and a p-type diamond transistor drain electrode (14); the p-type diamond layer (10) is arranged on the diamond substrate (1); the p-type diamond transistor source electrode (12), the p-type diamond transistor gate dielectric layer (11) and the p-type diamond transistor drain electrode (14) are arranged on the upper surface of the p-type diamond layer (10) in sequence from left to right; the p-type diamond transistor source electrode (12) and the p-type diamond transistor drain electrode (14) are respectively arranged at two ends of the p-type diamond layer (10) and are respectively connected to the two side surfaces of the p-type diamond transistor gate dielectric layer (11); wherein the upper surface of the p-type diamond layer (10) is composed of hydrogen-terminated diamond to form a two-dimensional hole gas to form a conductive channel of the p-type diamond transistor unit (002).

[0013] In one embodiment of the present application, based on the above scheme, the p-type diamond-based transistor unit (002) further includes a third SiN passivation layer (6c) and a fourth SiN passivation layer (6d), and the third SiN passivation layer (6c), the p-type diamond transistor gate electrode (13) and the fourth SiN passivation layer (6d) are sequentially arranged on the upper surface of the p-type diamond transistor gate dielectric layer (11) from left to right; the p-type diamond transistor source electrode (12) and the p-type diamond transistor gate electrode (13) are connected via the third SiN passivation layer (6c), the p-type diamond transistor gate electrode (13) and the p-type diamond transistor drain electrode (14) are connected via the fourth SiN passivation layer (6d), and the length ratio of the third SiN passivation layer (6c) to the fourth SiN passivation layer (6d) is in the range of 1.5-2.

[0014] In one embodiment of the present application, based on the above scheme, the material of the p-type diamond transistor gate dielectric layer (11) is one of aluminum oxide, molybdenum trioxide, tungsten trioxide, vanadium pentoxide, hafnium dioxide, zirconium dioxide, and boron nitride, and the thickness of the p-type diamond transistor gate dielectric layer (11) is 1nm-30nm; the materials of the p-type diamond transistor source electrode (12) and the p-type diamond transistor drain electrode (14) are both one or more of nickel, aluminum, gold, and titanium; the material of the p-type diamond transistor gate electrode (13) is one or more of titanium, aluminum, titanium nitride, tantalum, and tantalum nitride.

[0015] The beneficial effects of the present application are as follows: heterogeneous integration of diamond material and gallium nitride is performed, wherein n-channel transistors are formed by gallium nitride and p-channel transistors are formed by diamond, and they are connected to each other through electrode connection units to form complementary field effect transistor devices. The material structure of heterogeneous integration of diamond material and gallium nitride is compatible with gallium nitride RF devices, and can provide a material structure foundation for realizing a multifunctional gallium nitride RF chip with monolithic integrated analog drive, power management and digital processing.

[0016] Furthermore, by arranging both the n-type GaN-based transistor unit (001) and the p-type diamond-based transistor unit (002) on the diamond substrate (1), a monolithically integrated gallium nitride and diamond complementary inverter can be realized, forming the smallest unit of a digital integrated circuit, and providing structural design support for the manufacture of large-scale diamond substrates, gallium nitride and diamond heterogeneously integrated digital integrated circuits and analog integrated circuit logic circuits.

[0017] Furthermore, the n-type transistor adopts a gallium nitride-based structure, which has a high two-dimensional electron gas concentration, high mobility, and low square resistance. The gallium nitride-based channel material has a wide bandgap width, a low probability of inter-band tunneling, a high on-state current, and a low off-state leakage at a small size. The p-type transistor adopts a diamond-based semiconductor structure, which has a high two-dimensional hole gas concentration, high mobility, and a high device on-state current. The combined complementary field effect transistor device has the characteristics of fast switching speed and low power consumption.

[0018] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0020] Figure 1 The overall structure diagram of the diamond and gallium nitride heterogeneously integrated complementary field effect transistor device according to Example 1 of the present application;

[0021] Figure 2 A top view of a diamond and gallium nitride heterogeneously integrated complementary field effect transistor device according to Example 1 of the present application;

[0022] Figure 3 The overall structure diagram of a diamond and gallium nitride heterogeneously integrated complementary field effect transistor device according to Example 2 of the present application;

[0023] Figure 4 It is a top view of a diamond and gallium nitride heterogeneously integrated complementary field effect transistor device according to Example 2 of the present application. DETAILED DESCRIPTION

[0024] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0025] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0026] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or micro-control node devices.

[0027] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0028] It should be noted that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0029] The implementation details of the technical solution of the embodiment of the present application are described in detail below:

[0030] Example 1

[0031] According to one aspect of the present application, embodiment 1 of the present application provides a diamond and gallium nitride heterogeneously integrated complementary field effect transistor device, which can be referred to as Figure 1 and Figure 2 As shown, the structure and principle of the complementary field effect transistor device of heterogeneous integration of diamond and gallium nitride are introduced in detail as follows:

[0032] A diamond and gallium nitride heterogeneously integrated complementary field effect transistor device comprises: an n-type GaN-based transistor unit (001), a p-type diamond-based transistor unit (002), an electrode connection unit (003) and a diamond substrate (1); the n-type GaN-based transistor unit (001) and the p-type diamond-based transistor unit (002) are both arranged on the diamond substrate (1); the n-type GaN-based transistor unit (001) comprises an n-type GaN transistor gate electrode (8) and an n-type GaN transistor drain electrode (9); the p-type diamond-based transistor unit (002) comprises a p-type diamond transistor source electrode (12) and a p-type diamond transistor gate electrode (13); and the p-type diamond-based transistor unit (003) comprises a p-type diamond transistor source electrode (14) and a p-type diamond transistor gate electrode (15). Electrode (13); the electrode connection unit (003) comprises a first electrode connection metal (15a) and a second electrode connection metal (15b) which are spatially staggered, the first electrode connection metal (15a) being used to connect to an interface of an input signal, and the second electrode connection metal (15b) being used to connect to an interface of an output signal; the first electrode connection metal (15a) being respectively connected to the n-type GaN transistor gate electrode (8) and the p-type diamond transistor gate electrode (13), and the second electrode connection metal (15b) being respectively connected to the n-type GaN transistor drain electrode (9) and the p-type diamond transistor source electrode (12).

[0033] Specifically, Figure 1As shown, the first electrode connection metal (15a) is respectively connected to the n-type GaN transistor gate electrode (8) and the p-type diamond transistor gate electrode (13), and the second electrode connection metal (15b) is respectively connected to the n-type GaN transistor drain electrode (9) and the p-type diamond transistor source electrode (12). The first electrode connection metal (15a) is used to connect the gates in the n-type GaN-based transistor unit (001) and the p-type diamond-based transistor unit (002), and the second electrode connection metal (15b) is used to connect the drain electrode (9) in the n-type GaN-based transistor unit (001) and the p-type diamond transistor source electrode (12) in the p-type diamond-based transistor unit (002). The first electrode connection metal (15a) is connected to the input signal IN, and the second electrode connection metal (15b) is connected to the output signal OUT, thereby completing the conduction and transmission of electrical signals of the entire semiconductor device.

[0034] Furthermore, diamond material and gallium nitride are heterogeneously integrated, wherein n-channel transistors are formed using gallium nitride and p-channel transistors are formed using diamond, and they are connected to each other through electrode connection units to form complementary field effect transistor devices. The material structure of heterogeneous integration of diamond material and gallium nitride is compatible with gallium nitride RF devices, and can provide a material structure foundation for realizing a multifunctional gallium nitride RF chip with monolithic integrated analog drive, power management and digital processing.

[0035] Furthermore, by arranging both the n-type GaN-based transistor unit (001) and the p-type diamond-based transistor unit (002) on the diamond substrate (1), a monolithically integrated gallium nitride and diamond complementary inverter can be realized, forming the smallest unit of a digital integrated circuit, and providing structural design support for the manufacture of large-scale diamond substrates, gallium nitride and diamond heterogeneously integrated digital integrated circuits and analog integrated circuit logic circuits.

[0036] Furthermore, the n-type transistor adopts a gallium nitride-based structure, which has a high two-dimensional electron gas concentration, high mobility, and low square resistance. The gallium nitride-based channel material has a wide bandgap width, a low probability of inter-band tunneling, a high on-state current, and a low off-state leakage at a small size. The p-type transistor adopts a diamond-based semiconductor structure, which has a high two-dimensional hole gas concentration, high mobility, and a high device on-state current. The combined complementary field effect transistor device has the characteristics of fast switching speed and low power consumption.

[0037] In one embodiment of the present application, the n-type GaN transistor unit (001) and the p-type diamond transistor unit (002) are arranged on the upper surface of the diamond substrate (1) at intervals, and the interval distance between the n-type GaN transistor unit (001) and the p-type diamond transistor unit (002) is not less than a preset distance threshold.

[0038] Specifically, the preset distance threshold can be specifically the minimum process size of the electrode connection unit (003), that is, the n-type GaN transistor unit (001) and the p-type diamond transistor unit (002) are not connected, and a certain interval is retained, and the interval distance is not less than the preset distance threshold. The isolation between the n-type GaN transistor unit (001) and the p-type diamond transistor unit (002) can be dielectric isolation, or groove isolation, or ion implantation isolation. The first electrode connection metal (15a) and the second electrode connection metal (15b) of the electrode connection unit (003) form an air bridge-like vertical staggered position in space, which can be specifically as follows: Figure 1 and Figure 2 shown.

[0039] In one embodiment of the present application, the n-type GaN-based transistor unit (001) further comprises an n-type GaN transistor transition layer (2), an n-type GaN transistor buffer layer (3), an n-type GaN transistor channel layer (4), and an n-type GaN transistor barrier layer (5); the n-type GaN transistor transition layer (2), the n-type GaN transistor buffer layer (3), the n-type GaN transistor channel layer (4), and the n-type GaN transistor barrier layer (5) are arranged in sequence from bottom to top, and the n-type GaN transistor transition layer (2) is arranged on the diamond substrate (1).

[0040] Specifically, the n-type GaN transistor transition layer (2) is located on a diamond substrate (1); since the diamond substrate (1) as a dielectric substrate has a lattice mismatch problem with the n-type GaN transistor buffer layer (3), a transition layer (AlGaN or AlN) of a certain thickness needs to be introduced to reduce the interface tension caused by the lattice mismatch. The n-type GaN transistor transition layer (2) can reduce the current collapse caused by interface mismatch, defects or trap effects, reduce static current leakage and radio frequency conduction, and improve radio frequency performance.

[0041] The n-type GaN transistor buffer layer (3) is located on the n-type GaN transistor transition layer (2); a certain amount of doping is introduced into the n-type GaN transistor buffer layer (3) to achieve the functions of high resistance and low leakage, and its thickness is usually at the micrometer level, which is used to reduce the background carrier concentration to reduce the drain current collapse caused by the trap effect of the buffer layer.

[0042] The n-type GaN transistor channel layer (4) is located on the n-type GaN transistor buffer layer (3); the n-type GaN transistor channel layer (4) is unintentionally doped, a two-dimensional electron gas channel is formed on the upper surface of the n-type GaN transistor channel layer (4), and is isolated from the n-type GaN transistor buffer layer (3) into which certain doping impurities are intentionally introduced.

[0043] In one embodiment of the present application, the n-type GaN transistor channel layer (4) and the n-type GaN transistor barrier layer (5) are both group III nitrides, and the group III nitrides are one or more of gallium nitride, aluminum nitride and indium nitride; a two-dimensional electron gas is formed between the n-type GaN transistor channel layer (4) and the n-type GaN transistor barrier layer (5) to form a conductive channel of the n-type GaN-based transistor unit (001).

[0044] The material of the n-type GaN transistor transition layer (2) is aluminum nitride, the thickness of the n-type GaN transistor transition layer is 50nm-300nm, and the n-type GaN transistor transition layer (2) is used to release the lattice mismatch stress and thermal stress between the n-type GaN transistor buffer layer (3) and the diamond substrate (1); the material of the n-type GaN transistor buffer layer (3) is undoped gallium nitride or aluminum gallium nitride, the thickness is 200nm-5μm; the material of the n-type GaN transistor channel layer (4) is a ternary compound semiconductor formed by gallium nitride, indium nitride and gallium nitride or aluminum gallium nitride, the thickness is 50nm-500nm, and the material of the n-type GaN transistor barrier layer (5) is a ternary compound semiconductor formed by aluminum gallium nitride, indium nitride and gallium nitride or aluminum nitride, the thickness is 5nm-50nm.

[0045] The n-type GaN transistor barrier layer (5) is located on the n-type GaN transistor channel layer (4); since group III nitrides have relatively strong polarization charges, near the interface between the n-type GaN transistor barrier layer (5) and the n-type GaN transistor channel layer (4), the positive polarization charge density on the lower surface of the n-type GaN transistor barrier layer (5) is much greater than the negative polarization charge density of the n-type GaN transistor channel layer (4), resulting in a certain positive polarization charge being present at the interface between the n-type GaN transistor barrier layer (5) and the n-type GaN transistor channel layer (4), thereby inducing the generation of a two-dimensional electron gas within a nanometer-scale thickness range on the upper surface of the n-type GaN transistor channel layer (4); the two-dimensional electron gas has a relatively large concentration and a relatively high mobility, and can be used as a conductive channel of the n-type GaN transistor unit (001).

[0046] In one embodiment of the present application, the n-type GaN-based transistor unit (001) further includes a first SiN passivation layer (6a), a second SiN passivation layer (6b) and an n-type GaN transistor source electrode (7), wherein the n-type GaN transistor source electrode (7), the first SiN passivation layer (6a), the n-type GaN transistor gate electrode (8), the second SiN passivation layer (6b) and the n-type GaN transistor drain electrode (9) are sequentially arranged from left to right above the surface of the n-type GaN transistor barrier layer (5), and the n-type GaN transistor source electrode (7) is disposed on the surface of the n-type GaN transistor barrier layer (5). The electrode (7) and the n-type GaN transistor drain electrode (9) are respectively arranged at two ends of the n-type GaN transistor barrier layer (5); the n-type GaN transistor source electrode (7) and the n-type GaN transistor gate electrode (8) are connected via the first SiN passivation layer (6a), and the n-type GaN transistor gate electrode (8) and the n-type GaN transistor drain electrode (9) are connected via the second SiN passivation layer (6b), and the length ratio of the first SiN passivation layer (6a) to the second SiN passivation layer (6b) is in the range of 1.5-2.

[0047] Specifically, an n-type GaN transistor gate electrode (8) is located on an n-type GaN transistor barrier layer (5); a surface area of ​​the n-type GaN transistor barrier layer (5) corresponding to the surface area directly below the n-type GaN transistor gate electrode (8) is subjected to a first preset process, for example, the surface area of ​​the n-type GaN transistor barrier layer (5) directly below the n-type GaN transistor gate electrode (8) is etched to form a groove gate structure; or fluorine ions are implanted into the surface area of ​​the n-type GaN transistor barrier layer (5) directly below the n-type GaN transistor gate electrode (8); or a p-GaN layer is inserted between the n-type GaN transistor gate electrode (8) and the surface area of ​​the n-type GaN transistor barrier layer (5) directly below, so that the n-type GaN transistor unit (001) is in an enhanced working mode.

[0048] The first SiN passivation layer (6a) and the second SiN passivation layer (6b) are located on the n-type GaN transistor barrier layer (5). The first SiN passivation layer (6a) and the second SiN passivation layer (6b) play an important role in reducing the collapse of the drain current and maintaining the two-dimensional electron gas generated by the polarization characteristics. At the same time, they can also reduce the leakage current of the gate electrode (8) of the n-type GaN transistor and enhance the ohmic contact and breakdown voltage of the source and drain. At the same time, the length ratio of the first SiN passivation layer (6a) to the second SiN passivation layer (6b) is in the range of 1.5-2, which can improve the breakdown characteristics.

[0049] In one embodiment of the present application, the n-type GaN transistor source electrode (7) and the n-type GaN transistor drain electrode (9) are both stacked structures of titanium, aluminum, nickel and gold stacked from bottom to top; the n-type GaN transistor gate electrode (8) is a stacked structure of nickel and gold stacked from bottom to top; the electrode connection metal (003) material is one or more of titanium, aluminum, nickel, gold, copper, titanium nitride, and tantalum.

[0050] Specifically, the n-type GaN transistor source electrode (7) and the n-type GaN transistor drain electrode (9) are both stacked structures stacked from bottom to top by titanium, aluminum, nickel and gold, and the electrode connection metal (003) material is a combination of one or more of titanium, aluminum, nickel, gold, copper, titanium nitride and tantalum.

[0051] In one embodiment of the present application, the p-type diamond-based transistor unit (002) further comprises a p-type diamond layer (10), a p-type diamond transistor gate dielectric layer (11) and a p-type diamond transistor drain electrode (14); the p-type diamond layer (10) is arranged on the diamond substrate (1); the p-type diamond transistor source electrode (12), the p-type diamond transistor gate dielectric layer (11) and the p-type diamond transistor drain electrode (14) are arranged on the upper surface of the p-type diamond layer (10) in sequence from left to right; the p-type diamond transistor source electrode (12) and the p-type diamond transistor drain electrode (14) are respectively arranged at two ends of the p-type diamond layer (10) and are respectively connected to the two side surfaces of the p-type diamond transistor gate dielectric layer (11); wherein the upper surface of the p-type diamond layer (10) is composed of hydrogen-terminated diamond to form a two-dimensional hole gas to form a conductive channel of the p-type diamond transistor unit (002).

[0052] Specifically, the upper surface of the p-type diamond layer (10) is composed of hydrogen-terminated diamond to form a two-dimensional hole gas to form a conductive channel of the p-type diamond transistor unit (002), and the p-type diamond transistor drain electrode (14) is connected to a high level VDD.

[0053] In one embodiment of the present application, the p-type diamond-based transistor unit (002) further comprises a third SiN passivation layer (6c) and a fourth SiN passivation layer (6d), wherein the third SiN passivation layer (6c), the p-type diamond transistor gate electrode (13) and the fourth SiN passivation layer (6d) are sequentially arranged on the upper surface of the p-type diamond transistor gate dielectric layer (11) from left to right; the p-type diamond transistor source electrode (12) and the p-type diamond transistor gate electrode (13) are connected via the third SiN passivation layer (6c), the p-type diamond transistor gate electrode (13) and the p-type diamond transistor drain electrode (14) are connected via the fourth SiN passivation layer (6d), and the length ratio of the third SiN passivation layer (6c) to the fourth SiN passivation layer (6d) is in the range of 1.5-2.

[0054] Specifically, the third SiN passivation layer (6c) and the fourth SiN passivation layer (6d) play an important role in reducing the collapse of the drain current and maintaining the two-dimensional electron gas generated by the polarization characteristics, and can also reduce the leakage current of the gate electrode (8) of the n-type GaN transistor, and enhance the ohmic contact and breakdown voltage of the source and drain. At the same time, the length ratio of the third SiN passivation layer (6c) and the fourth SiN passivation layer (6d) is in the range of 1.5-2, which can improve the breakdown characteristics. The surface area directly below the gate electrode (13) of the p-type diamond transistor and corresponding to the p-type diamond layer (10) is subjected to a second preset treatment, and the preset treatment is to reduce the channel carrier concentration through the hydrogen-oxygen mixed terminal surface, or to form a gate dielectric stack through sputtering and atomic layer deposition process to change the hydrogen terminal surface charge balance, or to reduce the p-type channel carrier concentration through an annealing process, so as to realize the enhancement mode of the p-type diamond transistor unit (002).

[0055] In one embodiment of the present application, the material of the p-type diamond transistor gate dielectric layer (11) is one of aluminum oxide, molybdenum trioxide, tungsten trioxide, vanadium pentoxide, hafnium dioxide, zirconium dioxide, and boron nitride, and the thickness of the p-type diamond transistor gate dielectric layer (11) is 1nm-30nm; the materials of the p-type diamond transistor source electrode (12) and the p-type diamond transistor drain electrode (14) are both one or more of nickel, aluminum, gold, and titanium; the material of the p-type diamond transistor gate electrode (13) is one or more of titanium, aluminum, titanium nitride, tantalum, and tantalum nitride.

[0056] Specifically, different materials can be selected as the p-type diamond transistor source electrode (12), the p-type diamond transistor drain electrode (14) and the p-type diamond transistor gate electrode (13) to achieve a complementary field effect transistor device with higher performance.

[0057] Example 2

[0058] According to one aspect of the present application, Example 2 of the present application provides a diamond and gallium nitride heterogeneously integrated complementary field effect transistor device, which can be referred to Figure 3 and Figure 4 As shown (the main difference between Example 2 and Example 1 is the position and connection relationship of the electrode connection unit (003)), the structure and principle of the complementary field effect transistor device of heterogeneous integration of diamond and gallium nitride are introduced in detail as follows:

[0059] A diamond and gallium nitride heterogeneously integrated complementary field effect transistor device comprises: an n-type GaN-based transistor unit (001), a p-type diamond-based transistor unit (002), an electrode connection unit (003) and a diamond substrate (1); the n-type GaN-based transistor unit (001) and the p-type diamond-based transistor unit (002) are both arranged on the diamond substrate (1); the n-type GaN-based transistor unit (001) comprises an n-type GaN transistor gate electrode (8) and an n-type GaN transistor drain electrode (9); the p-type diamond-based transistor unit (002) comprises a p-type diamond transistor source electrode (12) and a p-type diamond transistor gate electrode (13); and the p-type diamond-based transistor unit (003) comprises a p-type diamond transistor source electrode (14) and a p-type diamond transistor gate electrode (15). Electrode (13); the electrode connection unit (003) comprises a first electrode connection metal (15a) and a second electrode connection metal (15b) which are spatially staggered, the first electrode connection metal (15a) being used to connect to an interface of an input signal, and the second electrode connection metal (15b) being used to connect to an interface of an output signal; the first electrode connection metal (15a) being respectively connected to the n-type GaN transistor gate electrode (8) and the p-type diamond transistor gate electrode (13), and the second electrode connection metal (15b) being respectively connected to the n-type GaN transistor drain electrode (9) and the p-type diamond transistor source electrode (12).

[0060] Specifically, Figure 3As shown, the first electrode connection metal (15a) is respectively connected to the n-type GaN transistor gate electrode (8) and the p-type diamond transistor gate electrode (13), and the second electrode connection metal (15b) is respectively connected to the n-type GaN transistor drain electrode (9) and the p-type diamond transistor source electrode (12). The first electrode connection metal (15a) is used to connect the gates in the n-type GaN-based transistor unit (001) and the p-type diamond-based transistor unit (002), and the second electrode connection metal (15b) is used to connect the drain electrode (9) in the n-type GaN-based transistor unit (001) and the p-type diamond transistor source electrode (12) in the p-type diamond-based transistor unit (002). The first electrode connection metal (15a) is connected to the input signal IN, and the second electrode connection metal (15b) is connected to the output signal OUT, so as to complete the conduction and transmission of electrical signals of the entire semiconductor device.

[0061] Furthermore, diamond material and gallium nitride are heterogeneously integrated, wherein n-channel transistors are formed using gallium nitride and p-channel transistors are formed using diamond, and they are connected to each other through electrode connection units to form complementary field effect transistor devices. The material structure of heterogeneous integration of diamond material and gallium nitride is compatible with gallium nitride RF devices, and can provide a material structure foundation for realizing a multifunctional gallium nitride RF chip with monolithic integrated analog drive, power management and digital processing.

[0062] Furthermore, by arranging both the n-type GaN-based transistor unit (001) and the p-type diamond-based transistor unit (002) on the diamond substrate (1), a monolithically integrated gallium nitride and diamond complementary inverter can be realized, forming the smallest unit of a digital integrated circuit, and providing structural design support for the manufacture of large-scale diamond substrates, gallium nitride and diamond heterogeneously integrated digital integrated circuits and analog integrated circuit logic circuits.

[0063] Furthermore, the n-type transistor adopts a gallium nitride-based structure, which has a high two-dimensional electron gas concentration, high mobility, and low square resistance. The gallium nitride-based channel material has a wide bandgap width, a low probability of inter-band tunneling, a high on-state current, and a low off-state leakage at a small size. The p-type transistor adopts a diamond-based semiconductor structure, which has a high two-dimensional hole gas concentration, high mobility, and a high device on-state current. The combined complementary field effect transistor device has the characteristics of fast switching speed and low power consumption.

[0064] In one embodiment of the present application, the n-type GaN transistor unit (001) and the p-type diamond transistor unit (002) are arranged on the upper surface of the diamond substrate (1) at intervals, and the interval distance between the n-type GaN transistor unit (001) and the p-type diamond transistor unit (002) is not less than a preset distance threshold.

[0065] Specifically, the preset distance threshold can be specifically the minimum process size of the electrode connection unit (003), that is, the n-type GaN transistor unit (001) and the p-type diamond transistor unit (002) are not connected, and a certain interval is retained, and the interval distance is not less than the preset distance threshold. The isolation between the n-type GaN transistor unit (001) and the p-type diamond transistor unit (002) can be dielectric isolation, or groove isolation, or ion implantation isolation. The first electrode connection metal (15a) and the second electrode connection metal (15b) of the electrode connection unit (003) are staggered in space, and a fifth SiN passivation layer (6e) is provided externally, which can be specifically as follows Figure 3 and Figure 4 As shown. The second SiN passivation layer (6b) and the third SiN passivation layer (6c) serve as supports for the first electrode connection metal (15a), and the fifth SiN passivation layer (6e) serves as a support for the second electrode connection metal (15b), that is, the second SiN passivation layer (6b) and the third SiN passivation layer (6c) are connected to the first electrode connection metal (15a), and the fifth SiN passivation layer (6e) is connected to the second electrode connection metal (15b).

[0066] In one embodiment of the present application, the n-type GaN-based transistor unit (001) further comprises an n-type GaN transistor transition layer (2), an n-type GaN transistor buffer layer (3), an n-type GaN transistor channel layer (4), and an n-type GaN transistor barrier layer (5); the n-type GaN transistor transition layer (2), the n-type GaN transistor buffer layer (3), the n-type GaN transistor channel layer (4), and the n-type GaN transistor barrier layer (5) are arranged in sequence from bottom to top, and the n-type GaN transistor transition layer (2) is arranged on the diamond substrate (1).

[0067] Specifically, the n-type GaN transistor transition layer (2) is located on a diamond substrate (1); since the diamond substrate (1) as a dielectric substrate has a lattice mismatch problem with the n-type GaN transistor buffer layer (3), a transition layer (AlGaN or AlN) of a certain thickness needs to be introduced to reduce the interface tension caused by the lattice mismatch. The n-type GaN transistor transition layer (2) can reduce the current collapse caused by interface mismatch, defects or trap effects, reduce static current leakage and radio frequency conduction, and improve radio frequency performance.

[0068] The n-type GaN transistor buffer layer (3) is located on the n-type GaN transistor transition layer (2); a certain amount of doping is introduced into the n-type GaN transistor buffer layer (3) to achieve the functions of high resistance and low leakage, and its thickness is usually at the micrometer level, which is used to reduce the background carrier concentration to reduce the drain current collapse caused by the trap effect of the buffer layer.

[0069] The n-type GaN transistor channel layer (4) is located on the n-type GaN transistor buffer layer (3); the n-type GaN transistor channel layer (4) is unintentionally doped, a two-dimensional electron gas channel is formed on the upper surface of the n-type GaN transistor channel layer (4), and is isolated from the n-type GaN transistor buffer layer (3) into which certain doping impurities are intentionally introduced.

[0070] In one embodiment of the present application, the n-type GaN transistor channel layer (4) and the n-type GaN transistor barrier layer (5) are both group III nitrides, and the group III nitrides are one or more of gallium nitride, aluminum nitride and indium nitride; a two-dimensional electron gas is formed between the n-type GaN transistor channel layer (4) and the n-type GaN transistor barrier layer (5) to form a conductive channel of the n-type GaN-based transistor unit (001).

[0071] The material of the n-type GaN transistor transition layer (2) is aluminum nitride, the thickness of the n-type GaN transistor transition layer is 50nm-300nm, and the n-type GaN transistor transition layer (2) is used to release the lattice mismatch stress and thermal stress between the n-type GaN transistor buffer layer (3) and the diamond substrate (1); the material of the n-type GaN transistor buffer layer (3) is undoped gallium nitride or aluminum gallium nitride, the thickness is 200nm-5μm; the material of the n-type GaN transistor channel layer (4) is a ternary compound semiconductor formed by gallium nitride, indium nitride and gallium nitride or aluminum gallium nitride, the thickness is 50nm-500nm, and the material of the n-type GaN transistor barrier layer (5) is a ternary compound semiconductor formed by aluminum gallium nitride, indium nitride and gallium nitride or aluminum nitride, the thickness is 5nm-50nm.

[0072] The n-type GaN transistor barrier layer (5) is located on the n-type GaN transistor channel layer (4); since group III nitrides have relatively strong polarization charges, near the interface between the n-type GaN transistor barrier layer (5) and the n-type GaN transistor channel layer (4), the positive polarization charge density on the lower surface of the n-type GaN transistor barrier layer (5) is much greater than the negative polarization charge density of the n-type GaN transistor channel layer (4), resulting in a certain positive polarization charge being present at the interface between the n-type GaN transistor barrier layer (5) and the n-type GaN transistor channel layer (4), thereby inducing the generation of a two-dimensional electron gas within a nanometer-scale thickness range on the upper surface of the n-type GaN transistor channel layer (4); the two-dimensional electron gas has a relatively large concentration and a relatively high mobility, and can be used as a conductive channel of the n-type GaN transistor unit (001).

[0073] In one embodiment of the present application, the n-type GaN-based transistor unit (001) further includes a first SiN passivation layer (6a), a second SiN passivation layer (6b) and an n-type GaN transistor source electrode (7), wherein the n-type GaN transistor source electrode (7), the first SiN passivation layer (6a), the n-type GaN transistor gate electrode (8), the second SiN passivation layer (6b) and the n-type GaN transistor drain electrode (9) are sequentially arranged from left to right above the surface of the n-type GaN transistor barrier layer (5), and the n-type GaN transistor source electrode (7) is disposed on the surface of the n-type GaN transistor barrier layer (5). The electrode (7) and the n-type GaN transistor drain electrode (9) are respectively arranged at two ends of the n-type GaN transistor barrier layer (5); the n-type GaN transistor source electrode (7) and the n-type GaN transistor gate electrode (8) are connected via the first SiN passivation layer (6a), and the n-type GaN transistor gate electrode (8) and the n-type GaN transistor drain electrode (9) are connected via the second SiN passivation layer (6b), and the length ratio of the first SiN passivation layer (6a) to the second SiN passivation layer (6b) is in the range of 1.5-2.

[0074] Specifically, the second SiN passivation layer (6b) and the third SiN passivation layer (6c) are connected to the first electrode connection metal (15a), and the fifth SiN passivation layer (6e) is connected to the second electrode connection metal (15b). The n-type GaN transistor gate electrode (8) is located on the n-type GaN transistor barrier layer (5); the surface area of ​​the n-type GaN transistor barrier layer (5) corresponding to the area directly below the n-type GaN transistor gate electrode (8) is subjected to a first preset treatment, for example, etching the surface area of ​​the n-type GaN transistor barrier layer (5) directly below the n-type GaN transistor gate electrode (8) to form a groove gate structure; or fluorine ion implantation is performed on the surface area of ​​the n-type GaN transistor barrier layer (5) directly below the n-type GaN transistor gate electrode (8); or a p-GaN layer is inserted between the n-type GaN transistor gate electrode (8) and the surface area of ​​the n-type GaN transistor barrier layer (5) directly below, so that the n-type GaN transistor unit (001) is in an enhanced working mode.

[0075] The first SiN passivation layer (6a) and the second SiN passivation layer (6b) are located on the n-type GaN transistor barrier layer (5). The first SiN passivation layer (6a) and the second SiN passivation layer (6b) play an important role in reducing the collapse of the drain current and maintaining the two-dimensional electron gas generated by the polarization characteristics. At the same time, they can also reduce the leakage current of the gate electrode (8) of the n-type GaN transistor and enhance the ohmic contact and breakdown voltage of the source and drain. At the same time, the length ratio of the first SiN passivation layer (6a) to the second SiN passivation layer (6b) is in the range of 1.5-2, which can improve the breakdown characteristics.

[0076] In one embodiment of the present application, the n-type GaN transistor source electrode (7) and the n-type GaN transistor drain electrode (9) are both stacked structures of titanium, aluminum, nickel and gold stacked from bottom to top; the n-type GaN transistor gate electrode (8) is a stacked structure of nickel and gold stacked from bottom to top; the electrode connection metal (003) material is one or more of titanium, aluminum, nickel, gold, copper, titanium nitride, and tantalum.

[0077] Specifically, the n-type GaN transistor source electrode (7) and the n-type GaN transistor drain electrode (9) are both stacked structures stacked from bottom to top by titanium, aluminum, nickel and gold, and the electrode connection metal (003) material is a combination of one or more of titanium, aluminum, nickel, gold, copper, titanium nitride and tantalum.

[0078] In one embodiment of the present application, the p-type diamond-based transistor unit (002) further comprises a p-type diamond layer (10), a p-type diamond transistor gate dielectric layer (11) and a p-type diamond transistor drain electrode (14); the p-type diamond layer (10) is arranged on the diamond substrate (1); the p-type diamond transistor source electrode (12), the p-type diamond transistor gate dielectric layer (11) and the p-type diamond transistor drain electrode (14) are arranged on the upper surface of the p-type diamond layer (10) in sequence from left to right; the p-type diamond transistor source electrode (12) and the p-type diamond transistor drain electrode (14) are respectively arranged at two ends of the p-type diamond layer (10) and are respectively connected to the two side surfaces of the p-type diamond transistor gate dielectric layer (11); wherein the upper surface of the p-type diamond layer (10) is composed of hydrogen-terminated diamond to form a two-dimensional hole gas to form a conductive channel of the p-type diamond transistor unit (002).

[0079] Specifically, the upper surface of the p-type diamond layer (10) is composed of hydrogen-terminated diamond to form a two-dimensional hole gas to form a conductive channel of the p-type diamond transistor unit (002), and the p-type diamond transistor drain electrode (14) is connected to a high level VDD.

[0080] In one embodiment of the present application, the p-type diamond-based transistor unit (002) further comprises a third SiN passivation layer (6c) and a fourth SiN passivation layer (6d), wherein the third SiN passivation layer (6c), the p-type diamond transistor gate electrode (13) and the fourth SiN passivation layer (6d) are sequentially arranged on the upper surface of the p-type diamond transistor gate dielectric layer (11) from left to right; the p-type diamond transistor source electrode (12) and the p-type diamond transistor gate electrode (13) are connected via the third SiN passivation layer (6c), the p-type diamond transistor gate electrode (13) and the p-type diamond transistor drain electrode (14) are connected via the fourth SiN passivation layer (6d), and the length ratio of the third SiN passivation layer (6c) to the fourth SiN passivation layer (6d) is in the range of 1.5-2.

[0081] Specifically, the third SiN passivation layer (6c) and the fourth SiN passivation layer (6d) play an important role in reducing the collapse of the drain current and maintaining the two-dimensional electron gas generated by the polarization characteristics, and can also reduce the leakage current of the gate electrode (8) of the n-type GaN transistor, and enhance the ohmic contact and breakdown voltage of the source and drain. At the same time, the length ratio of the third SiN passivation layer (6c) and the fourth SiN passivation layer (6d) is in the range of 1.5-2, which can improve the breakdown characteristics. The surface area directly below the gate electrode (13) of the p-type diamond transistor and corresponding to the p-type diamond layer (10) is subjected to a second preset treatment, and the preset treatment is to reduce the channel carrier concentration through the hydrogen-oxygen mixed terminal surface, or to form a gate dielectric stack through sputtering and atomic layer deposition process to change the hydrogen terminal surface charge balance, or to reduce the p-type channel carrier concentration through an annealing process, so as to realize the enhancement mode of the p-type diamond transistor unit (002).

[0082] In one embodiment of the present application, the material of the p-type diamond transistor gate dielectric layer (11) is one of aluminum oxide, molybdenum trioxide, tungsten trioxide, vanadium pentoxide, hafnium dioxide, zirconium dioxide, and boron nitride, and the thickness of the p-type diamond transistor gate dielectric layer (11) is 1nm-30nm; the materials of the p-type diamond transistor source electrode (12) and the p-type diamond transistor drain electrode (14) are both one or more of nickel, aluminum, gold, and titanium; the material of the p-type diamond transistor gate electrode (13) is one or more of titanium, aluminum, titanium nitride, tantalum, and tantalum nitride.

[0083] Specifically, different materials can be selected as the p-type diamond transistor source electrode (12), the p-type diamond transistor drain electrode (14) and the p-type diamond transistor gate electrode (13) to achieve a complementary field effect transistor device with higher performance.

[0084] In addition, the above-mentioned figures are only schematic illustrations of the processes included in the method according to the exemplary embodiments of the present application, and are not intended to be limiting. It is easy to understand that the processes shown in the above-mentioned figures do not indicate or limit the time sequence of these processes. In addition, it is also easy to understand that these processes can be performed synchronously or asynchronously, for example, in multiple modules.

[0085] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be performed without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A diamond and gallium nitride heterogeneously integrated complementary field effect transistor device, characterized in that: include: An n-type GaN-based transistor unit (001), a p-type diamond-based transistor unit (002), an electrode connection unit (003) and a diamond substrate (1); the n-type GaN-based transistor unit (001) and the p-type diamond-based transistor unit (002) are both arranged on the diamond substrate (1); the n-type GaN-based transistor unit (001) comprises an n-type GaN transistor gate electrode (8) and an n-type GaN transistor drain electrode (9); the p-type diamond-based transistor unit (002) comprises a p-type diamond transistor source electrode (12) and a p-type diamond transistor gate electrode (13); the electrode connection unit (003 ... The unit (003) comprises a first electrode connection metal (15a) and a second electrode connection metal (15b) which are spatially staggered with each other, wherein the first electrode connection metal (15a) is used to connect to an interface of an input signal, and the second electrode connection metal (15b) is used to connect to an interface of an output signal; the first electrode connection metal (15a) is respectively connected to the n-type GaN transistor gate electrode (8) and the p-type diamond transistor gate electrode (13), and the second electrode connection metal (15b) is respectively connected to the n-type GaN transistor drain electrode (9) and the p-type diamond transistor source electrode (12).

2. The diamond and gallium nitride heterogeneously integrated complementary field effect transistor device according to claim 1, characterized in that: The n-type GaN transistor unit (001) and the p-type diamond transistor unit (002) are arranged at intervals on the upper surface of the diamond substrate (1), and the interval distance between the n-type GaN transistor unit (001) and the p-type diamond transistor unit (002) is not less than a preset distance threshold.

3. The diamond and gallium nitride heterogeneously integrated complementary field effect transistor device according to claim 1, characterized in that: The n-type GaN-based transistor unit (001) further comprises an n-type GaN transistor transition layer (2), an n-type GaN transistor buffer layer (3), an n-type GaN transistor channel layer (4), and an n-type GaN transistor barrier layer (5); the n-type GaN transistor transition layer (2), the n-type GaN transistor buffer layer (3), the n-type GaN transistor channel layer (4), and the n-type GaN transistor barrier layer (5) are arranged in sequence from bottom to top, and the n-type GaN transistor transition layer (2) is arranged on the diamond substrate (1).

4. The diamond and gallium nitride heterogeneously integrated complementary field effect transistor device according to claim 3, characterized in that: The n-type GaN-based transistor unit (001) further comprises a first SiN passivation layer (6a), a second SiN passivation layer (6b) and an n-type GaN transistor source electrode (7), wherein the n-type GaN transistor source electrode (7), the first SiN passivation layer (6a), the n-type GaN transistor gate electrode (8), the second SiN passivation layer (6b) and the n-type GaN transistor drain electrode (9) are sequentially arranged from left to right above the surface of the n-type GaN transistor barrier layer (5), and the n-type GaN transistor source electrode (7) and The n-type GaN transistor drain electrode (9) is respectively arranged at two ends of the n-type GaN transistor barrier layer (5); the n-type GaN transistor source electrode (7) is connected to the n-type GaN transistor gate electrode (8) via the first SiN passivation layer (6a); the n-type GaN transistor gate electrode (8) is connected to the n-type GaN transistor drain electrode (9) via the second SiN passivation layer (6b); and the length ratio of the first SiN passivation layer (6a) to the second SiN passivation layer (6b) is in the range of 1.5-2.

5. The diamond and gallium nitride heterogeneously integrated complementary field effect transistor device according to claim 3, characterized in that: The n-type GaN transistor channel layer (4) and the n-type GaN transistor barrier layer (5) are both group III nitrides, and the group III nitrides are one or more of gallium nitride, aluminum nitride and indium nitride; a two-dimensional electron gas is formed between the n-type GaN transistor channel layer (4) and the n-type GaN transistor barrier layer (5) to form a conductive channel of the n-type GaN-based transistor unit (001).

6. The diamond and gallium nitride heterogeneously integrated complementary field effect transistor device according to claim 3, characterized in that: The material of the n-type GaN transistor transition layer (2) is aluminum nitride, the thickness of the n-type GaN transistor transition layer is 50nm-300nm, and the n-type GaN transistor transition layer (2) is used to release the lattice mismatch stress and thermal stress between the n-type GaN transistor buffer layer (3) and the diamond substrate (1); the material of the n-type GaN transistor buffer layer (3) is undoped gallium nitride or aluminum gallium nitride, the thickness is 200nm-5μm; the material of the n-type GaN transistor channel layer (4) is a ternary compound semiconductor formed by gallium nitride, indium nitride and gallium nitride or aluminum gallium nitride, the thickness is 50nm-500nm, and the material of the n-type GaN transistor barrier layer (5) is a ternary compound semiconductor formed by aluminum gallium nitride, indium nitride and gallium nitride or aluminum nitride, the thickness is 5nm-50nm.

7. The diamond and gallium nitride heterogeneously integrated complementary field effect transistor device according to claim 6, characterized in that: The n-type GaN transistor source electrode (7) and the n-type GaN transistor drain electrode (9) are both stacked structures of titanium, aluminum, nickel and gold stacked from bottom to top; the n-type GaN transistor gate electrode (8) is a stacked structure of nickel and gold stacked from bottom to top; the electrode connection metal (003) material is one or more of titanium, aluminum, nickel, gold, copper, titanium nitride and tantalum.

8. The diamond and gallium nitride heterogeneously integrated complementary field effect transistor device according to claim 1, characterized in that: The p-type diamond-based transistor unit (002) further comprises a p-type diamond layer (10), a p-type diamond transistor gate dielectric layer (11) and a p-type diamond transistor drain electrode (14); the p-type diamond layer (10) is arranged on the diamond substrate (1); the p-type diamond transistor source electrode (12), the p-type diamond transistor gate dielectric layer (11) and the p-type diamond transistor drain electrode (14) are arranged on the upper surface of the p-type diamond layer (10) in sequence from left to right; the p-type diamond transistor source electrode (12) and the p-type diamond transistor drain electrode (14) are respectively arranged at two ends of the p-type diamond layer (10) and are respectively connected to the two side surfaces of the p-type diamond transistor gate dielectric layer (11); wherein the upper surface of the p-type diamond layer (10) is composed of hydrogen-terminated diamond to form a two-dimensional hole gas to form a conductive channel of the p-type diamond transistor unit (002).

9. The diamond and gallium nitride heterogeneously integrated complementary field effect transistor device according to claim 8, characterized in that: The p-type diamond-based transistor unit (002) further comprises a third SiN passivation layer (6c) and a fourth SiN passivation layer (6d); the third SiN passivation layer (6c), the p-type diamond transistor gate electrode (13) and the fourth SiN passivation layer (6d) are sequentially arranged on the upper surface of the p-type diamond transistor gate dielectric layer (11) from left to right; the p-type diamond transistor source electrode (12) and the p-type diamond transistor gate electrode (13) are connected via the third SiN passivation layer (6c), the p-type diamond transistor gate electrode (13) and the p-type diamond transistor drain electrode (14) are connected via the fourth SiN passivation layer (6d), and the length ratio of the third SiN passivation layer (6c) to the fourth SiN passivation layer (6d) is in the range of 1.5-2.

10. The diamond and gallium nitride heterogeneously integrated complementary field effect transistor device according to claim 9, characterized in that: The material of the p-type diamond transistor gate dielectric layer (11) is one of aluminum oxide, molybdenum trioxide, tungsten trioxide, vanadium pentoxide, hafnium dioxide, zirconium dioxide, and boron nitride, and the thickness of the p-type diamond transistor gate dielectric layer (11) is 1nm-30nm; the material of the p-type diamond transistor source electrode (12) and the p-type diamond transistor drain electrode (14) are both one or more of nickel, aluminum, gold, and titanium; the material of the p-type diamond transistor gate electrode (13) is one or more of titanium, aluminum, titanium nitride, tantalum, and tantalum nitride.

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