Display device

Abstract

The invention relates to a display device. The reliability of a display device using a transistor including an oxide semiconductor is improved. A display device includes a plurality of pixels arranged in a matrix along a first direction and a second direction intersecting the first direction, each of the plurality of pixels including: a transistor; the semiconductor device includes an oxide semiconductor layer, a gate wiring line facing the oxide semiconductor layer and extending in a first direction, and a gate insulating layer between the oxide semiconductor layer and the gate wiring line. A first conductive layer provided on at least one first insulating layer on the transistor, the first conductive layer being in contact with the oxide semiconductor layer; a second insulating layer provided on the first conductive layer; a first inorganic layer provided on the second insulating layer and having an opening; and a second inorganic layer provided on the first inorganic layer and in contact with the second insulating layer in the opening portion, the first inorganic layer covering the first insulating layer being 85% or more with respect to the area of the pixel.

Description

Technical Field

[0001] One embodiment of the present invention relates to a display device. In particular, one embodiment of the present invention relates to a display device using a transistor including an oxide semiconductor. In addition, one embodiment of the present invention relates to a method for manufacturing a display device. Background Art

[0002] In recent years, the development of transistors using oxide semiconductors for channels instead of amorphous silicon, low-temperature polycrystalline silicon, and single-crystal silicon has been progressing (for example, see Patent Documents 1 and 2). Transistors using oxide semiconductors for channels are formed with a simple structure and a low-temperature process, similar to transistors using amorphous silicon for channels. Transistors using oxide semiconductors for channels are known to have high mobility and very low off-current compared to transistors using amorphous silicon for channels.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2014-146819

[0006] Patent Document 2: Japanese Patent Application Publication No. 2015-159315 Summary of the invention

[0007] Problems to be solved by the invention

[0008] It is known that the characteristics of a transistor including an oxide semiconductor may change due to the intrusion of water into the oxide semiconductor. In addition, in a display device, a planarization film formed of an organic resin layer is provided to alleviate the unevenness formed by the transistor. Since the organic resin layer contains a large amount of water, if hydrogen contained in the organic resin layer intrudes into the oxide semiconductor, the characteristics of the transistor may change, and the reliability of the display device may be reduced.

[0009] In one embodiment of the present invention, one of the objects is to improve the reliability of a display device using a transistor including an oxide semiconductor.

[0010] Means for solving problems

[0011] A display device involved in one embodiment of the present invention includes a plurality of pixels arranged in a matrix along a first direction and a second direction intersecting the first direction, each of the plurality of pixels respectively comprising: a transistor, which has an oxide semiconductor layer, a gate wiring opposite to the oxide semiconductor layer and extending in the first direction, and a gate insulating layer between the oxide semiconductor layer and the gate wiring; a first conductive layer, which is arranged on at least one first insulating layer above the transistor and is connected to the oxide semiconductor layer; a second insulating layer, which is arranged on the first conductive layer; a first inorganic layer, which is arranged on the second insulating layer and has an opening; and a second inorganic layer, which is arranged on the first inorganic layer and is connected to the second insulating layer in the opening, wherein the coverage rate of the first inorganic layer covering the first insulating layer is greater than 85% relative to the area of ​​the pixel. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a plan view schematically showing a display device according to one embodiment of the present invention.

[0013] Figure 2 It is a block diagram showing a circuit configuration of a display device according to one embodiment of the present invention.

[0014] Figure 3 1 is a circuit diagram showing a pixel circuit of a pixel of a display device according to an embodiment of the present invention.

[0015] Figure 4 It is a cross-sectional view showing the structure of a display device according to one embodiment of the present invention.

[0016] Figure 5 It is a plan view showing the structure of a display device according to one embodiment of the present invention.

[0017] Figure 6 It is a plan view showing the structure of a display device according to one embodiment of the present invention.

[0018] Figure 7 A flowchart for explaining a method for manufacturing a display device according to an embodiment of the present invention.

[0019] Figure 8 A flowchart for explaining a method for manufacturing a display device according to an embodiment of the present invention.

[0020] Fig. 9 A cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention.

[0021] Fig.10 A cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention.

[0022] Fig.11 A cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention.

[0023] Fig.12 A cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention.

[0024] Fig.13 A cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention.

[0025] Fig.14 A cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention.

[0026] Fig.15 A cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention.

[0027] Fig.16 A cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention.

[0028] Fig.17 A cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention.

[0029] Fig.18 A cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention.

[0030] Fig.19 It is a cross-sectional view showing the structure of a display device according to another embodiment of the present invention.

[0031] Fig. 20 It is a cross-sectional view showing the structure of a display device according to another embodiment of the present invention.

[0032] Fig.21 It is a cross-sectional view showing the structure of a display device according to another embodiment of the present invention.

[0033] Fig. 22 It is a cross-sectional view showing the structure of a display device according to another embodiment of the present invention.

[0034] Description of Reference Numerals

[0035] 10, 10A to 10D: display device, 22: liquid crystal region, 24: sealing region, 26: terminal region, 300: array substrate, 310: pixel, 320: source driver circuit, 321: source wiring, 330: gate driver circuit, 331: gate wiring, 333: terminal portion, 341: connection wiring, 342: connection wiring, 400: sealing portion, 410: liquid crystal element, 500: counter substrate, 600: flexible printed circuit substrate, 700: IC chip, 800: transistor, 810: gate electrode, 830: source electrode, 840: drain electrode, 890: holding capacitor, AOS: oxide semiconductor layer, CA: channel region, CMTL: common auxiliary Electrode, CON1, CON2: 2nd contact region, CTCO: common electrode, DA: drain region, IL1: 1st insulating layer, IL2: 2nd insulating layer, IL3: 3rd insulating layer, IL4: 4th insulating layer, IL5: 5th insulating layer, IL6: 6th insulating layer, IL7: 7th insulating layer, LS: light shielding layer, LS1: light shielding layer, LS2: light shielding layer, MO1, MO2: metal oxide layer, OS: oxide semiconductor layer, PCON: contact hole, POS: oxide semiconductor layer, PTCO: pixel electrode, SA: source region, SP: spacer, SUB: substrate, W1: wiring, WCON: contact hole, ZCON: contact hole, ZTCO: connection electrode DETAILED DESCRIPTION

[0036] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. The following disclosure is only an example. While maintaining the gist of the invention, the configuration that can be easily thought of by those skilled in the art by appropriately changing the configuration of the embodiment is of course included in the scope of the present invention. In order to make the description clearer, the width, film thickness, shape, etc. of each part are sometimes schematically indicated in the accompanying drawings compared to the actual method. However, the shape shown in the figure is only an example and does not limit the interpretation of the present invention. In this specification and the drawings, the same figure mark is marked for the same configuration as that described previously with respect to the accompanying drawings that have appeared, and the detailed description is sometimes appropriately omitted.

[0037] The so-called "display device" refers to a structure that uses an electro-optical layer to display an image. For example, the term display device sometimes refers to a display panel including an electro-optical layer, or sometimes refers to a structure in which other optical components (such as polarization components, backlight sources, touch panels, etc.) are installed on a display unit. The "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer as long as no technical contradiction arises. Therefore, with respect to the embodiments described below, as a display device, a liquid crystal display device including a liquid crystal layer is exemplified for explanation, but the structure in this embodiment can be applied to a display device including the above-mentioned other electro-optical layers.

[0038] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as up or above. On the contrary, the direction from the oxide semiconductor layer toward the substrate is referred to as down or below. Thus, for the sake of convenience, the description is made using the phrases such as up or below, but for example, the up-and-down relationship between the substrate and the oxide semiconductor layer may be configured in a direction different from that shown in the figure. In the following description, for example, the description of the oxide semiconductor layer on the substrate is merely a description of the up-and-down relationship between the substrate and the oxide semiconductor layer as described above, and other components may also be configured between the substrate and the oxide semiconductor layer. Up or down refers to the stacking order in a structure formed by stacking a plurality of layers, and in the case of a pixel electrode described as above the transistor, it may also be a positional relationship in which the transistor and the pixel electrode do not overlap when viewed from above. On the other hand, in the case of a pixel electrode described as vertically above the transistor, it refers to a positional relationship in which the transistor and the pixel electrode overlap when viewed from above.

[0039] In this specification, expressions such as “α includes A, B, or C”, “α includes any one of A, B, and C”, and “α includes one selected from the group consisting of A, B, and C” do not exclude the case where α includes a combination of multiple elements of A to C unless otherwise specified. In addition, these expressions do not exclude the case where α includes other elements.

[0040] It should be noted that the following embodiments can be combined with each other as long as no technical contradiction occurs.

[0041] [First embodiment]

[0042] [1. Overview of Display Device 10]

[0043] Reference Figure 1 to Figure 3 , an overview of a display device 10 according to an embodiment of the present invention will be described. Figure 1 1 is a plan view schematically showing a display device 10 according to an embodiment of the present invention. In this embodiment, a configuration of a liquid crystal display device will be described as the display device 10 .

[0044] like Figure 1As shown, the display device 10 has an array substrate 300, a sealing portion 400, an opposing substrate 500, a flexible printed circuit substrate 600 (FPC) and an IC chip 700. The array substrate 300 and the opposing substrate 500 are bonded together by the sealing portion 400. In the liquid crystal region 22 surrounded by the sealing portion 400, a plurality of pixels 310 are arranged in a matrix along the first direction D1 (row direction) and the second direction D2 (column direction) intersecting the first direction D1. The plurality of pixels 310 include red pixels R, green pixels G and blue pixels B corresponding to the color filters provided on the opposing substrate. The red pixels R, green pixels G and blue pixels B are also each referred to as a sub-pixel. The first direction D1 and the second direction D2 may be orthogonal. The liquid crystal region 22 is an area that overlaps with the liquid crystal element 410 described later when viewed from above. It should be noted that, hereinafter, the area including a plurality of pixels in the liquid crystal region 22 is sometimes referred to as an image display area or an active area.

[0045] Furthermore, in the display device 10 , a backlight unit is provided at the back of the array substrate 300 . When light emitted from the backlight unit passes through the image display area, the transmitted light is modulated in each pixel, thereby displaying an image.

[0046] The sealing area 24 provided with the sealing portion 400 is the area around the liquid crystal area 22. The FPC 600 is provided in the terminal area 26. The terminal area 26 is the area where the array substrate 300 is exposed from the opposing substrate 500, and is provided outside the sealing area 24. It should be noted that the so-called outside of the sealing area 24 refers to the area where the sealing portion 400 is provided and the outside of the area surrounded by the sealing portion 400. The IC chip 700 is provided on the FPC 600. The IC chip 700 supplies a signal for driving the pixel circuit of each pixel 310. It should be noted that, hereinafter, the sealing area 24 outside the image display area, the outside of the sealing area 24, and the terminal area 26 are sometimes collectively referred to as the peripheral area.

[0047] [2. Circuit Configuration of Display Device 10]

[0048] Figure 2 1 is a block diagram showing a circuit configuration of a display device 10 according to an embodiment of the present invention. Figure 2 As shown, a gate driver circuit 330 is provided at a position adjacent to the liquid crystal region 22 in the first direction D1 with respect to the pixel 310, and a source driver circuit 320 is provided at a position adjacent to the liquid crystal region 22 in the second direction D2. The source driver circuit 320 and the gate driver circuit 330 are provided in the above-mentioned sealing region 24. However, the region where the source driver circuit 320 and the gate driver circuit 330 are provided is not limited to the sealing region 24, and may be any region as long as it is outside the region where the pixel circuit of the pixel 310 is provided.

[0049] The gate wiring 331 extends from the gate driver circuit 330 in the first direction D1 and is connected to the pixel circuits of the plurality of pixels 310 arranged in the first direction D1. The source wiring 321 extends from the source driver circuit 320 in the second direction D2 and is connected to the pixel circuits of the plurality of pixels 310 arranged in the second direction D2.

[0050] The terminal region 26 is provided with a terminal portion 333. The terminal portion 333 and the source driver circuit 320 are connected by a connection wiring 341. Similarly, the terminal portion 333 and the gate driver circuit 330 are connected by a connection wiring 342. The FPC 600 is connected to the terminal portion 333, and thus an external device connected to the FPC 600 is connected to the display device 10, and a pixel circuit included in each pixel 310 provided in the display device 10 is driven by a signal from the external device.

[0051] [3. Pixel Circuit of Pixel 310 of Display Device 10]

[0052] Figure 3 1 is a circuit diagram showing a pixel circuit of a pixel 310 of a display device 10 according to an embodiment of the present invention. Figure 3 As shown, the pixel circuit includes components such as a transistor 800, a holding capacitor 890 and a liquid crystal element 410. One electrode of the holding capacitor 890 is a pixel electrode PTCO, and the other electrode is a common electrode CTCO, and the details are described later. Similarly, one electrode of the liquid crystal element 410 is a pixel electrode PTCO, and the other electrode is a common electrode CTCO. The transistor 800 has a gate electrode 810, a source electrode 830 and a drain electrode 840. The gate electrode 810 is connected to the gate wiring 331. The source electrode 830 is connected to the source wiring 321. The drain electrode 840 is connected to the holding capacitor 890 and the liquid crystal element 410. It should be noted that in this embodiment, for the sake of convenience of description, 830 is called a source electrode and 840 is called a drain electrode, but for each electrode, the function of being a source electrode and the function of being a drain electrode can be interchanged.

[0053] [4. Configuration of Display Device 10]

[0054] Reference Figures 4 to 6 , the details of the structure of the display device 10 involved in one embodiment of the present invention are described. Figure 4 It is a cross-sectional view showing the structure of a display device 10 according to one embodiment of the present invention. Figure 5 and Figure 6 FIG. 1 is a top view showing the structure of a display device 10 according to an embodiment of the present invention. Figure 4The cross-sectional view is a cross-sectional view for explaining the layer structure of the display device 10. In fact, the pixel circuit is provided in the image display area. Figure 4 In the pixel circuit in FIG. 1 , the periphery of the contact hole in the pixel area is shown in the center, and only a portion of the transparent area (opening area) involved in the display is shown. Figure 4 In the figure, the liquid crystal layer and the counter substrate are omitted. Figure 4 , an FFS (Fringe Field Switching) type liquid crystal display device is shown, but an IPS (In Plane Switching) type liquid crystal display device may also be used.

[0055] like Figure 4 As shown, the display device 10 is disposed above the substrate SUB. The display device 10 includes a transistor Tr, a wiring W1, a connecting electrode ZTCO, a pixel electrode PTCO, a common auxiliary electrode CMTL, and a common electrode CTCO. TCO is an abbreviation of Transparent Conductive Oxide. The transistor Tr is a transistor included in the pixel circuit of the pixel 310 of the display device 10.

[0056] [5. Configuration of transistor Tr]

[0057] In the transistor Tr, a light shielding layer LS is provided on the substrate SUB and provided on the first insulating layer IL1. The transistor Tr includes an oxide semiconductor layer POS, a second insulating layer IL2 and a gate wiring GL (corresponding to Figure 3 The gate electrode 810 and the gate wiring 331 are shown in the figure. In addition, the transistor Tr may also have a metal oxide layer MO1 provided between the oxide semiconductor layer POS and the first insulating layer IL1. The gate wiring GL is opposite to the oxide semiconductor layer POS. The second insulating layer IL2 is provided between the oxide semiconductor layer POS and the gate wiring GL. In this embodiment, a top-gate transistor in which the oxide semiconductor layer POS is provided on the substrate SUB side relative to the gate wiring GL is exemplified, but a bottom-gate transistor in which the positional relationship between the gate wiring GL and the oxide semiconductor layer POS is reversed may also be used.

[0058] The oxide semiconductor layer POS has a polycrystalline structure including a plurality of crystal grains. The oxide semiconductor layer POS having a polycrystalline structure can be formed by using the Poly-OS (Poly-crystalline Oxide Semiconductor) technology, and the details are described later. Hereinafter, an oxide semiconductor having a polycrystalline structure is sometimes referred to as Poly-OS.

[0059] The oxide semiconductor layer POS contains two or more metals including indium, and the ratio of indium in the two or more metals is 50% or more, which will be described in detail later. As metal elements other than indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr) and lanthanide elements can be used. However, the oxide semiconductor layer POS only needs to contain Poly-OS, and sometimes contains other metal elements other than the above.

[0060] The oxide semiconductor layer POS includes a channel region CA, a source region SA, and a drain region DA. The channel region CA is a region of the oxide semiconductor layer that overlaps with the gate wiring GL when viewed from above. The channel region CA is switched between a conductive state and a non-conductive state in accordance with a voltage supplied to the gate wiring GL. The source region SA and the drain region DA are regions with lower resistance than the channel region. For example, the source region SA and the drain region DA are regions whose resistance is reduced by doping the oxide semiconductor layer POS with impurities.

[0061] The gate wiring GL is arranged along the first direction D1. The oxide semiconductor layer POS is arranged to intersect the gate wiring GL. A region of the gate wiring GL that overlaps with the oxide semiconductor layer POS functions as a gate electrode.

[0062] A third insulating layer IL3 is provided on the gate wiring GL. A wiring W1 (corresponding to Figure 3 The wiring W1 is arranged along the second direction D2. The wiring W1 is connected to the source region SA via a contact hole WCON provided in the second insulating layer IL2 and the third insulating layer IL3. The wiring W1 transmits a data signal related to the grayscale of the pixel. A fourth insulating layer IL4 is provided on the third insulating layer IL3 and the wiring W1. A connection electrode ZTCO (corresponding to Figure 3 The connection electrode ZTCO is connected to the drain area DA via a contact hole ZCON provided in the second insulating layer IL2 to the fourth insulating layer IL4. The connection electrode ZTCO is in contact with the drain area DA at the bottom of the contact hole ZCON. The connection electrode ZTCO is a transparent conductive layer.

[0063] The area where the connection electrode ZTCO contacts the drain area DA is called the first contact area CON1. ​​In the first contact area CON1 that does not overlap the gate wiring GL and the wiring W1 in a plan view, the common electrode CTCO contacts the drain area DA, and the details will be described later. In a plan view, the first contact area CON1 is included in the display area of ​​the pixel.

[0064] A fifth insulating layer IL5 is provided on the connecting electrode ZTCO. The fifth insulating layer IL5 mitigates the step difference formed by the structure provided on the lower layer compared to the fifth insulating layer IL5. The fifth insulating layer IL5 is sometimes referred to as a planarization film. In addition, the fifth insulating layer is formed of an organic resin. A pixel electrode PTCO is provided on the fifth insulating layer IL5. The pixel electrode PTCO is connected to the connecting electrode ZTCO via a contact hole PCON provided in the fifth insulating layer IL5. The area where the connecting electrode ZTCO and the pixel electrode PTCO are connected is referred to as the second contact area CON2. When viewed from above, the second contact area CON2 overlaps with the gate wiring GL. The pixel electrode PTCO is a transparent conductive layer.

[0065] A sixth insulating layer IL6 is provided on the pixel electrode PTCO. A common auxiliary electrode CMTL and a common electrode CTCO are provided on the sixth insulating layer IL6. The common auxiliary electrode CMTL and the common electrode CTCO have different planar patterns from each other, and the details are described later. The common auxiliary electrode CMTL is a metal layer. The common electrode CTCO is a transparent conductive layer. The resistance of the common auxiliary electrode CMTL is lower than the resistance of the common electrode CTCO. In addition, the common auxiliary electrode CMTL also functions as a light shielding layer. For example, by shielding the light from the pixels adjacent to the common auxiliary electrode CMTL, the occurrence of color mixing is suppressed. A spacer SP is provided on the common electrode CTCO.

[0066] When viewed from above, the common auxiliary electrode CMTL is arranged in a grid shape. The common auxiliary electrode CMTL is configured in a manner that crosses the contact hole PCON in the first direction D1, and is arranged in a manner that overlaps with the wiring W1 in the second direction D2. An opening COP is provided in the common auxiliary electrode CMTL. The opening COP corresponds to the opening portion of the pixel. The common electrode CTCO is arranged on the common auxiliary electrode CMTL and is arranged in a manner that covers the entire image display area. In the common electrode CTCO, a slit pattern is provided in an area that overlaps with the opening COP and the pixel electrode PTCO. The slit pattern also overlaps with the pixel electrode PTCO. It should be noted that an opening portion IOP is provided in the sixth insulating layer IL6, and the opening portion IOP will be described in detail later.

[0067] The spacer SP is provided for a part of the pixels. For example, the spacer SP can be provided for any one of the red pixel R, the green pixel G, and the blue pixel B. However, the spacer SP can also be provided for all pixels. The height of the spacer SP is half the height of the cell gap. A spacer is also provided on the opposing substrate, and the spacer of the opposing substrate overlaps with the above-mentioned spacer SP when viewed from above. It should be noted that a structure in which the height of the spacer SP is equivalent to the cell gap can also be applied. In addition, if Figure 4 As shown, the spacer is filled in the contact hole PCON and protrudes toward the counter substrate side, but a configuration in which the contact hole is only filled with a filler may be adopted.

[0068] A light shielding layer LS is provided between the transistor Tr and the substrate SUB. In the present embodiment, light shielding layers LS1 and LS2 are provided as the light shielding layer LS. However, the light shielding layer LS may be formed only by the light shielding layer LS1 or only by the light shielding layer LS2. When observed from above, the light shielding layer LS is arranged along the first direction D1 and is provided in a region overlapping with the gate wiring GL. In addition, the light shielding layer LS is provided in a manner intersecting with the oxide semiconductor layer POS. That is, when observed from above, the light shielding layer LS is provided in a region overlapping with the channel region. The light shielding layer LS inhibits light incident from the side of the substrate SUB from reaching the channel region. When a conductive layer is used as the light shielding layer LS, a voltage may be applied to the light shielding layer LS to control the channel region. When a voltage is applied to the light shielding layer LS, the light shielding layer LS and the gate wiring GL may also be connected in the peripheral region of the pixel circuit. When observed from above, the above-mentioned first contact region CON1 is provided in a region that does not overlap with the light shielding layer LS.

[0069] It is known that the characteristics of a transistor including an oxide semiconductor may change due to the intrusion of water into the oxide semiconductor. In addition, in a display device, a planarization film formed of an organic resin is provided to alleviate the unevenness formed by the transistor. Since the organic resin contains a large amount of water, if the hydrogen contained in the organic resin intrudes into the oxide semiconductor, the characteristics of the transistor may change, and the reliability of the display device may be reduced.

[0070] In a display device using a transistor including an oxide semiconductor, it is necessary to fully release the moisture contained in the organic resin layer provided on the transistor. In the manufacturing process, even if the annealing treatment is performed with the organic resin layer exposed, the moisture is captured again from the surface of the exposed organic resin layer in the subsequent process.

[0071] For example, in the case of a liquid crystal display device, an inorganic layer such as a pixel electrode, a common electrode, an auxiliary electrode or an inorganic insulating layer is provided on the organic resin layer. The inorganic layer has a function of suppressing moisture penetration compared to the organic resin layer. Even if an annealing process is performed in a state where a pixel electrode is formed on the organic resin layer, since the surface of the organic resin layer is exposed from the pixel electrode, moisture will be captured from the outside again, and the characteristics of the transistor will sometimes change. Similarly, even if an annealing process is performed in a state where a common electrode is formed on the organic resin layer, since the surface of the organic resin layer is exposed from the common electrode, moisture will be captured from the outside again, and the characteristics of the transistor will sometimes change. As the fineness of the display device increases, the area of ​​the pixel and the area occupied by the transistor are reduced. Therefore, the change in the characteristics of the transistor will have a greater impact on the display quality of the display device.

[0072] Therefore, in order to suppress the variation in the characteristics of a transistor including an oxide semiconductor, it is important to release the moisture contained in the organic resin layer to the outside and to suppress the moisture from being captured again from the outside into the organic resin layer in a subsequent step.

[0073] In one embodiment of the present invention, a first inorganic layer is provided on an organic resin layer, and an opening portion IOP is provided on the first inorganic layer. The coverage rate of the first inorganic layer covering the organic resin layer is 85% or more relative to the area of ​​the pixel. A second inorganic layer is provided on the first inorganic layer, and the second inorganic layer is in contact with the organic resin layer in the opening portion. That is, the opening portion IOP provided on the first inorganic layer is blocked by the second inorganic layer provided on the first inorganic layer.

[0074] In the manufacturing process of the display device 10, after the opening IOP is formed in the first inorganic layer, an annealing process is performed, thereby allowing the moisture contained in the organic resin layer to be released to the outside through the opening IOP provided in the first inorganic layer. At this time, the coverage rate of the first inorganic layer covering the organic resin layer is more than 85% relative to the area of ​​the pixel, so that the moisture is concentratedly released from the opening IOP. In addition, it is possible to suppress the intrusion of moisture into the organic resin layer from the outside of the first inorganic layer. In addition, by blocking the opening IOP with the second inorganic layer provided on the first inorganic layer, it is possible to further suppress the intrusion of moisture into the organic resin layer from the outside.

[0075] In the display device 10 according to one embodiment of the present invention, the opening IOP provided in the first inorganic layer is blocked by the second inorganic layer, so that the intrusion of moisture into the organic resin layer can be suppressed not only in the manufacturing process but also when the display device is used. Therefore, the moisture contained in the organic resin layer can be suppressed from intruding into the oxide semiconductor again. Thus, the characteristic variation of the transistor can be suppressed, and the reliability of the display device can be improved.

[0076] In this specification and the like, the area of ​​a sub-pixel can be calculated by the following formula.

[0077] Active area / resolution = area of ​​sub-pixel

[0078] It should be noted that, depending on the display device, the areas of the red pixel R, the green pixel G, and the blue pixel B are sometimes different. In this case, the areas of the three sub-pixels can be calculated as the area of ​​one pixel. At this time, the coverage rate of the first inorganic layer covering the organic resin layer can be calculated by using the areas of the three sub-pixels as the area of ​​one pixel.

[0079] For example, the active area (mm 2 ) is 38.4 mm × 38.4 mm and the resolution is 1600 (RGB) × 1600, the area of ​​each sub-pixel is 192 μm 2 Therefore, if the first inorganic layer in the sub-pixel covers the organic resin layer by 163.2 μm 2 As described above, it is possible to release the moisture contained in the organic resin layer from the opening IOP of the first inorganic layer, and to suppress the moisture from being captured again in the organic resin layer in the subsequent steps.

[0080] The first inorganic layer and the second inorganic layer are each formed by a conductive layer, a transparent conductive layer and an inorganic insulating layer. The first inorganic layer and the second inorganic layer can each be a single-layer structure or a laminated structure. In the case of a laminated structure, for example, a laminated structure of a transparent conductive layer and an inorganic insulating layer can be used, or a structure in which an inorganic insulating layer is laminated multiple layers. The thickness of each of the first inorganic layer and the second inorganic layer is not particularly limited, but it is preferred to be at least 30 nm or more, 50 nm or more and 200 nm or less. When the thickness of the first inorganic layer is less than 30 nm, the barrier effect of moisture from the outside is sometimes weakened. In this case, a second inorganic layer thicker than the thickness of the first inorganic layer can also be provided on the first inorganic layer to fill the opening IOP provided in the first inorganic layer. It should be noted that the thickness of the second inorganic layer can also be 200 nm or more as long as it has no effect on the driving of the liquid crystal element.

[0081] The area of ​​the opening IOP provided in the sixth insulating layer IL6 may be smaller than the area of ​​the contact hole provided in the fifth insulating layer IL5. In other words, the coverage rate of the first inorganic layer covering the organic resin layer is 85% or more, preferably 95% or more, and more preferably 98% or more relative to the area of ​​the pixel. When the area of ​​the opening IOP is large, even if moisture is released from the organic resin layer to the outside through the opening IOP, moisture may be captured from the outside through the opening IOP during the annealing process. By making the area of ​​the opening IOP smaller than the area of ​​the contact hole, it is possible to suppress the moisture released from the organic resin layer from being captured again.

[0082] Figures 4 to 6 In the structure of the display device 10 shown, the first inorganic layer is a pixel electrode PTCO and a sixth insulating layer IL6, and the second inorganic layer is a common electrode CTCO. An opening IOP is provided in the sixth insulating layer IL6. The common electrode CTCO is connected to the fifth insulating layer IL5 in the opening IOP. The common electrode CTCO is not connected to other conductive layers in the opening IOP provided in the pixel. In addition, the coverage rate of the sixth insulating layer IL6 covering the fifth insulating layer IL5 is 85% or more relative to the area of ​​the pixel.

[0083] In addition, the opening IOP provided in the sixth insulating layer IL6 is preferably provided in a region overlapping with the oxide semiconductor layer POS. By providing the opening IOP near the oxide semiconductor layer POS, the influence of moisture contained in the organic resin layer can be reduced. More preferably, the opening IOP is configured to overlap with a region overlapping with the gate wiring in the oxide semiconductor layer POS.

[0084] As described above, in a display device according to an embodiment of the present invention, it is possible to suppress the moisture contained in the organic resin layer provided on the transistor from being captured again from the outside into the organic resin layer after the moisture is released. By suppressing the intrusion of moisture from the organic resin layer into the oxide semiconductor layer, it is possible to suppress the change in the characteristics of the transistor. Therefore, the reliability of the display device can be improved.

[0085] [6. Method for manufacturing display device]

[0086] A method for manufacturing the display device 10 according to one embodiment of the present invention will be described. Figure 7 and Figure 8 It is a sequence diagram for explaining a method for manufacturing the display device 10 according to one embodiment of the present invention. Figures 9 to 18 It is a cross-sectional view for explaining a method for manufacturing the display device 10 according to one embodiment of the present invention.

[0087] First, light shielding layers LS1 and LS2 are formed on the substrate SUB as the light shielding layer LS (see Figure 7 The "LS formation" of step S1001 shown in FIG. Fig. 9 ).

[0088] As the substrate SUB, a glass substrate, a quartz substrate, a sapphire substrate or other light-transmitting rigid substrate can be used. When the substrate SUB needs to be flexible, a polyimide substrate, an acrylic substrate, a siloxane-based substrate, a fluororesin substrate or the like, or a substrate containing an organic resin can be used as the substrate SUB. When a substrate containing an organic resin is used as the substrate SUB, in order to improve the heat resistance of the substrate SUB, an impurity element can be introduced into the above-mentioned organic resin.

[0089] The light shielding layer LS is formed by, for example, processing a conductive layer formed by a sputtering method. As the light shielding layer LS, a common metal material can be used. As the light shielding layer LS, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof can be used. Fig. 9 As shown, after forming the light shielding layer LS1, the light shielding layer LS2 is formed to cover the light shielding layer LS1. In this embodiment, the light shielding layer LS1 and the light shielding layer LS2 are stacked, but they may be formed as a single layer.

[0090] Next, a first insulating layer IL1 is formed on the light shielding layer LS as a base layer (see Figure 7 Step S1002 "IL1 film formation" and Fig. 9 ).

[0091] The first insulating layer IL1 is formed by CVD (Chemical Vapor Deposition) or sputtering. A common insulating material can be used as the first insulating layer IL1. For example, silicon oxide (SiO x ), silicon oxide nitride (SiO x N y ), Silicon Nitride (SiN x ), silicon oxide nitride (SiN x O y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum nitride (AlN x O y ) and aluminum nitride (AlN x ) and other inorganic insulating materials.

[0092] The above SiO x N y and AlO x N y It is a silicon compound or aluminum compound containing nitrogen (N) at a ratio (x>y) less than oxygen (O). x O y and AlN x O y These are silicon compounds and aluminum compounds containing oxygen at a ratio smaller than that of nitrogen (x>y).

[0093] The first insulating layer IL1 is formed in a single-layer structure or a stacked structure. When the first insulating layer IL1 is set to a stacked structure, it is preferable to sequentially form an insulating material containing nitrogen and an insulating material containing oxygen from the substrate SUB. By using an insulating material containing nitrogen, for example, impurities diffusing from the substrate SUB side to the oxide semiconductor layer POS can be blocked. In addition, by using an insulating material containing oxygen, oxygen can be released by heat treatment. The temperature of the heat treatment for causing the insulating material containing oxygen to release oxygen is, for example, below 600°C, below 500°C, below 450°C, or below 400°C. That is, with respect to the insulating material containing oxygen, for example, oxygen is released at the heat treatment temperature performed in the manufacturing process of the display device when a glass substrate is used as the substrate SUB. In this embodiment, as the insulating material containing nitrogen, for example, silicon nitride is formed. As the insulating material containing oxygen, for example, silicon oxide is formed.

[0094] Next, a metal oxide layer MO1 mainly composed of aluminum is formed on the first insulating layer IL1 (see Figure 7 Step S1003 "MO1 film formation" and Fig.10 )

[0095] The metal oxide layer MO1 is formed by sputtering. The metal oxide layer mainly composed of aluminum can be made of, for example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum nitride (AlN x O y ), aluminum nitride (AlN x ) or the like. The so-called "metal oxide layer with aluminum as the main component" means that the ratio of aluminum contained in the metal oxide layer MO1 is more than 1% of the entire metal oxide layer MO1. The ratio of aluminum contained in the metal oxide layer MO1 can be more than 5% and less than 70%, more than 10% and less than 60%, or more than 30% and less than 50% of the entire metal oxide layer MO1. The above ratio can be a mass ratio or a weight ratio.

[0096] The thickness of the metal oxide layer MO1 is, for example, 2 nm to 100 nm, 2 nm to 50 nm, 2 nm to 30 nm, or 2 nm to 15 nm. In this embodiment, aluminum oxide can be used as the metal oxide layer MO1. Aluminum oxide has high barrier properties against gases.

[0097] Next, an amorphous oxide semiconductor layer AOS is formed on the metal oxide layer MO1 (see Figure 7 The "OS film formation" of step S1004 and Fig.10 ).

[0098] The oxide semiconductor layer AOS is formed by sputtering or atomic layer deposition (ALD) and has a thickness of, for example, 10 nm to 100 nm, 15 nm to 70 nm, or 20 nm to 40 nm.

[0099] As the oxide semiconductor layer AOS, a metal oxide having semiconductor properties can be used. As the oxide semiconductor layer AOS, for example, an oxide semiconductor containing two or more metals including indium (In) can be used. In addition, the ratio of indium in the two or more metals is 50% or more. As the oxide semiconductor layer AOS, in addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr) or lanthanide elements can be used. As the oxide semiconductor layer AOS, other elements other than the above may also be used. In this embodiment, as the oxide semiconductor layer AOS, a metal oxide containing indium (In) and gallium (Ga) is used.

[0100] In the case where the oxide semiconductor layer AOS is crystallized by the OS annealing treatment described later, it is preferred that the oxide semiconductor layer AOS is amorphous (a state where the oxide semiconductor has a small amount of crystal components) after film formation and before the OS annealing treatment. That is, it is preferred that the film formation method of the oxide semiconductor layer AOS is such that the oxide semiconductor layer AOS is as non-crystallized as possible immediately after film formation. For example, in the case where the oxide semiconductor layer AOS is formed by sputtering, the oxide semiconductor layer AOS is formed while controlling the temperature of the object to be formed (substrate SUB and the structure formed thereon).

[0101] If a film is formed on the film-forming object by sputtering, the ions generated in the plasma and the atoms recoiled by the sputtering target collide with the film-forming object, so the temperature of the film-forming object rises along with the film-forming process. If the temperature of the film-forming object rises during the film-forming process, the oxide semiconductor layer AOS contains microcrystals in the state just after the film is formed, which will hinder the subsequent crystallization based on the OS annealing process. In order to control the temperature of the film-forming object as described above, for example, the film can be formed while the film is cooled. For example, the film-forming object can be cooled from the surface opposite to the film-forming surface in a manner such that the temperature of the film-forming surface of the film-forming object (hereinafter referred to as the "film-forming temperature") is below 100°C, below 70°C, below 50°C, or below 30°C. As described above, by cooling the film-forming object while forming the oxide semiconductor layer AOS, it is possible to form an oxide semiconductor layer AOS with a small crystal component in the state just after the film is formed.

[0102] Next, the oxide semiconductor layer AOS is patterned ( Figure 7 Although not shown in the figure, a resist mask is formed on the oxide semiconductor layer AOS, and the oxide semiconductor layer AOS is etched using the resist mask. As the etching of the oxide semiconductor layer AOS, wet etching can be used, or dry etching can be used. As wet etching, etching can be performed using an acidic etchant. As the etchant, for example, oxalic acid or hydrofluoric acid can be used.

[0103] It is preferred that the oxide semiconductor layer AOS is patterned before the OS annealing treatment. If the oxide semiconductor layer AOS is crystallized by the OS annealing treatment, it tends to be difficult to etch. In addition, even if damage is caused in the oxide semiconductor layer AOS by etching, the damage can be repaired by the OS annealing treatment, so it is preferred.

[0104] After the patterning of the oxide semiconductor layer AOS, the oxide semiconductor layer AOS is subjected to a heat treatment (OS annealing treatment) ( Figure 7 The "OS annealing process" of step S1006 shown in FIG. Fig.11 ). During the OS annealing treatment, the oxide semiconductor layer AOS is maintained at a predetermined reaching temperature for a predetermined time. The predetermined reaching temperature is between 300°C and 500°C, preferably between 350°C and 450°C. In addition, the holding time at the reaching temperature is between 15 minutes and 120 minutes, preferably between 30 minutes and 60 minutes. By performing the OS annealing treatment, the oxide semiconductor layer AOS is crystallized to form an oxide semiconductor layer POS having a polycrystalline structure.

[0105] Next, the oxide semiconductor layer POS is used as a mask to form a pattern of the metal oxide layer MO1 ( Figure 7 Step S1007 "MO1 pattern formation" and Fig.12 ). The metal oxide layer MO1 is etched using the crystallized oxide semiconductor layer POS as a mask. As the etching of the metal oxide layer MO1, wet etching or dry etching can be used. As wet etching, for example, diluted hydrofluoric acid (DHF) can be used. Compared with the amorphous oxide semiconductor layer AOS, the crystallized oxide semiconductor layer POS has etching resistance to diluted hydrofluoric acid. Therefore, the metal oxide layer MO1 can be etched using the oxide semiconductor layer POS as a mask. As a result, the photolithography process can be omitted.

[0106] Next, a second insulating layer IL2 is formed on the oxide semiconductor layer POS ( Figure 7 The "IL2 film formation" of step S1008 shown in FIG. Fig.13 ).

[0107] The film formation method and insulating material of the second insulating layer IL2 may refer to the description of the first insulating layer IL1. The film thickness of the second insulating layer IL2 is, for example, not less than 50 nm and not more than 150 nm.

[0108] As the second insulating layer IL2, an insulating material containing oxygen is preferably used. In addition, as the second insulating layer IL2, an insulating layer with fewer defects is preferably used. For example, when the composition ratio of oxygen in the second insulating layer IL2 is compared with the composition ratio of oxygen in an insulating layer having the same composition as the second insulating layer IL2 (hereinafter referred to as "other insulating layer"), the composition ratio of oxygen in the second insulating layer IL2 is closer to the stoichiometric ratio with respect to the insulating layer than the composition ratio of oxygen in the other insulating layer. For example, silicon oxide (SiO2) is used for each of the second insulating layer IL2 and the third insulating layer IL3. x ), the oxygen composition ratio of silicon oxide used as the second insulating layer IL2 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio of silicon oxide used as the third insulating layer IL3. For example, a layer in which no defects are observed when evaluated by an electron spin resonance method (ESR) can be used as the second insulating layer IL2.

[0109] In order to form an insulating layer with few defects as the second insulating layer IL2, the second insulating layer IL2 may be formed at a film forming temperature of 350° C. or higher. In addition, after the second insulating layer IL2 is formed, a process of implanting oxygen into a portion of the second insulating layer IL2 may be performed. In this embodiment, in order to form an insulating layer with few defects as the second insulating layer IL2, silicon oxide is formed at a film forming temperature of 350° C. or higher.

[0110] Next, a metal oxide layer MO2 containing aluminum as a main component is formed on the second insulating layer IL2 ( Figure 7 The "MO2 film formation" of step S1009 shown in FIG. Fig.13 ).

[0111] The film forming method and insulating material of the metal oxide layer MO2 may refer to the description of the metal oxide layer MO1. Oxygen is injected into the second insulating layer IL2 by forming the metal oxide layer MO2. The film thickness of the metal oxide layer MO2 is, for example, greater than 2nm and less than 100nm, greater than 2nm and less than 50nm, greater than 2nm and less than 30nm, or greater than 2nm and less than 15nm. In this embodiment, aluminum oxide can be used as the metal oxide layer MO2. Aluminum oxide has a high barrier property against gas. In this embodiment, aluminum oxide used as the metal oxide layer MO2 suppresses the outward diffusion of oxygen injected into the second insulating layer IL2 during the formation of the metal oxide layer MO2.

[0112] For example, when the metal oxide layer MO2 is formed by sputtering, the process gas used in sputtering remains in the film of the metal oxide layer MO2. For example, when Ar is used as the process gas for sputtering, Ar sometimes remains in the film of the metal oxide layer MO2. The remaining Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis of the metal oxide layer MO2.

[0113] In a state where the second insulating layer IL2 is formed on the oxide semiconductor layer POS and the metal oxide layer MO2 is formed on the second insulating layer IL2, a heat treatment (oxidation annealing treatment) for supplying oxygen to the oxide semiconductor layer POS is performed ( Figure 7 The "oxidation annealing treatment" of step S1010 shown in FIG. Fig.13 ).

[0114] In the process from when the oxide semiconductor layer POS is formed to when the second insulating layer IL2 is formed on the oxide semiconductor layer POS, many oxygen defects are generated on the upper surface and side surfaces of the oxide semiconductor layer POS. Through the above-mentioned oxidation annealing treatment, oxygen released from the first insulating layer IL1 is supplied to the upper surface and side surfaces of the oxide semiconductor layer POS, and the oxygen defects are repaired.

[0115] In the above-described oxidation annealing treatment, oxygen injected into the second insulating layer IL2 is blocked by the metal oxide layer MO2, thereby suppressing release into the atmosphere. Therefore, through the oxidation annealing treatment, the oxygen is efficiently supplied to the oxide semiconductor layer POS, and oxygen defects are repaired.

[0116] Next, after the oxidation annealing treatment, the metal oxide layer MO2 is etched (removed) ( Figure 7 The "MO2 removal" of step S1011 shown in FIG. Fig.14 ). As the etching of the metal oxide layer MO2, wet etching or dry etching can be used. As wet etching, for example, diluted hydrofluoric acid (DHF) can be used. By this etching, the metal oxide layer MO2 formed on the entire surface is removed. In other words, the removal of the metal oxide layer MO2 is performed without using a mask. In further other words, by this etching, at least the entire metal oxide layer MO2 in the area overlapping with the oxide semiconductor layer POS formed into a certain pattern when viewed from above is removed.

[0117] Next, a gate wiring GL ( Figure 7 Step S1012 "GL formation" and Fig.15 The film forming method and insulating material of the gate wiring GL may refer to the description of the light shielding layer LS. The gate wiring GL is arranged along the first direction D1.

[0118] Next, using the gate wiring GL as a mask, impurities are added to the oxide semiconductor layer POS ( Figure 7 Step S1013 "SA, DA formation" and Fig.15 ). In this embodiment, the case where impurities are added by ion implantation is described, but it can also be done by ion doping.

[0119] Specifically, by ion implantation, an impurity element is added to the oxide semiconductor layer POS through the second insulating layer IL2, thereby forming a source region SA and a drain region DA. As the impurity element, for example, argon (Ar), phosphorus (P), or boron (B) may be used. In addition, when boron (B) is added by ion implantation, the acceleration energy is set to 20 keV or more and 40 keV or less, and the implantation amount of boron (B) is set to 1×10 14 cm -2 Above 1×10 16 cm -2 The following will do.

[0120] The concentration of the impurity element contained in the source region SA and the drain region DA is preferably 1×10 18 cm -3 Above 1×10 21 cm -3 In addition, the source region SA and the drain region DA include 1×10 18 cm -3 Above 1×1021 cm -3 In the following cases, it is presumed that the impurity element is actively added by an ion implantation method or a doping method.

[0121] Next, a third insulating layer IL3 is formed on the second insulating layer IL2 and the gate wiring GL ( Figure 7 Step S1014 "IL3 film formation" and Fig.16 The film forming method and insulating material of the third insulating layer IL3 may refer to the description of the first insulating layer IL1.

[0122] Next, a contact hole WCON reaching the source region SA is formed in the third insulating layer IL3. Then, a wiring W1 is formed on the third insulating layer IL3, and the wiring W1 is connected to the source region SA via the contact hole ZCON ( Figure 7 Step S1015 "W1 formation" and Fig.16 The film forming method and insulating material of the wiring W1 may refer to the description of the light shielding layer LS. The wiring W1 is arranged along the second direction D2.

[0123] Next, a fourth insulating layer IL4 is formed on the third insulating layer IL3 and the wiring W1 ( Figure 8 Step S1016 "IL4 film formation" and Fig.16 The film forming method and insulating material of the fourth insulating layer IL4 may refer to the description of the first insulating layer IL1.

[0124] Next, a contact hole ZCON reaching the drain region DA is formed in the fourth insulating layer IL4. Then, a connection electrode ZTCO is formed on the fourth insulating layer IL4 and connected to the drain region DA via the contact hole ZCON ( Figure 8 Step S1017 "ZTCO formation" and Fig.16 ).

[0125] The connecting electrode ZTCO is formed by processing a light-transmitting oxide conductive layer (also referred to as a transparent conductive layer) formed by sputtering. As the oxide conductive layer, a transparent conductive material such as a mixture of indium oxide and tin oxide (ITO) or a mixture of indium oxide and zinc oxide (IZO) can be used. As the oxide conductive layer, a transparent conductive material other than the above can also be used.

[0126] Next, a fifth insulating layer IL5 is formed on the fourth insulating layer IL4 and the connection electrode ZTCO ( Figure 8 Step S1018 "IL5 film formation" and Fig.17 ).

[0127] The fifth insulating layer is formed by applying an organic insulating material and baking it. As the organic insulating material, an organic resin such as polyimide resin, acrylic resin, epoxy resin, silicone resin, fluororesin or siloxane resin is used. After that, a part of the fifth insulating layer is exposed and removed to form a contact hole PCON exposing the connection electrode ZTCO.

[0128] Next, a pixel electrode PTCO is formed on the fifth insulating layer IL5, and the pixel electrode PTCO is connected to the connection electrode ZTCO via the contact hole PCON ( Figure 8 Step S1019 "PTCO formation" and Fig.17 ). The film forming method and transparent conductive material of the pixel electrode PTCO may refer to the description of the connection electrode ZTCO.

[0129] Next, a sixth insulating layer IL6 is formed on the pixel electrode PTCO ( Figure 8 Step S1020 "IL6 film formation" and Fig.17 ).

[0130] The film forming method and insulating material of the sixth insulating layer IL6 may refer to the description of the first insulating layer IL1. The sixth insulating layer IL6 functions as a dielectric for forming a capacitor. In addition, the sixth insulating layer IL6 functions as a first inorganic layer. The film thickness of the sixth insulating layer IL6 is at least 30 nm or more and 50 nm or more and 200 nm or less. In this embodiment, silicon nitride is used to form the sixth insulating layer IL6.

[0131] Next, an opening IOP ( Figure 8 Step S1021 "IOP formation" and Fig.17 As described above, the opening IOP is provided to release moisture contained in the fifth insulating layer IL5.

[0132] It is preferred that the area of ​​the opening IOP is formed to be less than 15% relative to the area of ​​the pixel. In other words, the coverage rate of the sixth insulating layer IL6 covering the fifth insulating layer IL5 is 85% or more, preferably 90% or more, and more preferably 95% or more relative to the area of ​​the pixel. The opening IOP is not limited to one in each pixel, and may be multiple. In addition, in the case where multiple openings IOP are provided in each pixel, the total area of ​​the multiple openings IOP may be less than 15% relative to the area of ​​the pixel. It is preferred that the opening IOP is provided in a region overlapping with the oxide semiconductor layer POS. In addition, it is more preferred that the opening IOP is configured in a region overlapping with a region where the gate wiring overlaps in the oxide semiconductor layer POS (i.e., the channel region CA). By providing the opening IOP in a region overlapping with the oxide semiconductor layer POS or the channel region CA of the oxide semiconductor layer POS, the moisture contained in the organic resin layer can be released to the outside by the annealing process described later, and the moisture contained in the organic resin layer can be suppressed from intruding into the oxide semiconductor layer POS. However, the position where the opening IOP is provided is not limited to the above position, and may be provided, for example, at a position overlapping with the wiring W1 or at a position not overlapping with the oxide semiconductor layer POS.

[0133] Next, in a state where the sixth insulating layer IL6 covers the fifth insulating layer IL5, an annealing process is performed ( Figure 8 Step S1022 "annealing treatment" and Fig.17 The temperature of the annealing treatment is, for example, not less than 150° C. and not more than 300° C. By performing the annealing treatment, moisture contained in the fifth insulating layer IL5 can be released.

[0134] Next, a common auxiliary electrode CMTL ( Figure 8 Step S1023 "CMTL formation" and Fig.18 ).

[0135] The film formation method and conductive material of the common auxiliary electrode CMTL may refer to the description of the light shielding layer LS. The common auxiliary electrode CMTL is formed in a lattice shape so as to overlap with the gate wiring GL and the wiring W1.

[0136] Next, a common electrode CTCO ( Figure 8 Step S1024 "CTCO formation" and Fig.18). The film forming method and transparent conductive material of the common electrode CTCO can refer to the description of the connecting electrode ZTCO. The common electrode CTCO functions as the second inorganic layer. The film thickness of the common electrode CTCO can be at least 30nm or more and 50nm or more and 200nm or less. By forming the common electrode CTCO, the common electrode CTCO is connected to the fifth insulating layer IL5 in the opening IOP. That is, the common electrode CTCO can block the opening IOP provided in the sixth insulating layer IL6. Thereby, it is possible to suppress moisture from being captured from the outside into the fifth insulating layer IL5 through the opening IOP.

[0137] Next, a spacer SP is formed on the common electrode CTCO. Figure 8 In step S1025 (“SP formation”), a spacer SP is formed in the contact hole PCON. Finally, the array substrate manufactured as described above is bonded to the counter substrate on which the color filter and the spacer are formed via the sealing material and the liquid crystal layer.

[0138] Through the above steps, the display device 10 according to one embodiment of the present invention can be manufactured.

[0139] Typically, in a liquid crystal display device of the FFS method, a pixel electrode, a capacitor insulating layer and a common electrode are stacked on an organic resin layer, or a common electrode, a capacitor insulating layer and a pixel electrode are stacked. When a pixel electrode is arranged on an organic resin layer, in order to suppress the capacitive coupling between the pixel electrode and the wiring, the pixel electrode is mostly configured in a non-overlapping manner with the source wiring, etc. In addition, a slit pattern is sometimes provided on the pixel electrode. Therefore, the coverage rate of the pixel electrode covering the pixel is less than 85% relative to the area of ​​the pixel. In addition, when a common electrode is arranged on an organic resin layer, a slit pattern is sometimes provided on the common electrode and an opening is provided above the transistor. Therefore, the coverage rate of the pixel covered by the common electrode is less than 85% relative to the area of ​​the pixel. Therefore, even if an annealing process is performed in a state where a pixel electrode or a common electrode is arranged on the organic resin layer, although moisture can be released from the organic resin layer, moisture will be captured again in subsequent processing. The moisture contained in the organic resin layer invades the oxide semiconductor layer, thereby changing the characteristics of the transistor.

[0140] In addition, in the FFS liquid crystal display device, a capacitor insulating layer is provided on the organic resin layer, on the pixel electrode or the common electrode in a manner covering the active area. Even if the annealing treatment is performed in a state where the capacitor insulating layer is formed on the entire surface, the moisture contained in the organic resin layer is still blocked by the capacitor insulating layer and the pixel electrode, and the moisture cannot be released from the organic resin layer. Therefore, the excess moisture remains in the organic resin layer, and the moisture invades the oxide semiconductor layer, and the characteristics of the transistor will change.

[0141] In a method for manufacturing a display device according to an embodiment of the present invention, after the moisture contained in the fifth insulating layer IL5 formed of an organic resin is fully released from the opening IOP formed in the first inorganic layer by annealing, the opening IOP is blocked by the second inorganic layer. Thus, a state in which the amount of moisture contained in the organic resin layer is reduced can be maintained. Therefore, it is possible to suppress the moisture contained in the organic resin layer from invading the oxide semiconductor layer. Thus, since it is possible to suppress the variation of the characteristics of the transistor, it is possible to improve the reliability of the display device.

[0142] [7. Crystal structure of oxide semiconductor layer]

[0143] The oxide semiconductor layer POS described in this embodiment includes Poly-OS. The crystal grain size of the crystal grains contained in the Poly-OS observed from the upper surface of the oxide semiconductor layer POS (or the film thickness direction of the oxide semiconductor layer POS) is greater than 0.1 μm, preferably greater than 0.3 μm, and more preferably greater than 0.5 μm. The crystal grain size of the crystal grain can be obtained, for example, using cross-sectional SEM observation, cross-sectional TEM observation, or electron backscattered diffraction (EBSD) method.

[0144] In Poly-OS, a plurality of crystal grains may have one crystal structure or multiple crystal structures. The crystal structure of Poly-OS can be determined using electron diffraction or XRD. That is, the crystal structure of the oxide semiconductor layer POS can be determined using electron diffraction or XRD.

[0145] The crystal structure of the oxide semiconductor layer POS is preferably cubic. The symmetry of the cubic crystal structure is high, and even if oxygen defects are generated in the oxide semiconductor layer POS, it is not easy to cause structural relaxation, and the crystal structure is stable. As described above, by increasing the ratio of the indium element, the crystal structure of each of the plurality of crystal grains is controlled, and an oxide semiconductor layer POS having a cubic crystal structure can be formed.

[0146] In the transistor including the oxide semiconductor layer POS manufactured by the above manufacturing method, a mobility of 50 cm-1 can be obtained when the channel length L of the channel region CA is in the range of 2 μm to 4 μm and the channel width of the channel region CA is in the range of 2 μm to 25 μm. 2 / Vs or above, 55cm 2 / Vs or above or 60cm 2The mobility in this embodiment is the field effect mobility in the saturation region of the transistor, and refers to the maximum value of the field effect mobility in the region where the potential difference (Vd) between the source electrode and the drain electrode is greater than the value (Vg-Vth) obtained by subtracting the threshold voltage (Vth) of the transistor from the voltage supplied to the gate electrode (Vg).

[0147] In the formation process of the transistor Tr, the formation of the metal oxide layer MO1 provided under the oxide semiconductor layer POS may be omitted. In this case, the formation of the metal oxide layer MO1 provided under the oxide semiconductor layer POS may be omitted. Figure 7 In the process of forming the transistor Tr, after the metal oxide layer MO2 is formed on the second insulating layer IL2, the process of performing the annealing treatment may be omitted. In this case, the annealing treatment may be omitted. Figure 7 The process of step S1009 and step S1011 shown in FIG. Even when the formation of the metal oxide layer MO1 or the formation of the metal oxide layer MO2 is omitted, a good Poly-OS can be formed.

[0148] In the transistor formation process, even if the above process is omitted, Poly-OS can be formed. In the transistor using Poly-OS as the oxide semiconductor layer POS, when the channel length L of the channel region CA is 2 μm to 4 μm and the channel width of the channel region CA is 2 μm to 25 μm, a mobility of 30 cm 2 / Vs or above, 35cm 2 / Vs or above or 40cm 2 / Vs and above electrical characteristics.

[0149] It should be noted that IGZO may be used instead of the oxide semiconductor layer POS. Even when IGZO is used as the oxide semiconductor material, it is preferred to perform annealing in a state where the first inorganic layer provided on the fifth insulating layer IL5 formed of an organic resin has an opening, so that the moisture contained in the organic resin layer is released from the opening. Thereafter, by forming the second inorganic layer in a manner of blocking the opening, it is possible to suppress the capture of moisture from the outside into the organic resin layer, and to suppress the variation of the characteristics of the transistor. Thus, the reliability of the display device can be improved.

[0150] [8. Modification 1]

[0151] In modification 1, refer to Fig.19 Description Partly with Figure 4 The display device shown is a different display device 10A. Fig.19, a structure in which the opening IOP provided in the sixth insulating layer IL6 is blocked by the seventh insulating layer IL7 is shown.

[0152] Fig.19 In the display device 10A shown, the sixth insulating layer IL6 and the seventh insulating layer IL7 are provided between the pixel electrode PTCO and the common electrode CTCO. The common electrode CTCO has a slit pattern in the region overlapping with the pixel electrode PTCO. The film forming method and insulating material of the seventh insulating layer IL7 may refer to the description of the first insulating layer IL1. The thickness of the sixth insulating layer IL6 and the seventh insulating layer IL7 may be appropriately set according to the capacitance of the holding capacitor 890. The thickness of the seventh insulating layer IL7 may be smaller than the thickness of the sixth insulating layer IL6. The common electrode CTCO is provided on the seventh insulating layer IL7. If the thickness of the seventh insulating layer IL7 and the common electrode CTCO is at least 30 nm or more and 50 nm or more and 200 nm or less, the capture of moisture from the outside can be suppressed. In variant example 1, at least the sixth insulating layer IL6 may be included as the first inorganic layer, and at least the seventh insulating layer IL7 may be included as the second inorganic layer.

[0153] [9. Modification 2]

[0154] In modification 2, refer to Fig. 20 Description Partly with Figure 4 The display device 10 shown is a different display device 10B. Fig. 20 , a structure in which the opening IOP provided in the sixth insulating layer IL6 is blocked by the common auxiliary electrode CMTL is shown. In addition, a color filter CF is provided between the fourth insulating layer IL4 and the fifth insulating layer IL5.

[0155] Fig. 20 In the display device 10B shown, the opening portion IOP provided in the sixth insulating layer IL6 is provided above the wiring W1. In the present embodiment, a common auxiliary electrode CMTL is provided above the wiring W1. Therefore, the opening portion IOP can be blocked by the common auxiliary electrode CMTL. In addition, a common electrode CTCO is provided above the sixth insulating layer IL6 and the common auxiliary electrode CMTL. If the thickness of the common auxiliary electrode CMTL is at least 30 nm or more and 50 nm or more and 200 nm or less, the capture of moisture from the outside can be suppressed. In variant example 2, it is sufficient to include at least the sixth insulating layer IL6 as the first inorganic layer, and it is sufficient to include at least the common auxiliary electrode CMTL as the second inorganic layer. Thus, it is possible to suppress the entry of moisture from the outside through the opening portion IOP.

[0156] In a liquid crystal display device, when a color filter is provided on the opposing substrate, positional displacement may occur when the array substrate formed with transistors and the opposing substrate are bonded. In a high-definition liquid crystal display device such as a VR, the display quality of the display device is reduced due to a slight positional displacement between the pixels of the array substrate and the color filter of the opposing substrate. Therefore, by forming a color filter CF between the fourth insulating layer IL4 and the fifth insulating layer IL5, the positional displacement between the array substrate and the color filter when the array substrate and the opposing substrate are bonded can be suppressed. In addition, since the color filter CF is also formed of an organic resin, it also contains moisture. After the moisture contained in the color filter CF and the moisture contained in the fifth insulating layer IL5 are released from the opening IOP formed in the sixth insulating layer IL6 by annealing, the opening IOP is blocked by the common auxiliary electrode CMTL, thereby suppressing the moisture from being captured again from the outside to the fifth insulating layer IL5 and the color filter CF through the opening IOP.

[0157] It should be noted that, although not shown in the figure, Figure 4 , Fig.19 The display device shown and the following description Fig.21 , Fig. 22 The display device shown in the figure can also be applied to a structure in which a color filter CF is provided between the fourth insulating layer IL4 and the fifth insulating layer IL5.

[0158] [10. Modification 3]

[0159] In modification 3, refer to Fig.21 Description Partly with Figure 4 The display device 10 shown is a different display device 10C. Fig.21 , a structure in which a capacitor electrode CTCO1 is provided on the fifth insulating layer IL5 is shown.

[0160] Fig.21 In the display device 10C shown, a capacitor electrode CTCO1 is provided on the fifth insulating layer IL5. A holding capacitor is formed by the capacitor electrode CTCO1, the sixth insulating layer IL6 and the pixel electrode PTCO, and a holding capacitor is formed by the pixel electrode PTCO, the seventh insulating layer IL7 and the common electrode CTCO2. The sixth insulating layer IL6 is provided on the capacitor electrode CTCO1, so that the coverage rate of the capacitor electrode CTCO1 covering the fifth insulating layer IL5 with respect to the area of ​​the pixel is less than 85%. An opening may also be provided in the capacitor electrode CTCO1.

[0161] A sixth insulating layer IL6 is provided on the capacitor electrode CTCO1. It is preferred that the coverage rate of the sixth insulating layer IL6 covering the fifth insulating layer IL5 is 85% or more relative to the area of ​​the pixel. In addition, the opening portion IOP may overlap with the opening portion provided in the capacitor electrode CTCO1. A seventh insulating layer IL7 is provided on the sixth insulating layer IL6. The seventh insulating layer IL7 is provided in a manner that blocks the opening portion IOP and the opening portion provided in the capacitor electrode CTCO1. Therefore, the seventh insulating layer IL7 is in contact with the fifth insulating layer IL5 in the opening portion.

[0162] Furthermore, a common electrode CTCO2 is provided on the seventh insulating layer IL7. Fig.21 , an example in which the opening portion provided in the capacitor electrode CTCO1 overlaps with the opening portion IOP is shown, but the present invention is not limited thereto. The opening portion may be not formed in the capacitor electrode CTCO1, but the opening portion IOP may be formed in the sixth insulating layer IL6. In the modification example 3, at least the sixth insulating layer IL6 may be included as the first inorganic layer, and at least the seventh insulating layer IL7 may be included as the second inorganic layer.

[0163] In addition, the film thickness of the seventh insulating layer IL7 can be, for example, at least 30 nm or more, 50 nm or more and 200 nm or less. In addition, the film forming method and transparent conductive material of the capacitor electrode CTCO1 and the common electrode CTCO2 can refer to the description of the connecting electrode ZTCO. The film thickness of the capacitor electrode CTCO1 and the film thickness of the common electrode CTCO2 can be at least 30 nm or more, 50 nm or more and 200 nm or less.

[0164] [11. Modification 4]

[0165] In modification 4, refer to Fig. 22 Description Partly with Figure 4 The display device 10 shown is a display device 10D which is different from the display device 10. In the display device 10, the wiring W1 and the connection electrode ZTCO functioning as a drain electrode are provided on different insulating layers, but the wiring W1 and the connection electrode ZTCO may be provided on the same insulating layer.

[0166] Fig. 22In the display device 10D shown, the following structure is shown: the fourth insulating layer IL4 is omitted, and the wiring W1 and the drain electrode DE are provided on the third insulating layer IL3. The fifth insulating layer IL5 is provided on the wiring W1 and the drain electrode DE, and the contact hole PCON is formed in the fifth insulating layer IL5. The pixel electrode PTCO is provided on the fifth insulating layer IL5, and the pixel electrode PTCO and the drain electrode DE are connected via the contact hole PCON. The sixth insulating layer IL6 is provided on the fifth insulating layer IL5 and the pixel electrode PTCO. The opening IOP is provided in the sixth insulating layer IL6. The opening IOP is blocked by the common electrode CTCO provided on the sixth insulating layer IL6. In the modification example 4, at least the sixth insulating layer IL6 may be included as the first inorganic layer, and the common electrode CTCO may be included as the second inorganic layer.

[0167] As the embodiments of the present invention, the embodiments described above can be implemented in appropriate combination as long as they do not contradict each other. In addition, based on the display device of each embodiment, the solution obtained by the technicians in this field by appropriately adding, deleting or changing the design of the components, or by adding, omitting or changing the conditions of the process, is included in the scope of the present invention as long as it has the gist of the present invention.

[0168] Even if there are other effects different from the effects brought about by the above-mentioned embodiments, it should be understood that the effects that are clear from the description of this specification or the effects that can be easily predicted by those skilled in the art are the effects brought about by the present invention.

Claims

1. A display device comprising a plurality of pixels arranged in a matrix along a first direction and a second direction intersecting the first direction, Each of the plurality of pixels has: A transistor comprising an oxide semiconductor layer, a gate wiring which is opposed to the oxide semiconductor layer and extends in the first direction, and a gate insulating layer between the oxide semiconductor layer and the gate wiring; a first conductive layer disposed on at least one first insulating layer on the transistor and in contact with the oxide semiconductor layer; a second insulating layer disposed on the first conductive layer; a first inorganic layer provided on the second insulating layer and having an opening; and a second inorganic layer provided on the first inorganic layer and in contact with the second insulating layer in the opening; Here, the coverage rate of the first inorganic layer covering the first insulating layer is 85% or more with respect to the area of ​​the pixel.

2. The display device according to claim 1, wherein: The first inorganic layer includes a second transparent conductive layer and a first inorganic insulating layer provided on the second transparent conductive layer. The second transparent conductive layer is connected to the first conductive layer. The first inorganic insulating layer is provided with the opening.

3. The display device according to claim 2, wherein: The second inorganic layer includes a third transparent conductive layer, The third transparent conductive layer is in contact with the second insulating layer in the opening, and has a slit pattern in a region overlapping with the second transparent conductive layer.

4. The display device according to claim 2, wherein: The second inorganic layer includes a second inorganic insulating layer, The second inorganic insulating layer is in contact with the second insulating layer in the opening.

5. The display device according to claim 4, wherein: The second inorganic layer further includes a fourth transparent conductive layer disposed on the second inorganic insulating layer. The fourth transparent conductive layer has a slit pattern in a region overlapping with the second transparent conductive layer.

6. The display device according to claim 2, wherein: The second inorganic layer includes a metal layer, The metal layer is in contact with the second insulating layer in the opening.

7. The display device according to claim 1, wherein: The first inorganic layer includes a first inorganic insulating layer and a second transparent conductive layer provided on the first inorganic insulating layer. The second transparent conductive layer is connected to the first conductive layer via a contact hole provided in the first inorganic insulating layer. The first inorganic insulating layer is provided with the opening.

8. The display device according to claim 7, wherein: The second inorganic layer includes a second inorganic insulating layer, The second inorganic insulating layer is in contact with the second insulating layer in the opening.

9. The display device according to claim 1, further comprising a first wiring, the first wiring being provided between the transistor and the first conductive layer and being in contact with the oxide semiconductor layer, The first conductive layer has light-transmitting properties.

10. The display device according to claim 1, further comprising a first wiring, the first wiring being provided on the first insulating layer and being in contact with the oxide semiconductor layer, The first wiring is provided along the second direction.

11. The display device according to claim 1, wherein: The opening is provided in a region overlapping with the oxide semiconductor layer.

12. The display device according to claim 1, wherein: The opening is arranged in a region overlapping with a region of the oxide semiconductor layer that overlaps with the gate wiring.

13. The display device according to claim 1, wherein: The oxide semiconductor layer has a polycrystalline structure. 14 . The display device according to claim 1 , further comprising an aluminum oxide layer between the gate insulating layer and the oxide semiconductor layer.

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