Electronic device

Abstract

The invention discloses an electronic device which comprises a substrate, a shading layer, a first insulating layer, a semiconductor layer, a second insulating layer and a drain. The shading layer is arranged on the substrate. The first insulating layer is disposed on the light shielding layer. The semiconductor layer is disposed on the first insulating layer. The second insulating layer is disposed on the semiconductor layer and has a hole exposing a portion of the first insulating layer. The drain electrode is connected with the semiconductor layer through the hole. A first minimum distance exists between the part of the first insulating layer and the light shielding layer, a second minimum distance exists between the semiconductor layer and the light shielding layer, and the ratio of the first minimum distance to the second minimum distance is larger than or equal to 0.1 and smaller than or equal to 1.0.

Description

Technical Field

[0001] The invention relates to an electronic device, in particular to an electronic device comprising a light shielding layer and an insulating layer. Background Art

[0002] With the advancement of technology, electronic devices have become an indispensable item in modern people's lives. The components in electronic devices can be electrically connected to each other through contact holes, and the distance between components in products with small pixel sizes will be reduced. In the vicinity of the contact holes, other layers may be exposed due to etching, patterning and other processes, causing short circuits in subsequent layers. Summary of the invention

[0003] The main purpose of the present invention is to provide an electronic device to reduce the probability of short circuit, thereby improving the reliability of the electronic device.

[0004] To achieve the above-mentioned purpose, one embodiment of the present invention provides an electronic device, which includes a substrate, a light shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer and a drain. The light shielding layer is arranged on the substrate. The first insulating layer is arranged on the light shielding layer. The semiconductor layer is arranged on the first insulating layer. The second insulating layer is arranged on the semiconductor layer and has a hole, and the hole exposes a part of the first insulating layer. The drain is connected to the semiconductor layer through the hole. There is a first minimum distance between the above-mentioned part of the first insulating layer and the light shielding layer, and there is a second minimum distance between the semiconductor layer and the light shielding layer, and the ratio of the first minimum distance to the second minimum distance is greater than or equal to 0.1 and less than or equal to 1.0. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 FIG. 1 is a partial top view of an electronic device according to a first embodiment of the present invention.

[0006] Figure 2 FIG. 1 is a partial cross-sectional diagram of an electronic device according to a first embodiment of the present invention.

[0007] Figure 3 for Figure 2 A partial enlarged schematic diagram of the electronic device shown.

[0008] Figure 4 FIG. 4 is a partial cross-sectional diagram of an electronic device according to a second embodiment of the present invention.

[0009] Figure 5 FIG. 4 is a partial cross-sectional diagram of an electronic device according to a third embodiment of the present invention.

[0010] Explanation of the reference numerals: 100-substrate; 100a, IPa, LSa-upper surface; 110-thin film transistor; D1-first distance; D2-second distance; D3-third distance; DE-drain; Df-difference; DL-data line; DR-direction; e1, e2, e3, e4, e5-edge; ED-electronic device; GE-gate; GL-scan line; H1-first minimum distance; H2-second minimum distance; I1-first insulating layer; I2-second insulating layer; I3-third insulating layer; I4-fourth insulating layer; I5-fifth insulating layer; IP-portion; LS-shading layer; LSU-shading element; M1-first conductive layer; M2-second conductive layer; M3-third conductive layer; M4-fourth conductive layer; PL-plane; R-region; SC-semiconductor layer; SE-source; V1, V2, V3-holes; W-width. DETAILED DESCRIPTION

[0011] The present invention is described in detail with reference to specific embodiments and drawings. It should be noted that, in order to make it easier for readers to understand and to keep the drawings concise, the multiple drawings in the present invention only depict a portion of the device or structure, and the specific elements in the drawings are not drawn according to the actual scale. In addition, the number and size of each element in the drawing are only for illustration and are not intended to limit the scope of the present invention.

[0012] Certain words are used throughout the specification and claims of the present invention to refer to specific components. It should be understood by those skilled in the art that electronic equipment manufacturers may refer to the same components by different names. The present invention is not intended to distinguish between components that have the same function but different names. In the specification and claims of the present invention, the words "comprise", "include" and "have" are open-ended words, and therefore should be interpreted as "including but not limited to..." When the terms "comprise", "include" and / or "have" are used in this specification, they specify the presence of the features, regions, steps, operations and / or elements, but do not exclude the presence or addition of one or more other features, regions, steps, operations, elements and / or combinations thereof.

[0013] When an element or film layer is referred to as being "on" or "connected to" another element or film layer, it may be directly on or directly connected to the other element or film layer, or there may be intervening elements or film layers between the two. Conversely, when an element is referred to as being "directly on" or "directly connected to" another element or film layer, there may be no intervening elements or film layers between the two.

[0014] Directional terms mentioned in the present invention, such as "upper", "lower", "front", "back", "left", "right", etc., are only used to refer to the directions of the accompanying drawings. Therefore, the directional terms used are used for explanation, not for limiting the present invention.

[0015] The ordinal numbers used in the specification and claims, such as "first", "second", etc., are used to modify the elements. They do not imply or represent any previous ordinal numbers of the element (or elements), nor do they represent the order of one element and another element, or the order of the manufacturing method. The use of these ordinal numbers is only used to make the element with a certain name clearly distinguishable from another element with the same name. The same words may not be used in the claims and the specification. Accordingly, the first component in the specification may be the second component in the claims.

[0016] According to the embodiment of the present invention, the thickness, length, width and / or distance between components of each component can be measured by using an optical microscope (OM), a scanning electron microscope (SEM) or other suitable methods. For example, the thickness, length, width and / or distance between components of each component can be measured from a cross-sectional image obtained by a scanning electron microscope, but the invention is not limited thereto.

[0017] The terms "equal," "equal" or "same," "substantially" or "approximately" are generally interpreted as being within 20% of a given value or range, or within 10%, 5%, 3%, 2%, 1% or 0.5% of a given value or range.

[0018] The electronic device described in the present invention can be applied to a display device, a light-emitting device, a backlight device, a virtual reality device, an augmented reality device, an antenna device, a sensing device or a splicing device, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The electronic device may, for example, include liquid crystal, a light-emitting diode, fluorescence, phosphorescence, other suitable display media, or a combination of the foregoing, but is not limited thereto. The display device may be a non-self-luminous display device or a self-luminous display device. The antenna device may be a liquid crystal antenna device or a non-liquid crystal antenna device, and the sensing device may be a sensing device for sensing capacitance, light, heat or ultrasound, but is not limited thereto. The electronic device may, for example, include electronic components such as passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light-emitting diode or a photodiode. The light emitting diode may include, for example, an organic light emitting diode (OLED), a sub-millimeter light emitting diode (miniLED), a micro LED or a quantum dot light emitting diode (quantum dot LED), but is not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device may be any arrangement or combination of the foregoing, but is not limited thereto. In addition, the appearance of the electronic device may be rectangular, circular, polygonal, a shape with curved edges or other suitable shapes. The electronic device may have peripheral systems such as a drive system, a control system, a light source system, etc. to support a display device, an antenna device, a wearable device (for example, including augmented reality or virtual reality), a vehicle-mounted device (for example, including a car windshield) or a splicing device.

[0019] It should be understood that the features of several different embodiments may be replaced, reorganized, or mixed to implement other embodiments without departing from the spirit of the present invention.

[0020] Please refer to Figure 1 , Figure 2 and Figure 3 . Figure 1 FIG. 1 is a partial top view of an electronic device according to a first embodiment of the present invention. Figure 2 FIG. 1 is a partial cross-sectional diagram of an electronic device according to a first embodiment of the present invention. Figure 3 for Figure 2 The partially enlarged schematic diagram of the electronic device shown is shown. Figure 1 Only shown in Figure 2 A top view of some components of the electronic device ED is shown. Figure 3 Only shown in Figure 2The enlarged schematic diagram of some components of the electronic device ED is shown. Figure 1 The local cross-sectional structure of the electronic device ED corresponding to the cross-sectional line AA' can be referred to Figure 2 ,and Figure 2 The local enlarged structure of the electronic device ED corresponding to the region R can be referred to Figure 3 .like Figure 1 , Figure 2 and Figure 3 As shown, the electronic device ED may include a substrate 100, a light shielding layer LS, a first insulating layer I1, a semiconductor layer SC, a second insulating layer I2 and a drain DE. The light shielding layer 110 is disposed on the substrate 100. The substrate 100 may include a hard material or a flexible material. The material of the substrate 100 may include, for example, glass, quartz, sapphire, ceramic, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), other suitable materials or a combination of the above materials, but is not limited thereto. The light shielding layer LS may include, for example, a metal material, a black photoresist material or other material with better light absorption, but is not limited thereto. In some embodiments, an insulating layer (not shown) may also be provided between the substrate 100 and the light shielding layer 110, but the present invention is not limited thereto.

[0021] The first insulating layer I1 is disposed on the light shielding layer LS, and the semiconductor layer SC is disposed on the first insulating layer I1. The second insulating layer I2 is disposed on the semiconductor layer SC and has a portion of a hole V1, wherein the hole V1 exposes a portion IP of the first insulating layer I1, that is, a portion IP of the first insulating layer I1 is not covered by the second insulating layer I2. The drain DE is connected to the semiconductor layer SC through the hole V1. A portion of the projection of the semiconductor layer SC on the substrate 100 may be located within the projection of the hole V1 on the substrate 100, and the drain DE may be electrically connected to the semiconductor layer SC through the hole V1. Specifically, the electronic device ED may include a thin film transistor 110 disposed on the first insulating layer I1, and the thin film transistor 110 may include a drain DE, a source SE, a gate GE, and a semiconductor layer SC, and the second insulating layer I2 may be disposed between the gate GE and the semiconductor layer SC to serve as a gate dielectric layer in the thin film transistor 110. The electronic device ED may include a scan line GL and a data line DL disposed on the substrate 100, the scan line GL may extend along a direction X, and the data line DL may extend along a direction Y, wherein the direction X is not parallel to the direction Y, for example, the direction X may be perpendicular to the direction Y, but not limited thereto. The gate GE of the thin film transistor 110 may be a part of the scan line GL, and the source SE may be a part of the data line DL. In some embodiments, a plurality of scan lines GL and a plurality of data lines DL may be formed on the substrate 100, intersecting with each other to define a plurality of pixel (or sub-pixel) regions, and the thin film transistor 110 may be used as a driving element or a switching element of the pixel, and the electronic device ED may have the function of displaying a picture, but not limited thereto.

[0022] like Figure 1 and Figure 2 As shown, the electronic device ED may include, for example, a light shielding layer LS, a first insulating layer I1, a patterned semiconductor layer SC, a second insulating layer I2, a patterned first conductive layer M1, a third insulating layer I3, and a patterned second conductive layer M2, which are sequentially arranged along a direction Z on the upper surface 100a of the substrate 100. The direction Z may be a normal direction of the electronic device ED and parallel to the top view direction of the electronic device ED. The direction Z may be, for example, perpendicular to the upper surface 100a or the lower surface of the substrate 100, and the direction X and the direction Y may be perpendicular to the direction Z and parallel to the upper surface 100a of the substrate 100, respectively. The patterned first conductive layer M1 may constitute a scan line GL and a gate GE. The patterned second conductive layer M2 may constitute a data line DL, a source SE, and a drain DE. The drain DE may be electrically connected to the semiconductor layer SC through a hole V1 in the second insulating layer I2 and the third insulating layer I3, and the source SE may be electrically connected to the semiconductor layer SC through a hole V2 in the second insulating layer I2 and the third insulating layer I3. In some embodiments, for example, a second insulating layer 12 and a third insulating layer 13 may be formed as follows. Figure 1The groove GR extending along the direction X as shown in FIG. Figure 2 The hole V1 and the hole V2 are shown in the figure, but the present invention is not limited to the above. In other embodiments, for example, a plurality of holes separated from each other can be formed in the second insulating layer I2 and the third insulating layer I3 to form the hole V1 and the hole V2. Figure 2 and Figure 3 In the cross-sectional view shown, one side (for example, the left side) of the hole V1 can extend from the third insulating layer I3 through the second insulating layer I2 to the upper surface of the semiconductor layer SC to expose a portion of the semiconductor layer SC, and the other side (for example, the right side) of the hole V1 can extend from the third insulating layer I3 through the second insulating layer I2 to the upper surface of the first insulating layer I1 to expose a portion IP of the first insulating layer I1.

[0023] like Figure 1 As shown, in the direction Z, the light shielding layer LS may at least partially overlap the scanning line GL, and in the direction Y, the width of the light shielding layer LS may be greater than the width of the scanning line GL. Figures 1 to 3 In the embodiment shown, the light shielding layer LS may partially overlap with the hole V1 in the direction Z. Specifically, the light shielding layer LS may have a large size, for example, the light shielding layer LS may have a large area or the light shielding layer LS may have a large width in the direction Y, so that the projection of the hole V1 on the substrate 100 may be at least partially located within the projection of the light shielding layer LS on the substrate 100. Figure 3 As shown, a portion of the projection of the hole V1 on the substrate 100 may be located within the projection of the light shielding layer LS on the substrate 100. According to the structural design of the light shielding layer LS, light leakage can be reduced to improve electrical performance, and / or the area where the thin film transistor 110 is disposed and / or the pixel opening area can be more clearly separated to improve the contrast of the display image.

[0024] like Figure 2 and Figure 3 As shown, in the direction Z, there is a first minimum distance H1 between the portion IP of the first insulating layer I1 exposed by the hole V1 and the light shielding layer LS, there is a second minimum distance H2 between the semiconductor layer SC and the light shielding layer LS, and the ratio of the first minimum distance H1 to the second minimum distance H2 is greater than or equal to 0.1 and less than or equal to 1.0, that is, 0.1≤H1 / H2≤1.0. Specifically, in the direction Z, the minimum distance between the upper surface IPa of the portion IP of the first insulating layer I1 and the plane PL where the upper surface LSa of the light shielding layer LS is located may be the first minimum distance H1, and the minimum distance between the lower surface of the semiconductor layer SC and the upper surface LSa of the light shielding layer LS may be the second minimum distance H2. The first insulating layer I1 may have a thickness T in the direction Z, and the thickness T of the first insulating layer I1 may range from greater than or equal to 1.0. and is less than or equal to 3000 angstroms. The first minimum distance H1 may be, for example, The second minimum distance H2 may be, for example, However, this is not limited to the above. Since the process of forming the hole V1 and / or the drain DE (e.g., a patterning process such as an etching process) may cause the portion IP of the first insulating layer I1 exposed by the hole V1 to have a concave surface, resulting in the risk of the light shielding layer LS being exposed. Therefore, through the above-mentioned design of the ratio range of the first minimum distance H1 to the second minimum distance H2 and / or the thickness T range of the first insulating layer I1, the first insulating layer I1 can protect the light shielding layer LS to reduce the risk of the light shielding layer being exposed, thereby reducing the probability of a short circuit. For example, the probability of a short circuit caused by the drain contacting the light shielding layer due to the exposure of the light shielding layer can be reduced, thereby improving the reliability of the electronic device.

[0025] according to Figure 2 In the illustrated embodiment, the electronic device ED may further include, for example, a fourth insulating layer I4, a third conductive layer M3, a fifth insulating layer I5, and a fourth conductive layer M4. The fourth insulating layer I4 is disposed on the second conductive layer M2 and has a hole V3, and the hole V3 exposes a portion of the drain DE. The third conductive layer M3 is disposed on the fourth insulating layer I4 and is electrically connected to the drain DE through the hole V3. The fifth insulating layer I5 is disposed on the third conductive layer M3, and the fourth conductive layer M4 is disposed on the fifth insulating layer I5. The fifth insulating layer I5 and a portion of the fourth conductive layer M4 may be disposed in the hole V3, and the fifth insulating layer I5 is located between the fourth conductive layer M4 and the third conductive layer M3, so that the fourth conductive layer M4 and the third conductive layer M3 in the hole V3 are insulated from each other. Among them, the third conductive layer M3 may, for example, be used as a pixel electrode, and the fourth conductive layer M4 may, for example, be used as a common electrode. In some embodiments, as Figure 2 As shown, the electronic device ED may further include a light shielding element LSU disposed between the fifth insulating layer I5 and the fourth conductive layer M4, and the light shielding element LSU may partially overlap with the data line DL in the direction Z to reduce light leakage and improve optical and / or electrical performance. The light shielding element LSU may include, for example, a metal material, a black photoresist material, or other materials with better light absorption, but is not limited thereto.

[0026] The first conductive layer M1 and the second conductive layer M2 may include metal materials, wherein the metal materials include, for example, aluminum, molybdenum, copper, titanium, other suitable materials or combinations of the above materials, but are not limited thereto. The semiconductor layer SC may include, for example, amorphous silicon, polycrystalline silicon, metal oxides or combinations of the above materials, but are not limited thereto. Metal oxides include, for example, indium-gallium-zinc oxide (IGZO), but are not limited thereto. The third conductive layer M3 and the fourth conductive layer M4 may include transparent conductive materials, such as (but not limited to) indium tin oxide (ITO). The first insulating layer I1, the second insulating layer I2, the third insulating layer I3, the fourth insulating layer I4, and the fifth insulating layer I5 may include organic materials, inorganic materials, dielectric materials or other suitable insulating materials. Organic materials include, for example, polyimide (PI), photosensitive polyimide (PSPI), epoxy, Ajinomoto build-up film (ABF) material or other suitable materials, and inorganic materials include, for example, silicon oxide (SiOx), silicon nitride (SiN), silicon oxynitride (SiOxNy), other suitable materials or combinations of the above materials, but are not limited thereto. For example, the third insulating layer I3 may include a dielectric material and serve as an inter-layer dielectric layer, the fourth insulating layer I4 may include an organic material and serve as a planar layer, and the fifth insulating layer I5 may include an inorganic material and serve as a passivation layer, but are not limited thereto.

[0027] according to Figure 3 In the embodiment shown, in the direction DR, the edge e1 of the drain DE may protrude from the light shielding layer LS by a first distance D1, and the first distance D1 may be greater than or equal to 0.2 micrometers (μm). By making the first distance D1 of the edge e1 of the drain DE protruding from the light shielding layer LS have a certain length, the risk of the light shielding layer LS being exposed due to the process can be reduced, thereby reducing the probability of a short circuit between the drain DE and the light shielding layer LS. Wherein, the direction DR may be perpendicular to the direction Z and parallel to the upper surface 100a of the substrate 100. For example, the drain DE may extend along the direction DR and the edge e1 of the drain DE may protrude from the edge e2 of the light shielding layer LS, and the shortest distance between the edge e1 of the drain DE and the edge e2 of the light shielding layer LS may be the first distance D1.

[0028] The hole V1 may have a structure close to the gate GE (shown in FIG. Figure 2) and a lower edge e3 away from the gate GE. For example, in the cross-sectional view, the edge e3 and the edge e4 of the hole V1 are located at opposite ends in the direction DR, the edge e3 may be located at the junction of the second insulating layer I2 and the semiconductor layer SC, and the edge e4 may be located at the junction of the second insulating layer I2 and the first insulating layer I1. In the direction DR, the edge e1 of the drain DE may protrude from the edge e3 of the hole V1 by a second distance D2, and the second distance D2 may be greater than or equal to 0.3 microns to increase the area of ​​the drain DE contacting the semiconductor layer SC, thereby reducing the risk of disconnection. For example, the drain DE may extend along the direction DR and the edge e1 of the drain DE protrudes from the edge e3 of the hole V1, and the shortest distance between the edge e1 of the drain DE and the edge e3 of the hole V1 may be the second distance D2. In the direction DR, the hole V1 may have a width W, for example, the width W may be obtained by measuring the shortest distance between the edge e3 of the hole V1 and the edge e4 of the hole V1 along the direction DR. The difference Df between the width W and the second distance D2 may be greater than or equal to 0 and less than or equal to one half of the width W, that is, Df = (W-D2) and 0≤Df≤W / 2. The above design allows the edge e1 of the drain DE to protrude from the edge e3 of the hole V1 by a certain length of the second distance D2, which can increase the area of ​​the drain DE contacting the semiconductor layer SC and reduce the risk of the light shielding layer LS being exposed due to the process. In some embodiments, Figure 3 As shown, the difference Df may be equal to the shortest distance between the edge e1 of the drain DE and the edge e4 of the hole V1 in the direction DR.

[0029] The electronic device of the present invention is not limited to the above-mentioned embodiments. Other embodiments of the electronic device of the present invention will be described in detail below. To simplify the description, the same reference numerals are used to mark the same components in the present invention. The following mainly describes the differences between different embodiments, and does not repeat the same features.

[0030] Please refer to Figure 4 . Figure 4 FIG. 4 is a partial cross-sectional diagram of an electronic device according to a second embodiment of the present invention. Figure 4 The electronic device ED shown is Figure 3The difference of the first embodiment shown is that, in the direction DR, the edge e5 of the semiconductor layer SC may protrude from the edge e1 of the drain DE by a third distance D3, so as to increase the area of ​​the drain DE contacting the semiconductor layer SC, and the protruding semiconductor layer SC may reduce the risk of the light shielding layer LS being exposed due to the process, thereby reducing the probability of a short circuit between the drain DE and the light shielding layer LS. For example, the semiconductor layer SC may extend along the direction DR and the edge e5 of the semiconductor layer SC may protrude from the edge e1 of the drain DE, and the shortest distance between the edge e5 of the semiconductor layer SC and the edge e1 of the drain DE may be the third distance D3. In other embodiments, the semiconductor layer SC may extend along the direction DR, and the edge e5 of the semiconductor layer SC may protrude from the edge e4 of the hole V1 by a distance, that is, the projection of the hole V1 on the substrate 100 may be located within the projection of the semiconductor layer SC on the substrate 100, so that the protruding semiconductor layer SC may further reduce the risk of the light shielding layer LS being exposed, but the present invention is not limited thereto.

[0031] Please refer to Figure 5 . Figure 5 FIG. 4 is a partial cross-sectional diagram of an electronic device according to a third embodiment of the present invention. Figure 5 The electronic device ED shown is Figure 4 The difference of the second embodiment shown is that the projection of the hole V1 on the substrate 100 can be located within the projection of the light shielding layer LS on the substrate 100. For example, the light shielding layer LS can extend along the direction DR, and the edge e2 of the light shielding layer LS can protrude from the edge e4 of the hole V1 by a certain distance, that is, the light shielding layer LS can overlap with the hole V1 in the direction Z. The light shielding layer LS with a larger size can improve the contrast of the display image, but is not limited thereto.

[0032] In summary, the electronic device according to the embodiment of the present invention can reduce the risk of exposure of the light shielding layer by designing the range of the ratio of the first minimum distance between a portion of the first insulating layer and the light shielding layer to the second minimum distance between the semiconductor layer and the light shielding layer and / or the range of the thickness of the first insulating layer, thereby reducing the probability of short circuits and improving the reliability of the electronic device. In addition, by designing a structure in which the drain and / or the semiconductor layer protrude a certain distance, the risk of exposure of the light shielding layer can be further reduced, and the area of ​​the drain contacting the semiconductor layer can be increased.

[0033] The above description is only an embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An electronic device, characterized in that: include: a substrate; a light shielding layer, disposed on the substrate; a first insulating layer, disposed on the light shielding layer; a semiconductor layer disposed on the first insulating layer; a second insulating layer disposed on the semiconductor layer and having a hole, wherein the hole exposes a portion of the first insulating layer; as well as a drain electrode connected to the semiconductor layer through the hole; There is a first minimum distance between the portion of the first insulating layer and the light-shielding layer, there is a second minimum distance between the semiconductor layer and the light-shielding layer, and the ratio of the first minimum distance to the second minimum distance is greater than or equal to 0.1 and less than or equal to 1.

0.

2. The electronic device according to claim 1, wherein: The thickness of the first insulating layer is in a range of greater than or equal to 500 angstroms and less than or equal to 3000 angstroms.

3. The electronic device according to claim 1, wherein: In one direction, the edge of the drain protrudes from the light shielding layer by a first distance.

4. The electronic device as claimed in claim 3, characterized in that: The first distance is greater than or equal to 0.2 micrometers.

5. The electronic device according to claim 1, wherein: In one direction, the edge of the drain protrudes from the edge of the hole by a second distance.

6. The electronic device as claimed in claim 5, characterized in that: The second distance is greater than or equal to 0.3 micrometers.

7. The electronic device as claimed in claim 5, characterized in that: In the direction, the hole has a width, wherein a difference between the width and the second distance is greater than or equal to 0 and less than or equal to one half of the width.

8. The electronic device as claimed in claim 1, wherein: The light shielding layer partially overlaps with the hole.

9. The electronic device as claimed in claim 1, wherein: The projection of the hole on the substrate is located within the projection of the light shielding layer on the substrate.

10. The electronic device according to claim 1, wherein: In one direction, the edge of the semiconductor layer protrudes from the edge of the drain by a third distance.

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