Processor private storage architecture, access method and device

Abstract

The invention discloses a processor private storage architecture and an access method and device. The processor private storage architecture comprises a private storage access unit used for executing a target operation corresponding to a target private storage instruction on a private storage unit when the target private storage instruction is received. The processor architecture is provided with a private storage unit which can be accessed only by a processor core and a private storage access unit used for accessing the private storage unit, and the private storage unit, the private storage access unit and a private storage instruction provide a strict quick data access path for a processor. And the memory access performance and real-time performance of the processor are improved.

Description

Technical Field

[0001] The present invention relates to the field of processor technology, and in particular to a processor private storage architecture, access method and device. Background Art

[0002] In the existing reduced instruction set architecture, the source operands are all register data. The memory data must be loaded into the register through the memory access instruction before the corresponding operation is performed. The number of registers is fixed by the instruction set architecture, and the result is written from the register to the memory after the operation. Therefore, the speed of loading and writing data back to the memory will affect the execution efficiency of the processor. The source of the source operands of the complex instruction set can be register data or data in the memory. Although the data exchange between the displayed memory data and the register is eliminated, the memory access action still implicitly exists in the actual processor operation process. How to improve the memory access efficiency of the processor is a problem that technicians in this field need to solve. Summary of the invention

[0003] The present invention aims to solve one of the technical problems in the related art at least to a certain extent. To this end, one object of the present invention is to propose a processor private storage architecture to improve the performance and real-time performance of processor memory access.

[0004] The second object of the present invention is to provide an access method.

[0005] A third objective of the present invention is to provide a device with a private storage architecture.

[0006] A fourth objective of the present invention is to provide a chip.

[0007] A fifth object of the present invention is to provide a computer-readable storage medium.

[0008] To achieve the above objectives, a first aspect of the present invention proposes a processor private storage architecture, including: a private storage access unit, which is used to perform a target operation corresponding to the target private storage instruction on the private storage unit when receiving the target private storage instruction.

[0009] According to the processor private storage architecture of an embodiment of the present invention, there is a private storage unit that can only be accessed by the processor core, and a private storage access unit for accessing the private storage unit. The private storage unit and the private storage access unit provide the processor with a fast data access path in a strict sense, thereby improving the performance and real-time performance of the processor's memory access.

[0010] In addition, the processor private storage architecture proposed in the above embodiment of the present invention may also have the following additional technical features:

[0011] According to one embodiment of the present invention, the target private storage instruction includes a private storage declaration instruction, and the private storage access unit is specifically used to: when receiving the private storage declaration instruction, allocate storage space of the private storage unit to the program corresponding to the target private storage instruction.

[0012] According to an embodiment of the present invention, the private storage declaration instruction is sent to the private storage access unit when the program has a need to use the private storage unit for the first time.

[0013] According to one embodiment of the present invention, the need for the program to use the private storage unit includes: temporary data greater than a preset quantity threshold appears when a thread in the program executes function processing, data is saved and restored in function calls and / or function returns, parameter is passed, and interrupt field protection is performed.

[0014] According to an embodiment of the present invention, the target private storage instruction includes a private storage access instruction, and the private storage access unit is specifically used to:

[0015] When the private storage access instruction is received, an access operation corresponding to the private storage access instruction is performed on the private storage unit.

[0016] According to an embodiment of the present invention, the target private storage instruction includes a private storage release instruction, and the private storage access unit is specifically used to:

[0017] When the private storage release instruction is received, a release operation is performed on the storage space corresponding to the private storage release instruction in the private storage unit.

[0018] According to an embodiment of the present invention, the private storage release instruction is sent to the private storage access unit after the program is executed or the storage space is no longer needed.

[0019] According to one embodiment of the present invention, the private storage access unit includes a register, which is used to record the starting address of the storage space of the target thread in the program in the private storage unit, wherein the target thread is determined according to the private storage access instruction, and the starting address is determined according to the private storage access instruction and the storage space of the private storage unit allocated to the program.

[0020] According to an embodiment of the present invention, the number of the processor core is one, and the private storage unit is integrated in the processor core.

[0021] According to an embodiment of the present invention, there are multiple processor cores, and each of the processor cores has one private storage unit.

[0022] According to an embodiment of the present invention, there are multiple processor cores, and the multiple processor cores share the private storage unit.

[0023] According to one embodiment of the present invention, a first processor core runs at least two programs simultaneously. For any two programs, they are respectively recorded as a first program and a second program. A private storage access unit of the first processor core allocates a first storage space and a second storage space of the private storage unit to the first program and the second program respectively. If the priority of the first program is higher than that of the second program, the private storage access unit of the first processor core is further used to: when executing a private storage access instruction based on the first program, access the second storage space according to the private storage access instruction.

[0024] According to one embodiment of the present invention, for any N processor cores, respectively recorded as the first processor core, the second processor core and the Nth processor core, if the first processor core runs a first program, the second processor core runs a second program, and the Nth processor core runs an Nth program, then the first storage space of the private storage unit allocated by the private storage access unit of the first processor core to the first program, the second storage space of the private storage unit allocated by the private storage access unit of the second processor core to the second program, and the Nth storage space of the private storage unit allocated by the private storage access unit of the Nth processor core to the N program do not overlap.

[0025] According to one embodiment of the present invention, the number of processor cores is two, the first storage space is the upper part of the private storage unit, the second storage space is the lower part of the private storage unit, and the private storage access unit of the first processor core performs a top-down access operation on the first storage space, and the private storage access unit of the second processor core performs a bottom-up access operation on the second storage space.

[0026] According to one embodiment of the present invention, the processor core also includes a memory access unit, a cache memory CACHE and / or a tightly coupled memory TCM, and the memory access unit is used to declare, access and release the target CACHE when receiving a target CACHE instruction, and to declare, access and release the target TCM when receiving a target TCM instruction.

[0027] To achieve the above-mentioned purpose, a second aspect of the present invention provides an access method, which includes: receiving a target private storage instruction; and executing a target operation corresponding to the target private storage instruction on a private storage unit.

[0028] To achieve the above-mentioned purpose, the third aspect of the present invention proposes a device with a private storage architecture, including a processor private storage architecture as proposed in the first aspect of the present invention, and a private storage access unit in the processor private storage architecture executes the access method proposed in the second aspect of the present invention.

[0029] To achieve the above-mentioned purpose, a fourth embodiment of the present invention proposes a chip, including the processor private storage architecture proposed in the first embodiment of the present invention.

[0030] To achieve the above objectives, the fifth aspect of the present invention proposes a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the access method proposed in the second aspect of the present invention is implemented.

[0031] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Schematic diagram of a processor private storage architecture according to an embodiment of the present invention Figure 1 ;

[0033] Figure 2 Schematic diagram of a processor private storage architecture according to an embodiment of the present invention Figure 2 ;

[0034] Figure 3 Schematic diagram of a processor private storage architecture according to an embodiment of the present invention Figure 3 ;

[0035] Figure 4 Schematic diagram of a processor private storage architecture according to an embodiment of the present invention Figure 4 ;

[0036] Figure 5 is a flow chart of an access method according to an embodiment of the present invention;

[0037] Figure 6 is a schematic diagram of a device with a private storage structure according to an embodiment of the present invention;

[0038] Figure 7 is a schematic diagram of a chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0039] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0040] It should be noted that the relevant CPU uses CACHE (high-speed cache memory) and / or TCM (Tightly Coupled Memory) to improve the CPU's memory access performance.

[0041] CACHE can be used as a backup of some data in the main memory on the CPU side, thereby transferring the memory access interaction between the main memory and the main memory to the interaction between the CACHE and the main memory. In addition, CPUs with high real-time requirements often also contain TCM. The difference between TCM and CACHE is that TCM is part of the entire system memory. TCM is coupled to the CPU side and can quickly respond to CPU requests.

[0042] The CPU core contains a variety of storage resources including registers, CACHE, and TCM. Among them, registers and CACHE are private storage, but CACHE is only a backup of the main memory and needs to be consistent with the main memory or the CACHE in other CPU cores. Although the performance problem caused by direct access to the main memory is solved, the CPU cache structure after the introduction of CACHE, especially the multi-core CPU cache structure, will become extremely complex. Therefore, in some cases, such as when CACHE handles consistency issues, the internal memory access efficiency will deteriorate. In addition, there is a certain limit on the number of memory access instructions that the memory access unit can process. Once it exceeds, it needs to wait. Although TCM is a storage structure coupled to the CPU side, TCM is also part of the system memory and needs to respond to the access of the system bus. In addition, although TCM and CACHE access different addresses, they still use memory access instructions for read and write operations, and share memory access units with CACHE. After the memory access instruction previously assigned to CACHE blocks the memory access unit, the subsequent TCM access will also be blocked, and the efficiency of TCM will be limited. Although register access is fast, the number of registers specified in the architecture cannot be modified, so it cannot be arbitrarily expanded.

[0043] Due to the limited number of registers in the processor's private storage architecture, temporary data can only be temporarily stored in the system memory through memory access instructions. Although the CPU has a CACHE structure, the first access also needs to fill the CACHE and compete with other memory access operations for memory access units and bus bandwidth. In addition, temporary data will also occupy CACHE resources. Some CPUs have a TCM structure, but TCM shares memory access units like CACHE, and TCM is generally used for strong real-time related processing programs. Ordinary threads in user mode are generally in other memory areas.

[0044] Therefore, the embodiment of the present invention provides a processor private storage architecture, access method and device. Figure 1-7 And specific implementation methods describe in detail the processor private storage architecture, access method and device of the embodiments of the present invention.

[0045] Figure 1 FIG. 1 is a schematic diagram of a processor private storage architecture according to an embodiment of the present invention. Figure 1 As shown, the processor private storage architecture may include:

[0046] The private storage access unit is used to perform a target operation corresponding to the target private storage instruction on the private storage unit when receiving the target private storage instruction.

[0047] In order to improve the data access efficiency of the processor, the embodiment of the present invention adds a private storage unit in the processor private storage architecture that can quickly access data with the processor core. The private storage unit added by the embodiment of the present invention is not included in the system memory, nor is it hung on the system bus. The private storage unit can only be accessed by the processor core connected to it.

[0048] At the same time, the instruction set level is extended with private storage instructions that support access to private storage units. The private storage instructions are different from traditional memory access instructions. Therefore, the decoding stage can transmit the private storage access instructions to the corresponding private storage access unit. Among them, the private storage access unit is used to process the private access instructions of the private storage unit. The instruction types included in the private storage instructions include but are not limited to private storage declaration instructions, private storage access instructions, and private storage release instructions.

[0049] It can be implemented that when a program running on the processor core needs to access data with a private storage unit, a target private storage instruction is issued, and when the private storage unit receives the target private storage instruction, the private storage unit performs a target operation corresponding to the target private storage instruction on the private storage unit.

[0050] The processor private storage architecture of the embodiment of the present invention has a private storage unit and a private storage access unit, which provide a fast data access path for the processor in a strict sense. Accessing the private storage unit through the private storage access unit can speed up the data access speed and improve the performance and real-time performance of the processor memory access compared to accessing CACHE and TCM through the memory access unit.

[0051] The processor in the embodiment of the present invention may be a CPU (Central Processing Unit). The processor in the embodiment of the present invention is not limited to a CPU, but may also be other processors.

[0052] The private storage unit in the embodiment of the present invention can be implemented by RAM (Random Access Memory) or registers, etc. It should be noted that the implementation of the private storage unit includes but is not limited to RAM, registers, etc.

[0053] In an embodiment of the present invention, the target private storage instruction includes at least one of a private storage declaration instruction, a private storage access instruction, and a private storage release instruction.

[0054] In one embodiment of the present invention, the target private storage instruction includes a private storage declaration instruction, and the private storage access unit may be specifically used for:

[0055] When a private storage declaration instruction is received, storage space of a private storage unit is allocated to a program corresponding to the target private storage instruction.

[0056] In one embodiment of the present invention, the private storage declaration instruction is sent to the private storage access unit when the program has a need to use the private storage unit for the first time.

[0057] It should be noted that when a program running on a processor core uses a private storage unit for the first time, it needs to declare the size of the space to be used with an instruction. The space declared for use is not unlimited, and the program declares the corresponding size of private storage space according to its own needs, such as 32bit, 64bit, and 128bit.

[0058] As a specific implementation, when a program running on the processor core needs to use a private storage unit, a private storage declaration instruction is sent to the private storage access unit. When the private storage access unit receives the private storage declaration instruction, it allocates storage space of the private storage unit to the program corresponding to the target private storage instruction.

[0059] In one embodiment of the present invention, the private storage access unit may be specifically configured to: after allocating storage space of the private storage unit for a program corresponding to a target private storage instruction, feedback a flag indicating whether the declaration is successful.

[0060] Specifically, after the program running on the processor core declares how much space to use, it can also read the flag of whether the allocation is successful fed back by the private storage access unit. If the private storage access unit declares successfully, the private storage access instruction can be executed normally during the program running. If the private storage access unit declares unsuccessfully, the private storage access instruction executed in the program will report an exception.

[0061] In one embodiment of the present invention, the need for a program to use a private storage unit includes: temporary data greater than a preset threshold value appears when a thread in the program executes function processing, data is saved and restored in a function call and / or function return, parameter is passed, or interrupt context protection is performed.

[0062] Exemplarily, when temporary data greater than a preset threshold value appears during function processing of a thread in a program, when data is saved and restored during function calls and / or function returns, when parameter passing is performed, or when interrupt context protection is performed, it can be determined that the program running on the processor core has a need to use a private storage unit.

[0063] It should be noted that the requirement for the program in the embodiment of the present invention to use a private storage unit is not limited to the above situation.

[0064] In one embodiment of the present invention, the target private storage instruction includes a private storage access instruction, and the private storage access unit may be specifically used for:

[0065] When a private storage access instruction is received, an access operation corresponding to the private storage access instruction is performed on the private storage unit.

[0066] As a specific implementation, when a program running on a processor core accesses a private storage unit, a private storage access instruction is sent to the private storage access unit. When the private storage access unit receives the private storage access instruction, it performs an access operation corresponding to the private storage access instruction on the private storage unit.

[0067] In one embodiment of the present invention, the private storage access unit may include a register for recording the starting address of the storage space of the target thread in the program in the private storage unit, wherein the target thread is determined according to the private storage access instruction, and the starting address is determined according to the private storage access instruction and the storage space of the private storage unit allocated to the program.

[0068] The private storage access unit of the embodiment of the present invention has a hardware register for recording the storage space (first address) of the target thread in the program in the private storage unit.

[0069] As a specific implementation method, when a program running on the processor core accesses a private storage unit, the private storage access unit determines the final access address of the private storage unit based on the private storage access instruction, such as the offset in the private storage access instruction and the first address of the register in the private storage access unit.

[0070] In an embodiment of the present invention, a process running on a processor core may have one or more threads at the same time, and the corresponding private storage access unit includes multiple registers, and the target register is determined according to the target thread. The embodiment of the present invention does not limit the number of registers included in the private storage access unit.

[0071] In one embodiment of the present invention, the target private storage instruction includes a private storage release instruction, and the private storage access unit may be specifically used to:

[0072] When a private storage release instruction is received, a release operation is performed on the storage space corresponding to the private storage release instruction in the private storage unit.

[0073] In one embodiment of the present invention, the private storage release instruction is sent to the private storage access unit after the program is executed or no storage space is needed.

[0074] Specifically, when the program is executed and completed, or the program does not need the declared storage space subsequently, a private storage release instruction is sent to the private storage access unit.

[0075] As a specific implementation method, after the program running on the processor core is executed, a private storage release instruction is issued. When the private storage access unit receives the private storage release instruction, it performs a release operation on the storage space corresponding to the private storage release instruction in the private storage unit, so that the storage space on the private storage unit can be reallocated to other running programs.

[0076] In one embodiment of the present invention, Figure 1 As shown, the number of processor cores is one, and the private storage unit is integrated in the processor core.

[0077] In the embodiment of the present invention, when the number of the processor core is one, the private storage unit may be integrated into the processor core.

[0078] Specifically, when there is one processor core in the processor private memory architecture, the private memory unit may be integrated into the processor core.

[0079] In an embodiment of the present invention, there are multiple processor cores, and each processor core has a private storage unit.

[0080] Specifically, when there are multiple processor cores in the processor private storage architecture, each processor core is correspondingly provided with a private storage unit.

[0081] In one embodiment of the present invention, Figure 2 As shown, when there are multiple processor cores, the multiple processor cores share a private storage unit.

[0082] It is feasible that when there is one processor core in the processor private storage architecture, multiple processor cores can share a private storage unit. The private storage access unit of each processor core allocates storage space from the private storage unit to the program running on the corresponding processor core based on the program running on the processor core. The size of the allocated storage space is determined based on the requirements of the running program, and the allocated storage spaces do not overlap with each other.

[0083] In one embodiment of the present invention, the first processor core runs at least two programs simultaneously. For any two programs, they are respectively recorded as the first program and the second program. The private storage access unit of the first processor core allocates the first storage space and the second storage space of the private storage unit to the first program and the second program respectively. If the priority of the first program is higher than that of the second program, the private storage access unit of the first processor core is further used to:

[0084] When executing the private storage access instruction based on the first program, an access operation is performed on the second storage space according to the private storage access instruction.

[0085] In the embodiment of the present invention, no matter there is one processor core or multiple processor cores in the processor private storage architecture, any processor core may run only one program or may run multiple programs simultaneously.

[0086] In one embodiment of the present invention, a first processor core runs a first program, and a private storage access unit of the first processor core allocates a first storage space of a private storage unit to the first program. When the first processor core runs a second program while running the first program, the private storage access unit of the first processor core allocates a second storage space of the private storage unit to the second program, wherein the first storage space and the second storage space do not overlap. If the priority of the first program is higher than that of the second program, the private storage access unit of the first processor core executes a private storage access instruction based on the first program, and can perform an access operation on the second storage space according to the private storage access instruction.

[0087] Exemplarily, in a low priority mode such as a user mode, each thread can only access the address space allocated to the current thread. In a high priority mode, the thread can access the private storage space of its current mode and its subordinate modes. In practice, a thread in a high priority mode can specify the private storage space corresponding to the subordinate mode and the target thread to be accessed in the private storage access instruction issued by the thread.

[0088] In one embodiment of the present invention, for any N processor cores, respectively recorded as the first processor core, the second processor core and the Nth processor core, if the first processor core runs a first program, the second processor core runs a second program, and the Nth processor core runs an Nth program, then the first storage space of the private storage unit allocated by the private storage access unit of the first processor core for the first program does not overlap with the second storage space of the private storage unit allocated by the private storage access unit of the second processor core for the second program, and does not overlap with the Nth storage space of the private storage unit allocated by the private storage access unit of the Nth processor core for the Nth program.

[0089] In an embodiment of the present invention, when there are multiple processor cores, the multiple processor cores may share one private storage unit.

[0090] As a specific example, for any two processor cores (the first processor core and the second processor core), if the first processor core (CPU core 1) runs the first program while the second processor core (CPU core 2) runs the second program, the private storage access unit of the first processor core allocates the first storage space on the private storage unit for the first program, and the private storage access unit of the second processor core allocates the second storage space on the private storage unit for the second program. The first storage space and the second storage space of the allocated storage unit cannot overlap.

[0091] It should be noted that when programs are run simultaneously on any number of processor cores, the storage space on the shared private storage unit allocated to each program cannot overlap, and the size of the allocated storage space is determined based on the needs of the running programs.

[0092] In one embodiment of the present invention, the number of processor cores is two, the first storage space is the upper part of the private storage unit, the second storage space is the lower part of the private storage unit, and the private storage access unit of the first processor core performs a top-down access operation on the first storage space, and the private storage access unit of the second processor core performs a bottom-up access operation on the second storage space.

[0093] Specifically, when there are two processor cores, the two processor cores (the first processor core and the second processor core) share a private storage unit. The private storage unit is composed of a dual-port RAM, which can control the program running on the first processor core to access the private storage unit from top to bottom, and the program running on the second processor core to access the private storage unit from bottom to top, and compare the two memory access pointers in real time to determine whether the first storage space overlaps with the second storage space. When the first processor core attempts to declare a private storage space, it overlaps with the second storage space allocated by the second processor core, and returns a flag of allocation failure, so that when the two processor cores run different programs and the use of private storage is unequal, resources can be shared.

[0094] Other storage structures of the processor private storage architecture of the embodiment of the present invention may or may not include CACHE and / or TCM.

[0095] In one embodiment of the present invention, Figure 3 and Figure 4 As shown, the processor core may also include a memory access unit, a cache memory CACHE and / or a tightly coupled memory TCM, the memory access unit being used to execute a target operation corresponding to a target CACHE instruction on a target CACHE when a target CACHE instruction is received, and to execute a target operation corresponding to a target TCM instruction on a target TCM when a target TCM instruction is received.

[0096] The processor private storage architecture in the embodiment of the present invention may also include a cache memory CACHE and / or a tightly coupled memory TCM, and a memory access unit for executing a target operation corresponding to a target CACHE instruction on a target CACHE and / or executing a target operation corresponding to a target TCM instruction on a target TCM.

[0097] In the embodiment of the present invention, the private storage unit can be accessed only by the processor core connected to it. It is also possible to use a dual-port RAM to realize that two cores share a private storage structure. However, the access pointers of the two processor cores cannot overlap, ensuring the exclusivity of the private storage.

[0098] In the embodiment of the present invention, the private storage spaces accessed by different threads through the same private storage instruction are inconsistent, thereby ensuring isolation between threads.

[0099] In an embodiment of the present invention, a program in a high priority mode can access a private storage space of a program in a low priority mode by specifying a thread number.

[0100] The processor private storage architecture of the embodiment of the present invention realizes temporary storage of temporary data by adding a private storage unit, thereby realizing scenarios such as fast temporary data storage or fast interruption site protection, and can process two instructions in parallel with the memory access unit through an independent private storage access unit, so as to execute programs more quickly. Especially for multi-issue processors, the performance and real-time performance are more significantly improved.

[0101] The present invention provides an access method.

[0102] The access method according to the embodiment of the present invention may be used in a private storage access unit in the above-mentioned processor private storage architecture.

[0103] Figure 5 FIG. 1 is a flow chart of an access method according to an embodiment of the present invention. Figure 5 As shown, the access method may include:

[0104] S101, receiving a target private storage instruction;

[0105] S102, executing a target operation corresponding to a target private storage instruction on a private storage unit.

[0106] It can be implemented that when a program running on the processor core needs to access data with a private storage unit, a target private storage instruction is issued, and when the private storage unit receives the target private storage instruction, the private storage unit performs a target operation corresponding to the target private storage instruction on the private storage unit.

[0107] In one embodiment of the present invention, the target private storage instruction includes a private storage declaration instruction, and performing a target operation corresponding to the target private storage instruction on the private storage unit may include:

[0108] When a private storage declaration instruction is received, storage space of a private storage unit is allocated to a program corresponding to the target private storage instruction.

[0109] In one embodiment of the present invention, the private storage declaration instruction is sent to the private storage access unit when the program has a need to use the private storage unit for the first time.

[0110] It should be noted that when a program running on a processor core uses a private storage unit for the first time, it needs to declare the size of the space to be used with an instruction. The space declared for use is not unlimited, and the program declares the corresponding size of private storage space according to its own needs, such as 32bit, 64bit, and 128bit.

[0111] Specifically, when a program running on the processor core needs to use a private storage unit, a private storage declaration instruction is sent to the private storage access unit. When the private storage access unit receives the private storage declaration instruction, it allocates storage space of the private storage unit to the program corresponding to the target private storage instruction.

[0112] In one embodiment of the present invention, the need for a program to use a private storage unit includes: temporary data greater than a preset threshold value appears when a thread in the program executes function processing, data is saved and restored in a function call and / or function return, parameter is passed, and interrupt field protection is performed.

[0113] Exemplarily, when temporary data greater than a preset threshold value appears during function processing of a thread in a program, when data is saved and restored during function calls and / or function returns, when parameter passing is performed, or when interrupt context protection is performed, it can be determined that the program running on the processor core has a need to use a private storage unit.

[0114] It should be noted that the requirement for the program in the embodiment of the present invention to use a private storage unit is not limited to the above situation.

[0115] In one embodiment of the present invention, the target private storage instruction includes a private storage access instruction, and performing a target operation corresponding to the target private storage instruction on the private storage unit may include:

[0116] When a private storage access instruction is received, an access operation corresponding to the private storage access instruction is performed on the private storage unit.

[0117] Specifically, when a program running on the processor core accesses a private storage unit, a private storage access instruction is sent to the private storage access unit. When the private storage access unit receives the private storage access instruction, it performs an access operation corresponding to the private storage access instruction on the private storage unit.

[0118] In one embodiment of the present invention, the target private storage instruction includes a private storage release instruction, and performing a target operation corresponding to the target private storage instruction on the private storage unit may include:

[0119] When a private storage release instruction is received, a release operation is performed on the storage space corresponding to the private storage release instruction in the private storage unit.

[0120] Specifically, after the program running on the processor core is executed or no longer needs private storage space, a private storage release instruction is issued. When the private storage access unit receives the private storage release instruction, it performs a release operation on the storage space in the private storage unit corresponding to the private storage release instruction, so that the storage space of the private storage unit can be reallocated to other running programs.

[0121] In one embodiment of the present invention, the private storage release instruction is sent to the private storage access unit after the program is executed.

[0122] It should be noted that other specific implementations of the access method provided in the embodiment of the present invention may refer to other specific implementations of the processor private storage architecture in the above embodiment of the present invention.

[0123] The access method of the embodiment of the present invention, based on the above processor private storage architecture, realizes scenarios such as fast temporary data storage or fast interruption scene protection, and improves the memory access performance of the processor.

[0124] The present invention provides a device with a private storage structure.

[0125] Figure 6 FIG. 1 is a schematic diagram of a device with a private storage structure according to an embodiment of the present invention. Figure 6 As shown, the device 100 with a private storage structure includes the processor private storage architecture as described above, and the private storage access unit in the processor private storage architecture executes the access method as described above.

[0126] The device with a private storage structure in the embodiment of the present invention realizes scenarios such as fast temporary data storage or fast interruption site protection, and has the advantage of high memory access performance.

[0127] The invention provides a chip.

[0128] Figure 7 Schematic diagram of a chip according to an embodiment of the present invention. Figure 7 As shown, chip 1000 includes the processor private memory architecture 200 as described above.

[0129] The chip of the embodiment of the present invention realizes scenarios such as fast temporary data storage or fast interruption site protection, and has the advantage of high memory access performance.

[0130] The present invention provides a computer-readable storage medium.

[0131] In this embodiment, a computer program is stored on a computer-readable storage medium, and when the computer program is executed by a processor, the access method described above is implemented.

[0132] The computer-readable storage medium of the embodiment of the present invention utilizes the above access method to realize scenarios such as fast temporary data storage or fast interruption site protection, and has the advantage of high memory access performance.

[0133] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0134] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0135] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0136] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0137] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0138] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0139] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0140] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A processor private storage architecture, characterized in that: include: The private storage access unit is used to perform a target operation corresponding to the target private storage instruction on the private storage unit when receiving the target private storage instruction.

2. The processor private storage architecture according to claim 1, characterized in that: The target private storage instruction includes a private storage declaration instruction, and the private storage access unit is specifically used to: When the private storage declaration instruction is received, storage space of the private storage unit is allocated to the program corresponding to the target private storage instruction.

3. The processor private storage architecture according to claim 2, characterized in that: The private storage declaration instruction is sent to the private storage access unit when the program has a need to use the private storage unit for the first time.

4. The processor private storage architecture according to claim 3, characterized in that: The program has a need to use the private storage unit including: temporary data greater than a preset threshold value appears when the thread in the program executes function processing, data is saved and restored in function calls and / or function returns, parameter is passed, and interrupt field protection is performed.

5. The processor private storage architecture according to claim 2, characterized in that: The target private storage instruction includes a private storage access instruction, and the private storage access unit is specifically used to: When the private storage access instruction is received, an access operation corresponding to the private storage access instruction is performed on the private storage unit.

6. The processor private storage architecture according to claim 5, characterized in that: The target private storage instruction includes a private storage release instruction, and the private storage access unit is specifically used to: When the private storage release instruction is received, a release operation is performed on the storage space corresponding to the private storage release instruction in the private storage unit.

7. The processor private storage architecture according to claim 6, characterized in that: The private storage release instruction is sent to the private storage access unit after the program is executed or the storage space is no longer needed.

8. The processor private storage architecture according to claim 5, characterized in that: The private storage access unit includes a register, which is used to record the starting address of the storage space of the target thread in the program in the private storage unit, wherein the target thread is determined according to the private storage access instruction, and the starting address is determined according to the private storage access instruction and the storage space of the private storage unit allocated to the program.

9. The processor private storage architecture according to any one of claims 1 to 8, characterized in that: The number of the processor core is one, and the private storage unit is integrated in the processor core.

10. The processor private storage architecture according to any one of claims 1 to 8, characterized in that: There are multiple processor cores, and each processor core has one private storage unit.

11. The processor private storage architecture according to any one of claims 1 to 8, characterized in that: There are multiple processor cores, and the multiple processor cores share the private storage unit.

12. The processor private storage architecture according to claim 10, characterized in that: The first processor core runs at least two programs simultaneously. For any two programs, they are respectively recorded as the first program and the second program. The private storage access unit of the first processor core allocates the first storage space and the second storage space of the private storage unit to the first program and the second program respectively. If the priority of the first program is higher than that of the second program, the private storage access unit of the first processor core is further used to: When executing a private storage access instruction based on the first program, an access operation is performed on the second storage space according to the private storage access instruction.

13. The processor private storage architecture according to claim 11, characterized in that: For any N processor cores, respectively recorded as the first processor core, the second processor core and the Nth processor core, if the first processor core runs a first program, the second processor core runs a second program, and the Nth processor core runs an Nth program, then the first storage space of the private storage unit allocated by the private storage access unit of the first processor core for the first program, the second storage space of the private storage unit allocated by the private storage access unit of the second processor core for the second program, and the Nth storage space of the private storage unit allocated by the private storage access unit of the Nth processor core for the N program do not overlap.

14. The processor private storage architecture according to claim 13, characterized in that: The number of the processor cores is two, the first storage space is the upper part of the private storage unit, the second storage space is the lower part of the private storage unit, and the private storage access unit of the first processor core performs a top-down access operation on the first storage space, and the private storage access unit of the second processor core performs a bottom-up access operation on the second storage space.

15. The processor private storage architecture according to claim 11, characterized in that: The processor core also includes a memory access unit, a cache memory CACHE and / or a tightly coupled memory TCM. The memory access unit is used to declare, access and release the target CACHE when receiving a target CACHE instruction, and to declare, access and release the target TCM when receiving a target TCM instruction.

16. An access method, characterized in that: The method comprises: receiving a target private storage instruction; A target operation corresponding to the target private storage instruction is performed on the private storage unit.

17. The access method according to claim 16, characterized in that: The target private storage instruction includes a private storage declaration instruction, and the performing of a target operation corresponding to the target private storage instruction on the private storage unit includes: When the private storage declaration instruction is received, storage space of the private storage unit is allocated to the program corresponding to the target private storage instruction.

18. The access method according to claim 17, characterized in that: The private storage declaration instruction is sent to the private storage access unit when the program has a need to use the private storage unit for the first time.

19. The access method according to claim 18, characterized in that: The program has a need to use the private storage unit including: temporary data greater than a preset threshold value appears when the thread in the program executes function processing, data is saved and restored in function calls and / or function returns, parameter is passed, and interrupt field protection is performed.

20. The access method according to claim 17, characterized in that: The target private storage instruction includes a private storage access instruction, and the performing of a target operation corresponding to the target private storage instruction on the private storage unit includes: When the private storage access instruction is received, an access operation corresponding to the private storage access instruction is performed on the private storage unit.

21. The access method according to claim 20, characterized in that: The target private storage instruction includes a private storage release instruction, and the performing of a target operation corresponding to the target private storage instruction on the private storage unit includes: When the private storage release instruction is received, a release operation is performed on the storage space corresponding to the private storage release instruction in the private storage unit.

22. The access method according to claim 21, characterized in that: The private storage release instruction is sent to the private storage access unit after the program is executed.

23. A device having a private storage architecture, characterized in that: It comprises a processor private storage architecture as described in any one of claims 1-15, and a private storage access unit in the processor private storage architecture executes an access method as described in any one of claims 16-22.

24. A chip, characterized in that: Includes a processor private storage architecture as described in any one of claims 1-15.

25. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the access method according to any one of claims 16 to 22 is implemented.

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