Program uploading system and method of satellite hyperspectral camera

Abstract

The invention belongs to the field of program uploading, and particularly relates to a program uploading system and method for a satellite hyperspectral camera. The system mainly comprises an FPGA (Field Programmable Gate Array) module, a program uploading module, a program refreshing communication interface module, an internal communication bus interface module and an SDRAM (Synchronous Dynamic Random Access Memory) storage module, a first interface of the FPGA module is connected with an external comprehensive electronic subsystem through the program uploading module, a second interface of the FPGA module is connected with the lower computer control module CPU through the internal communication bus interface module, a third interface of the FPGA module is connected with the satellite hyperspectral camera to be subjected to program uploading through the program refreshing communication interface module, and a fourth interface of the FPGA module is connected with the SDRAM storage module. The program uploading system is based on the FPGA module, the SDRAM storage module is adopted to store the uploading program, the performance is stable, the reliability is high, the uploading program speed can reach 100 Mbs, the capacity can reach 1 G, the requirements of a satellite hyperspectral camera subsystem are met, and the cost is low.

Description

Technical Field

[0001] The present invention relates to a program annotation system, and in particular to a program annotation system and method for a satellite hyperspectral camera. Background Art

[0002] The satellite hyperspectral camera is an interferometric spaceborne camera with a wide spectral band and high spatial resolution. The design life of the satellite hyperspectral camera is 8 years. It usually consists of 8 components, including a controller component, a data processor, a panchromatic focal plane component, a short-wave infrared focal plane component, a long-wave infrared focal plane component, a medium-wave infrared focal plane component, a visible near-infrared focal plane component, and a synchronous calibration spectrometer.

[0003] Among them, the program upload system is an important component of the satellite hyperspectral camera controller component. It has the functions of receiving bus command data sent by the lower computer control board or the upload program data input by the satellite SpaceWire bus interface, and outputting 485 bus communication data of the panchromatic camera, short-wave infrared camera, long-wave infrared camera, medium-wave infrared camera, visible spectrum camera, synchronous calibration spectrum camera, focusing circuit, data processor and black-gray body temperature control circuit.

[0004] However, the existing program uploading system has the problems of low program uploading speed, small capacity, low reliability and weak stability, which can hardly meet the actual needs. Therefore, there is an urgent need for a program uploading system with high uploading speed, large capacity, high reliability and strong stability. Summary of the invention

[0005] The purpose of the present invention is to solve the technical problems of low program uploading speed, small capacity, low reliability and weak stability of the existing program uploading system, and to provide a program uploading system and method for a satellite hyperspectral camera.

[0006] To achieve the above purpose, the technical solution adopted by the present invention is:

[0007] A program injection system for a satellite hyperspectral camera, which is special in that:

[0008] It includes FPGA module, program injection module, program refresh communication interface module, internal communication bus interface module and SDRAM storage module;

[0009] The first interface of the FPGA module is connected to the external integrated electronic subsystem through the program injection module, the second interface is connected to the lower computer control module CPU through the internal communication bus interface module, the third interface is connected to the satellite hyperspectral camera to be injected through the program refresh communication interface module, and the fourth interface is connected to the SDRAM storage module;

[0010] The FPGA module is used to realize information exchange with the CPU of the lower computer control module through the internal communication bus interface module, and receive parameter setting instructions from the CPU of the lower computer control module; according to the parameter setting instructions sent by the CPU of the lower computer control module, set the working mode of the program refresh communication interface module, and send the corresponding working status information to the CPU of the lower computer control module; receive the FPGA injection program sent by the integrated electronic subsystem through the program injection module, and store it in the SDRAM storage module; after receiving the FPGA injection program, send a program reception end signal to the CPU of the lower computer control module; read the FPGA injection program in the SDRAM storage module according to the parameter setting instructions of the CPU of the lower computer control module, and send it to the satellite hyperspectral camera to be injected through the program refresh communication interface module.

[0011] Further, the program injection module includes a SpaceWire bus controller circuit and two SpaceWire bus interfaces;

[0012] The first interface of the SpaceWire bus controller circuit is connected to the first interface of the FPGA module, the second interface and the third interface are connected to one end of two SpaceWire bus interfaces through two SpaceWire interface chips respectively, and the other ends of the two SpaceWire bus interfaces are connected to the external integrated electronic subsystem respectively.

[0013] Furthermore, the SpaceWire bus controller circuit is a BM4803AMQRH circuit, and the two SpaceWire interface chips corresponding to the second interface and the third interface of the SpaceWire bus controller circuit are respectively a B54LVDS032LVRH differential-to-single-ended chip and a B54LVDS031LVRH single-ended-to-differential chip.

[0014] Furthermore, the program refresh communication interface module is connected to the satellite hyperspectral camera to be program-uploaded via a program refresh output electrical connector.

[0015] Further, the program refresh communication interface circuit includes a first level conversion unit, a first 485 chip and a second 485 chip;

[0016] The satellite hyperspectral camera includes a panchromatic camera and a short-wave infrared camera;

[0017] The first input end of the first level conversion unit is connected to the third interface of the FPGA module, and the first output end is connected to the program refresh output electrical connectors of the full-color camera and the short-wave infrared camera to be program-annotated through the first 485 chip, so as to realize program-annotation;

[0018] The second output end of the first level conversion unit is connected to the third interface of the FPGA module, and the second input end is connected to the program refresh output electrical connector of the full-color camera and the short-wave infrared camera to be program-uploaded through the second 485 chip to realize the uploading response.

[0019] Further, the internal communication bus interface module includes a second level conversion unit, a third 485 chip and a fourth 485 chip;

[0020] The first interactive end of the second level conversion unit is connected to the second interface of the FPGA module, the second interactive end and the third interactive end are respectively connected to the first interactive ends of the third 485 chip and the fourth 485 chip, and the second interactive ends of the third 485 chip and the fourth 485 chip are respectively connected to the CPU of the lower computer control module through the internal communication electrical connector.

[0021] At the same time, the present invention also provides a method for program injection of a satellite hyperspectral camera, which is based on the aforementioned program injection system of a satellite hyperspectral camera, and is special in that it includes the following steps:

[0022] Step 1: Receive parameter setting instructions from the CPU of the lower computer control module through the FPGA module;

[0023] Step 2, the FPGA module sets the program to refresh the working mode of the communication interface module according to the parameter setting instruction sent by the CPU of the lower computer control module, and sends the corresponding working status information to the CPU of the lower computer control module;

[0024] Step 3, the FPGA module receives the FPGA upload program sent from the integrated electronic subsystem through the program upload module, and stores it in the SDRAM storage module;

[0025] Step 4: After receiving the FPGA injection program, the FPGA module sends a program reception end signal to the CPU of the lower computer control module;

[0026] Step 5: The FPGA module reads out the FPGA injection program in the SDRAM storage module according to the parameter setting instructions of the CPU of the lower computer control module, and sends it to the corresponding satellite hyperspectral camera to be injected with the program through the program refresh communication interface module, thereby realizing the program injection of the satellite hyperspectral camera.

[0027] The beneficial effects of the present invention are:

[0028] The program uploading system of the present invention is based on an FPGA module and uses an SDRAM storage module to store the uploading program. It has stable performance, high reliability, a program uploading speed of up to 100Mbs, and a capacity of up to 1G, which meets the requirements of the satellite hyperspectral camera subsystem and has a low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic structural diagram of an embodiment of the present invention;

[0030] Figure 2 This is a block diagram of the connection relationship of B17V16 configuration FPGA in an embodiment of the present invention;

[0031] Figure 3 is a schematic diagram of a crystal oscillator circuit in an embodiment of the present invention;

[0032] Figure 4 It is a PROM design principle diagram in an embodiment of the present invention;

[0033] Figure 5 is a waveform diagram of the requirement for powering on the power supply and the core power supply at the same time in an embodiment of the present invention;

[0034] Figure 6 This is a block diagram of the BM4803A control topology structure in an embodiment of the present invention;

[0035] Figure 7 This is a pull-up and pull-down circuit diagram of the BM4803A control module in an embodiment of the present invention;

[0036] Figure 8 is a schematic diagram of a connector interface in an embodiment of the present invention;

[0037] Fig. 9 is a block diagram of the power supply principle of the FPGA module in an embodiment of the present invention;

[0038] Fig.10 is a principle block diagram of a program cache circuit in an embodiment of the present invention;

[0039] Fig.11 This is a schematic diagram of a one-way 485 serial output interface circuit for a full-color camera focal plane program refresh in an embodiment of the present invention;

[0040] Fig.12 It is a schematic diagram of a one-way 485 serial input interface circuit for refreshing the focus plane program of a full-color camera in an embodiment of the present invention;

[0041] Fig.13 It is a schematic diagram of the circuit design of the pulse per second signal output interface in an embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to make the purpose, advantages and features of the present invention more clear, the following is a further detailed description of a satellite hyperspectral camera program injection system and method proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following specific implementation methods, the advantages and features of the present invention will be more clear.

[0043] Program note board hardware circuit composition

[0044] like Figure 1 As shown, this board consists of five functional circuits, namely FPGA module, program upload module, SDRAM storage circuit, program refresh communication interface module and internal communication bus interface module.

[0045] The first interface of the FPGA module is connected to the external integrated electronic subsystem through the program upload module, the second interface is connected to the lower computer control module CPU through the internal communication bus interface module, the third interface is connected to the satellite hyperspectral camera to be program uploaded through the program refresh communication interface module, and the fourth interface is connected to the SDRAM storage module.

[0046] 1. FPGA module

[0047] The main functions of the FPGA module include:

[0048] 1) Realize information exchange with the lower computer control circuit CPU through the internal communication bus interface module, and receive parameter setting instructions from the lower computer control circuit CPU;

[0049] 2) According to the parameter setting instruction sent by the lower computer control circuit CPU, the program is set to refresh the working mode of the communication interface module, and the corresponding working status information is sent to the lower computer control circuit CPU;

[0050] 3) After receiving the FPGA injection program sent from the integrated electronic subsystem, it is stored in the SDRAM storage module;

[0051] 4) After receiving the FPGA injection program, it sends a receiving end signal back to the lower computer control circuit CPU;

[0052] 5) According to the parameter setting instruction of the lower computer control circuit CPU, the injection program in the SDRAM storage module is read out and sent to the satellite hyperspectral camera to be injected with the program through the program refresh communication interface module.

[0053] The FPGA module uses the JFM4VSX55RT-CCGA1140 produced by Fudan Microelectronics and benchmarked against the US XILINX company (XQR4VSX55). This model of device has been widely used in aerospace products. It has 24576 logic slice resources, 5.76Mb of RAM resources, 640 IO pins, including 8 64-pin banks, 2 48-pin banks, and 2 16-pin banks. FPGA power supply: V4 series FPGA voltages mainly include VCCINT (core voltage) 1.2V, VCCAUX (auxiliary voltage) 2.5V, VCCO (IO voltage) 2.5V, 3.3V.

[0054] The total number of IO required for the internal communication and program refresh control board is 236 (121 for 4803, 56 for SDRAM, 57 for communication and refresh MAX485 (12*2 for refresh, 9*3 for communication, 6*1 for frame synchronization), and 6 for PROM).

[0055] The FPGA chip is JFM4VSX55RT produced by Fudan Microelectronics Company, and two B17V16 chips are selected for program storage PROM. The block diagram of the connection relationship between FPGA and configuration PROM is as follows: Figure 2 shown.

[0056] Crystal Oscillator Circuit

[0057] The crystal oscillator circuit uses Wuhan Haichuang Company's ZA715CB-100MHz, and its quality level meets CAST C requirements. The schematic diagram is as follows: Figure 3 shown.

[0058] Program memory circuit

[0059] The program memory PROM uses two B17V16 chips, and its structure is as follows Figure 4 shown.

[0060] 2. Program injection module design

[0061] The program injection module includes a SpaceWire bus controller circuit and two SpaceWire bus interfaces.

[0062] The first interface of the SpaceWire bus controller circuit is connected to the first interface of the FPGA module, the second interface and the third interface are connected to one end of the SpaceWire bus interface through two SpaceWire interface chips, and the other ends of the two SpaceWire bus interfaces are connected to the external integrated electronic subsystem.

[0063] SpaceWire bus is a high-speed, point-to-point, full-duplex serial bus for aerospace applications. The interface device uses radiation-resistant 200Mbps SpaceWire bus series products, which are compatible with the SpaceWire bus protocol ECSS-E-50-12A / ECSS-E-ST-50-12C. It has the characteristics of high speed, high reliability and low power consumption, and provides a system solution for high-speed data transmission and exchange of electronic equipment, meeting the application requirements of electronic systems for high-speed, delay-controlled, high-reliability and scalable data buses.

[0064] The SpaceWire bus interface is connected to the integrated electronic subsystem and is used to transmit FPGA program files of each component. The interface parameters are as follows:

[0065] Signal form: LVDS differential voltage signal;

[0066] Interface: BM4803AMQRH, B54LVDS031LVRH, B54LVDS032LVRH;

[0067] Data transfer rate: 100Mbps;

[0068] Signal direction: integrated electronic subsystem---->controller;

[0069] Number of signal paths: 1 primary and 1 backup.

[0070] BM4803AMQRH circuit

[0071] like Figure 6 As shown in the figure, BM4803AMQRH is a domestically produced radiation-resistant 200Mbps SpaceWire bus controller circuit, compatible with the SpaceWire standard ECSS-E-50-12A / ECSS-E-ST-50-12C, providing eight full-duplex SpaceWire ports with a transmission rate of 2Mbps to 200Mbps. At the same time, BM4803AMQRH is also equipped with two external parallel ports, which are connected to the FPGA module to save the received data.

[0072] Two external parallel ports

[0073] Each port consists of a 9-bit wide input FIFO and an output FIFO.

[0074] Configuring Ports

[0075] Used to read / write the internal registers of the router.

[0076] Access is possible via both the SpaceWire port and the external parallel port.

[0077] Uses Remote Memory Access Protocol (RMAP).

[0078] Time code interface

[0079] Can be configured as master / slave mode.

[0080] Supports path address and logical address routing.

[0081] Operating voltage

[0082] I / O power supply voltage: 3.3V±0.33V; core power supply voltage: 1.8V±0.18V.

[0083] Power-on requirements

[0084] To ensure that the BM4803AMQRH power supply must be powered on strictly in the correct order, the specific requirements are:

[0085] *The digital I / O power supply and the analog I / O power supply (collectively referred to as I / O power supply) are powered on at the same time;

[0086] *The digital core power supply and the analog core power supply (collectively referred to as the core power supply) are powered on at the same time;

[0087] *The I / O power supply is powered on before the core power supply or the I / O power supply and the core power supply are powered on at the same time.

[0088] The other is to power on the I / O power supply and the core power supply at the same time. It is required that the voltage difference (△V) of the core power supply higher than the I / O power supply during the power-on process shall not exceed 0.5V. Figure 5 shown.

[0089] Control Module

[0090] The control module can be implemented by the above-mentioned FPGA module, and connected to the external parallel port 9, external parallel port 10, time code interface and status port of BM4803AMQRH to realize the control and status monitoring of BM4803AMQRH. The status port pin stat_mux_out (7:0) of BM4803AMQRH is input during reset initialization, and is used to configure the initial value of the internal control register function bit of BM4803AMQRH; after the reset is completed, the pin stat_mux_out (7:0) is used as an output, and outputs the working status of BM4803AMQRH according to the value of the pin stat_mux_addr (3:0). Pin stat_mux_out (7:0) needs to be connected to the power supply / ground through a resistor. The recommended resistance value of the resistor is 4.7KΩ. The specific pull-up and pull-down conditions are as follows. Figure 7 shown.

[0091] SpaceWire Interface Chip

[0092] The SpaceWire interface is an LVDS level differential signal input and output, while the BM4803AMQRH chip is a differential signal input and output, with a designed communication rate of 100Mbps. The interface uses B54LVDS032LVRH differential to single-ended and B54LVDS031LVRH single-ended to differential as the driver chip for receiving and sending SpaceWire bus signals.

[0093] SpaceWire Connectors and Cables

[0094] The connector uses a micro 9-pin D-type connector, including 8 signal wires and 1 ground wire. The model is MDSA209S000B. The connector specifications meet the ESCC 3401 / 071 specification or domestic compatible specifications, such as Figure 8 shown.

[0095] 3. Power supply circuit design

[0096] like Fig. 9 As shown, the FPGA module requires three power supplies as follows: +3.3V, +2.5V, +1.8V, +1.2V, a total of four power supply types. The power consumption of the BM4803AMQRH chip is ≤1.5W, the power consumption of the SDRAM chip is ≤1.5W, and the power consumption of the FPGA is ≤3W.

[0097] +1.2V: FPGA core voltage

[0098] +1.8V: BM4803MQRH core voltage

[0099] ◆+2.5V: FPGA auxiliary circuit voltage;

[0100] ◆+3.3V: BM4803QRH IO power supply voltage SDRAM power supply FPGA power supply PROM power supply

[0101] ◆+5.5V: 485 interface circuit power supply voltage

[0102] Table 1 Main parameters of power conversion chip

[0103] model RSS0508 RSW1101 RSW1201 factory Shengyu Shengyu Shengyu Maximum output current 8A 5A 3A Encapsulation CFP20 CFP16 CFP16 TID(Krads(Si)) 100K 100K 100Krad(Si) SEL (Mev.cm2 / mg) 81.4 75 75 Input voltage range 3～6.3V 3～16V 3～16V Minimum pressure difference (full load) 45mV@400mA 70mV / 400mA Output voltage range 1.2～6.5V 1V8 / 2V5 / 3V3 / 5V0 <![CDATA[1.2~(V I -V d )]]> Overcurrent protection support Support support

[0104] The power consumption of the control module is shown in the table below.

[0105] Table 2 Internal communication and program refresh control board circuit power consumption

[0106] Power properties Supply voltage (V) Power consumption (W) Secondary power supply +5.5 14.4

[0107] 4. Program cache circuit design

[0108] The program cache circuit is composed of FPGA module and SDRAM storage module. The SDRAM uses Zhuhai Orbit VDSD1G32xS70xx2V75, with a storage capacity of 1Gbit, a storage organization of 32M*32, a power supply voltage of +3.3V, a clock frequency of 133MHz, and a package form of SOP70. The circuit design is as follows: Fig.10 shown.

[0109] 5. Program refresh communication interface module, internal communication bus interface module

[0110] 1) Program refresh communication interface module design

[0111] The program refresh usually has 7 unit circuits, including the full-color camera focus plane program refresh circuit, the visible spectrum camera focus plane refresh circuit, the short-wave infrared camera focus plane refresh circuit, the medium-wave infrared camera focus plane refresh circuit, the long-wave infrared camera focus plane refresh circuit, the data processor refresh circuit and the focus refresh circuit.

[0112] This board is designed with a full-color camera focus plane program refresh circuit and a short-wave infrared camera focus plane refresh circuit. The principle of the full-color camera focus plane program refresh circuit is as follows Fig.11 and Fig.12 As shown below, the focal plane refresh circuit of the short-wave infrared camera is the same.

[0113] 2) Internal communication bus interface module

[0114] The internal communication bus interface module provides working parameters and auxiliary data settings for the full-color camera and short-wave infrared camera, so that each camera can work in the required mode.

[0115] The internal bus communication rate is 115200bps, and the interface chip uses LC485RHA.

[0116] 3) Second pulse signal output interface circuit design

[0117] The pulse-per-second signal output interface uses a 485 chip to form a single-phase signal transmission, and is also used to output the pulse-per-second signal of the full-color camera and the short-wave infrared camera. The circuit principle is as follows Fig.13 shown.

Claims

1. A program injection system for a satellite hyperspectral camera, characterized in that: It includes FPGA module, program injection module, program refresh communication interface module, internal communication bus interface module and SDRAM storage module; The first interface of the FPGA module is connected to the external integrated electronic subsystem through the program injection module, the second interface is connected to the lower computer control module CPU through the internal communication bus interface module, the third interface is connected to the satellite hyperspectral camera to be injected through the program refresh communication interface module, and the fourth interface is connected to the SDRAM storage module; The FPGA module is used to realize information exchange with the CPU of the lower computer control module through the internal communication bus interface module, and receive parameter setting instructions from the CPU of the lower computer control module; according to the parameter setting instructions sent by the CPU of the lower computer control module, set the working mode of the program refresh communication interface module, and send the corresponding working status information to the CPU of the lower computer control module; receive the FPGA injection program sent by the integrated electronic subsystem through the program injection module, and store it in the SDRAM storage module; after receiving the FPGA injection program, send a program reception end signal to the CPU of the lower computer control module; read the FPGA injection program in the SDRAM storage module according to the parameter setting instructions of the CPU of the lower computer control module, and send it to the satellite hyperspectral camera to be injected through the program refresh communication interface module.

2. The program injection system for a satellite hyperspectral camera according to claim 1, characterized in that: The program injection module includes a SpaceWire bus controller circuit, four SpaceWire interface chips and two SpaceWire bus interfaces; The first interface of the SpaceWire bus controller circuit is connected to the first interface of the FPGA module, the second interface and the third interface are connected to one end of two SpaceWire bus interfaces through two SpaceWire interface chips respectively, and the other ends of the two SpaceWire bus interfaces are connected to the external integrated electronic subsystem respectively.

3. The program uploading system for a satellite hyperspectral camera according to claim 2, characterized in that: The SpaceWire bus controller circuit is a BM4803AMQRH circuit, and the two SpaceWire interface chips corresponding to the second interface and the third interface of the SpaceWire bus controller circuit are respectively a B54LVDS032LVRH differential-to-single-ended chip and a B54LVDS031LVRH single-ended-to-differential chip.

4. A program injection system for a satellite hyperspectral camera according to any one of claims 1 to 3, characterized in that: The program refresh communication interface module is connected to the satellite hyperspectral camera to be program-uploaded via a program refresh output electrical connector.

5. The program uploading system for a satellite hyperspectral camera according to claim 4, characterized in that: The program refresh communication interface circuit includes a first level conversion unit, a first 485 chip and a second 485 chip; The satellite hyperspectral camera includes a panchromatic camera and a short-wave infrared camera; The first input end of the first level conversion unit is connected to the third interface of the FPGA module, and the first output end is connected to the program refresh output electrical connectors of the full-color camera and the short-wave infrared camera to be program-annotated through the first 485 chip, so as to realize program-annotation; The second output end of the first level conversion unit is connected to the third interface of the FPGA module, and the second input end is connected to the program refresh output electrical connectors of the full-color camera and the short-wave infrared camera to be program-uploaded through the second 485 chip to realize the uploading response.

6. The program uploading system for a satellite hyperspectral camera according to claim 5, characterized in that: The internal communication bus interface module includes a second level conversion unit, a third 485 chip and a fourth 485 chip; The first interactive end of the second level conversion unit is connected to the second interface of the FPGA module, the second interactive end and the third interactive end are respectively connected to the first interactive ends of the third 485 chip and the fourth 485 chip, and the second interactive ends of the third 485 chip and the fourth 485 chip are respectively connected to the CPU of the lower computer control module through the internal communication electrical connector.

7. A method for program annotation of a satellite hyperspectral camera, based on a system for program annotation of a satellite hyperspectral camera according to any one of claims 1 to 6, characterized in that: The following steps are involved: Step 1: Receive parameter setting instructions from the CPU of the lower computer control module through the FPGA module; Step 2, the FPGA module sets the program to refresh the working mode of the communication interface module according to the parameter setting instruction sent by the CPU of the lower computer control module, and sends the corresponding working status information to the CPU of the lower computer control module; Step 3, the FPGA module receives the FPGA upload program sent from the integrated electronic subsystem through the program upload module, and stores it in the SDRAM storage module; Step 4: After receiving the FPGA injection program, the FPGA module sends a program reception end signal to the CPU of the lower computer control module; Step 5: The FPGA module reads out the FPGA injection program in the SDRAM storage module according to the parameter setting instructions of the CPU of the lower computer control module, and sends it to the corresponding satellite hyperspectral camera to be injected with the program through the program refresh communication interface module, thereby realizing the program injection of the satellite hyperspectral camera.

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