Pixel and display device including same
By using a single capacitor and low-level data voltage in the pixels of the display device, the problems of high power consumption, many stains and low resolution in the prior art are solved, and a display effect with lower power consumption and higher resolution is achieved.
Patent Information
- Application Number
- CN202411205239.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-05
- Filing Date
- 2024-08-30
- Publication Date
- 2025-03-07
AI Technical Summary
In existing display devices, pixels contain two capacitors, resulting in increased potential for stains caused by process changes, and limits the resolution of the display panel.
Design a pixel that includes a driving switching element, a write switching element, a compensation switching element, a storage capacitor and a light emitting element, using a single capacitor, driven by a low level data voltage, reduces the possibility of stains and improves resolution.
Reduces power consumption of display devices, reduces stains caused by process changes, and achieves a high-resolution design.
Smart Images
Figure CN119580647A_ABST
Abstract
Description
Technical Field
[0001] The present inventive concept relates to a pixel and a display device including the pixel. More particularly, the present inventive concept relates to a pixel including a capacitor and thus reducing power consumption, reducing stains due to process variations, and realizing a high-resolution design, and a display device including the pixel. Background Art
[0002] Typically, a display device includes a display panel and a display panel driver. The display panel includes a plurality of gate lines, a plurality of data lines, a plurality of emission lines and a plurality of pixels. The display panel driver includes a gate driver, a data driver, an emission driver and a drive controller. The gate driver outputs a gate signal to the gate line. The data driver outputs a data voltage to the data line. The emission driver outputs an emission signal to the emission line. The drive controller controls the gate driver, the data driver and the emission driver.
[0003] When a pixel includes two capacitors, the data voltage is distributed between the two capacitors. Therefore, the data voltage must be at a sufficiently high level to drive a pixel having two capacitors. A high data voltage increases the power consumption of the display device.
[0004] Furthermore, due to process variations, there is a high possibility that stains are generated in the manufacturing process of the capacitor, so that when a pixel includes two capacitors, the possibility of generating stains may further increase.
[0005] Furthermore, when a pixel includes two capacitors, a space occupied by the capacitors increases, so that the resolution of the display panel may be limited. Summary of the invention
[0006] Embodiments of the inventive concept provide a pixel capable of reducing power consumption, reducing stains due to process variations, and realizing a high-resolution design.
[0007] An embodiment of the inventive concept provides a display device including a pixel.
[0008] In an embodiment of a pixel according to the concept of the present invention, the pixel includes a driving switch element, a writing switch element, a compensating switch element, a storage capacitor and a light-emitting element. The driving switch element includes a control electrode connected to a first node, a first electrode connected to a second node and a second electrode connected to a third node. The writing switch element includes a control electrode configured to receive a writing gate signal, a first electrode configured to receive a data voltage and a second electrode connected to a second node. The compensating switch element includes a control electrode configured to receive a compensating gate signal, a first electrode connected to a first node and a second electrode connected to a third node. The storage capacitor includes a first electrode configured to receive a first power voltage and a second electrode connected to a first node. The light-emitting element is configured to emit light based on a driving current flowing through the driving switch element. The writing gate signal is an nth level writing gate signal. The compensating gate signal is an n+kth level writing gate signal. n is a positive integer. k is a positive integer.
[0009] In an embodiment, the write gate signal may be an nth level write gate signal. The compensation gate signal may be an n+1th level write gate signal.
[0010] In an embodiment, the pixel may further include: a first emission switching element including a first electrode connected to a third node and a second electrode connected to the first electrode of the light emitting element; and a second emission switching element including a first electrode configured to receive a first power voltage and a second electrode connected to the second node.
[0011] In an embodiment, the (n+1)th level emission signal may be applied to the control electrode of the first emission switch element. The (n)th level emission signal may be applied to the control electrode of the second emission switch element.
[0012] In an embodiment, the signal applied to the control electrode of the first emission switch element may be the same as the signal applied to the control electrode of the second emission switch element.
[0013] In an embodiment, the pixel may further include an initialization switching element including a control electrode configured to receive an initialization gate signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to the first electrode of the light emitting element.
[0014] In an embodiment, in a first period, the nth level emission signal applied to the control electrode of the second emission switch element may have an invalid level, the n+1th level emission signal applied to the control electrode of the first emission switch element may have an effective level, the write gate signal may have an effective pulse, the compensation gate signal may have an invalid level, and the initialization gate signal may have an invalid level. In a second period after the first period, the nth level emission signal may have an invalid level, the n+1th level emission signal may have an invalid level, the write gate signal may have an invalid level, the compensation gate signal may have an effective pulse, and the initialization gate signal may have an invalid level. In a third period after the second period, the nth level emission signal may have an invalid level and an effective level after the invalid level, the n+1th level emission signal may have an invalid level, the write gate signal may have an invalid level, the compensation gate signal may have an invalid level, and the initialization gate signal may have an effective pulse. In a fourth period after the third period, the nth level emission signal may have an effective level, the n+1th level emission signal may have an effective level, the write gate signal may have an invalid level, the compensation gate signal may have an invalid level, and the initialization gate signal may have an invalid level.
[0015] In an embodiment, in a first period, the nth level emission signal applied to the control electrode of the second emission switch element may have an invalid level, the n+1th level emission signal applied to the control electrode of the first emission switch element may have an effective level, the write gate signal may have a first effective pulse, the compensation gate signal may have an invalid level, and the initialization gate signal may have an invalid level. In a second period after the first period, the nth level emission signal may have an invalid level, the n+1th level emission signal may have an invalid level, the write gate signal may have a second effective pulse, the compensation gate signal may have a first effective pulse, and the initialization gate signal may have an invalid level. In a third period after the second period, the nth level emission signal may have an invalid level and an effective level after the invalid level, the n+1th level emission signal may have an invalid level, the write gate signal may have an invalid level, the compensation gate signal may have a second effective pulse, and the initialization gate signal may have an effective pulse. In a fourth period after the third period, the nth level emission signal may have a valid level, the n+1th level emission signal may have a valid level, the write gate signal may have an invalid level, the compensation gate signal may have an invalid level, and the initialization gate signal may have an invalid level.
[0016] In an embodiment, in a first period, the n-th level emission signal applied to the control electrode of the first emission switch element and the control electrode of the second emission switch element may have an invalid level, the write gate signal may have a first valid pulse, the compensation gate signal may have an invalid level, and the initialization gate signal may have an invalid level. In a second period after the first period, the n-th level emission signal may have an invalid level, the write gate signal may have a second valid pulse, the compensation gate signal may have a first valid pulse, and the initialization gate signal may have an invalid level. In a third period after the second period, the n-th level emission signal may have an invalid level, the write gate signal may have an invalid level, the compensation gate signal may have a second valid pulse, and the initialization gate signal may have a valid pulse. In a fourth period after the third period, the n-th level emission signal may have an invalid level, the write gate signal may have an invalid level, the compensation gate signal may have an invalid level, and the initialization gate signal may have an invalid level.
[0017] In an embodiment, in a first period, the n-th level emission signal applied to the control electrode of the first emission switch element and the control electrode of the second emission switch element may have an invalid level, the write gate signal may have a valid pulse, the compensation gate signal may have an invalid level, and the initialization gate signal may have an invalid level. In a second period after the first period, the n-th level emission signal may have an invalid level, the write gate signal may have an invalid level, the compensation gate signal may have a valid pulse, and the initialization gate signal may have an invalid level. In a third period after the second period, the n-th level emission signal may have an invalid level, the write gate signal may have an invalid level, the compensation gate signal may have an invalid level, and the initialization gate signal may have a valid pulse. In a fourth period after the third period, the n-th level emission signal may have an invalid level, the write gate signal may have an invalid level, the compensation gate signal may have an invalid level, and the initialization gate signal may have an invalid level.
[0018] In an embodiment of a display device according to the present invention, the display device includes: a display panel including pixels; and a display panel driver configured to output a data voltage to the pixels. The pixel includes: a driving switch element, a writing switch element, a compensation switch element, a storage capacitor and a light-emitting element. The driving switch element includes a control electrode connected to a first node, a first electrode connected to a second node and a second electrode connected to a third node. The writing switch element includes a control electrode configured to receive a writing gate signal, a first electrode configured to receive a data voltage and a second electrode connected to a second node. The compensation switch element includes a control electrode configured to receive a compensation gate signal, a first electrode connected to a first node and a second electrode connected to a third node. The storage capacitor includes a first electrode configured to receive a first power voltage and a second electrode connected to a first node. The light-emitting element is configured to emit light based on a driving current flowing through the driving switch element. The writing gate signal is an n-th level writing gate signal. The compensation gate signal is an n+k-th level writing gate signal. n is a positive integer. k is a positive integer.
[0019] In an embodiment, a display panel driver may include: a power regulator including a power terminal configured to receive a data power voltage, a first input terminal configured to receive a reference voltage, and a second input terminal and an output terminal connected to each other; and an amplifier including a power terminal connected to an output terminal of the power regulator, a first input terminal configured to receive first data, a second input terminal configured to receive second data, and an output terminal.
[0020] In an embodiment, the display panel driver may further include a reference voltage generator configured to output a reference voltage to a first input terminal of the power regulator. The reference voltage generator may include: a bipolar junction transistor configured to output a first voltage; a second voltage generator configured to generate a second voltage; a multiplier configured to generate a multiplied voltage by multiplying the second voltage; and an adder configured to add the multiplied voltage to the first voltage to generate the reference voltage.
[0021] In an embodiment, the amplifier may include: a first circuit configured to receive first data and second data; and a second circuit connected to the first circuit to output operation data.
[0022] In an embodiment, the first circuit may include: a first transistor, including a control electrode connected to a first operating node, a first electrode configured to receive a second data power voltage, and a second electrode connected to the first operating node; a second transistor, including a control electrode connected to the first operating node, a first electrode configured to receive the second data power voltage, and a second electrode connected to the second operating node; a third transistor, including a control electrode configured to receive the first data, a first electrode connected to the first operating node, and a second electrode connected to the third operating node; a fourth transistor, including a control electrode configured to receive the second data, a first electrode connected to the second operating node, and a second electrode connected to the third operating node; and a fifth transistor, including a control electrode configured to receive an enable signal, a first electrode connected to the third operating node, and a second electrode connected to ground.
[0023] In an embodiment, the second circuit may include: a sixth transistor, including a control electrode connected to the second operating node, a first electrode configured to receive a second data power voltage, and a second electrode connected to the output terminal of the amplifier; and a seventh transistor, including a control electrode configured to receive a disable signal, a first electrode connected to the output terminal of the amplifier, and a second electrode connected to ground.
[0024] In an embodiment, a level of the second data power voltage may be substantially the same as a level of the data power voltage. A ripple of the second data power voltage may be smaller than a ripple of the data power voltage.
[0025] In an embodiment, the display panel driver may further include a filter including: a diode connected to the output terminal of the amplifier; and a first capacitor connected to the diode.
[0026] In an embodiment, the power conditioner, amplifier and filter may be integrated in the peripheral area of the display panel.
[0027] In an embodiment, the power conditioner, amplifier and filter may be formed as an integrated component. The integrated component may be connected to a display panel.
[0028] According to the pixel and the display device including the pixel, the pixel may include a capacitor. Therefore, the pixel may be driven using a data voltage having a low level. The data voltage having a low level may be used, thereby reducing power consumption of the display device.
[0029] In order to stably drive the display panel using the data voltage having a low level, the power voltage applied to the amplifier may be generated by a power regulator. In addition, the amplifier includes an operator and a driver separated from each other, so that the ripple component of the data voltage can be reduced.
[0030] Furthermore, the number of capacitors of a pixel is reduced to one, thereby making it possible to reduce the possibility of occurrence of stains.
[0031] Furthermore, the number of capacitors of a pixel is reduced to one, so that the space occupied by the capacitor can be reduced, thereby making it possible to improve the resolution of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] The above and other features and advantages of the present inventive concept will become more apparent by describing in detail embodiments of the present inventive concept with reference to the accompanying drawings, in which: Figure 1 is a block diagram illustrating a display device according to an embodiment of the inventive concept; Figure 2 It is shown Figure 1 A circuit diagram of a pixel of a display panel; Figure 3 is shown applied to Figure 2 A timing diagram of an input signal of a pixel; Figure 4 It is shown Figure 1 A circuit diagram of a data driver; Figure 5A is shown to generate an Figure 4 A circuit diagram of a reference voltage generator for a reference voltage of a power regulator; Figure 5B It is shown Figure 5A a graph of a voltage level of a first voltage according to temperature; Figure 5C It is shown Figure 5A a graph of a voltage level of a second voltage according to temperature; Figure 6 It is shown Figure 4 The circuit diagram of the amplifier; Figure 7 is a timing diagram illustrating input signals applied to a pixel of a display device according to an embodiment of the inventive concept; Figure 8 is a circuit diagram illustrating a pixel of a display device according to an embodiment of the inventive concept; Fig. 9 is shown applied to Figure 8 A timing diagram of an input signal of a pixel; Fig.10 is a timing diagram illustrating input signals applied to a pixel of a display device according to an embodiment of the inventive concept; Fig.11 is a block diagram illustrating an electronic device according to an embodiment of the inventive concept; Fig.12 It is shown Fig.11An example diagram of an electronic device implemented as a smart phone; and Fig.13 It is shown Fig.11 FIG. 1 is a diagram of an example of an electronic device implemented as a virtual reality display system. DETAILED DESCRIPTION
[0033] Hereinafter, the inventive concept will be described in detail with reference to the accompanying drawings.
[0034] Figure 1 is a block diagram illustrating a display device according to an embodiment of the inventive concept.
[0035] Reference Figure 1 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, an emission driver 600, and a power voltage generator 700.
[0036] The display panel 100 has a display area on which an image is displayed and a peripheral area adjacent to the display area.
[0037] The display panel 100 includes a plurality of gate lines GWL and GBL, a plurality of data lines DL, a plurality of emission lines EL, and a plurality of pixels electrically connected to the gate lines GWL and GBL, the data lines DL, and the emission lines EL. The gate lines GWL and GBL may extend in a first direction D1, the data lines DL may extend in a second direction D2 crossing the first direction D1, and the emission lines EL may extend in the first direction D1.
[0038] The driving controller 200 receives input image data IMG and input control signal CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, cyan image data, and yellow image data. The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.
[0039] The driving controller 200 generates a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , a fourth control signal CONT4 , and a data signal DATA based on input image data IMG and an input control signal CONT.
[0040] The driving controller 200 generates a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.
[0041] The driving controller 200 generates a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.
[0042] The driving controller 200 generates a data signal DATA based on the input image data IMG. The driving controller 200 outputs the data signal DATA to the data driver 500.
[0043] The driving controller 200 generates a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and outputs the third control signal CONT3 to the gamma reference voltage generator 400 .
[0044] The driving controller 200 generates a fourth control signal CONT4 for controlling the operation of the emission driver 600 based on the input control signal CONT, and outputs the fourth control signal CONT4 to the emission driver 600 .
[0045] The gate driver 300 generates a gate signal driving the gate lines GWL and GBL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may output the gate signal to the gate lines GWL and GBL.
[0046] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to a level of the data signal DATA.
[0047] In an embodiment, the gamma reference voltage generator 400 may be provided in the driving controller 200 or in the data driver 500 .
[0048] The data driver 500 receives the second control signal CONT2 and the data signal DATA from the driving controller 200 and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 converts the data signal DATA into an analog type data voltage using the gamma reference voltage VGREF. The data driver 500 outputs the data voltage to the data line DL.
[0049] The emission driver 600 generates an emission signal to drive the emission line EL in response to the fourth control signal CONT4 received from the driving controller 200. The emission driver 600 may output the emission signal to the emission line EL.
[0050] The power voltage generator 700 may output the data power voltage VDD to the data driver 500. Although not shown in the drawing, the power voltage generator 700 may also output the power voltage to at least one of the display panel 100, the driving controller 200, the gate driver 300, and the gamma reference voltage generator 400.
[0051] Although for ease of explanation, Figure 1 In the embodiment, the gate driver 300 is disposed at a first side of the display panel 100, and the emission driver 600 is disposed at a second side of the display panel 100 opposite to the first side, but the inventive concept may not be limited thereto. For example, both the gate driver 300 and the emission driver 600 may be disposed at a first side of the display panel 100. For example, both the gate driver 300 and the emission driver 600 may be disposed at both sides (e.g., the first side and the second side) of the display panel 100. For example, the gate driver 300 and the emission driver 600 may be integrally formed.
[0052] Figure 2 It is shown Figure 1 1 is a circuit diagram of a pixel of the display panel 100. Figure 3 is shown applied to Figure 2 Timing diagram of the pixel input signal.
[0053] Reference Figures 1 to 3 , the display panel 100 includes a plurality of pixels. Each pixel includes a light emitting element EE.
[0054] The pixel receives a write gate signal GW(n), a compensation gate signal GW(n+1), an initialization gate signal GB, a data voltage VDATA, and emission signals EM(n) and EM(n+1), and the light-emitting element EE of the pixel emits light having a brightness level corresponding to the level of the data voltage VDATA to display an image.
[0055] The pixel includes a driving switching element T1, a writing switching element T2, a compensation switching element T3, a storage capacitor CST, and a light emitting element EE.
[0056] The driving switching element T1 includes a control electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3.
[0057] The write switching element T2 includes a control electrode receiving the write gate signal GW(n), a first electrode receiving the data voltage VDATA, and a second electrode connected to the second node N2.
[0058] The compensation switching element T3 includes a control electrode receiving the compensation gate signal GW(n+1), a first electrode connected to the first node N1, and a second electrode connected to the third node N3.
[0059] The storage capacitor CST (hereinafter, also referred to as “capacitor CST”) includes a first electrode receiving the first power voltage ELVDD and a second electrode connected to the first node N1 .
[0060] The light emitting element EE emits light based on the driving current flowing through the driving switching element T1. The light emitting element EE may be a micro organic light emitting diode (Micro-OLED).
[0061] In the present embodiment, the write gate signal may be the nth level write gate signal GW(n), and the compensation gate signal may be the n+kth level write gate signal GW(n+k), wherein n and k are positive integers independent of each other. For example, the write gate signal may be the nth level write gate signal GW(n), and the compensation gate signal may be the n+1th level write gate signal GW(n+1). In this case, an additional gate drive circuit for generating the compensation gate signal is not required, thereby reducing the dead space of the display device.
[0062] The pixel may further include a first emission switching element T4 and a second emission switching element T5, the first emission switching element T4 including a first electrode connected to the third node N3 and a second electrode connected to the first electrode of the light emitting element EE, the second emission switching element T5 including a first electrode receiving the first power voltage ELVDD and a second electrode connected to the second node N2.
[0063] In this embodiment, the n+mth level emission signal EM(n+m) can be applied to the control electrode of the first emission switch element T4, and the nth level emission signal EM(n) can be applied to the control electrode of the second emission switch element T5. Here, m is a positive integer. For example, the n+1th level emission signal EM(n+1) can be applied to the control electrode of the first emission switch element T4, and the nth level emission signal EM(n) can be applied to the control electrode of the second emission switch element T5.
[0064] The pixel may further include an initialization switching element T6 including a control electrode receiving an initialization gate signal GB, a first electrode receiving an initialization voltage VINT, and a second electrode connected to the first electrode of the light emitting element EE.
[0065] For example, the drive switch element T1, the write switch element T2, the compensation switch element T3, the first emission switch element T4, the second emission switch element T5 and the initialization switch element T6 may be p-type thin film transistors. For example, the drive switch element T1, the write switch element T2, the compensation switch element T3, the first emission switch element T4, the second emission switch element T5 and the initialization switch element T6 may be low temperature polysilicon (LTPS) thin film transistors.
[0066] like Figure 3 As shown in, in the first period DU1, the nth level emission signal EM(n) applied to the control electrode of the second emission switch element T5 may have an invalid level, the n+1th level emission signal EM(n+1) applied to the control electrode of the first emission switch element T4 may have an effective level, the write gate signal GW(n) may have an effective pulse, the compensation gate signal GW(n+1) may have an invalid level, and the initialization gate signal GB may have an invalid level. The first period DU1 may be a data write period.
[0067] In the second period DU2 after the first period DU1, the nth stage emission signal EM(n) may have an invalid level, the n+1th stage emission signal EM(n+1) may have an invalid level, the write gate signal GW(n) may have an invalid level, the compensation gate signal GW(n+1) may have a valid pulse, and the initialization gate signal GB may have an invalid level. The second period DU2 may be a threshold voltage compensation period for the drive switching element T1.
[0068] In the third period DU3 after the second period DU2, the nth level emission signal EM(n) may have an invalid level and an effective level after the invalid level, the n+1th level emission signal EM(n+1) may have an invalid level, the write gate signal GW(n) may have an invalid level, the compensation gate signal GW(n+1) may have an invalid level, and the initialization gate signal GB may have an effective pulse. The third period DU3 may be an initialization period of the light emitting element EE.
[0069] In the fourth period DU4 after the third period DU3, the nth stage emission signal EM(n) may have an effective level, the n+1th stage emission signal EM(n+1) may have an effective level, the write gate signal GW(n) may have an ineffective level, the compensation gate signal GW(n+1) may have an ineffective level, and the initialization gate signal GB may have an ineffective level. The fourth period DU4 may be a light emitting period.
[0070] Figure 4 It is shown Figure 1 1 is a circuit diagram of a data driver 500. Figure 5A is shown to generate an Figure 4 A circuit diagram of a reference voltage generator of a reference voltage VREF of a power regulator PR. Figure 5B It is shown Figure 5A FIG. 1 is a graph of a voltage level of the first voltage VBASE according to temperature. Figure 5C It is shown Figure 5A FIG. 1 is a graph of a voltage level of the second voltage VT according to temperature. Figure 6 It is shown Figure 4 Circuit diagram of amplifier AMP.
[0071] Reference Figures 1 to 6 , the display panel driver may output the data voltage to the pixel. The display panel driver may include a power regulator PR and an amplifier AMP. The display panel driver may further include a reference voltage generator. The display panel driver may further include a filter FT. The power regulator PR, the amplifier AMP, the reference voltage generator, and the filter FT may be included in the data driver 500. However, the inventive concept may not be limited thereto. Alternatively, the power regulator PR, the amplifier AMP, the reference voltage generator, and the filter FT may be disposed outside the data driver 500. At least one of the power regulator PR, the amplifier AMP, the reference voltage generator, and the filter FT may be included in another element or integrated in the display panel 100.
[0072] The power conditioner PR includes a power terminal receiving the data power voltage VDD, a first input terminal receiving the reference voltage VREF, and a second input terminal and an output terminal connected to each other.
[0073] The amplifier AMP may include a power terminal connected to the output terminal of the power regulator PR, a first input terminal receiving the first data PDATA, a second input terminal receiving the second data NDATA, and an output terminal.
[0074] like Figure 4 and Figure 5A As shown in , the reference voltage generator can output the reference voltage VREF to the first input terminal of the power regulator PR. The reference voltage generator may include a bipolar junction transistor B that outputs a first voltage VBASE, a second voltage generator VTG that generates a second voltage VT, a multiplier MP that generates a multiplied voltage MVT by multiplying the second voltage VT, and an adder SUM that adds the multiplied voltage MVT to the first voltage VBASE to generate the reference voltage VREF. The reference voltage generator may also include a current source It provided between the terminal of the reference power voltage VCC and the bipolar junction transistor B.
[0075] like Figure 5B As shown in , the voltage level of the first voltage VBASE may decrease as the temperature increases.
[0076] On the contrary, Figure 5C As shown in , the voltage level of the second voltage VT may increase as the temperature increases.
[0077] The reference voltage generator may generate the reference voltage VREF by adding the multiplication voltage MVT to the first voltage VBASE, so that the reference voltage VREF may be hardly affected by temperature.
[0078] like Figure 6 As shown in , the amplifier AMP may include a first circuit and a second circuit, the first circuit receiving first data PDATA and second data NDATA, the second circuit being connected to the first circuit and outputting operation data VD.
[0079] For example, the first circuit may include: a first transistor TA1, including a control electrode connected to the first operating node NA1, a first electrode receiving the second data power voltage VDD2, and a second electrode connected to the first operating node NA1; a second transistor TA2, including a control electrode connected to the first operating node NA1, a first electrode receiving the second data power voltage VDD2, and a second electrode connected to the second operating node NA2; a third transistor TA3, including a control electrode receiving the first data PDATA, a first electrode connected to the first operating node NA1, and a second electrode connected to the third operating node NA3; a fourth transistor TA4, including a control electrode receiving the second data NDATA, a first electrode connected to the second operating node NA2, and a second electrode connected to the third operating node NA3; and a fifth transistor TA5, including a control electrode receiving an enable signal EN, a first electrode connected to the third operating node NA3, and a second electrode connected to ground.
[0080] The second circuit may include: a sixth transistor TA6, including a control electrode connected to the second operating node NA2, a first electrode receiving the second data power voltage VDD2, and a second electrode connected to the output terminal of the amplifier AMP; and a seventh transistor TA7, including a control electrode receiving a disable signal DIS, a first electrode connected to the output terminal of the amplifier AMP, and a second electrode connected to the ground.
[0081] The data power voltage VDD outputted by the power voltage generator 700 is not directly applied to the amplifier AMP but is applied to the amplifier AMP through the power regulator PR.
[0082] The level of the second data power voltage VDD2 generated by the power regulator PR may be substantially the same as that of the data power voltage VDD. In contrast, the ripple VRIP2 of the second data power voltage VDD2 may be smaller than the ripple VRIP1 of the data power voltage VDD.
[0083] The amplifier AMP includes a first circuit corresponding to the operator and a second circuit corresponding to the driver, and the first circuit and the second circuit are separated from each other so that the ripple component VRIP3 is generated along with the output voltage VD of the amplifier AMP. The ripple component VRIP3 of the output voltage VD of the amplifier AMP may be smaller than the ripple VRIP2 of the second data power voltage VDD2.
[0084] The filter FT may include a diode DD connected to the output terminal of the amplifier AMP and a first capacitor C1 connected to the diode DD.
[0085] The output voltage VD supplied to the filter FT may be substantially the same as the data voltage VDATA output by the filter FT. In contrast, the ripple component VRIP4 of the output voltage VDATA of the filter FT may be smaller than the ripple component VRIP3 of the voltage VD supplied to the filter FT.
[0086] The pixel of the display panel 100 includes only one capacitor, so that the range of the data application voltage and the power consumption of the display device can be reduced. When the range of the data application voltage is small, it is generally difficult to express grayscale well.
[0087] The data voltage VDATA outputted from the display panel driver has a very small ripple component VRIP4, so that even if the range of the data applied voltage is small, a gray scale can be represented. Therefore, the reliability of the display device can be improved.
[0088] In an embodiment of the inventive concept, the power conditioner PR, the amplifier AMP, and the filter FT may be integrated as a system circuit in the peripheral area of the display panel 100 .
[0089] Alternatively, in an embodiment of the inventive concept, the power conditioner PR, the amplifier AMP, and the filter FT may be formed as a separate integrated component. A separate integrated component including the power conditioner PR, the amplifier AMP, and the filter FT may be connected to the display panel 100. For example, the power conditioner PR, the amplifier AMP, and the filter FT may be formed as a separate component that may be mounted on the display panel 100.
[0090] According to the present embodiment, the pixel may include one capacitor CST. Therefore, the pixel may be driven using a data voltage VDATA having a low level. Using the data voltage VDATA having a low level may reduce power consumption of the display device compared to a pixel having two capacitors.
[0091] In order to stably drive the display panel 100 with the data voltage VDATA having a low level, the second data power voltage VDD2 applied to the amplifier AMP may be generated through the power regulator PR. In addition, the amplifier AMP includes an operator and a driver separated from each other, so that the ripple component of the data voltage VDATA can be reduced.
[0092] Furthermore, the number of capacitors CST in a pixel is reduced to one, so that the possibility of occurrence of stains can be reduced.
[0093] Furthermore, the number of capacitors CST of a pixel is reduced to one so that a space occupied by the capacitor CST is reduced, and the resolution of the display panel 100 can be improved.
[0094] For example, the display device according to the present embodiment may be a micro display including a micro organic light emitting diode (Micro-OLED). For example, the pixel may be formed on a silicon substrate. For example, the display device may be a micro display including a pixel formed on a silicon substrate. In the micro display, the level of the data voltage VDATA is reduced, so that power consumption can be reduced. In the micro display, the number of capacitors CST of the pixel is reduced, so that the resolution can be improved.
[0095] Figure 7 is a timing diagram illustrating input signals applied to a pixel of a display device according to an embodiment of the inventive concept.
[0096] Except for the timing of the gate signal, the display device according to the present embodiment is different from the reference Figures 1 to 6 The display device of the previous embodiment described is substantially the same. Therefore, the same reference numerals will be used to refer to the same Figures 1 to 6 The same or similar parts as those described in the previous embodiments are described herein, and any repeated explanation on the above elements will be omitted.
[0097] Reference Figure 1 , Figure 2 as well as Figures 4 to 7 , the display panel 100 includes a plurality of pixels. Each pixel includes a light emitting element EE.
[0098] The pixel receives a write gate signal GW(n), a compensation gate signal GW(n+1), an initialization gate signal GB, a data voltage VDATA, and emission signals EM(n) and EM(n+1), and the light-emitting element EE of the pixel emits light having a brightness level corresponding to the level of the data voltage VDATA to display an image.
[0099] The pixel includes a driving switching element T1, a writing switching element T2, a compensation switching element T3, a storage capacitor CST, and a light emitting element EE.
[0100] The driving timing of the pixel of this embodiment is similar to that of the embodiment except that the write gate signal GW(n) and the compensation gate signal GW(n+1) include two pulses. Figure 3 The driving timing of the pixels is substantially the same. However, the inventive concept may not be limited thereto. Alternatively, the write gate signal GW(n) and the compensation gate signal GW(n+1) may include three or more pulses.
[0101] For example, in the first time period DU1, the nth level emission signal EM(n) applied to the control electrode of the second emission switch element T5 may have an invalid level, the n+1th level emission signal EM(n+1) applied to the control electrode of the first emission switch element T4 may have a valid level, the write gate signal GW(n) may have a first valid pulse, the compensation gate signal GW(n+1) may have an invalid level, and the initialization gate signal GB may have an invalid level.
[0102] In the second period DU2 after the first period DU1, the nth stage emission signal EM(n) may have an inactive level, the n+1th stage emission signal EM(n+1) may have an inactive level, the write gate signal GW(n) may have a second active pulse, the compensation gate signal GW(n+1) may have a first active pulse, and the initialization gate signal GB may have an inactive level. Figure 3 and Figure 7 In the embodiment of the present invention, the second time period DU2 immediately follows the first time period DU1.
[0103] In the third period DU3 after the second period DU2, the nth stage emission signal EM(n) may have an invalid level and an effective level after the invalid level, the n+1th stage emission signal EM(n+1) may have an invalid level, the write gate signal GW(n) may have an invalid level, the compensation gate signal GW(n+1) may have a second effective pulse, and the initialization gate signal GB may have an effective pulse. Figure 3 and Figure 7 In the embodiment of the present invention, the third time period DU3 immediately follows the second time period DU2.
[0104] In the fourth period DU4 after the third period DU3, the nth stage emission signal EM(n) may have a valid level, the n+1th stage emission signal EM(n+1) may have a valid level, the write gate signal GW(n) may have an invalid level, the compensation gate signal GW(n+1) may have an invalid level, and the initialization gate signal GB may have an invalid level. Figure 3 and Figure 7 In the embodiment of the present invention, the fourth time period DU4 immediately follows the third time period DU3.
[0105] According to the present embodiment, the pixel may include one capacitor CST. Therefore, the pixel may be driven using the data voltage VDATA having a low level. Using the data voltage VDATA having a low level may reduce power consumption of the display device.
[0106] In order to stably drive the display panel 100 with the data voltage VDATA having a low level, the second data power voltage VDD2 applied to the amplifier AMP may be generated through the power regulator PR. In addition, the amplifier AMP includes an operator and a driver separated from each other, so that the ripple component of the data voltage VDATA can be reduced.
[0107] Furthermore, the number of capacitors CST of a pixel is reduced to one, so that the possibility of occurrence of stains can be reduced.
[0108] Furthermore, the number of capacitors CST of a pixel is reduced to one, so that a space occupied by the capacitor CST may be reduced, and thus the resolution of the display panel 100 may be improved.
[0109] Figure 8 is a circuit diagram illustrating a pixel of a display device according to an embodiment of the inventive concept. Fig. 9 is shown applied to Figure 8 Timing diagram of the pixel input signal.
[0110] In addition to the emission signal applied to the first emission switch element T4, the display device according to the present embodiment is different from the reference Figures 1 to 6 The display device of the previous embodiment described is substantially the same. Therefore, the same reference numerals will be used to refer to the same Figures 1 to 6 The same or similar parts as those described in the previous embodiments are described herein, and any repeated explanation on the above elements will be omitted.
[0111] Reference Figure 1 , Figures 4 to 6 , Figure 8 and Fig. 9 , the display panel 100 includes a plurality of pixels. Each pixel includes a light emitting element EE.
[0112] The pixel receives the write gate signal GW(n), the compensation gate signal GW(n+1), the initialization gate signal GB, the data voltage VDATA and the emission signal EM(n), and the light emitting element EE of the pixel emits light having a brightness level corresponding to the level of the data voltage VDATA to display an image.
[0113] The pixel includes a driving switching element T1, a writing switching element T2, a compensation switching element T3, a storage capacitor CST, and a light emitting element EE.
[0114] The pixel may further include a first emission switching element T4 and a second emission switching element T5, the first emission switching element T4 including a first electrode connected to the third node N3 and a second electrode connected to the first electrode of the light emitting element EE, the second emission switching element T5 including a first electrode receiving the first power voltage ELVDD and a second electrode connected to the second node N2.
[0115] In this embodiment, the signal applied to the control electrode of the first emission switch element T4 can be the same as the signal applied to the control electrode of the second emission switch element T5. For example, the nth level emission signal EM(n) can be applied to the control electrode of the first emission switch element T4 and the control electrode of the second emission switch element T5.
[0116] In the first time period DU1, the nth level emission signal EM(n) applied to the control electrode of the first emission switch element T4 and the control electrode of the second emission switch element T5 may have an invalid level, the write gate signal GW(n) may have a valid pulse, the compensation gate signal GW(n+1) may have an invalid level, and the initialization gate signal GB may have an invalid level.
[0117] In the second period DU2 after the first period DU1, the nth stage emission signal EM(n) may have an invalid level, the write gate signal GW(n) may have an invalid level, the compensation gate signal GW(n+1) may have a valid pulse, and the initialization gate signal GB may have an invalid level.
[0118] In the third period DU3 after the second period DU2, the nth stage emission signal EM(n) may have an invalid level, the write gate signal GW(n) may have an invalid level, the compensation gate signal GW(n+1) may have an invalid level, and the initialization gate signal GB may have a valid pulse.
[0119] In the fourth period DU4 after the third period DU3, the nth stage emission signal EM(n) may have a valid level, the write gate signal GW(n) may have an invalid level, the compensation gate signal GW(n+1) may have an invalid level, and the initialization gate signal GB may have an invalid level.
[0120] According to the present embodiment, the pixel may include one capacitor CST. Therefore, the pixel may be driven using the data voltage VDATA having a low level. Using the data voltage VDATA having a low level may reduce power consumption of the display device.
[0121] In order to stably drive the display panel 100 with the data voltage VDATA having a low level, the second data power voltage VDD2 applied to the amplifier AMP may be generated through the power regulator PR. In addition, the amplifier AMP includes an operator and a driver separated from each other, so that the ripple component of the data voltage VDATA can be reduced.
[0122] Furthermore, the number of capacitors CST of a pixel is reduced to one, so that the possibility of occurrence of stains can be reduced.
[0123] Furthermore, the number of capacitors CST of a pixel is reduced to one, so that a space occupied by the capacitor CST may be reduced, and thus the resolution of the display panel 100 may be improved.
[0124] Fig.10 is a timing diagram illustrating input signals applied to a pixel of a display device according to an embodiment of the inventive concept.
[0125] Except for the timing of the gate signal, the display device according to the present embodiment is different from the reference Figure 8 and Fig. 9 The display device of the previous embodiment described is substantially the same. Therefore, the same reference numerals will be used to refer to the same Figure 8 and Fig. 9 The same or similar parts as those described in the previous embodiments are described herein, and any repeated explanation on the above elements will be omitted.
[0126] Reference Figure 1 , Figures 4 to 6 , Figure 8 and Fig.10 , the display panel 100 includes a plurality of pixels. Each pixel includes a light emitting element EE.
[0127] The pixel receives a write gate signal GW(n), a compensation gate signal GW(n+1), an initialization gate signal GB, a data voltage VDATA and an emission signal EM(n). The light emitting element EE of the pixel emits light having a brightness level corresponding to the level of the data voltage VDATA to display an image.
[0128] The pixel includes a driving switching element T1, a writing switching element T2, a compensation switching element T3, a storage capacitor CST, and a light emitting element EE.
[0129] The pixel may further include a first emission switching element T4 and a second emission switching element T5, the first emission switching element T4 including a first electrode connected to the third node N3 and a second electrode connected to the first electrode of the light emitting element EE, the second emission switching element T5 including a first electrode receiving the first power voltage ELVDD and a second electrode connected to the second node N2.
[0130] In this embodiment, the signal applied to the control electrode of the first emission switch element T4 can be the same as the signal applied to the control electrode of the second emission switch element T5. For example, the nth level emission signal EM(n) can be applied to the control electrode of the first emission switch element T4 and the control electrode of the second emission switch element T5.
[0131] The driving timing of the pixel of this embodiment is similar to that of the embodiment except that the write gate signal GW(n) and the compensation gate signal GW(n+1) include two pulses. Fig. 9 The driving timing of the pixels is substantially the same. However, the inventive concept may not be limited thereto. Alternatively, the write gate signal GW(n) and the compensation gate signal GW(n+1) may include three or more pulses.
[0132] For example, in the first time period DU1, the nth level emission signal EM(n) applied to the control electrode of the first emission switch element T4 and the control electrode of the second emission switch element T5 may have an invalid level, the write gate signal GW(n) may have a first valid pulse, the compensation gate signal GW(n+1) may have an invalid level, and the initialization gate signal GB may have an invalid level.
[0133] In the second period DU2 after the first period DU1, the n-th stage emission signal EM(n) may have an inactive level, the write gate signal GW(n) may have a second active pulse, the compensation gate signal GW(n+1) may have a first active pulse, and the initialization gate signal GB may have an inactive level. Fig. 9 and Fig.10 In the embodiment of the present invention, the second time period DU2 immediately follows the first time period DU1.
[0134] In the third period DU3 after the second period DU2, the n-th stage emission signal EM(n) may have an inactive level, the write gate signal GW(n) may have an inactive level, the compensation gate signal GW(n+1) may have a second active pulse, and the initialization gate signal GB may have an active pulse. Fig. 9 and Fig.10 In the embodiment of the present invention, the third time period DU3 immediately follows the second time period DU2.
[0135] In the fourth period DU4 after the third period DU3, the n-th stage emission signal EM(n) may have a valid level, the write gate signal GW(n) may have an invalid level, the compensation gate signal GW(n+1) may have an invalid level, and the initialization gate signal GB may have an invalid level. Fig. 9 and Fig.10 In the embodiment of the present invention, the fourth time period DU4 immediately follows the third time period DU3.
[0136] According to the present embodiment, the pixel may include one capacitor CST. Therefore, the pixel may be driven using the data voltage VDATA having a low level. Using the data voltage VDATA having a low level may reduce power consumption of the display device.
[0137] In order to stably drive the display panel 100 with the data voltage VDATA having a low level, the second data power voltage VDD2 applied to the amplifier AMP may be generated through the power regulator PR. In addition, the amplifier AMP includes an operator and a driver separated from each other, so that the ripple component of the data voltage VDATA can be reduced.
[0138] Furthermore, the number of capacitors CST of a pixel is reduced to one, so that the possibility of occurrence of stains can be reduced.
[0139] Furthermore, the number of capacitors CST of a pixel is reduced to one, so that a space occupied by the capacitor CST may be reduced, and thus the resolution of the display panel 100 may be improved.
[0140] Fig.11 is a block diagram illustrating an electronic device according to an embodiment of the inventive concept. Fig.12 It is shown Fig.11 The electronic device is implemented as an example of a smart phone.
[0141] Reference Figures 1 to 12 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 may be Figure 1 In addition, the electronic device 1000 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.
[0142] In an embodiment, Fig.12 As shown in , the electronic device 1000 may be implemented as a smart phone. However, the electronic device 1000 is not limited thereto. For example, the electronic device 1000 may be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet PC, a car navigation system, a computer monitor, a laptop computer, a head mounted display (HMD) device, etc.
[0143] The processor 1010 may perform various computing functions or various tasks. The processor 1010 may be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 1010 may be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 1010 may be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.
[0144] The processor 1010 can output the input image data IMG and the input control signal CONT to Figure 1 A drive controller 200 is provided.
[0145] The memory device 1020 may store data used for the operation of the electronic device 1000. For example, the memory device 1020 may include at least one nonvolatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc.).
[0146] The storage device 1030 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 1040 may include an input device such as a keyboard, a keypad, a mouse device, a touch pad, a touch screen, etc. and an output device such as a printer, a speaker, etc. In some embodiments, a display device 1060 may be included in the I / O device 1040. The power supply 1050 may provide power for the operation of the electronic device 1000. The display device 1060 may be coupled to other components via a bus or other communication link.
[0147] Fig.13 It is shown Fig.11 FIG. 1 is a diagram of an example of an electronic device implemented as a virtual reality display system.
[0148] Reference Fig.11 and Fig.13 , a virtual reality (VR) display system may include a lens 10, a display device 20, and a housing 30. The display device 20 may be disposed adjacent to the lens 10. The housing 30 may accommodate the lens 10 and the display device 20. Fig.13 The lens 10 and the display device 20 are accommodated on a first side of the housing 30, but the inventive concept may not be limited thereto. For example, the lens 10 may be accommodated on a first side of the housing 30, and the display device 20 may be accommodated on a second side of the housing 30 opposite to the first side of the housing 30. When the lens 10 and the display device 20 are accommodated on opposite sides relative to the housing 30, the housing 30 may have a transmissive portion to transmit light.
[0149] For example, the VR display system can be a head-mounted display system worn on the user's head. Although not shown in the figure, the VR display system can also include a headband to fix the VR display system to the user's head.
[0150] Alternatively, the VR display system may be in the form of smart glasses designed in the shape of glasses.
[0151] In addition, the electronic device may be implemented as an augmented reality (AR) display system for supporting augmented reality. The AR display system may have a smartphone shape, a smart glasses shape, a head mounted display shape, etc., but may not be limited to those shapes.
[0152] In addition, the electronic device may be implemented as a mixed reality (MR) display system for supporting mixed reality. The MR display system may have a smartphone shape, a smart glasses shape, a head mounted display shape, etc., but may not be limited to those shapes.
[0153] According to the display device of the inventive concept as explained above, power consumption of the display device may be reduced and display quality of the display panel may be improved.
[0154] The foregoing is an illustration of the inventive concept and is not to be construed as limiting it. Although several embodiments of the inventive concept have been described, it will be readily appreciated by those skilled in the art that many modifications may be made in the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, the device-plus-function clause is intended to cover structures described herein as performing the functions described, and not only structural equivalents, but also equivalent structures. Therefore, it will be understood that the foregoing is an illustration of the inventive concept and is not to be construed as being limited to the specific embodiments disclosed, and modifications to the disclosed embodiments as well as other embodiments are intended to be included within the scope of the appended claims. The inventive concept is defined by the claims and the equivalents of the claims to be included therein.
Claims
1. A pixel, comprising: a driving switch element including a control electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to the third node; a write switch element including a control electrode configured to receive a write gate signal, a first electrode configured to receive a data voltage, and a second electrode connected to the second node; a compensation switching element comprising a control electrode configured to receive a compensation gate signal, a first electrode connected to the first node, and a second electrode connected to the third node; a storage capacitor including a first electrode configured to receive a first power voltage and a second electrode connected to the first node; as well as a light emitting element configured to emit light based on a driving current flowing through the driving switching element, Wherein, the write gate signal is an n-th level write gate signal, Wherein, the compensation gate signal is the n+kth level write gate signal, and Wherein, n is a positive integer, and k is a positive integer.
2. The pixel according to claim 1, wherein: The write gate signal is the nth level write gate signal, and The compensation gate signal is the n+1th level write gate signal.
3. The pixel according to claim 1, further comprising: a first emission switch element, comprising a first electrode connected to the third node and a second electrode connected to the first electrode of the light emitting element; as well as The second emission switch element includes a first electrode configured to receive the first power voltage and a second electrode connected to the second node.
4. The pixel according to claim 3, wherein: The n+1th emission signal is applied to the control electrode of the first emission switch element, and The nth level emission signal is applied to the control electrode of the second emission switch element.
5. The pixel according to claim 3, wherein: The signal applied to the control electrode of the first emission switch element is the same as the signal applied to the control electrode of the second emission switch element.
6. The pixel according to claim 3 further comprises an initialization switching element, wherein the initialization switching element comprises a control electrode configured to receive an initialization gate signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to the first electrode of the light-emitting element.
7. The pixel according to claim 6, wherein: In a first period, the nth level emission signal applied to the control electrode of the second emission switch element has an invalid level, the n+1th level emission signal applied to the control electrode of the first emission switch element has an effective level, the write gate signal has an effective pulse, the compensation gate signal has an invalid level, and the initialization gate signal has an invalid level, wherein, in a second period after the first period, the nth level emission signal has an invalid level, the n+1th level emission signal has an invalid level, the write gate signal has an invalid level, the compensation gate signal has a valid pulse, and the initialization gate signal has an invalid level, wherein, in a third period after the second period, the nth level emission signal has an invalid level and a valid level after the invalid level, the n+1th level emission signal has an invalid level, the write gate signal has an invalid level, the compensation gate signal has an invalid level, and the initialization gate signal has a valid pulse, and Among them, in a fourth time period after the third time period, the nth level emission signal has a valid level, the n+1th level emission signal has a valid level, the write gate signal has an invalid level, the compensation gate signal has an invalid level, and the initialization gate signal has an invalid level.
8. The pixel according to claim 6, wherein: In a first period, the nth level emission signal applied to the control electrode of the second emission switch element has an invalid level, the n+1th level emission signal applied to the control electrode of the first emission switch element has an effective level, the write gate signal has a first effective pulse, the compensation gate signal has an invalid level, and the initialization gate signal has an invalid level, wherein, in a second period after the first period, the nth level emission signal has an invalid level, the n+1th level emission signal has an invalid level, the write gate signal has a second valid pulse, the compensation gate signal has a first valid pulse, and the initialization gate signal has an invalid level, wherein, in a third period after the second period, the nth level emission signal has an invalid level and a valid level after the invalid level, the n+1th level emission signal has an invalid level, the write gate signal has an invalid level, the compensation gate signal has a second valid pulse, and the initialization gate signal has a valid pulse, and Among them, in a fourth time period after the third time period, the nth level emission signal has a valid level, the n+1th level emission signal has a valid level, the write gate signal has an invalid level, the compensation gate signal has an invalid level, and the initialization gate signal has an invalid level.
9. The pixel according to claim 6, wherein: In a first period, the n-th level emission signal applied to the control electrode of the first emission switch element and the control electrode of the second emission switch element has an invalid level, the write gate signal has a first valid pulse, the compensation gate signal has an invalid level, and the initialization gate signal has an invalid level, wherein, in a second period after the first period, the nth level emission signal has an invalid level, the write gate signal has a second valid pulse, the compensation gate signal has a first valid pulse, and the initialization gate signal has an invalid level, wherein, in a third period after the second period, the nth level emission signal has an invalid level, the write gate signal has an invalid level, the compensation gate signal has a second valid pulse, and the initialization gate signal has a valid pulse, and In a fourth period after the third period, the nth stage emission signal has a valid level, the write gate signal has an invalid level, the compensation gate signal has an invalid level, and the initialization gate signal has an invalid level.
10. The pixel according to claim 6, wherein: In a first period, the n-th level emission signal applied to the control electrode of the first emission switch element and the control electrode of the second emission switch element has an invalid level, the write gate signal has a valid pulse, the compensation gate signal has an invalid level, and the initialization gate signal has an invalid level, wherein, in a second period after the first period, the nth level emission signal has an invalid level, the write gate signal has an invalid level, the compensation gate signal has a valid pulse, and the initialization gate signal has an invalid level, wherein, in a third period after the second period, the nth level emission signal has an invalid level, the write gate signal has an invalid level, the compensation gate signal has an invalid level, and the initialization gate signal has a valid pulse, and In a fourth period after the third period, the nth stage emission signal has a valid level, the write gate signal has an invalid level, the compensation gate signal has an invalid level, and the initialization gate signal has an invalid level.
11. A display device, comprising: A display panel, including pixels; as well as A display panel driver is configured to output data voltages to the pixels. Wherein, the pixels include: a driving switch element including a control electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to the third node; a write switch element, comprising a control electrode configured to receive a write gate signal, a first electrode configured to receive the data voltage, and a second electrode connected to the second node; a compensation switching element comprising a control electrode configured to receive a compensation gate signal, a first electrode connected to the first node, and a second electrode connected to the third node; a storage capacitor including a first electrode configured to receive a first power voltage and a second electrode connected to the first node; and a light emitting element configured to emit light based on a driving current flowing through the driving switching element, Wherein, the write gate signal is an n-th level write gate signal, Wherein, the compensation gate signal is the n+kth level write gate signal, and Wherein, n is a positive integer, and k is a positive integer.
12. The display device according to claim 11, wherein: The display panel driver comprises: a power conditioner including a power terminal configured to receive a data power voltage, a first input terminal configured to receive a reference voltage, and a second input terminal and an output terminal connected to each other; and An amplifier includes a power terminal connected to the output terminal of the power conditioner, a first input terminal configured to receive first data, a second input terminal configured to receive second data, and an output terminal.
13. The display device according to claim 12, wherein: The display panel driver further includes a reference voltage generator configured to output the reference voltage to the first input terminal of the power conditioner, and Wherein, the reference voltage generator comprises: a bipolar junction transistor configured to output a first voltage; a second voltage generator configured to generate a second voltage; a multiplier configured to generate a multiplied voltage by multiplying the second voltage; and An adder is configured to add the multiplied voltage to the first voltage to generate the reference voltage.
14. The display device according to claim 12, wherein: The amplifier comprises: a first circuit configured to receive the first data and the second data; and The second circuit is connected to the first circuit to output operation data.
15. The display device according to claim 14, wherein: The first circuit comprises: a first transistor including a control electrode connected to a first operating node, a first electrode configured to receive a second data power voltage, and a second electrode connected to the first operating node; a second transistor including a control electrode connected to the first operating node, a first electrode configured to receive the second data power voltage, and a second electrode connected to a second operating node; a third transistor including a control electrode configured to receive the first data, a first electrode connected to the first operating node, and a second electrode connected to a third operating node; a fourth transistor including a control electrode configured to receive the second data, a first electrode connected to the second operating node, and a second electrode connected to the third operating node; and The fifth transistor includes a control electrode configured to receive an enable signal, a first electrode connected to the third operation node, and a second electrode connected to the ground.
16. The display device according to claim 15, wherein: The second circuit comprises: a sixth transistor including a control electrode connected to the second operating node, a first electrode configured to receive the second data power voltage, and a second electrode connected to the output terminal of the amplifier; and A seventh transistor includes a control electrode configured to receive a disable signal, a first electrode connected to the output terminal of the amplifier, and a second electrode connected to ground.
17. The display device according to claim 16, wherein: The level of the second data power voltage is substantially the same as the level of the data power voltage, and The ripple of the second data power voltage is smaller than the ripple of the data power voltage.
18. The display device according to claim 12, wherein: The display panel driver further includes a filter, wherein the filter includes: a diode connected to the output terminal of the amplifier; and A first capacitor is connected to the diode.
19. The display device according to claim 18, wherein: The power conditioner, the amplifier, and the filter are integrated in a peripheral area of the display panel.
20. The display device according to claim 18, wherein: The power conditioner, the amplifier and the filter are formed as an integrated component, and Wherein, the integrated component is connected to the display panel.