Annealing process for improving stress uniformity of non-doped polycrystalline silicon
By reducing the inlet temperature of the wafer and controlling the annealing temperature in the annealing process, the problem of poor stress uniformity of the non-doped polycrystalline silicon layer in the prior art is solved, and the improvement of stress uniformity and product yield is achieved.
Patent Information
- Application Number
- CN202411663148.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-20
- Publication Date
- 2025-03-07
AI Technical Summary
The existing annealing process is difficult to effectively improve the stress uniformity of the non-doped polysilicon layer while reducing the average stress, resulting in the wafer deformation and product yield being affected.
By adjusting the process chamber temperature of the furnace tube machine to a first preset temperature (usually between 500-600°C), the inlet temperature of the wafer during annealing process is reduced, and the process temperature and cooling rate are controlled during the annealing process to improve stress uniformity.
It is achieved to effectively improve the stress uniformity of the non-doped polysilicon layer while reducing stress, improve product yield, and compatible with existing processes without additional process steps.
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Figure CN119581326A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to an annealing process for improving stress uniformity of non-doped polysilicon. Background Art
[0002] Polysilicon layers are widely used in the formation of semiconductor structures due to their advantages such as mobility due to strong electric field effects and low resistance. However, deposited polysilicon layers usually have large stress. For example, when growing non-doped polysilicon on a single-crystal silicon wafer, due to the lattice mismatch and difference in thermal expansion coefficient between polysilicon and single-crystal silicon, non-doped polysilicon will generate large stress after growth, causing the wafer to have a certain degree of warpage and / or curvature. When the stress is too large, the wafer will also be significantly deformed or even broken.
[0003] In semiconductor technology, furnace annealing is often used to release stress. However, although conventional annealing can reduce the average stress, it is difficult to control the stress uniformity of the wafer, and poor stress uniformity will also affect product yield.
[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention
[0005] The object of the present invention is to provide a new annealing process, which can effectively improve the stress uniformity of the non-doped polysilicon layer after annealing while reducing the average stress.
[0006] In order to solve the above problems, an annealing process for improving stress uniformity of non-doped polysilicon is provided below, comprising the following steps:
[0007] S1. providing a wafer, on which a non-doped polysilicon layer is formed;
[0008] S2, providing a furnace tube machine, and adjusting the temperature of a process chamber of the furnace tube machine to a first preset temperature, wherein the first preset temperature is lower than a standby temperature of the furnace tube machine;
[0009] S3, transferring the wafer into the process chamber;
[0010] S4, raising the temperature of the process chamber to the process temperature and maintaining it for a first preset time;
[0011] S5, adjusting the temperature of the process chamber of the furnace tube to a second preset temperature;
[0012] S6. The wafer is transported out.
[0013] The technical solution of the present application can reduce stress and effectively improve the stress uniformity of non-doped polysilicon after annealing by reducing the chamber temperature of the wafer during annealing.
[0014] In some embodiments, the non-doped polysilicon layer is formed by a chemical vapor deposition process. The annealing process provided in the present application can be applied to various non-doped polysilicon layers.
[0015] In some embodiments, the first preset temperature is below 600° C. Generally, a more suitable stress uniformity can be achieved when the temperature of the inlet cavity is reduced to below 600° C.
[0016] In some embodiments, the first preset temperature is 500-600° C. By controlling the temperature within this range, better stress uniformity can be obtained without increasing the heating time and thermal process too much, and both product performance and production efficiency can be taken into account.
[0017] In some embodiments, the process temperature is 1050° C. to 1070° C. A more suitable annealing temperature is provided to ensure that the stress release requirement is met.
[0018] In some embodiments, in step S4, the heating rate from the first preset temperature to the process temperature is 3-5°C / min.
[0019] In some embodiments, in step S4, the first preset time is 0.5-2 hours. The actual annealing time is selected according to actual needs, and the process compatibility is good.
[0020] In some embodiments, in step S4, a protective gas is introduced, wherein the protective gas is any one of nitrogen, argon or hydrogen. The introduction of the protective gas can ensure a better treatment effect and can ensure that the original structure is not affected.
[0021] In some embodiments, the second preset temperature is 500-600°C.
[0022] In some embodiments, in step S5, the cooling rate from the process temperature to the second preset temperature is 1-3°C / min. Selecting a lower cooling rate can further improve the stress distribution of the wafer.
[0023] Compared with the prior art, the beneficial effects of the present invention mainly include the following: the present application can reduce stress while effectively improving the stress uniformity of non-doped polysilicon after annealing by lowering the chamber temperature of the wafer during annealing treatment, without the need for additional process steps, and has good compatibility with existing processes. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0025] Figure 1 The present invention provides the results of the influence of reducing the annealing process temperature on wafer stress.
[0026] Figure 2 A schematic flow chart of an annealing process provided by the present invention.
[0027] Figure 3 The results of the influence of the annealing process provided in the embodiment of the present invention on wafer stress. DETAILED DESCRIPTION
[0028] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.
[0029] The following will describe the various embodiments of the present application in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present application, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present application can be implemented.
[0030] The steps in the following embodiments do not correspond one to one with the summary of the invention.
[0031] In the prior art, after the growth of non-doped polysilicon, an annealing process is usually used to release stress. However, based on the inventor's long-term observation and experience summary of the actual production process, it is found that the existing annealing process can only play a role in reducing the average stress. After annealing, the polysilicon layer still has the problem of uneven stress distribution, which in turn affects the subsequent process and product yield.
[0032] In order to further improve the problem of stress uniformity, there are several different technical ideas in the prior art, but they all have certain disadvantages and the improvement effect is not obvious.
[0033] Solution 1: Reduce the annealing process temperature and / or annealing time; this solution can only slightly improve stress uniformity. However, reducing the annealing process temperature or annealing time will lead to insufficient stress release, resulting in a high stress mean. Since the main purpose of annealing is to release stress, this solution cannot take into account the requirements of average stress and stress uniformity. Figure 1 As shown, Figure 1 a in the figure is the stress test result after the process temperature is 1070℃. Figure 1 Figure b is the stress test result after the process temperature is 1050°C. As the process temperature drops from 1070°C to 1050°C, the stress uniformity (standard deviation value) of the wafer drops from 8.278 to 6.823, but the average stress increases significantly, from 8.5Mpa to 15.89Mpa.
[0034] Solution 2: Reduce the heating rate; It is understandable that the process temperature of annealing is higher than the standby temperature of the furnace tube. The usual annealing temperature is above 1000°C, such as 1050°C and 1070°C. After the wafer is transferred into the furnace tube, the furnace tube will start to heat up. The rate of heating from the standby temperature to the process temperature is the heating rate; as the heating rate decreases, the stress uniformity will improve. However, a lower heating rate means a longer heating time, and this period is a high-temperature process. Since this increases the high-temperature thermal process, it will have a greater impact on the product structure and electrical parameters.
[0035] Embodiment 1:
[0036] When using a furnace tube for annealing, the temperature of the furnace tube machine when it is in hot standby (idle) is relatively high, usually 800°C. Therefore, when the wafer enters the process chamber of the furnace tube along with the wafer boat, the room temperature environment will change to a high temperature environment of 800°C, and this process only takes a dozen minutes. This causes the surface of non-doped polysilicon to undergo a drastic temperature change, resulting in poor stress uniformity.
[0037] refer to Figure 2 The present invention provides an annealing process for improving stress uniformity of non-doped polysilicon, comprising the following steps:
[0038] Step 1: providing a wafer and growing a non-doped polysilicon layer on the wafer;
[0039] In this embodiment, the wafer used is a single crystal silicon wafer. In other embodiments, other semiconductor wafers may also be used, such as a germanium wafer, a silicon carbide wafer, or a gallium nitride wafer.
[0040] The polysilicon layer grown on the wafer is, in this embodiment, a non-doped polysilicon layer; it can be understood that the polysilicon layer can be grown directly on the surface of the wafer, or can be grown after a semiconductor structure is formed on the wafer, which is not limited here.
[0041] In this embodiment, the non-doped polysilicon layer is formed by a low-pressure chemical vapor deposition process. In other embodiments, a plasma enhanced chemical vapor deposition process may also be used.
[0042] Step 2: providing a furnace tube machine for annealing treatment, and adjusting the temperature of the process chamber to a first preset temperature;
[0043] It is understandable that, under normal circumstances, when the furnace tube is in hot standby mode, the temperature in the process chamber is 800°C, while the temperature of the wafer to be introduced for annealing is room temperature, which is usually between 20-30°C. According to the situation in a general Fab, the room temperature can be considered to be 25°C. The temperature difference here is the main reason for the poor stress uniformity of the wafer after annealing.
[0044] In order to reduce the problem of poor stress uniformity of wafers caused by temperature difference, the method provided in the present application is to reduce the temperature of the process chamber of the furnace tube from the standby temperature to a preset temperature, i.e., the first preset temperature, before the wafer to be annealed is introduced into the process chamber; in the present embodiment, the first preset temperature is 500°C.
[0045] The specific value of the first preset temperature can be determined according to the specific parameters of the annealing process and the characteristics of the product to be annealed. Normally, the first preset temperature can be set between 500-600°C. Of course, in other embodiments, the first preset temperature can be below 500°C. According to the inventor's experiments, the lower the first preset temperature, the better the stress uniformity of amorphous silicon. However, a first preset temperature that is too low will require a longer heating time, thereby reducing the overall production efficiency. In the actual production process, the balance between the annealing process effect and the production efficiency can be considered, and the first preset temperature can be adjusted according to actual needs.
[0046] Step 3: The wafer is passed into the furnace tube for annealing;
[0047] Specifically, the wafer to be processed is loaded into the wafer boat, and then the wafer boat is moved to the process chamber of the furnace tube; at this time, the temperature in the process chamber is the first preset temperature, and in this embodiment, the first preset temperature is 500°C; then the temperature is raised to the process temperature and maintained for the first preset time for annealing. In this embodiment, the process temperature is 1050°C, the heating rate is 5°C / min, and the annealing time is 60min; during the annealing process, a protective gas, such as nitrogen, argon or hydrogen, may also be introduced. In other embodiments, the specific parameters of the annealing process, such as the process temperature, heating rate, annealing time, and the type and flow rate of the protective gas, can be confirmed according to actual needs. For example, the annealing time can be 0.5-2h.
[0048] Step 4: After the process chamber temperature is lowered to a second preset temperature, the wafer is transferred out;
[0049] When the annealing treatment is completed, the process chamber is cooled to a second preset temperature so that the wafer is slowly cooled. A preferred second preset temperature may be between 500-600°C. Normally, the first preset temperature and the second preset temperature may be kept consistent. In other embodiments, the cooling rate to the second preset temperature may also be lower, such as 1°C / min to 3°C / min. The stress distribution of the wafer may be improved by slow cooling. Of course, the second preset temperature may also be set to a higher temperature or directly transmitted.
[0050] In this embodiment, compared with the conventional annealing process, the annealing process of the present application is not changed, so the purpose of releasing the wafer stress can be achieved, and the stress uniformity of the non-doped polysilicon is effectively improved by lowering the initial temperature; Figure 3 As shown, Figure 3 a in the figure is the stress test result of this embodiment. When the wafer is transferred at 500°C, the stress uniformity (standard deviation value) of the wafer after annealing is 4.042. At the same time, since only the first preset temperature is increased to a low-temperature thermal process of 800°C, it will not cause a significant change to the structure and electrical parameters of the product itself, and meets the product's requirements for the annealing process.
[0051] Embodiment 2:
[0052] The steps in this embodiment are basically the same as those in the first embodiment, except that the first preset temperature in this embodiment is 600° C. Figure 3 As shown, Figure 3 b in FIG. 5 is the stress test result of this embodiment. When the wafer is transferred at 600° C., the stress uniformity (standard deviation value) of the wafer after annealing is 5.71.
[0053] In order to facilitate the description, some common English nouns or letters used in the present invention are only used for exemplary reference rather than restrictive interpretation or specific usage, and the protection scope of the present invention should not be limited by their possible Chinese translations or specific letters.
[0054] It should also be noted that, in this document, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.
Claims
1. An annealing process for improving stress uniformity of non-doped polysilicon, characterized in that: The steps include: S1. providing a wafer, on which a non-doped polysilicon layer is formed; S2, providing a furnace tube machine, and adjusting the temperature of a process chamber of the furnace tube machine to a first preset temperature, wherein the first preset temperature is lower than a standby temperature of the furnace tube machine; S3, transferring the wafer into the process chamber; S4, raising the temperature of the process chamber to the process temperature and maintaining it for a first preset time; S5, adjusting the temperature of the process chamber of the furnace tube to a second preset temperature; S6. The wafer is transported out.
2. The annealing process for improving stress uniformity of non-doped polysilicon according to claim 1, characterized in that: The non-doped polysilicon layer is formed by a chemical vapor deposition process.
3. The annealing process for improving stress uniformity of non-doped polysilicon according to claim 1, characterized in that: The first preset temperature is below 600° C.
4. The annealing process for improving stress uniformity of non-doped polysilicon according to claim 3, characterized in that: The first preset temperature is 500-600°C.
5. The annealing process for improving stress uniformity of non-doped polysilicon according to claim 1, characterized in that: The process temperature is 1050°C to 1070°C.
6. The annealing process for improving stress uniformity of non-doped polysilicon according to claim 1, characterized in that: In step S4, the temperature is increased from the first preset temperature to the process temperature at a rate of 3-5°C / min.
7. The annealing process for improving stress uniformity of non-doped polysilicon according to claim 1, characterized in that: In step S4, the first preset time is 0.5-2h.
8. The annealing process for improving stress uniformity of non-doped polysilicon according to claim 1, characterized in that: In step S4, a protective gas is introduced, wherein the protective gas is any one of nitrogen, argon or hydrogen.
9. The annealing process for improving stress uniformity of non-doped polysilicon according to claim 1, characterized in that: The second preset temperature is 500-600°C.
10. The annealing process for improving stress uniformity of non-doped polysilicon according to claim 1, characterized in that: In step S5, the temperature is lowered from the process temperature to the second preset temperature at a rate of 1-3°C / min.