Deep groove shimming isolation device of high-voltage integrated circuit and manufacturing method

Abstract

The invention provides a deep groove shimming isolation device of a high-voltage integrated circuit and a manufacturing method, a groove is carved between an LDMOS (Laterally Diffused Metal Oxide Semiconductor) region and a high-voltage circuit and then is filled with a medium and polycrystalline silicon to form longitudinal floating field plates, and the longitudinal floating field plates are uniformly distributed on a third medium oxide layer to realize isolation of the LDMOS region and a high-voltage circuit region; compared with traditional PN junction isolation, the area is saved; and the longitudinal floating field plate enables the potential of the high-voltage junction terminal to be associated with the potential of the LDMOS through the first metal strip so as to realize uniform distribution of the potentials, so that stronger voltage coupling is realized, and the withstand voltage is improved.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor power devices, and in particular relates to a deep trench shim isolation device for a high voltage integrated circuit and a manufacturing method thereof. Background Art

[0002] High-voltage integrated circuits are monolithic integrated circuits composed of high-voltage electronic devices and traditional control logic circuits or analog circuits. They are widely used in motor control, electronic ballasts, automotive electronics and other fields. High-voltage integrated circuits consist of high-voltage areas and low-voltage areas. LDMOS is usually used as a level converter between the two sides. In the traditional structure, PN isolation is used between the LDMOS area and the high-voltage circuit area, and a PN junction with a low doping concentration is used for withstand voltage. However, due to the large potential difference between the high-voltage area and the low-voltage area, a longer PN junction is required, resulting in a larger layout area. When the device in the LDMOS area itself is reduced in area, it usually causes the device to have a smaller curvature radius on the surface. The small curvature radius of the drain end curvature junction will concentrate the electric field in this area, causing the device to avalanche breakdown prematurely. Summary of the invention

[0003] In view of the shortcomings of the background technology, the present invention proposes a deep trench uniform field isolation technology for high-voltage integrated circuits. A groove is cut in the substrate between the LDMOS area and the high-voltage circuit area to form a dielectric, and then the groove is cut again to deposit polysilicon to form a longitudinal floating field plate. The longitudinal floating field plate is evenly distributed in the dielectric oxide layer to achieve isolation between the LDMOS area and the high-voltage circuit area, saving layout area compared to traditional PN junction isolation. The longitudinal floating field plate uses metal to associate the potential of the high-voltage junction end with the potential distribution of the LDMOS to achieve uniform potential distribution, achieve stronger voltage coupling, and improve withstand voltage.

[0004] To achieve the above-mentioned purpose of the invention, the technical solution of the present invention is as follows:

[0005] A deep trench shim isolation device for a high voltage integrated circuit, comprising:

[0006] A first conductive type semiconductor contact region 11, a first conductive type well region 12, a first conductive type semiconductor substrate 13, a second conductive type semiconductor contact region A21, a second conductive type semiconductor contact region B22, a second conductive type well region A23, a second conductive type drift region A24, a second conductive type semiconductor contact region C25, a second conductive type well region B26, a second conductive type drift region B27, a first dielectric oxide layer 31, a second dielectric oxide layer 32, a third dielectric oxide layer 33, a fourth dielectric oxide layer 34, a control gate polysilicon electrode 41, a first polysilicon electrode 42, a second polysilicon electrode 43, a first metal strip 51, and a second metal strip 52;

[0007] The second conductive type drift region A24 is located above the first conductive type semiconductor substrate 13, the first conductive type well region 12 is located on the left side of the second conductive type drift region A24, the second conductive type well region A23 is located on the right side of the second conductive type drift region A24, the first conductive type semiconductor contact region 11 and the second conductive type semiconductor contact region A21 are located in the first conductive type well region 12, the second conductive type semiconductor contact region B22 is located in the second conductive type well region A23, the second conductive type drift region B27 is located above the first type semiconductor substrate 13, the second conductive type well region B26 is located on the right side of the second conductive type drift region B27, and the second conductive type semiconductor contact region C25 is located in the first conductive type well region B26; the first dielectric oxide layer 31 is located above the first conductive type well region 12, and the left end is in contact with the second conductive type semiconductor contact region A21 and the right end is in contact with the second conductive type drift region A24, the second dielectric oxide layer 32 is located on the upper surface of the second conductive type drift region A24, and the third dielectric oxide layer 33 is located in the high voltage region (marked V in the figure). H ) and the LDMOS region, the fourth dielectric oxide layer 34 is an open rectangle, surrounding the high voltage region and separating the high voltage region from the LDMOS region; the control polysilicon gate 41 covers the upper surface of the first dielectric oxide layer 31 and partially extends to the upper surface of the second dielectric oxide layer 32; the third dielectric oxide layer 33 and the first polysilicon electrode 42 and the fourth dielectric oxide layer 34 and the second polysilicon electrode 43 respectively constitute the longitudinal floating field plate of the isolation region, and the third dielectric oxide layer 33 and the fourth dielectric oxide layer 34 respectively surround the first polysilicon electrode 42 and the second polysilicon electrode 43, the longitudinal The floating field plates are distributed throughout the third dielectric oxide layer 33 and the fourth dielectric oxide layer 34; the first metal strip 51 is located on the upper surface of the third dielectric oxide layer 33, and the longitudinal floating field plate formed by the third dielectric oxide layer 33 and the first polysilicon electrode 42 is connected through the first metal strip 51, and the first metal strip 51 extends to the upper surface of the second dielectric oxide layer 32 in the LDMOS region and is evenly distributed there; the second metal strip 52 is located on the upper surface of the fourth dielectric oxide layer 34, and the longitudinal floating field plate formed by the third dielectric oxide layer 34 and the second polysilicon electrode 43 is connected through the second metal strip 52.

[0008] As a preferred embodiment, the depth of the longitudinal floating field plate is greater than the depth of the second conductive type drift region A24 and the second conductive type drift region B25.

[0009] As a preferred embodiment, the longitudinal spacing of the longitudinal field plates distributed throughout the third dielectric oxide layer 33 is equal, the lateral spacing from the near LDMOS region to the isolation region decreases as the lateral spacing of the third dielectric oxide layer 33 decreases, and finally the lateral spacing is equal, and the lateral and longitudinal spacing of the longitudinal field plates distributed throughout the fourth dielectric oxide layer 34 are equal; and / or the cross-sectional shape of the longitudinal floating field plate in the drift region is rectangular, circular, elliptical, or hexagonal.

[0010] As a preferred embodiment, the first polysilicon electrode 42 and the second polysilicon electrode 43 are formed of heavily doped polysilicon, which can be considered as equipotential bodies when a voltage is applied.

[0011] As a preferred method, the longitudinal field plates distributed throughout the third dielectric oxide layer 33 realize the potential of the high-voltage junction terminal to be associated with the potential of the LDMOS through the first metal strip 51 to achieve uniform potential distribution, achieve stronger voltage coupling, and improve the isolation effect of the high-voltage circuit area. In addition, the width of the third dielectric oxide layer 33 gradually decreases as it moves away from the LDMOS, and is eventually smaller than the width of the second dielectric oxide layer 32, so that the low-voltage circuit area and the high-voltage circuit area have larger areas, which can effectively save layout area compared to PN junction isolation.

[0012] As a preferred method, the process steps of the longitudinal field plate distributed throughout the fourth dielectric oxide layer 34 and the longitudinal field plate distributed in the third dielectric oxide layer 33 are the same, which can simultaneously reduce the process steps and isolate the drain of the LDMOS from the high voltage area.

[0013] As a preferred embodiment, both ends of the third dielectric oxide layer 33 are in contact with the LDMOS and form an open rectangle surrounding the high-voltage area; the fourth dielectric oxide layer 34 and the second metal strip 52 are in contact with the LDMOS and form an open rectangle surrounding the high-voltage area; the width of the third dielectric oxide layer 33 is funnel-shaped near the LDMOS, so that the high-voltage area is isolated from the low-voltage area and there is no sudden change in potential, thereby avoiding premature breakdown here and improving the withstand voltage.

[0014] As a preferred method, the longitudinal floating field plates are uniformly distributed in the isolation region, and the electric field is associated with the LDMOS through the first metal strip 51. Since most of the isolation region is composed of the longitudinal field plates, it can be considered that the voltage of the first metal strip 51 is controlled by the high-voltage junction terminal HVJT, and the first metal strip 51 introduces a series of uniform voltages into the LDMOS to achieve stronger voltage coupling.

[0015] As a preferred embodiment, AA' is a section line pointing from the source end of the LDMOS to the high voltage region and passing through the high voltage junction terminal HVJT. In the device cross-sectional view along the AA' line, the first conductive type well region 12 is above the first conductive type semiconductor substrate 13, the first conductive type semiconductor contact region 11 is located in the first conductive type well region 12 and at the upper left, the left end of the third dielectric oxide layer 33 is in contact with the first conductive type well region 12, and the right end is in contact with the fourth dielectric oxide layer 34, the first polysilicon electrode 42 is uniformly distributed in the third dielectric oxide layer 33, the second polysilicon electrode 43 is uniformly distributed in the fourth dielectric oxide layer 34, the first metal strip 51 is connected to the longitudinal field plate formed by the third dielectric oxide layer 33 and covers the second dielectric oxide layer 32, the second metal strip 52 is connected to the longitudinal field plate in the fourth dielectric oxide layer 34, the second conductive type drift region B27 is located above the first type semiconductor substrate 13, the second conductive type well region B26 is located on the right side of the second conductive type drift region B27, and the second conductive type semiconductor contact region C25 is located in the first conductive type well region B26.

[0016] As a preferred embodiment, the longitudinal field plate is formed by the second polysilicon electrode 43 and the fourth dielectric oxide layer 34 , and the fourth dielectric oxide layer 34 surrounds the second polysilicon electrode 43 . The longitudinal field plates are connected by the second metal strip 52 to form an equipotential body.

[0017] As a preferred method, a longitudinal field plate is formed by the first polysilicon electrode 42 and the third dielectric oxide layer 33, and the third dielectric oxide layer 33 surrounds the first polysilicon electrode 42. The longitudinal field plate realizes that the potential of the high-voltage junction end is associated with the potential distribution of the LDMOS through the first metal strip 51 to achieve uniform potential distribution, achieve stronger voltage coupling, and improve the isolation effect of the high-voltage circuit area.

[0018] As a preferred embodiment, BB' is a section line pointing from the middle of the second dielectric oxide layer 32 to the third dielectric oxide layer 33. In the device cross-sectional view along line BB', the second conductive type drift region A24 is located at the upper left of the first type semiconductor substrate 13, the second dielectric oxide layer 32 is located above the second conductive type drift region A24, the third dielectric oxide layer 33 is located at the upper right of the first type semiconductor substrate 13, the first metal strip 51 is located on the device surface, and the third dielectric oxide layer 33 surrounds the first polysilicon electrode 42.

[0019] As a preferred embodiment, the third dielectric oxide layer 33 surrounds the first polysilicon electrode 42, wherein the first polysilicon electrode 42 is a discrete polysilicon electrode connected by a first metal strip 51 to achieve equipotential, or a continuous polysilicon electrode.

[0020] The present invention also provides a method for manufacturing the deep trench shim isolation device of a high voltage integrated circuit, comprising the following steps:

[0021] Step 1: Select a semiconductor substrate 13 of the first conductivity type;

[0022] Step 2: ion implantation of second conductivity type impurities and thermal process to form a second conductivity type drift region 24;

[0023] Step 3: ion implantation of first conductivity type impurities and push junctions to form a first conductivity type well region 12, and then ion implantation of second conductivity type impurities and push junctions to form a second conductivity type well region A23 and a second conductivity type well region B26;

[0024] Step 4: forming a first dielectric oxide layer 31, and then forming a second dielectric oxide layer 32;

[0025] Step 5: deposit polysilicon and etch to form a control gate polysilicon electrode 41;

[0026] Step 6: forming deep grooves by photolithography and etching;

[0027] Step 7: forming a third dielectric oxide layer 33 and a fourth dielectric oxide layer 34 in the deep trench;

[0028] Step 8: deposit polycrystalline and etch to the silicon plane to form a second polycrystalline silicon electrode 43;

[0029] Step 9: ion implantation to form a first conductivity type semiconductor contact region 11, a second conductivity type semiconductor contact region A21, a second conductivity type semiconductor contact region B22, and a second conductivity type semiconductor contact region C25;

[0030] Step 10: Etching to form contact holes, then depositing and etching the first metal strip 51 , the second metal strip 52 , and the third metal strip 53 .

[0031] As a preferred method, the second conductive type drift region 24 formed by injection and push junction in step 2 is obtained by an epitaxial method; and / or the second conductive type well region A23 and the second conductive type well region B26 obtained by injection and push junction in step 3 are formed by multiple injections of different energies and activations.

[0032] As a preferred embodiment, all the dielectric oxide layers are formed by thermal growth, or by deposition and etching.

[0033] The beneficial effects of the present invention are as follows: an isolation region is formed by using a dielectric, and a uniformly distributed longitudinal field plate is introduced into the isolation region, and the longitudinal field plate is used to associate the potential of the high-voltage junction terminal with the potential distribution of the LDMOS through the metal. Since most of the isolation region is composed of the longitudinal field plate, it can be considered that the voltage of the metal is controlled by the high-voltage junction terminal (HVJT), and a series of uniform voltages are introduced into the LDMOS to achieve stronger voltage coupling, and the isolation effect of the high-voltage circuit region is improved. The width of the isolation region gradually decreases as it moves away from the LDMOS, and is eventually smaller than the width of the LDMOS field oxide, so that the low-voltage circuit region and the high-voltage circuit region have a larger area, which can effectively save the layout area compared to the PN junction isolation. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic structural diagram of a deep trench shim isolation device for a high voltage integrated circuit of Example 1;

[0035] Figure 2 for Figure 1 A top view of

[0036] Figure 3 For along Figure 1 The device cross-section diagram along line AA';

[0037] Figure 4(a)-(b) shows the Figure 1 4(a) is a cross-sectional view of a device with discrete polysilicon electrodes, and FIG. 4(b) is a cross-sectional view of a device with continuous polysilicon electrodes.

[0038] Figure 5(a)-Figure 5(j) This is a schematic diagram of the process flow described in Example 1;

[0039] 11-first conductive type semiconductor contact region, 12-first conductive type well region, 13-first conductive type semiconductor substrate, 21-second conductive type semiconductor contact region A, 22-second conductive type semiconductor contact region B, 23-second conductive type well region A, 24-second conductive type drift region A, 25-second conductive type semiconductor contact region C, 26-second conductive type well region B, 27-second conductive type drift region B, 31-first dielectric oxide layer, 32-second dielectric oxide layer, 33-third dielectric oxide layer, 34-fourth dielectric oxide layer, 41-control gate polysilicon electrode, 42-first polysilicon electrode, 43-second polysilicon electrode, 51-first metal strip, 52-second metal strip, 53-third metal strip. DETAILED DESCRIPTION

[0040] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0041] Example 1

[0042] The deep trench shim isolation device structure of the high voltage integrated circuit described in Example 1 is as follows: Figure 1 shown.

[0043] A first conductive type semiconductor contact region 11, a first conductive type well region 12, a first conductive type semiconductor substrate 13, a second conductive type semiconductor contact region A21, a second conductive type semiconductor contact region B22, a second conductive type well region A23, a second conductive type drift region A24, a second conductive type semiconductor contact region C25, a second conductive type well region B26, a second conductive type drift region B27, a first dielectric oxide layer 31, a second dielectric oxide layer 32, a third dielectric oxide layer 33, a fourth dielectric oxide layer 34, a control gate polysilicon electrode 41, a first polysilicon electrode 42, a second polysilicon electrode 43, a first metal strip 51, and a second metal strip 52;

[0044] The second conductive type drift region A24 is located above the first conductive type semiconductor substrate 13, the first conductive type well region 12 is located on the left side of the second conductive type drift region A24, the second conductive type well region A23 is located on the right side of the second conductive type drift region A24, the first conductive type semiconductor contact region 11 and the second conductive type semiconductor contact region A21 are located in the first conductive type well region 12, the second conductive type semiconductor contact region B22 is located in the second conductive type well region A23, the second conductive type drift region B27 is located above the first type semiconductor substrate 13, the second conductive type well region B26 is located on the right side of the second conductive type drift region B27, and the second conductive type semiconductor contact region C25 is located in the first conductive type well region B26; the first dielectric oxide layer 31 is located above the first conductive type well region 12, and the left end is in contact with the second conductive type semiconductor contact region A21 and the right end is in contact with the second conductive type drift region A24, the second dielectric oxide layer 32 is located on the upper surface of the second conductive type drift region A24, and the third dielectric oxide layer 33 is located in the high voltage region (marked V in the figure). H) and the LDMOS region, the fourth dielectric oxide layer 34 is an open rectangle, surrounding the high voltage region and separating the high voltage region from the LDMOS region; the control polysilicon gate 41 covers the upper surface of the first dielectric oxide layer 31 and partially extends to the upper surface of the second dielectric oxide layer 32; the third dielectric oxide layer 33 and the first polysilicon electrode 42 and the fourth dielectric oxide layer 34 and the second polysilicon electrode 43 respectively constitute the longitudinal floating field plate of the isolation region, and the third dielectric oxide layer 33 and the fourth dielectric oxide layer 34 respectively surround the first polysilicon electrode 42 and the second polysilicon electrode 43, the longitudinal The floating field plates are distributed throughout the third dielectric oxide layer 33 and the fourth dielectric oxide layer 34; the first metal strip 51 is located on the upper surface of the third dielectric oxide layer 33, and the longitudinal floating field plate formed by the third dielectric oxide layer 33 and the first polysilicon electrode 42 is connected through the first metal strip 51, and the first metal strip 51 extends to the upper surface of the second dielectric oxide layer 32 in the LDMOS region and is evenly distributed there; the second metal strip 52 is located on the upper surface of the fourth dielectric oxide layer 34, and the longitudinal floating field plate formed by the third dielectric oxide layer 34 and the second polysilicon electrode 43 is connected through the second metal strip 52.

[0045] Preferably, the depth of the longitudinal floating field plate is greater than the depth of the second conductive type drift region A24 and the second conductive type drift region B25.

[0046] Preferably, the longitudinal spacing of the longitudinal field plates distributed throughout the third dielectric oxide layer 33 is equal, the lateral spacing from the near LDMOS region to the isolation region decreases as the lateral spacing of the third dielectric oxide layer 33 decreases, and finally the lateral spacing is equal, and the lateral and longitudinal spacing of the longitudinal field plates distributed throughout the fourth dielectric oxide layer 34 are equal; and / or the cross-sectional shape of the longitudinal floating field plate in the drift region is rectangular, circular, elliptical, or hexagonal.

[0047] Preferably, the first polysilicon electrode 42 and the second polysilicon electrode 43 are formed of heavily doped polysilicon and can be considered as equipotential bodies when a voltage is applied.

[0048] Preferably, the longitudinal field plates distributed throughout the third dielectric oxide layer 33 realize that the potential of the high-voltage junction terminal is associated with the potential of the LDMOS through the first metal strip 51 to achieve uniform potential distribution, achieve stronger voltage coupling, and improve the isolation effect of the high-voltage circuit area. In addition, the width of the third dielectric oxide layer 33 gradually decreases as it moves away from the LDMOS and is eventually smaller than the width of the second dielectric oxide layer 32, so that the low-voltage circuit area and the high-voltage circuit area have larger areas, which can effectively save layout area compared to PN junction isolation.

[0049] Preferably, the process steps of the longitudinal field plate distributed in the entire fourth dielectric oxide layer 34 and the longitudinal field plate distributed in the third dielectric oxide layer 33 are the same, which can simultaneously form reduced process steps and isolate the drain of the LDMOS from the high voltage area.

[0050] Preferably, the longitudinal floating field plates are uniformly distributed in the isolation region, and are associated with the LDMOS to realize the electric field through the first metal strip 51. Since most of the isolation region is composed of the longitudinal field plates, it can be considered that the voltage of the first metal strip 51 is controlled by the high-voltage junction terminal HVJT, and the first metal strip 51 introduces a series of uniform voltages into the LDMOS to achieve stronger voltage coupling.

[0051] Preferably, the longitudinal field plate is formed by the second polysilicon electrode 43 and the fourth dielectric oxide layer 34 , and the fourth dielectric oxide layer 34 surrounds the second polysilicon electrode 43 , and the longitudinal field plates are connected through the second metal strip 52 to form an equipotential body.

[0052] Preferably, a longitudinal field plate is formed by the first polysilicon electrode 42 and the third dielectric oxide layer 33, and the third dielectric oxide layer 33 surrounds the first polysilicon electrode 42. The longitudinal field plate realizes that the potential of the high-voltage junction end is associated with the potential distribution of the LDMOS through the first metal strip 51 to achieve uniform potential distribution, achieve stronger voltage coupling, and improve the isolation effect of the high-voltage circuit area.

[0053] Preferably, the third dielectric oxide layer 33 surrounds the first polysilicon electrode 42, wherein the first polysilicon electrode 42 is a discrete polysilicon electrode which is then connected by a first metal strip 51 to achieve equipotential, or is a continuous polysilicon electrode.

[0054] Figure 2 for Figure 1 The top view includes: the third dielectric oxide layer 33 contacts the LDMOS at both ends and forms an open rectangle surrounding the high voltage area; the fourth dielectric oxide layer 34 and the second metal strip 52 contact the LDMOS and form an open rectangle surrounding the high voltage area; the width of the third dielectric oxide layer 33 is close to that of the LDMOS and is funnel-shaped; the high voltage area is isolated from the low voltage area and there is no sudden change in potential, and the breakdown voltage is increased.

[0055] Figure 3 For along Figure 1The device cross-sectional view along line AA', AA' being a section line from the source end of the LDMOS to the high voltage region and passing through the high voltage junction terminal HVJT, comprises: in the device cross-sectional view along line AA', the first conductive type well region 12 is above the first conductive type semiconductor substrate 13, the first conductive type semiconductor contact region 11 is located in the first conductive type well region 12 and at the upper left, the left end of the third dielectric oxide layer 33 contacts the first conductive type well region 12, and the right end contacts the fourth dielectric oxide layer 34, the first polysilicon electrode 42 is uniformly distributed in the third dielectric oxide layer 33, the second polysilicon electrode 43 is uniformly distributed in the fourth dielectric oxide layer 34, the first metal strip 51 is respectively connected to the longitudinal field plate formed by the third dielectric oxide layer 33, the second metal strip 52 is connected to the longitudinal field plate in the fourth dielectric oxide layer 34, the second conductive type drift region B27 is located above the first type semiconductor substrate 13, the second conductive type well region B26 is located on the right side of the second conductive type drift region B27, and the second conductive type semiconductor contact region C25 is located in the first conductive type well region B26.

[0056] Figure 4 Figure 1 In the device cross-sectional view along line BB', BB' is a section line pointing from the middle of the second dielectric oxide layer 32 to the third dielectric oxide layer 33. In the device cross-sectional view along line BB', the second conductive type drift region A24 is located at the upper left of the first type semiconductor substrate 13, the second dielectric oxide layer 32 is located above the second conductive type drift region A24, the third dielectric oxide layer 33 is located at the upper right of the first type semiconductor substrate 13, the first metal strip 51 is located on the device surface, and the third dielectric oxide layer 33 surrounds the first polysilicon electrode 42. The polysilicon electrodes can be discrete polysilicon electrodes connected by metal strips to achieve equipotential, or they can be continuous polysilicon electrodes.

[0057] Its basic working principle is as follows:

[0058] Taking the first conductive type semiconductor material as P type as an example, grooves are cut in the substrate between the LDMOS area and the high-voltage circuit area, dielectrics are deposited, and then grooves are cut again to deposit polysilicon to form a vertical floating field plate. The vertical floating field plate is evenly distributed in the dielectric oxide layer to achieve isolation between the LDMOS area and the high-voltage circuit area, replacing the PN junction isolation to reduce the layout area. Most of the isolation area is composed of a vertical field plate. Since it is formed by heavily doped polysilicon, it can be considered that the potential of the vertical field plate is controlled by the high-voltage junction terminal (HVJT). For the LDMOS vertical field plate, it is equivalent to a series of external voltage sources, realizing subjective modulation of the LDMOS potential distribution, achieving stronger voltage coupling, effectively suppressing collision ionization and premature saturation, and improving withstand voltage. At the same time, the isolation area is wider when it is close to the LDMOS area to avoid excessive voltage difference between the silicon layer and the dielectric layer, which leads to premature breakdown.

[0059] As shown in FIG5 , it is a schematic diagram of the process flow of Example 1 of the present invention, which specifically includes the following steps:

[0060] Step 1: Select a semiconductor substrate 13 of the first conductivity type, as shown in FIG5(a);

[0061] Step 2: ion implantation of second conductivity type impurities and thermal process advancement to form a second conductivity type drift region 24, as shown in FIG. 5( b );

[0062] Step 3: ion implant the first conductivity type impurities and push the junction to form the first conductivity type well region 12, and then ion implant the second conductivity type impurities and push the junction to form the second conductivity type well region A23 and the second conductivity type well region B26, as shown in FIG5(c);

[0063] Step 4: forming a first dielectric oxide layer 31, and then forming a second dielectric oxide layer 32, as shown in FIG. 5(d);

[0064] Step 5: depositing polysilicon and etching to form a control gate polysilicon electrode 41, as shown in FIG. 5( e );

[0065] Step 6: forming a deep groove by photolithography and etching, as shown in FIG5(f);

[0066] Step 7: forming a third dielectric oxide layer 33 and a fourth dielectric oxide layer 34 in the deep trench, as shown in FIG. 5( g );

[0067] Step 8: deposit polycrystalline and etch to the silicon plane to form a second polycrystalline silicon electrode 43, as shown in FIG5(h);

[0068] Step 9: ion implantation to form a first conductivity type semiconductor contact region 11, a second conductivity type semiconductor contact region A21, a second conductivity type semiconductor contact region B22, and a second conductivity type semiconductor contact region C25, as shown in FIG. 5( i );

[0069] Step 10: Etching to form contact holes, then depositing and etching the first metal strip 51, the second metal strip 52, and the third metal strip 53, as shown in FIG5(j).

[0070] It should be noted that:

[0071] In the manufacturing method, the second conductive type drift region 24 formed by implantation and push junction in step 2 is obtained by epitaxy;

[0072] In the manufacturing method, the second conductivity type well region A23 and the second conductivity type well region B26 obtained by injection and push junction in step 3 are formed by multiple injections and activations with different energies.

[0073] In the manufacturing method, all the dielectric oxide layers are formed by thermal growth or by deposition and etching.

[0074] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A deep trench shim isolation device for high voltage integrated circuits, characterized in that include: A first conductive type semiconductor contact region (11), a first conductive type well region (12), a first conductive type semiconductor substrate (13), a second conductive type semiconductor contact region A (21), a second conductive type semiconductor contact region B (22), a second conductive type well region A (23), a second conductive type drift region A (24), a second conductive type semiconductor contact region C (25), a second conductive type well region B (26), a second conductive type drift region B (27), a first dielectric oxide layer (31), a second dielectric oxide layer (32), a third dielectric oxide layer (33), a fourth dielectric oxide layer (34), a control gate polysilicon electrode (41), a first polysilicon electrode (42), a second polysilicon electrode (43), a first metal strip (51), and a second metal strip (52); The second conductive type drift region A (24) is located above the first conductive type semiconductor substrate (13), the first conductive type well region (12) is located on the left side of the second conductive type drift region A (24), the second conductive type well region A (23) is located on the right side of the second conductive type drift region A (24), the first conductive type semiconductor contact region (11) and the second conductive type semiconductor contact region A (21) are located in the first conductive type well region (12), the second conductive type semiconductor contact region B (22) is located in the second conductive type well region A (23), and the second conductive type drift region B (27) is located in the first type semiconductor substrate (13). The second conductive type well region B (26) is located on the right side of the second conductive type drift region B (27), and the second conductive type semiconductor contact region C (25) is located in the first conductive type well region B (26); the first dielectric oxide layer (31) is located above the first conductive type well region (12), and the left end is in contact with the second conductive type semiconductor contact region A (21), and the right end is in contact with the second conductive type drift region A (24), the second dielectric oxide layer (32) is located on the upper surface of the second conductive type drift region A (24), the third dielectric oxide layer (33) is located between the high voltage region and the LDMOS region, and the fourth dielectric oxide layer (34) is located between the high voltage region and the LDMOS region. ) is an open rectangle, surrounding the high voltage region and separating the high voltage region from the LDMOS region; the control polysilicon gate (41) covers the upper surface of the first dielectric oxide layer (31) and partially extends to the upper surface of the second dielectric oxide layer (32); the third dielectric oxide layer (33) and the first polysilicon electrode (42) and the fourth dielectric oxide layer (34) and the second polysilicon electrode (43) respectively constitute longitudinal floating field plates of the isolation region, and the third dielectric oxide layer (33) and the fourth dielectric oxide layer (34) respectively surround the first polysilicon electrode (42) and the second polysilicon electrode (43), and the longitudinal floating field plates are distributed throughout the third dielectric oxide layer. The invention relates to a first metal strip (51) located on the upper surface of the third dielectric oxide layer (33) and a fourth dielectric oxide layer (34); the first metal strip (51) is located on the upper surface of the third dielectric oxide layer (33) and connects the third dielectric oxide layer (33) and a vertical floating field plate formed by the first polysilicon electrode (42) through the first metal strip (51); and the first metal strip (51) extends to the upper surface of the second dielectric oxide layer (32) in the LDMOS region and is evenly distributed there; the second metal strip (52) is located on the upper surface of the fourth dielectric oxide layer (34) and connects the third dielectric oxide layer (34) and a vertical floating field plate formed by the second polysilicon electrode (43) through the second metal strip (52).

2. The deep trench shim isolation device for high voltage integrated circuit according to claim 1, characterized in that: The depth of the vertical floating field plate is greater than the depth of the second conductivity type drift region A (24) and the second conductivity type drift region B (25); And / or the longitudinal spacing of the longitudinal field plates distributed throughout the third dielectric oxide layer (33) is equal, the lateral spacing from the near LDMOS region to the isolation region decreases as the lateral spacing of the third dielectric oxide layer (33) decreases, and the lateral spacing is finally equal, and the lateral and longitudinal spacing of the longitudinal field plates distributed throughout the fourth dielectric oxide layer (34) is equal; and / or the cross-sectional shape of the longitudinal floating field plate in the drift region is rectangular, circular, elliptical, or hexagonal; And / or the process steps of the longitudinal field plate distributed in the entire fourth dielectric oxide layer (34) and the longitudinal field plate distributed in the third dielectric oxide layer (33) are the same, which can simultaneously form a reduction in process steps and isolate the drain of the LDMOS from the high voltage area.

3. The deep trench shim isolation device for a high voltage integrated circuit according to claim 1, characterized in that: The longitudinal field plates distributed throughout the third dielectric oxide layer (33) realize the potential of the high-voltage junction terminal being associated with the potential of the LDMOS through the first metal strip (51) to realize the potential uniform distribution. Since most of the isolation region is composed of the longitudinal field plates, it can be considered that the voltage of the first metal strip (51) is controlled by the high-voltage junction terminal HVJT, and the first metal strip (51) introduces a series of uniform voltages into the LDMOS to achieve stronger voltage coupling, thereby improving the isolation effect of the high-voltage circuit region. In addition, the width of the third dielectric oxide layer (33) gradually decreases as it moves away from the LDMOS and is eventually smaller than the width of the second dielectric oxide layer (32), so that the low-voltage circuit region and the high-voltage circuit region have larger areas, and compared with PN junction isolation, it can effectively save the layout area.

4. The deep trench shim isolation device for a high voltage integrated circuit according to claim 1, characterized in that: The two ends of the third dielectric oxide layer (33) are in contact with the LDMOS and form an open rectangle surrounding the high-voltage area; the fourth dielectric oxide layer (34) and the second metal strip (52) are in contact with the LDMOS and form an open rectangle surrounding the high-voltage area; the width of the third dielectric oxide layer (33) is funnel-shaped near the LDMOS, so that the high-voltage area is isolated from the low-voltage area and there is no sudden change in electric potential, thereby avoiding premature breakdown here and improving the withstand voltage.

5. The deep trench shim isolation device for a high voltage integrated circuit according to claim 1, characterized in that: AA' is a section line pointing from the source end of the LDMOS to the high voltage region and passing through the high voltage junction terminal HVJT. In the device cross-sectional view along line AA', the first conductive type well region (12) is above the first conductive type semiconductor substrate (13), the first conductive type semiconductor contact region (11) is located in the first conductive type well region (12) and at the upper left, the left end of the third dielectric oxide layer (33) contacts the first conductive type well region (12), and the right end contacts the fourth dielectric oxide layer (34), the first polysilicon electrode (42) is evenly distributed on the third dielectric oxide layer (33), and the second polysilicon electrode ( 43) are uniformly distributed in the fourth dielectric oxide layer (34), the first metal strip (51) is connected to the longitudinal field plate formed by the third dielectric oxide layer (33) and covers the second dielectric oxide layer (32), the second metal strip (52) is connected to the longitudinal field plate in the fourth dielectric oxide layer (34), the second conductive type drift region B (27) is located above the first type semiconductor substrate (13), the second conductive type well region B (26) is located on the right side of the second conductive type drift region B (27), and the second conductive type semiconductor contact region C (25) is located in the first conductive type well region B (26).

6. The deep trench shim isolation device for high voltage integrated circuit according to claim 5, characterized in that: A longitudinal field plate formed by a second polysilicon electrode (43) and a fourth dielectric oxide layer (34), wherein the fourth dielectric oxide layer (34) surrounds the second polysilicon electrode (43), and the longitudinal field plates are connected via a second metal strip (52) to form an equipotential body; And / or a longitudinal field plate formed by the first polysilicon electrode (42) and the third dielectric oxide layer (33), and the third dielectric oxide layer (33) surrounds the first polysilicon electrode (42), and the longitudinal field plate realizes the potential of the high-voltage junction end to be associated with the potential distribution of the LDMOS through the first metal strip (51) to achieve uniform potential distribution, achieve stronger voltage coupling, and improve the isolation effect of the high-voltage circuit area.

7. The deep trench shim isolation device for high voltage integrated circuit according to claim 1, characterized in that: BB' is a section line pointing from the middle of the second dielectric oxide layer (32) to the third dielectric oxide layer (33). In the device cross-sectional view along line BB', the second conductive type drift region A (24) is located at the upper left of the first type semiconductor substrate (13), the second dielectric oxide layer (32) is located above the second conductive type drift region A (24), the third dielectric oxide layer (33) is located at the upper right of the first type semiconductor substrate (13), the first metal strip (51) is located on the device surface, and the third dielectric oxide layer (33) surrounds the first polysilicon electrode (42).

8. The deep trench shim isolation device for high voltage integrated circuit according to claim 7, characterized in that: The third dielectric oxide layer (33) surrounds the first polysilicon electrode (42), wherein the first polysilicon electrode (42) is a discrete polysilicon electrode, which is then connected by a first metal strip (51) to achieve equipotential, or a continuous polysilicon electrode.

9. A method for manufacturing a deep trench shim isolation device for a high voltage integrated circuit according to any one of claims 1 to 8, characterized in that The steps include: Step 1: Selecting a semiconductor substrate of a first conductivity type (13); Step 2: ion implantation of second conductivity type impurities and thermal process advancement to form a second conductivity type drift region (24); Step 3: ion-implanting first conductivity type impurities and pushing junctions to form a first conductivity type well region (12), and then ion-implanting second conductivity type impurities and pushing junctions to form a second conductivity type well region A (23) and a second conductivity type well region B (26); Step 4: forming a first dielectric oxide layer (31), and then forming a second dielectric oxide layer (32); Step 5: depositing polysilicon and etching to form a control gate polysilicon electrode (41); Step 6: forming deep grooves by photolithography and etching; Step 7: forming a third dielectric oxide layer (33) and a fourth dielectric oxide layer (34) in the deep trench; Step 8: depositing polycrystalline and etching to the silicon plane to form a second polycrystalline silicon electrode (43); Step 9: ion implantation to form a first conductivity type semiconductor contact region (11), a second conductivity type semiconductor contact region A (21), a second conductivity type semiconductor contact region B (22), and a second conductivity type semiconductor contact region C (25); Step 10: Etching to form contact holes, then depositing and etching the first metal strip (51), the second metal strip (52), and the third metal strip (53).

10. The method for manufacturing a deep trench shim isolation device for a high voltage integrated circuit according to claim 9, characterized in that: The second conductivity type drift region (24) formed by implantation and push junction in step 2 is obtained by epitaxy; and / or the second conductivity type well region A (23) and the second conductivity type well region B (26) obtained by implantation and push junction in step 3 are formed by multiple implantations and activations with different energies; And / or all the dielectric oxide layers are formed by thermal growth, or by deposition and etching.

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