Method for manufacturing rear-section super through hole and current metal layer, and super through hole

Abstract

The invention provides a manufacturing method of a back-end super through hole and a current metal layer, and a super through hole, and belongs to the field of semiconductors. The manufacturing method of the rear-section super through hole and the current metal layer comprises the steps that a substrate with grooves is provided, the grooves comprise a through hole groove and a metal layer groove, and the through hole groove penetrates through a dielectric layer in the current metal layer and a dielectric layer in a middle metal layer and exposes a lower metal layer. And partially filling first metal in the through hole groove. And depositing second metal on the surface of the first metal so as to fill the rest part of the through hole groove. Wherein the first metal material is different from the second metal material. According to the method, the super through hole is filled in a segmented manner, so that holes can be prevented from being formed when the super through hole is filled, and the electromigration resistance of the super through hole can be further improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a back-end super via and a current metal layer, and a super via. Background Art

[0002] An integrated circuit (e.g., a chip) may include multiple semiconductor devices such as transistors to perform a desired set of functions. For example, the transistor may be a metal oxide semiconductor (MOS) transistor. Billions of transistors may be used on a single monolithic device to manufacture an integrated circuit (IC). In order to further improve IC capabilities, it is desirable to increase scalability. One form of increasing scalability is to integrate super vias in an integrated circuit (IC). In some semiconductor advanced technologies, super vias may be formed in multiple insulating layers to bypass one or more metal wiring structures in the insulating layer and connect to the metal wiring structure below the insulating layer to reduce via resistance and parasitic capacitance.

[0003] However, when filling the super via, due to the high aspect ratio, voids may be generated during the filling of the super via, which may affect the electromigration of the super via and thus affect the reliability of the super via.

[0004] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0005] The purpose of the present invention is to provide a method for manufacturing a back-end super via and a current metal layer, and a super via, so as to solve the problem that due to the high aspect ratio of the super via, holes will be generated when the super via is filled, thereby affecting the anti-electromigration performance of the super via.

[0006] In order to solve the above technical problems, the present invention provides a method for manufacturing a back-end super via and a current metal layer, wherein the super via at least crosses an intermediate metal layer to connect a lower metal layer with the current metal layer, comprising: Providing a substrate formed with grooves, wherein the grooves include through-hole grooves and metal layer grooves, wherein the through-hole grooves penetrate the dielectric layer in the current metal layer and the middle metal layer and expose the lower metal layer; Partially filling the through-hole trench with a first metal; Depositing a second metal on the surface of the first metal to fill the through-hole trench and the metal layer trench; Wherein, the first metal and the second metal are made of different materials.

[0007] Preferably, partially filling the first metal in the through-hole trench comprises: Depositing a layer of first metal on the inner wall and bottom of the through-hole trench; The first metal is reflowed to partially fill the through-hole trench with the first metal.

[0008] Preferably, the height of the first metal reflow-filled in the through-hole trench is lower than that of the intermediate metal layer.

[0009] Preferably, the first metal ruthenium is formed by ALD / PVD process.

[0010] Preferably, the process conditions for reflowing the metal ruthenium are: in a nitrogen atmosphere, the temperature is in the range of 100° C. to 400° C., and the reflow duration is 10 seconds to 1000 seconds.

[0011] Preferably, the first metal ruthenium in the grooves of the metal layer and on the surface of the dielectric layer is removed by RIE.

[0012] Preferably, the second metal is copper.

[0013] Preferably, the second metal copper is produced by an electrochemical plating process.

[0014] Based on the same inventive concept, the present invention also provides a super through hole, comprising: The above-mentioned production method is used for production.

[0015] Compared with the prior art, the back-end super via and the current metal layer manufacturing method and super via of the present invention have the following advantages: The present invention provides a substrate formed with grooves, wherein the grooves include through-hole grooves and metal layer grooves, wherein the through-hole grooves penetrate the dielectric layer in the current metal layer and the intermediate metal layer and expose the lower metal layer. A first metal is partially filled in the through-hole grooves. A second metal is deposited on the surface of the first metal to fill the remaining portion of the through-hole grooves. The first metal and the second metal are different in material. Therefore, the method for manufacturing the back-end super via and the current metal layer provided by the present invention can avoid the formation of holes when filling the super via by filling the through-hole grooves in sections, thereby improving the anti-electromigration performance of the super via.

[0016] The super via provided by the present invention and the method for manufacturing the back-end super via and the current metal layer provided by the present invention belong to the same inventive concept. Therefore, the super via provided by the present invention has at least all the advantages of the method for manufacturing the back-end super via and the current metal layer provided by the present invention, and can avoid the generation of holes when filling the super via, thereby further improving the anti-electromigration performance of the super via. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a flow chart of a method for manufacturing a back-end super via and a current metal layer in one embodiment of the present invention.

[0018] Figure 2 It is a schematic diagram of a structure for forming a through-hole trench in one embodiment of the present invention.

[0019] Figure 3 It is a schematic structural diagram of sequentially depositing a barrier layer and a seed layer in a through-hole trench in one embodiment of the present invention.

[0020] Figure 4 It is a schematic diagram of the structure after the first metal is reflowed in the through hole trench in one embodiment of the present invention.

[0021] Figure 5 In one embodiment of the present invention, Figure 4 Schematic diagram of the structure formed after the first metal etching.

[0022] Figure 6 It is a schematic diagram of the structure after the second metal is used to fill the through-hole trench in one embodiment of the present invention.

[0023] Figure 7 In one embodiment of the present invention Figure 6 Schematic diagram of the structure after the second metal in the process is ground.

[0024] Figure 8 It is a schematic diagram of the structure after a cap layer is deposited on the surface of the third dielectric layer in one embodiment of the present invention.

[0025] Fig. 9 It is a flow chart of a method for manufacturing a back-end super via and a current metal layer in another embodiment of the present invention.

[0026] Fig.10 It is a schematic diagram of the structure after reflow of the first metal in another embodiment of the present invention.

[0027] Fig.11 It is a schematic structural diagram of using a second metal to fill a through-hole trench in another embodiment of the present invention.

[0028] Fig.12 It is a schematic diagram of the structure after the filled second metal is ground in another embodiment of the present invention.

[0029] Fig.13 It is a schematic diagram of the structure after a cap layer is deposited on the surface of the third dielectric layer in another embodiment of the present invention.

[0030] In the figure, 100-first metal layer; 110-first dielectric layer; 120-cap layer; 200-second metal layer; 210-second dielectric layer; 300-third metal layer; 310-third dielectric layer; 320-through hole groove; 330-metal layer groove; 340-barrier layer; 350-seed layer; 360-first metal; 370-second metal. DETAILED DESCRIPTION

[0031] In order to make the purpose, advantages and features of the present invention clearer, the following is a further detailed description of the back-end super via and the current metal layer manufacturing method and super via proposed by the present invention in combination with the drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to illustrate certain principles of the present invention in the drawings in the specification will also adopt a slightly simplified drawing method. The specific design features of the present invention disclosed herein include, for example, specific dimensions, directions, positions and shapes, which will be determined in part by the specific application and use environment. And, in the embodiments described below, sometimes the same figure mark is used in common between different drawings to represent the same part or a part with the same function, and its repeated description is omitted. In this specification, similar numbers and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0032] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0033] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0034] In the prior art, when making super vias, for mature process nodes of 55 nanometers and below, the aspect ratio of the super vias reaches 8 to 15. Due to the high aspect ratio of the super vias, holes are generated when the super vias are filled, which affects the anti-electromigration problem of the super vias.

[0035] The core idea of ​​the present invention is to provide a method for manufacturing a back-end super via and a current metal layer, which can avoid generating holes in the super via when filling the super via, thereby avoiding affecting the anti-electromigration purpose of the super via.

[0036] In order to realize the above idea, the present invention provides a method for manufacturing a back-end super via and a current metal layer. Figures 1 to 8 A specific implementation of a method for manufacturing a back-end super via and a current metal layer is disclosed. The method for manufacturing a back-end super via and a current metal layer includes the following steps S11 to S15.

[0037] Step S11: providing a substrate formed with grooves, wherein the grooves include a through-hole groove 320 and a metal layer groove 330, wherein the through-hole groove 320 penetrates the dielectric layer in the current metal layer and the middle metal layer and exposes the lower metal layer.

[0038] Specifically, refer to Figure 1 and Figure 2 As shown, multiple metal layers are arranged on the integrated circuit. In this embodiment, the integrated circuit has completed the production of semiconductor devices. By setting the metal layers and interconnecting the metal layers, metal interconnections between different semiconductor devices on the integrated circuit are realized. The multiple metal layers include three or more metal layers. In this embodiment, three metal layers will be used as an example for explanation. The three metal layers are respectively marked as the first metal layer 100, the second metal layer 200 and the third metal layer 300. The three metal layers can also be marked as "MX", "MX+1" and "MX+2" respectively. The first metal layer 100 includes a first dielectric layer 110 and a first metal interconnection structure (not shown in the figure). The second metal layer 200 includes a second dielectric layer 210 and a second metal interconnection structure (not shown in the figure). The third metal layer 300 includes a third dielectric layer 310. A cap layer 120 is deposited between the upper and lower adjacent metal layers to prevent the metal deposited in the metal layer from diffusing. The cap layer 120 is made of insulating materials such as SiN and SiC.

[0039] The first metal layer 100 is adjacent to the second metal layer 200. The first metal layer 100 is not adjacent to the third metal layer 300. The via trench 320 passes through the third dielectric layer 310 and the second dielectric layer 210 and exposes the first metal layer 100 to interconnect the first metal layer 100 and the third metal layer 300.

[0040] When etching to form the grooves, photoresist may be first coated on the surface of the third dielectric layer 310, and the photoresist used to form the through-hole groove 320 and the metal layer groove 330 may be removed by photolithography and development, and the photoresist in other areas may be retained. Then, dry etching, wet etching, or a combination of the two methods may be used to etch the photoresist and the third dielectric layer 310 to form the through-hole groove 320 and the metal layer groove 330, such as Figure 2 The structure shown. For different layer materials, different etching parameters or etching solutions can be used to implement the corresponding process, which will not be described in detail in the present invention. Since the metal layer groove 330 is not the inventive point of the present invention, it will not be described in detail here.

[0041] Step S12: depositing a barrier layer 340 and a seed layer 350 on the inner wall and the bottom of the through-hole trench 320 in sequence.

[0042] Specifically, refer to Figure 1 and Figure 3 As shown, a physical vapor deposition (PVD) or atomic layer deposition (ALD) process can be used on the inner wall and bottom of the through-hole groove 320. First, a barrier layer 340 is deposited on the through-hole groove 320. The material of the barrier layer 340 is tantalum nitride. By depositing tantalum nitride, the metal filled in the through-hole groove 320 can be prevented from diffusion. Then, a seed layer 350 can also be deposited on the surface of the barrier layer 340 by a physical vapor deposition (PVD) or atomic layer deposition (ALD) process. The seed layer 350 can be made of copper metal material to provide electroplating conditions for the subsequent electroplating deposition process of the through-hole groove 320.

[0043] It should be noted that when the barrier layer 340 and the seed layer 350 are deposited by physical vapor deposition (PVD) or atomic layer deposition (ALD) process, the barrier layer 340 and the seed layer 350 are also deposited on the surface of the third dielectric layer 310 .

[0044] Step S13 : depositing a layer of first metal 360 on the surface of the seed layer 350 , and reflowing the first metal 360 to partially fill the through-hole trench 320 with the first metal 360 .

[0045] Specifically, refer to Figure 1 and Figure 4As shown, first, a layer of first metal 360 is deposited on the surface of the seed layer 350 by physical vapor deposition (PVD) or atomic layer deposition (ALD). The thickness of the first metal 360 deposited is in the range of 4nm to 100nm. Then, through a reflow process, the deposited first metal 360 is used as a filling material to partially fill the through-hole trench 320. The first metal 360 can be one of cobalt, ruthenium, rhodium, tungsten, iridium, and nickel. In this embodiment, preferably, the first filling metal is ruthenium. The ruthenium metal reflow condition is in nitrogen (N 2 ) atmosphere, the temperature of the reflow process is 100°C~400°C, and the duration of the reflow process is 10 seconds~1000 seconds. The temperature of the reflow process can be 100°C, 200°C, 250°C, 300°C, 350°C, 400°C, or any temperature in the range of 100°C~400°C. The duration of the reflow process can be 10 seconds, 50 seconds, 100 seconds, 200 seconds, 250 seconds, 300 seconds, or any time in the range of 10 seconds~300 seconds. In this embodiment, preferably, the temperature is 350°C and the reflow duration is 90 seconds.

[0046] By controlling the temperature and duration of the reflow process, the height of the partially filled through-hole trench 320 along the longitudinal direction of the through-hole trench 320 can be controlled by repeating the reflow process once or multiple times. In this embodiment, preferably, the process of metal ruthenium reflow is to 2 The temperature of the reflow process is 350°C and the duration of the reflow process is 90 seconds. The height of the first metal 360 filled in the through-hole groove 320 is lower than the middle metal layer. By controlling the reflow temperature and the reflow time, the first metal 360 filled in the through-hole groove 320 is formed in the longitudinal direction (i.e., Figure 4 The height of the first metal 360 (in the direction of the arrow a in the middle) accounts for 20-40% of the total height of the through-hole trench 320 along the longitudinal direction. By first reflowing the filled portion of the first metal 360 in the through-hole trench 320, when the first filling is performed, the height of the first metal 360 along the longitudinal direction accounts for 20-40% of the total height of the through-hole trench 320, thereby preventing the formation of holes when the super through-hole is filled once, thereby improving the anti-electromigration performance of the super through-hole.

[0047] Step S14 : After the through-hole trench 320 is filled with the first metal 360 , the second metal 370 is filled in the through-hole trench 320 to fill the remaining through-hole trench 320 . When the second metal 370 fills the through-hole trench 320 , the metal layer trench 330 is also filled.

[0048] Specifically, refer to Figure 1 , Figure 5 and Figure 6As shown in FIG. 1 , after the through hole trench 320 is partially filled with the first metal 360, the first metal 360 still remains on the inner wall of the through hole trench 320 and on the surface of the seed layer 350. The remaining first metal 360 is removed by RIE. 2 10~20% CL is introduced into the 2 A higher etching rate can be obtained, and the morphology required for etching can be obtained by adjusting the etching rate. Since dry etching of metal ruthenium to form the required morphology is a prior art, those skilled in the art are already familiar with its specific process steps and process conditions, and will not be described in detail here. After removing the remaining first metal 360, the second metal 370 is filled in the remaining through-hole groove 320 by electroplating process. When filling the remaining through-hole groove 320, the metal layer groove 330 is also filled with the second metal 370. The second metal 370 is copper. The thickness of the copper filled with the second metal 370 is generally 200nm~600nm. Under the same conditions, the diffusion coefficient of the first metal 360 is lower than the diffusion coefficient of the second metal 370. Since the diffusion coefficient of the first metal 360 is ruthenium is lower than that of the second metal 370 copper, a barrier layer 340 for preventing the diffusion of the second metal 370 is not included between the first metal 360 and the second metal 370. That is, the second metal 370 copper is directly filled on the surface of the first metal 360. Ruthenium has a higher anti-electromigration performance than copper, so it can enhance the anti-electromigration of the super through hole. In addition, by filling the through hole groove 320 in sections, the super through hole with a high aspect ratio forms a "short and long" characteristic, making it difficult for the structure to have an electromigration problem, thereby avoiding the formation of holes when filling the through hole groove 320, thereby further improving the anti-electromigration performance of the through hole groove 320. The same conditions include the same temperature, the same impurities, etc.

[0049] Step S15: After filling the second metal 370, a grinding process is performed to planarize the surface of the second metal.

[0050] Specifically, refer to Figure 1 , Figure 7 and Figure 8 As shown in FIG. 1 , the thickness of the formed second metal 370 is higher than the depth of the metal layer trench 330 and covers the surface of the third dielectric layer 310 where the metal layer trench 330 is located. The surface of the second metal 370 is planarized by a chemical mechanical polishing (CMP) process to form the following: Figure 7 After chemical mechanical polishing, the thickness of the second metal 370 copper is in the range of 100nm to 180nm. Then, a cap layer 120 is deposited on the surface of the third metal layer 300 to form a Figure 8At this point, the filling process of the super via is completed, and the production of the "MX+2" metal layer is completed, and the metal interconnection between the first metal layer 100 and the third metal layer 300 is realized.

[0051] In order to realize the above idea, the present invention provides another method for manufacturing a back-end super via and a current metal layer, referring to Figure 2 , Figures 9 to 13 Another specific implementation of a method for manufacturing a back-end super via and a current metal layer is disclosed. The method for manufacturing a back-end super via and a current metal layer includes the following steps S21 to S23.

[0052] Step 21: Provide a substrate with grooves formed thereon, wherein the grooves include a through-hole groove 320 and a metal layer groove 330, wherein the through-hole groove 320 penetrates the dielectric layer in the current metal layer and the middle metal layer and exposes the lower metal layer.

[0053] Specifically, refer to Figure 2 and Fig. 9 As shown, step S21 is the same as step S11, and will not be described in detail. The following description will be made by taking three metal layers, namely, the first metal layer 100, the second metal layer 200 and the third metal layer 300, as an example.

[0054] Step 22 : depositing a layer of first metal 360 on the inner wall and bottom of the through-hole trench 320 , and reflowing the first metal 360 to partially fill the through-hole trench 320 .

[0055] Specifically, refer to Fig. 9 and Fig.10 As shown, the first metal layer 100 can be deposited on the inner wall and bottom of the through-hole trench 320 by using an atomic layer deposition (ALD) process. Then, the first metal layer 100 is used as a filling material, and a reflow process is used to reflow the first metal layer 100 to partially fill the through-hole trench 320, forming a Fig.10 The first metal may be one of cobalt, ruthenium, rhodium, tungsten, iridium and nickel. In this embodiment, preferably, the first filler metal is ruthenium. The ruthenium metal reflow condition is in nitrogen (N 2 ) atmosphere, the temperature of the reflow process is 100°C~400°C, and the duration of the reflow process is 10 seconds~1000 seconds. The temperature of the reflow process can be 100°C, 200°C, 250°C, 300°C, 350°C, 400°C, or any temperature in the range of 100°C~400°C. The duration of the reflow process can be 10 seconds, 50 seconds, 100 seconds, 200 seconds, 250 seconds, 300 seconds, or any time in the range of 10 seconds~300 seconds. In this embodiment, preferably, the temperature is 350°C and the reflow duration is 90 seconds.

[0056] By controlling the temperature and duration of the reflow process, the height of the partially filled through-hole trench 320 along the longitudinal direction of the through-hole trench 320 can be controlled by repeating the reflow process once or multiple times. In this embodiment, preferably, the process of metal ruthenium reflow is to 2 Under the atmosphere, the temperature of the reflow process is 350° C., and the duration of the reflow process is 90 seconds.

[0057] By controlling the reflow temperature and the reflow time, the height of the first metal 360 filled in the via trench 320 along the longitudinal direction accounts for 20-40% of the total height of the via trench 320 along the longitudinal direction.

[0058] In addition, after the first metal 360 is partially filled, the first metal layer 100 remaining in the through-hole trench 320 also enables the next electroplating process to be implemented.

[0059] Step 23: After the through-hole trench 320 is filled with the first metal, a second metal 370 is deposited on the surface of the first metal to fill the remaining through-hole trench 320 . When the second metal 370 fills the through-hole trench 320 , it also includes filling the metal layer trench 330 .

[0060] Specifically, refer to Fig. 9 and Fig.11 As shown, in this embodiment, it is not necessary to sequentially deposit the barrier layer 340 and the seed layer 350 before depositing the metal ruthenium, thereby simplifying the steps of the through-hole trench 320 filling process.

[0061] Step 24: After filling the second metal 370 , a grinding process is performed to planarize the surface of the second metal 370 .

[0062] Specifically, refer to Fig. 9 , Fig.12 and Fig.13 As shown, the through hole trench 320 filled with copper metal is polished by a chemical mechanical polishing (CMP) process to planarize the surface of the second metal 370 to form a Fig.12 Next, a cap layer 120 is deposited on the surface of the third dielectric layer 310 and the second metal 370 to form a Fig.13 At this point, the filling process of the super via is completed, and the manufacturing of the third metal layer 300 is completed, and the metal interconnection between the first metal layer 100 and the third metal layer 300 is realized.

[0063] To realize the above idea, this embodiment also discloses a super through hole, including: manufactured by the manufacturing method as described above.

[0064] The super via provided in this embodiment belongs to the same inventive concept as the method for manufacturing the back-end super via and the current metal layer. Therefore, the super via provided in this embodiment has at least all the advantages of the method for manufacturing the back-end super via and the current metal layer provided in this embodiment, and can avoid the formation of holes when filling the via groove 320, thereby further improving the anti-electromigration performance of the super via.

[0065] In summary, the above embodiments provide detailed descriptions of the methods for making the back-end super vias and the current metal layer, and the different configurations of the super vias. Of course, the above descriptions are only descriptions of the preferred embodiments of the present invention, and are not any limitation to the scope of the present invention. The present invention includes but is not limited to the configurations listed in the above embodiments. Those skilled in the art can draw inferences based on the contents of the above embodiments. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosures shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a back-end super via and a current metal layer, wherein the super via at least crosses an intermediate metal layer to connect a lower metal layer with the current metal layer, characterized in that: include: Providing a substrate with grooves formed thereon, wherein the grooves include through-hole grooves and metal layer grooves, wherein the through-hole grooves penetrate the dielectric layer in the current metal layer and the middle metal layer and expose the lower metal layer; Partially filling the through-hole trench with a first metal; Depositing a second metal on the surface of the first metal to fill the through-hole trench and the metal layer trench; Wherein, the first metal and the second metal are made of different materials.

2. The method according to claim 1, characterized in that: Partially filling the first metal in the through-hole trench comprises: Depositing a layer of first metal on the inner wall and bottom of the through-hole trench; The first metal is reflowed to partially fill the through-hole trench with the first metal.

3. The method according to claim 2, characterized in that: The height of the first metal reflow-filled in the through-hole trench is lower than that of the intermediate metal layer.

4. The method according to claim 3, characterized in that: The first metal is metal ruthenium.

5. The manufacturing method according to claim 4, characterized in that: The first metal ruthenium is formed by ALD / PVD process.

6. The method according to claim 5, characterized in that: The process conditions for reflowing the metal ruthenium are as follows: in a nitrogen atmosphere, the temperature is in the range of 100° C. to 400° C., and the reflow duration is 10 seconds to 1000 seconds.

7. The manufacturing method according to claim 6, characterized in that: The first metal ruthenium in the metal layer groove and on the surface of the dielectric layer is removed by RIE.

8. The manufacturing method according to claim 4, characterized in that: The second metal is copper.

9. The manufacturing method according to claim 8, characterized in that: The second metal copper is produced by electrochemical plating process.

10. A super through hole, characterized in that: include: The method is as described in any one of claims 1 to 9.

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