Semiconductor structure and forming method thereof
By placing the capacitor in the semiconductor structure at the trench surface in the substrate and using a through-silicon conductive structure to penetrate the interlayer dielectric layer and capacitor, the problem of poor performance of the existing semiconductor structure is solved, and the effect of reducing signal loss and adjusting the capacitance value is achieved.
Patent Information
- Application Number
- CN202311155329.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-07
- Publication Date
- 2025-03-07
AI Technical Summary
The existing semiconductor structures have poor performance and are difficult to effectively control parasitic resistance and inductance, which leads to the chip being sensitive to fluctuations in the power supply voltage.
A semiconductor structure is designed in which the capacitor is located on the trench surface within the substrate, the interlayer dielectric layer is located on the substrate surface and the capacitance surface, and the through-silicon conductive structure penetrates the interlayer dielectric layer and the capacitance, and the bottom extends into the substrate.
By surrounding the via-silicon conductive structure by capacitors, the length of the metal trace between the capacitor and the via-silicon conductive structure is shortened, signal loss is reduced, and the capacitance value of the capacitor is adjusted by adjusting the trench depth, so that the capacitance value of the capacitor is adjusted with depth, thus having a wide range of use.
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Figure CN119581456A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art
[0002] Three-dimensional Integrated Circuit (3D IC) stacks multiple homogeneous or heterogeneous chips or circuit modules in the vertical direction and uses through silicon via (TSV) conductive structure to achieve vertical electrical connection. It has many advantages such as high interconnection density, small size, low power consumption and large bandwidth.
[0003] As the driving strength of semiconductor devices increases, the devices have higher current density and larger current transients, causing the chip to be more and more sensitive to fluctuations in the power supply voltage. The circuit needs to reduce the PDN impedance through decoupling capacitors and suppress noise through decoupling or bypass circuits. Therefore, parasitic resistance and inductance must be controlled. The decoupling capacitors must be close to the circuit, so it is necessary to integrate a larger number of capacitor trenches (DTCs) and TSVs in the packaging structure (2.5DInterposer) that uses a vertical interconnect through-hole (TSV) adapter.
[0004] However, existing semiconductor structures have poor performance. Summary of the invention
[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.
[0006] To solve the above problems, the present invention provides a semiconductor structure, including: a substrate having a groove therein; a capacitor located in the groove; and a through silicon via conductive structure penetrating the capacitor, wherein the bottom of the through silicon via conductive structure extends into the substrate.
[0007] Optionally, the width of the trench in a direction parallel to the substrate is greater than a characteristic dimension of the through silicon via conductive structure in a direction parallel to the substrate.
[0008] Optionally, the capacitor includes a capacitor pad located on a portion of the substrate surface and in the groove, a first electrode layer located on the surface of the capacitor pad, a capacitor dielectric layer located on the surface of the first electrode layer, and a second electrode layer located on the surface of the capacitor dielectric layer.
[0009] Optionally, the number of electrode layers of the capacitor is two or more.
[0010] Optionally, the capacitance value of the capacitor is proportional to the depth of the trench.
[0011] Optionally, the symmetry axis of the capacitor overlaps with the symmetry axis of the through silicon via conductive structure.
[0012] Optionally, it also includes an interlayer dielectric layer located on the surface of the substrate and the surface of the capacitor, and a connecting plug located in the interlayer dielectric layer and electrically connected to the capacitor.
[0013] Optionally, it also includes a first dielectric layer located on the surface of the interlayer dielectric layer and the surface of the silicon via conductive structure; a first interconnection layer and a second interconnection layer located on the first dielectric layer, the first interconnection layer is connected to the connecting plug, and the second interconnection layer is connected to the silicon via conductive structure; several layers of second dielectric layers located on the surface of the first dielectric layer; a first interconnection structure and a second interconnection structure located on the surfaces of several layers of second dielectric layers, the first interconnection structure is connected to the first interconnection layer, and the second interconnection structure is connected to the second interconnection layer; a third dielectric layer located on the surface of the second dielectric layer on the top layer; a first pin and a second pin are formed in the third dielectric layer, the first pin is connected to the first interconnection structure, and the second pin is connected to the second interconnection structure.
[0014] Correspondingly, the present invention also provides a method for forming a semiconductor structure, including: providing a substrate; etching the substrate to form a groove in the substrate; forming a capacitor on the surface of a portion of the substrate and in the groove; forming a silicon-through via conductive structure that penetrates the capacitor, wherein the bottom of the silicon-through via conductive structure extends into the substrate.
[0015] Optionally, the width of the trench in a direction parallel to the substrate is greater than a characteristic dimension of the through silicon via conductive structure in a direction parallel to the substrate.
[0016] Optionally, the step of forming a capacitor includes forming a capacitor pad on the surface and in the groove of a portion of the substrate, forming a first electrode layer on the surface of the capacitor pad; forming a capacitor dielectric layer on the surface of the first electrode layer; and forming a second electrode layer on the surface of the capacitor dielectric layer.
[0017] Optionally, the number of electrode layers of the capacitor is two or more.
[0018] Optionally, the capacitance value of the capacitor is proportional to the depth of the trench.
[0019] Optionally, before forming the through silicon via conductive structure, an interlayer dielectric layer is formed on the substrate surface and the capacitor surface, and the interlayer dielectric layer fills the groove; a portion of the interlayer dielectric layer is etched to expose a portion of the capacitor surface on the substrate surface, and a connection hole is formed in the interlayer dielectric layer; and a conductive layer is filled in the connection hole to form a connection plug.
[0020] Optionally, after forming the through silicon via conductive structure, a first dielectric layer is formed on the surface of the interlayer dielectric layer and the surface of the through silicon via conductive structure; a first interconnection layer and a second interconnection layer are formed in the first dielectric layer, the first interconnection layer is connected to the connecting plug, and the second interconnection layer is connected to the through silicon via conductive structure.
[0021] Optionally, after forming the first dielectric layer, the method further includes forming several second dielectric layers on the surface of the first dielectric layer; forming a first interconnect structure and a second interconnect structure in the several second dielectric layers, wherein the first interconnect structure is connected to the first interconnect layer, and the second interconnect structure is connected to the second interconnect layer.
[0022] Optionally, after forming several layers of second dielectric layers, the method further includes forming a third dielectric layer on the surface of the top second dielectric layer; forming a first pin and a second pin in the third dielectric layer, the first pin being connected to the first interconnection structure, and the second pin being connected to the second interconnection structure.
[0023] Optionally, before forming the through silicon via conductive structure, the top surface of the interlayer dielectric layer is planarized.
[0024] Optionally, the steps of forming a through silicon via conductive structure include: etching the interlayer dielectric layer, the capacitor and a partial thickness of the substrate in sequence to form a through hole penetrating the interlayer dielectric layer and the capacitor, wherein the bottom of the through hole extends into the substrate; forming a through silicon via conductive structure liner layer on the surface of the through hole; forming a metal layer on the through silicon via conductive structure liner layer, wherein the metal layer fills the through hole to form a through silicon via conductive structure.
[0025] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0026] In the semiconductor structure of the technical solution of the present invention, the capacitor is located on the surface of the groove in the substrate, and the interlayer dielectric layer is located on the surface of the substrate and the surface of the capacitor; the silicon-through-hole conductive structure penetrates the interlayer dielectric layer and the capacitor, and the bottom extends into the substrate; this semiconductor structure realizes that the silicon-through-hole conductive structure is surrounded by the capacitor, which can shorten the length of the metal routing between the capacitor and the silicon-through-hole conductive structure and reduce signal loss; and the depth of the silicon-through-hole conductive structure is very deep, and the capacitor can also deepen the groove depth as needed, thereby increasing the capacitance of the capacitor, and realizing that the capacitance of the capacitor can be adjusted with the depth, thereby having a wider range of uses.
[0027] In the method for forming a semiconductor structure of the technical solution of the present invention, a substrate is provided; the substrate is etched to form a groove in the substrate; a capacitor is formed on the surface of the groove; an interlayer dielectric layer is formed on the surface of the substrate and the surface of the capacitor, and the interlayer dielectric layer is filled with the capacitor; a silicon-through via conductive structure penetrating the interlayer dielectric layer and the capacitor is formed, and the bottom of the silicon-through via conductive structure extends into the substrate; this formation method enables the silicon-through via conductive structure to be surrounded by the capacitor, which can shorten the length of the metal routing between the capacitor and the silicon-through via conductive structure and reduce signal loss; and the silicon-through via conductive structure is very deep, and the capacitor can also deepen the groove depth as needed, thereby increasing the capacitance of the capacitor, and achieving that the capacitance of the capacitor can be adjusted with the depth, thereby having a wider range of uses. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 It is a cross-sectional schematic diagram of a semiconductor structure;
[0029] Figures 2 to 13 It is a schematic structural diagram of each step of a semiconductor structure and a method for forming the same in one embodiment of the present invention. DETAILED DESCRIPTION
[0030] As the background technology, the performance of the existing split-gate flash memory is relatively poor.
[0031] Figure 1 It is a cross-sectional schematic diagram of a semiconductor structure.
[0032] Please refer to Figure 1 A semiconductor structure includes: a substrate 100; a capacitor 101 located on the substrate 100; a connecting plug 102 electrically connected to the capacitor 101; a through silicon via conductive structure 103 located in the substrate 100; a plurality of dielectric layers 104 located on the surface of the substrate 100 and covering the capacitor 101, wherein at least one dielectric layer 104 is penetrated from the top of the through silicon via conductive structure 103; a first interconnection structure 105 and a second interconnection structure 106 located in the plurality of dielectric layers 104, wherein the first interconnection structure 105 is electrically connected to the connecting plug 102, and the second interconnection structure 106 is electrically connected to the through silicon via conductive structure 103.
[0033] However, in the above semiconductor structure, since the through silicon via conductive structure 103 and the capacitor 101 are separate, the area occupied by the interconnection through the first interconnection structure 105 and the second interconnection structure is very large, the process is very complicated, and the capacitance value of the capacitor 101 is greatly affected by the depth of the capacitor. This is because the size of the independent capacitor 101 is generally less than 1um, and the depth-to-width ratio of the capacitor 101 is generally not large due to the limitation of process capabilities.
[0034] On this basis, the present invention provides a semiconductor structure and a method for forming the same, wherein the capacitor is located on the surface of a groove in a substrate, and the interlayer dielectric layer is located on the surface of the substrate and the surface of the capacitor; a through silicon via conductive structure penetrates the interlayer dielectric layer and the capacitor, and the bottom extends into the substrate; this semiconductor structure realizes that the through silicon via conductive structure is surrounded by the capacitor, which can shorten the length of the metal routing between the capacitor and the through silicon via conductive structure and reduce signal loss; and the through silicon via conductive structure has a very deep depth, and the capacitor can also deepen the groove depth as needed, thereby increasing the capacitance of the capacitor, and realizing that the capacitance of the capacitor can be adjusted with the depth, thereby having a wider range of uses.
[0035] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0036] Figures 2 to 13It is a schematic structural diagram of each step of a semiconductor structure and a method for forming the same in one embodiment of the present invention.
[0037] First, please refer to Figure 2 , providing a substrate 200 , etching the substrate 200 , and forming a trench 201 in the substrate 200 .
[0038] The material of the substrate 200 may include at least one of the following: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, and may also include a multilayer structure consisting of material layers or silicon on insulator (SOI), stacked silicon on insulator (SSOI), etc.
[0039] In this embodiment, the substrate 200 is made of single crystal silicon.
[0040] In this embodiment, the trench 201 is formed by a wet etching process.
[0041] In other embodiments, the trench 201 may be formed by using a dry etching process or a wet ashing process.
[0042] In this embodiment, the trench 201 is formed to provide space for the subsequent formation of a capacitor.
[0043] The process of forming the capacitor on the surface of the substrate 200 and in the groove 201 is shown in FIG. Figures 3 to 5 .
[0044] Please refer to Figure 3 , a capacitor pad 202 is formed on a surface of a portion of the substrate 200 and in the trench 201 .
[0045] In this embodiment, the capacitor pad 202 is formed to isolate the capacitor to be formed subsequently from the substrate 200 .
[0046] In this embodiment, the capacitor pad 202 is formed by an atomic layer deposition process.
[0047] In other embodiments, the capacitor pad 202 may be formed by chemical vapor deposition or physical vapor deposition.
[0048] Please refer to Figure 4 A first electrode layer 203 is formed on the surface of the capacitor pad 202 , a capacitor dielectric layer 204 is formed on the surface of the first electrode layer 203 , and a second electrode layer 205 is formed on the surface of the capacitor dielectric layer 204 .
[0049] In this embodiment, the capacitance value of the capacitor is proportional to the depth of the trench, that is, the deeper the depth of the trench, the greater the capacitance value of the capacitor.
[0050] In this embodiment, the change of the capacitance value of the capacitor is associated with the change of the depth of the groove 201. Where ε-dielectric constant, S-capacitor effective area d-capacitor substrate spacing (constant), and capacitor effective area S = πR 2 +2πR·h, where R is the radius of the capacitor groove and h is the depth of the capacitor groove, so the capacitance value is Therefore, the capacitance value C is positively correlated with the depth h of the trench.
[0051] Please refer to Figure 5 , a portion of the second electrode layer 205 , the capacitor dielectric layer 204 and the first electrode layer 203 on the substrate 200 are etched in sequence to form a capacitor electrode on the substrate 200 to constitute a capacitor 206 .
[0052] In this embodiment, the number of electrode layers of the capacitor 206 is two.
[0053] In other embodiments, the number of electrode layers of the capacitor 206 may also be multiple layers.
[0054] In this embodiment, a wet etching process is used to sequentially etch a portion of the second electrode layer 205 , the capacitor dielectric layer 204 , and the first electrode layer 203 on the substrate 200 to form a capacitor electrode on the substrate 200 .
[0055] In this embodiment, the material of the capacitor dielectric layer 204 is a high-K material.
[0056] In other embodiments, the material of the capacitor dielectric layer 204 may also be silicon nitride or the like.
[0057] In other embodiments, dry etching or other processes may be used to sequentially etch a portion of the second electrode layer 205 , the capacitor dielectric layer 204 , and the first electrode layer 203 on the substrate 200 to form a capacitor electrode on the substrate 200 .
[0058] Please refer to Figure 6 An interlayer dielectric layer 207 is formed on the surface of the substrate 200 and the surface of the capacitor 206 , and the interlayer dielectric layer 207 fills the trench 201 .
[0059] In this embodiment, the material of the interlayer dielectric layer 207 is silicon nitride, silicon oxide, etc.
[0060] In this embodiment, the process of forming the interlayer dielectric layer 207 includes a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, and the like.
[0061] Please refer to Figure 7, partially etching the interlayer dielectric layer 207 to expose the surface of the capacitor 206 on the surface of the substrate 200 , forming a connection hole in the interlayer dielectric layer 207 ; filling the connection hole with a conductive layer to form a connection plug 208 .
[0062] In this embodiment, the capacitor electrodes are led out using the connecting plugs 208 .
[0063] In this embodiment, the connecting plug 208 includes a first connecting plug 208 a and a second connecting plug 208 b . The first connecting plug 208 a is electrically connected to the first electrode layer 203 , and the second connecting plug 208 b is electrically connected to the second electrode layer 205 .
[0064] In this embodiment, before forming the through silicon via conductive structure, the top surface of the interlayer dielectric layer 207 is planarized.
[0065] The process of forming a through silicon via conductive structure penetrating the capacitor 206 and extending the bottom of the through silicon via conductive structure into the substrate 200 is described in detail in detail. Figures 8 to 10 .
[0066] Please refer to Figure 8 , the interlayer dielectric layer 207 , the capacitor 206 and a portion of the thickness of the substrate 200 are etched in sequence to form a through hole 209 penetrating the interlayer dielectric layer 207 and the capacitor 206 , and the bottom of the through hole 209 extends into the substrate 200 .
[0067] In this embodiment, the process of forming the through hole 209 is a wet etching process.
[0068] In this embodiment, in a direction parallel to the surface of the substrate 200 (ie, the X direction in the figure), the through hole 209 has a width D2 that is smaller than a width D1 of the trench 201 .
[0069] In this embodiment, the purpose of forming the through hole 209 is to provide space for the subsequent formation of a through silicon via conductive structure.
[0070] In this embodiment, the width of the through hole 209 is smaller than the width of the trench 201 , thereby forming a structure in which the through hole 209 is surrounded by the trench 201 , preparing for the subsequent formation of a through silicon via conductive structure surrounded by the capacitor 206 .
[0071] Please refer to Fig. 9 , a through silicon via conductive structure liner layer 210 is formed on the surface of the through hole 209 .
[0072] In this embodiment, the TSV conductive structure liner layer 210 serves to isolate the TSV conductive structure from the capacitor 206 and the substrate 200 .
[0073] In this embodiment, a TSV conductive structure liner is formed on the bottom and sidewall surface of the through hole 209 , and a TSV conductive structure liner is also formed on the surface of the interlayer dielectric layer 207 .
[0074] Please refer to Fig.10 A metal layer is formed on the TSV conductive structure liner layer 210 , and the metal layer fills the through hole 209 to form a TSV conductive structure 211 .
[0075] In this embodiment, the process of forming the metal layer is a chemical electroplating process.
[0076] In other embodiments, the metal layer may be formed by chemical vapor deposition or physical vapor deposition.
[0077] In this embodiment, the material of the metal layer is copper.
[0078] In other embodiments, the material of the metal layer may also be aluminum, platinum, etc.
[0079] In this embodiment, after the metal layer is formed, the surface of the metal layer is planarized so that the surface of the metal layer is flush with the surface of the interlayer dielectric layer 207 .
[0080] In this embodiment, please refer to Fig.10 The width ( D1 ) of the trench 201 in a direction parallel to the substrate 200 is greater than the characteristic dimension (CD) of the through silicon via conductive structure 211 in a direction parallel to the substrate 200 .
[0081] In the present embodiment, the through silicon via conductive structure 211 and the capacitor 206 are made into a concentric structure, the symmetry axis of the through silicon via conductive structure 211 coincides with the symmetry axis of the capacitor 206, and the through silicon via conductive structure 211 is surrounded by the capacitor 206, which can shorten the length of the metal routing between the capacitor 206 and the through silicon via conductive structure 211 and reduce signal loss; and the depth of the through silicon via conductive structure 211 is very deep, and the depth of the groove 201 of the capacitor 206 can also be deepened as needed, thereby increasing the capacitance of the capacitor 206, so that the capacitance of the capacitor 206 can be adjusted with the depth, thereby having a wider range of uses.
[0082] In this embodiment, a through silicon via conductive structure 211 is formed on the capacitor 206. This structure can adjust the capacitance of the capacitor 206 by controlling the depth of the groove 201 to meet the requirements of the through silicon via conductive structure 211. At the same time, this concentric structure occupies a smaller area, and more transmission channels can be made in the same area to achieve higher bandwidth transmission.
[0083] In this embodiment, a through silicon via conductive structure 211 is formed in the capacitor 206. After the metal routing of the front capacitor and the interconnection structure is completed, the back side will be thinned to expose the through silicon via conductive structure 211. The through silicon via conductive structure 211 will be connected to the circuit substrate. After the connection, the front capacitor and other devices are connected to the back substrate through the through silicon via conductive structure 211 to realize signal transmission.
[0084] Please refer to Fig.11 A first dielectric layer 212 is formed on the surface of the interlayer dielectric layer 207 and the surface of the through silicon via conductive structure 211, and a first interconnection layer 213 and a second interconnection layer 214 are formed in the first dielectric layer 212. The first interconnection layer 213 is connected to the connecting plug 208, and the second interconnection layer 214 is connected to the through silicon via conductive structure 211.
[0085] In this embodiment, the process of forming the first dielectric layer 212 is a chemical vapor deposition process.
[0086] In other embodiments, the process of forming the first dielectric layer 212 is a physical vapor deposition process or an atomic layer deposition process.
[0087] In this embodiment, the material of the first interconnection layer 213 is copper.
[0088] In other embodiments, the material of the first interconnect layer 213 may also be other metals such as aluminum.
[0089] In this embodiment, the material of the second interconnect layer 214 is copper.
[0090] In other embodiments, the material of the second interconnect layer 214 may also be other metals such as aluminum.
[0091] In this embodiment, the steps of forming the first interconnection layer 213 and the second interconnection layer 214 include forming a first dielectric layer 212 on the surface of the interlayer dielectric layer 207 and the surface of the through silicon via conductive structure 211; etching the first dielectric layer 212 to form a plurality of interconnection layer through holes in the first dielectric layer 212, wherein the interconnection layer through holes respectively expose the surface of the through silicon via conductive structure 211 and the surface of the connecting plug 208; and forming the first interconnection layer 213 and the second interconnection layer 214 in the plurality of interconnection layer through holes.
[0092] Please refer to Fig.12 , a plurality of second dielectric layers 215 are formed on the surface of the first dielectric layer 212 ; a first interconnect structure 216 and a second interconnect structure 217 are formed in the plurality of second dielectric layers 215 , the first interconnect structure 216 is connected to the first interconnect layer 213 , and the second interconnect structure 217 is connected to the second interconnect layer 214 .
[0093] In this embodiment, the material of the first interconnect structure 216 is copper.
[0094] In other embodiments, the material of the first interconnect structure 216 is aluminum or other metals.
[0095] In this embodiment, the material of the second interconnect structure 217 is copper.
[0096] In other embodiments, the material of the second interconnect structure 217 is aluminum or other metals.
[0097] Please refer to Fig.13 A third dielectric layer 218 is formed on the surface of the second dielectric layer 215 at the top layer; a first pin 219 and a second pin 220 are formed in the third dielectric layer 218 , the first pin 219 is connected to the first interconnection structure 216 , and the second pin 220 is connected to the second interconnection structure 217 .
[0098] In this embodiment, the material of the first pin 219 is aluminum.
[0099] In other embodiments, the first pin 219 may be made of other metals.
[0100] In this embodiment, the second pin 220 is made of aluminum.
[0101] In other embodiments, the second pin 220 may be made of other metals.
[0102] Accordingly, please refer to Fig.13 The present invention also provides a semiconductor structure, including a substrate 200 having a groove 201 therein; a capacitor 206 located in the groove 201; a through silicon via conductive structure 211 penetrating the capacitor 206, and the bottom of the through silicon via conductive structure 211 extends into the substrate 200.
[0103] In the present embodiment, this semiconductor structure realizes that the silicon via conductive structure 211 is surrounded by the capacitor 206, which can shorten the length of the metal routing between the capacitor 206 and the silicon via conductive structure 211 and reduce signal loss; and the depth of the silicon via conductive structure 211 is very deep, and the capacitor 206 can also deepen the depth of the groove 201 as needed, thereby increasing the capacitance of the capacitor 206, and realizing that the capacitance of the capacitor 206 can be adjusted with the depth, thereby having a wider range of uses.
[0104] In this embodiment, the TSV conductive structure 211 and the capacitor 206 are formed into a concentric structure, the symmetry axis of the TSV conductive structure 211 coincides with the symmetry axis of the capacitor 206, and the TSV conductive structure 211 is surrounded by the capacitor 206, which can shorten the length of the metal wiring between the capacitor 206 and the TSV conductive structure 211 and reduce signal loss; and the TSV conductive structure 211 is very deep, and the capacitor 206 can also deepen the groove 201 as required, thereby increasing the capacitance of the capacitor 206, so that the capacitance of the capacitor 206 can be adjusted with the depth, thereby having a wider range of uses; at the same time, this structure can adjust the capacitance of the capacitor 206 by controlling the depth of the groove 201 to meet the requirements of the TSV conductive structure 211, and at the same time, the concentric structure occupies a smaller area, and more transmission channels can be made on the same area to achieve higher bandwidth transmission.
[0105] In the present embodiment, the width of the trench 201 in the direction parallel to the substrate 200 is greater than the characteristic dimension of the TSV conductive structure 211 in the direction parallel to the substrate 200 .
[0106] In this embodiment, the capacitor 206 includes a capacitor pad 202 located on a surface of a portion of the substrate 200 and in the groove 201, a first electrode layer 203 located on the surface of the capacitor pad 202, a capacitor dielectric layer 204 located on the surface of the first electrode layer 203, and a second electrode layer 205 located on the surface of the capacitor dielectric layer 204.
[0107] In this embodiment, the number of electrode layers of the capacitor 206 is two.
[0108] In other embodiments, the number of electrode layers of the capacitor 206 may also be multiple layers.
[0109] In this embodiment, the capacitance of the capacitor 206 is proportional to the depth of the trench 201 .
[0110] In this embodiment, the symmetry axis of the capacitor 206 overlaps with the symmetry axis of the TSV conductive structure 211 .
[0111] In this embodiment, an interlayer dielectric layer 207 is further included, which is located on the surface of the substrate 200 and the surface of the capacitor 206 , and a connecting plug 208 is located in the interlayer dielectric layer 207 and is electrically connected to the capacitor 206 .
[0112] In this embodiment, the device further includes a first dielectric layer 212 located on the surface of the interlayer dielectric layer 207 and the surface of the through silicon via conductive structure 211; a first interconnection layer 213 and a second interconnection layer 214 located on the first dielectric layer 212, wherein the first interconnection layer 213 is connected to the connection plug 208, and the second interconnection layer 214 is connected to the through silicon via conductive structure 211; a plurality of second dielectric layers 215 located on the surface of the first dielectric layer 212; a first interconnection structure 216 and a second interconnection structure 217 located on the surface of the plurality of second dielectric layers 215, wherein the first interconnection structure 216 is connected to the first interconnection layer 213, and the second interconnection structure 217 is connected to the second interconnection layer 214; a third dielectric layer 218 located on the surface of the second dielectric layer 215 at the top layer; a first pin 219 and a second pin 220 are formed in the third dielectric layer 218, wherein the first pin 219 is connected to the first interconnection structure 216, and the second pin 220 is connected to the second interconnection structure 217.
[0113] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A semiconductor structure, characterized in that: include: A substrate having a groove therein; a capacitor located within the trench; A through silicon via conductive structure passes through the capacitor, and the bottom of the through silicon via conductive structure extends into the substrate.
2. The semiconductor structure according to claim 1, wherein: The width of the trench in a direction parallel to the substrate is greater than a characteristic dimension of the through silicon via conductive structure in a direction parallel to the substrate.
3. The semiconductor structure according to claim 1, wherein: The capacitor includes a capacitor pad located on a portion of the substrate surface and in the groove, a first electrode layer located on the surface of the capacitor pad, a capacitor dielectric layer located on the surface of the first electrode layer, and a second electrode layer located on the surface of the capacitor dielectric layer.
4. The semiconductor structure according to claim 1, wherein: The capacitor has two or more electrode layers.
5. The semiconductor structure according to claim 1, wherein: The capacitance value of the capacitor is proportional to the depth of the groove.
6. The semiconductor structure according to claim 1, wherein: The symmetry axis of the capacitor overlaps with the symmetry axis of the through silicon via conductive structure.
7. The semiconductor structure according to claim 1, wherein: It also includes an interlayer dielectric layer located on the surface of the substrate and the surface of the capacitor, and a connecting plug located in the interlayer dielectric layer and electrically connected to the capacitor.
8. The semiconductor structure according to claim 7, wherein: It also includes a first dielectric layer located on the surface of the interlayer dielectric layer and the surface of the through silicon via conductive structure; A first interconnect layer and a second interconnect layer located in the first dielectric layer, the first interconnect layer being connected to the connection plug, and the second interconnect layer being connected to the through silicon via conductive structure; A plurality of second dielectric layers located on the surface of the first dielectric layer; A first interconnect structure and a second interconnect structure located on the surface of the second dielectric layer of several layers, the first interconnect structure is connected to the first interconnect layer, and the second interconnect structure is connected to the second interconnect layer; a third dielectric layer located on the surface of the second dielectric layer of the top layer; A first pin and a second pin are formed in the third dielectric layer, the first pin is connected to the first interconnection structure, and the second pin is connected to the second interconnection structure.
9. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; Etching the substrate to form a groove in the substrate; forming a capacitor on a surface of a portion of the substrate and in the trench; A through silicon via conductive structure is formed to penetrate the capacitor, and a bottom of the through silicon via conductive structure extends into the substrate.
10. The method for forming a semiconductor structure according to claim 9, wherein: The width of the trench in a direction parallel to the substrate is greater than a characteristic dimension of the through silicon via conductive structure in a direction parallel to the substrate.
11. The method for forming a semiconductor structure according to claim 9, wherein: The step of forming the capacitor includes forming a capacitor pad on a surface of a portion of the substrate and in the groove, forming a first electrode layer on the surface of the capacitor pad; forming a capacitor dielectric layer on the surface of the first electrode layer; A second electrode layer is formed on the surface of the capacitor dielectric layer.
12. The method for forming a semiconductor structure according to claim 9, wherein: The capacitor has two or more electrode layers.
13. The method for forming a semiconductor structure according to claim 9, wherein: The capacitance value of the capacitor is proportional to the depth of the groove.
14. The method for forming a semiconductor structure according to claim 9, wherein: Before forming the through silicon via conductive structure, an interlayer dielectric layer is formed on the surface of the substrate and the surface of the capacitor, and the interlayer dielectric layer fills the trench completely; A portion of the interlayer dielectric layer is etched to expose a portion of the surface of the capacitor on the surface of the substrate, and a connection hole is formed in the interlayer dielectric layer; and a conductive layer is filled in the connection hole to form a connection plug.
15. The method for forming a semiconductor structure according to claim 14, wherein: After forming the through silicon via conductive structure, the method further includes forming a first dielectric layer on the surface of the interlayer dielectric layer and the surface of the through silicon via conductive structure; forming a first interconnection layer and a second interconnection layer in the first dielectric layer, wherein the first interconnection layer is connected to the connection plug, and the second interconnection layer is connected to the through silicon via conductive structure.
16. The method for forming a semiconductor structure according to claim 15, wherein: After forming the first dielectric layer, the method further includes forming several second dielectric layers on the surface of the first dielectric layer; forming a first interconnect structure and a second interconnect structure in the several second dielectric layers, wherein the first interconnect structure is connected to the first interconnect layer, and the second interconnect structure is connected to the second interconnect layer.
17. The method for forming a semiconductor structure according to claim 16, wherein: After forming several layers of the second dielectric layer, the method further includes forming a third dielectric layer on the surface of the top layer of the second dielectric layer; forming a first pin and a second pin in the third dielectric layer, wherein the first pin is connected to the first interconnection structure, and the second pin is connected to the second interconnection structure.
18. The method for forming a semiconductor structure according to claim 14, wherein: Before forming the through silicon via conductive structure, the top surface of the interlayer dielectric layer is planarized.
19. The method for forming a semiconductor structure according to claim 14, wherein: The steps of forming the silicon via conductive structure include: etching the interlayer dielectric layer, the capacitor and a partial thickness of the substrate in sequence to form a through hole penetrating the interlayer dielectric layer and the capacitor, wherein the bottom of the through hole extends into the substrate; forming a silicon via conductive structure liner layer on the surface of the through hole; forming a metal layer on the silicon via conductive structure liner layer, wherein the metal layer fills the through hole to form the silicon via conductive structure.