Solid-state relay

Abstract

The invention relates to the field of relay structures, in particular to a solid-state relay. Comprising a bias module for generating bias current and bias voltage, an oscillation module for generating high-frequency carrier waves by using the bias current, a voltage transformation module for signal coupling, a boosting module for boosting output voltage of the voltage transformation module, and two transistors of which grid electrodes are connected to the boosting module and realize circuit disconnection or connection, the oscillation module is connected with a jittering frequency module which enables the carrier frequency of the circuit to fluctuate, and the jittering frequency module comprises a current bias circuit, a first phase inverter, a second phase inverter and a hysteresis phase inverter, so that the carrier frequency of the circuit fluctuates in a small range, and the electromagnetic interference of a high-frequency signal on the circuit is reduced.

Description

Technical Field

[0001] The present application relates to the field of relay structures, and in particular to a solid-state relay. Background Art

[0002] Solid-state relays do not have the mechanical contact parts of traditional electromagnetic relays during the switching process, and have low noise when working, such as optocoupler relays. Traditional optocoupler relays use transparent insulating media to isolate circuits, and use light-emitting diodes and photosensitive devices to transmit signals to achieve the function of switching control. However, during long-term use, the transparent insulating medium will turn yellow, resulting in a decrease in the transmission performance of light, affecting the normal function of the relay. For this reason, some solid-state relays will use transformer coupling to achieve switching control.

[0003] For example, an analog optical MOS relay with publication number CN115347890A generates bias current through a diode input from a peripheral circuit and generates an AC signal through an LC oscillator. The AC signal then generates a DC signal through a rectifier circuit and then passes through a boost module. When the boosted voltage is greater than the threshold voltage of the two transistors, the circuits corresponding to the two transistors are turned on.

[0004] With respect to the above-mentioned related technologies, the high-frequency signal generated by the LC oscillator is likely to cause electromagnetic interference to the overall circuit and affect the normal operation of the relay. Summary of the invention

[0005] In order to reduce the impact on the normal operation of a relay, the present application provides a solid-state relay.

[0006] A solid-state relay provided in the present application adopts the following technical solution.

[0007] A solid-state relay comprises a bias module for generating a bias current and a bias voltage, an oscillation module for generating a high-frequency carrier using the bias current, a transformer module for signal coupling, a boost module for boosting the output voltage of the transformer module, and two transistors whose gates are connected to the boost module and realize circuit disconnection or conduction. The oscillation module is connected to a frequency jittering module for causing the carrier frequency of the circuit to fluctuate, and the frequency jittering module comprises a current biasing circuit, a first inverter, a second inverter, and a hysteresis inverter.

[0008] By adopting the above technical solution, the high-frequency carrier generated by the oscillation module fluctuates in a small range, thereby reducing the electromagnetic interference to the circuit.

[0009] Optionally, the current bias circuit includes a bias resistor connected to a power supply voltage, a first NMOS tube whose gate and drain are connected to the bias resistor and whose source is grounded, a second NMOS tube whose gate is connected to the bias resistor and whose source is grounded, a first PMOS tube whose drain and the drain of the second NMOS tube are connected and whose source is connected to the power supply voltage and whose gate is connected to the drain of the second NMOS tube, a second PMOS tube whose gate is connected to the gate of the first PMOS tube and whose source is connected to the power supply voltage, and a fourth NMOS tube whose source is grounded and whose gate is connected to the bias resistor.

[0010] By adopting the above technical solution, a bias current is provided for the first inverter.

[0011] Optionally, the first inverter includes a third PMOS tube whose source is connected to the second PMOS tube, a third NMOS tube whose gate is connected to the gate of the third PMOS tube, whose drain is connected to the drain of the third PMOS tube, and whose source is connected to the drain of the fourth NMOS tube.

[0012] The second inverter includes a fifth NMOS tube whose drain is connected to the gate of the third PMOS tube and the gate of the third NMOS tube and whose source is grounded, a fourth PMOS tube whose drain is connected to the gate of the third PMOS tube and the gate of the third NMOS tube and whose source is connected to the power supply voltage and whose gate is connected to the gate of the fifth NMOS tube. By adopting the above technical solution, two inverters are connected so that the current signal entering the oscillation circuit is shaped and synchronized. Optionally, the hysteresis inverter includes a fifth PMOS tube with a drain grounded, a sixth NMOS tube with a drain connected to a power supply voltage, a sixth PMOS tube with a source connected to the power supply voltage and a drain connected to the source of the fifth PMOS tube, a seventh PMOS tube with a source connected to the drain of the sixth PMOS tube and a drain connected to the gates of the fourth PMOS tube, the fifth PMOS tube, the fifth NMOS tube and the sixth NMOS tube, a seventh NMOS tube with a drain connected to the drain of the seventh PMOS tube and a source connected to the drain of the sixth NMOS tube, an eighth NMOS tube with a drain connected to the source of the seventh NMOS tube and a source grounded, and the gates of the sixth PMOS tube, the seventh PMOS tube, the seventh NMOS tube and the eighth NMOS tube are connected to the drain of the third PMOS tube.

[0013] By adopting the above technical solution, the oscillation module is continuously charged and discharged, so that the voltage fluctuates in a triangular wave.

[0014] Optionally, the oscillation module includes a first capacitor connected in series with the voltage transformation module, a second capacitor and a third capacitor connected in parallel with the first capacitor and whose capacitance values ​​can be changed, an eighth PMOS tube and a ninth PMOS tube whose sources are connected to the bias voltage, a ninth NMOS tube whose drain is connected to the drain of the eighth PMOS tube, whose source is grounded and whose gate is connected to the drain of the ninth PMOS tube, a tenth NMOS tube whose drain is connected to the drain of the ninth PMOS tube, whose source is grounded and whose gate is connected to the drain of the eighth PMOS tube, a tenth PMOS tube connected to the first capacitor and the voltage transformation module, whose source is connected to the power supply voltage and whose gate is connected to the starting voltage, the second capacitor and the third capacitor are connected to the drain of the third PMOS tube, and the second capacitor and the third capacitor are connected in series.

[0015] By adopting the above technical solution, a fully differential cross-coupled negative resistance pair structure is used to provide negative resistance to the oscillation module. Compared with a structure using only a PMOS cross-coupled pair or an NMOS cross-coupled pair, the transconductance of the oscillation module is doubled. At the same time, this structure is more symmetrical. Even when the inductance quality factor of the transformer module coil is relatively low, this structure can still maintain oscillation.

[0016] Optionally, the resistance of the structure composed of the eighth PMOS tube, the ninth PMOS tube, the ninth NMOS tube and the tenth NMOS tube is Rp, and the transconductance of the eighth PMOS tube and the ninth PMOS tube is g mp The transconductance of the ninth NMOS tube and the tenth NMOS tube is g mn , Rp range is 3 / (g mp +g mn )~5 / (g mp +g mn ).

[0017] By adopting the above technical solution, the circuit can maintain normal oscillation operation under the condition of lower input current.

[0018] In summary, the present application includes at least the following beneficial effects.

[0019] This causes the high-frequency carrier generated by the oscillation module to fluctuate in a small range, thereby reducing the electromagnetic interference to the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the circuit principle of this application; Figure 2 This is a schematic diagram of the principle of the frequency jitter circuit; Figure 3 (a) is the circuit schematic diagram of the LC resonant cavity, (b) is the series equivalent model of the actual LC, and (c) is the parallel equivalent model of the actual LC; Figure 4 This is a graph showing how Cvar changes with Vctrl.

[0021] Explanation of the accompanying drawings: 1. bias module; 2. oscillation module; 3. voltage conversion module; 4. boost module; 5. transistor; 51. frequency jitter module; 52. hysteresis inverter; 53. current bias circuit; 54. first inverter; 55. second inverter. DETAILED DESCRIPTION

[0022] The present application is further described in detail below in conjunction with the accompanying drawings.

[0023] The present application embodiment discloses a solid state relay, referring to Figure 1 , including a bias module 1 for generating bias current and bias voltage, an oscillation module 2 for generating a high-frequency carrier using the bias current, a transformer module 3 for signal coupling, a boost module 4 for boosting the output voltage of the transformer module 3, and two transistors 5 whose gates are connected to the boost module 4 and realize circuit disconnection or conduction. The bias module 1 is a general bias circuit, so it will not be expanded too much. The boost module 4 is a general boost circuit, so it will not be expanded too much. The two transistors 5 are high-voltage resistant NMOS tubes, the source of one transistor 5 is connected to the source of the other transistor 5, and the drains of the two transistors 5 are connected to the S1 terminal and S2 terminal of the external circuit one by one, and the S1 terminal and the S2 terminal are respectively connected to the high and low potentials of the external circuit.

[0024] Reference Figure 2 The frequency jitter module 51 includes a current bias circuit 53, a first inverter 54, a second inverter 55 and a hysteresis inverter 52, and the hysteresis inverter 52 is connected to the current bias circuit 53 and the oscillation module 2. The current bias circuit 53 includes a bias resistor R connected to the power supply voltage, a first NMOS transistor N1 with a gate and a drain connected to the bias resistor and a source grounded, a second NMOS transistor N2 with a gate connected to the bias resistor and a source grounded, a first PMOS transistor P1 with a drain connected to the drain of the second NMOS transistor N2 and a source connected to the power supply voltage and a gate connected to the drain of the second NMOS transistor N2, a second PMOS transistor P2 with a gate connected to the gate of the first PMOS transistor P1 and a source connected to the power supply voltage, and a fourth NMOS transistor N4 with a source grounded and a gate connected to the bias resistor.

[0025] Reference Figure 2The first inverter 54 includes a third PMOS transistor P3 whose source is connected to the second PMOS transistor P2, a third NMOS transistor N3 whose gate is connected to the gate of the third PMOS transistor P3, whose drain is connected to the drain of the third PMOS transistor P3, and whose source is connected to the drain of the fourth NMOS transistor N4. The second inverter 55 includes a fifth NMOS transistor N5 whose drain is connected to the gate of the third PMOS transistor P3 and the gate of the third NMOS transistor N3 and whose source is grounded, a fourth PMOS transistor P4 whose drain is connected to the gate of the third PMOS transistor P3 and the gate of the third NMOS transistor N3, whose source is connected to the power supply voltage, and whose gate is connected to the gate of the fifth NMOS transistor N5.

[0026] Reference Figure 2 The hysteresis inverter 52 includes a fifth PMOS transistor P5 with a drain connected to the ground, a sixth NMOS transistor N6 with a drain connected to the power supply voltage, a sixth PMOS transistor P6 with a source connected to the power supply voltage and a drain connected to the source of the fifth PMOS transistor P5, a seventh PMOS transistor P7 with a source connected to the drain of the sixth PMOS transistor P6 and a drain connected to the gates of the fourth PMOS transistor P4, the fifth PMOS transistor P5, the fifth NMOS transistor N5 and the sixth NMOS transistor N6, a seventh NMOS transistor N7 with a drain connected to the drain of the seventh PMOS transistor P7 and a source connected to the drain of the sixth NMOS transistor N6, an eighth NMOS transistor N8 with a drain connected to the source of the seventh NMOS transistor N7 and a source grounded, and the gates of the sixth PMOS transistor P6, the seventh PMOS transistor P7, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are connected to the drain of the third PMOS transistor P3.

[0027] Reference Figure 1 The oscillation module 2 includes a first capacitor C1 connected in series with the voltage conversion module 3, a second capacitor C2 and a third capacitor C3 connected in parallel with the first capacitor C1 and having a changeable capacitance value, an eighth PMOS transistor P8 and a ninth PMOS transistor P9 whose sources are connected to the bias voltage, a ninth NMOS transistor N9 whose drain is connected to the drain of the eighth PMOS transistor P8, whose source is grounded and whose gate is connected to the drain of the ninth PMOS transistor P9, a tenth NMOS transistor N10 whose drain is connected to the drain of the ninth PMOS transistor P9, whose source is grounded and whose gate is connected to the drain of the eighth PMOS transistor P8, a tenth PMOS transistor P10 connected to the first capacitor C1 and the voltage conversion module 3, whose source is connected to the power supply voltage and whose gate is connected to the start-up voltage, a second capacitor C2 and a third capacitor C3 connected to the drain of the third PMOS transistor P3, and the second capacitor C2 and the third capacitor C3 are connected in series.

[0028] Reference Figure 3, the coil inductance of the transformer module 3 is L, the capacitance of the first capacitor C1 is C, the capacitance of the second capacitor C2 and the third capacitor C3 are both Cvar, the capacitance of the oscillation module 2 is Ctot, then Ctot=C+Cvar / 2. The angular frequency of the resonance of the oscillation module 2 is ω, then ω=1 / √(L Ctot). The resistance of the transformer module 3 coil is Rs, which can be equivalently transformed into Rp. The fully differential cross-coupled negative resistance pair connected in parallel to the transformer module 3 coil, that is, the negative resistance of the structure composed of the eighth PMOS tube P8, the ninth PMOS tube P9, the ninth NMOS tube N9 and the tenth NMOS tube N10 is -Rp. The inductance quality factor of the transformer module 3 coil is Q, then Q=(L ω) / Rs,Rp=(1+Q 2 ) Rs=L 2 ω 2 / Rs. The transconductance of the eighth PMOS tube P8 and the ninth PMOS tube P9 is g mp , the transconductance of the ninth NMOS tube N9 and the tenth NMOS tube N10 is g mn , then the equivalent negative resistance is -2 / (g mp +g mn ), if g mp =g mn In order to maintain oscillation, Rp≥1 / g mp In order to maintain normal oscillation at low input current, the Rp range is 1.5 / g mp ~2.5 / g mp .

[0029] Reference Figure 4 The triangular wave voltage Vctrl generated by the frequency jitter module 51 controls the change of Cvar, and the oscillation frequency of the circuit is f=1 / (2π √(L (C+Cvar / 2)), that is, the oscillation frequency of the circuit will fluctuate within a certain range as Cvar changes, and the fluctuation range is about 40MHz, so that the carrier frequency of the circuit fluctuates within a small range, reducing the electromagnetic interference of high-frequency signals on the circuit.

[0030] Reference Figure 1 and Figure 2 , the current flowing through the first NMOS tube N1 is I=(VDD-1 / ) / R, where is the channel length modulation coefficient determined by the process, VDD is the power supply voltage, and the current can be adjusted by adjusting the bias resistor R. The width-to-length ratio of the second NMOS tube N2 to the first NMOS tube N1 is k1, and the width-to-length ratio of the fourth NMOS tube N4 to the second NMOS tube N2, and the width-to-length ratio of the second PMOS tube P2 to the first PMOS tube P1 is k2. Therefore, the current flowing through the branch where the second PMOS tube P2 and the fourth NMOS tube N4 are located is k1. k2 I, by controlling the current size, the flipping speed of the first inverter 54 can be controlled, thereby controlling the change speed of the capacitance of the first capacitor C1, and further controlling the speed of the carrier frequency fluctuation.

[0031] The implementation principle of a solid-state relay in an embodiment of the present application is as follows: the bias module 1 generates a bias voltage and a bias current to the oscillation module 2, and the oscillation module 2 generates a high-frequency carrier that changes with the input signal. At the same time, a frequency jitter module 51 is added to the oscillation module 2 to make the high-frequency carrier fluctuate in a small range, thereby reducing the electromagnetic interference of the circuit. The oscillation signal is transmitted to the boost module 4 through the transformer module 3. When the boosted voltage is greater than the threshold voltage of the two transistors 5, the transistor 5 with a lower drain potential is turned on first, and the source potential of the transistor 5 connected to the lower point is pulled down, and then the transistor 5 with a higher drain potential is turned on. At this time, both transistors 5 are in the on state to connect the S1 terminal and the S2 terminal.

[0032] The above are all preferred embodiments of the present application, and the protection scope of the present application is not limited thereto. Therefore, any equivalent changes made according to the structure, shape, and principle of the present application should be included in the protection scope of the present application.

Claims

1. A solid-state relay, comprising a bias module (1) for generating a bias current and a bias voltage, an oscillation module (2) for generating a high-frequency carrier using the bias current, a transformer module (3) for signal coupling, a boost module (4) for boosting the output voltage of the transformer module (3), and two transistors (5) whose gates are connected to the boost module (4) and realize circuit disconnection or conduction, characterized in that: The oscillation module (2) is connected to a frequency jittering module (51) for causing the carrier frequency of the circuit to fluctuate. The frequency jittering module (51) comprises a current biasing circuit (53), a first inverter (54), a second inverter (55) and a hysteresis inverter (52).

2. A solid-state relay according to claim 1, characterized in that: The current bias circuit (53) comprises a bias resistor connected to a power supply voltage, a first NMOS tube with a gate and a drain connected to the bias resistor and a source connected to ground, a second NMOS tube with a gate connected to the bias resistor and a source connected to ground, a first PMOS tube with a drain connected to the drain of the second NMOS tube and a source connected to the power supply voltage and a gate connected to the drain of the second NMOS tube, a second PMOS tube with a gate connected to the gate of the first PMOS tube and a source connected to the power supply voltage, and a fourth NMOS tube with a source connected to ground and a gate connected to the bias resistor.

3. A solid state relay according to claim 2, characterized in that: The first inverter (54) comprises a third PMOS tube whose source is connected to the second PMOS tube, a third NMOS tube whose gate is connected to the gate of the third PMOS tube, whose drain is connected to the drain of the third PMOS tube, and whose source is connected to the drain of the fourth NMOS tube.

4. A solid-state relay according to claim 3, characterized in that: The second inverter (55) comprises a fifth NMOS tube having a drain connected to the gate of the third PMOS tube and the gate of the third NMOS tube and a source connected to the ground, and a fourth PMOS tube having a drain connected to the gate of the third PMOS tube and the gate of the third NMOS tube and a source connected to the power supply voltage and a gate connected to the gate of the fifth NMOS tube.

5. A solid state relay according to claim 2, characterized in that: The hysteresis inverter (52) comprises a fifth PMOS tube with a drain connected to a grounded electrode, a sixth NMOS tube with a drain connected to a power supply voltage, a sixth PMOS tube with a source connected to a power supply voltage and a drain connected to a source of the fifth PMOS tube, a seventh PMOS tube with a source connected to a drain of the sixth PMOS tube and a drain connected to the gate electrodes of the fourth PMOS tube, the fifth PMOS tube, the fifth NMOS tube and the sixth NMOS tube, a seventh NMOS tube with a drain connected to a drain of the seventh PMOS tube and a source connected to a drain of the sixth NMOS tube, an eighth NMOS tube with a drain connected to a source of the seventh NMOS tube and a source grounded electrode, and the gate electrodes of the sixth PMOS tube, the seventh PMOS tube, the seventh NMOS tube and the eighth NMOS tube are connected to the drain of the third PMOS tube.

6. A solid state relay according to claim 2, characterized in that: The oscillation module (2) comprises a first capacitor connected in series with the voltage conversion module (3), a second capacitor and a third capacitor connected in parallel with the first capacitor and having a changeable capacitance value, an eighth PMOS tube and a ninth PMOS tube whose sources are connected to a bias voltage, a ninth NMOS tube whose drain is connected to the drain of the eighth PMOS tube, whose source is grounded and whose gate is connected to the drain of the ninth PMOS tube, a tenth NMOS tube whose drain is connected to the drain of the ninth PMOS tube, whose source is grounded and whose gate is connected to the drain of the eighth PMOS tube, a tenth PMOS tube connected to the first capacitor and the voltage conversion module (3), whose source is connected to a power supply voltage and whose gate is connected to a start-up voltage, the second capacitor and the third capacitor are connected to the drain of the third PMOS tube, and the second capacitor and the third capacitor are connected in series.

7. A solid-state relay according to claim 4, characterized in that: The resistance of the structure composed of the eighth PMOS tube, the ninth PMOS tube, the ninth NMOS tube and the tenth NMOS tube is Rp, and the transconductance of the eighth PMOS tube and the ninth PMOS tube is g mp The transconductance of the ninth NMOS tube and the tenth NMOS tube is g mn , Rp range is 3 / (g mp +g mn )~5 / (g mp +g mn ).

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