Intelligent computing optical switching networking system and enhanced data processing unit

Abstract

The invention relates to the technical field of intelligent computing networks, in particular to an intelligent computing optical switching networking system and an enhanced data processing unit.The intelligent computing optical switching networking system comprises computing nodes and an optical path switch; the computing node comprises an enhanced data processing unit, a data processing unit and a computing unit, the enhanced data processing unit is provided with an RDMA network interface and realizes priority flow control (PFC) and quantitative congestion control (QCN) based on an RoCEV2 protocol; the enhanced data processing unit is also provided with a first switching port and a second switching port, and the first switching port and the second switching port are respectively connected with the optical path switch to construct a Scale-Up network and a Scale-Out network. Compared with an electric switching scheme, the intelligent calculation optical switching networking system provided by the invention has the characteristics of low power consumption and low time delay, and can adjust the networking topology according to the requirement of an intelligent calculation parallelization strategy, thereby remarkably improving the networking performance and the parallel calculation speed.

Description

Technical Field

[0001] The present invention relates to the field of intelligent computing network technology, and in particular to an intelligent computing optical switching networking system and an enhanced data processing unit. Background Art

[0002] Intelligent computing networks require switching ports to have large scale, low latency, high bandwidth, low energy consumption, and flexible topology configuration. However, existing intelligent computing networks mostly use electrical switching solutions, which have high power consumption, and the electrical switching network topology is relatively rigid, which cannot support One-to-All and All-to-All network communication modes well. At present, building an optical switching network based on a large-scale optical path cross matrix is ​​the best solution to meet the above requirements, but the optical path switching matrix itself does not have the networking capability. The construction of an optoelectronic hybrid network has technical problems such as how to achieve optical topology mapping, optoelectronic hybrid routing, and multi-path load balancing. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems in the above-mentioned technology to a certain extent, and proposes an intelligent optical switching networking system, including:

[0004] Computing nodes and optical path switches; wherein,

[0005] The computing node comprises: an enhanced data processing unit;

[0006] The enhanced data processing unit is provided with an RDMA network interface, and implements priority flow control (PFC) and quantized congestion control (QCN) based on the RoCEV2 protocol;

[0007] The enhanced data processing unit is further provided with a first switching port and a second switching port, and the first switching port and the second switching port are respectively connected to the optical path switch to construct a Scale-Up network and a Scale-Out network.

[0008] Furthermore, the computing node includes:

[0009] CPU, PCIe bus switching unit and computing communication unit; wherein,

[0010] The computing and communication unit comprises: a GPU and the enhanced data processing unit;

[0011] The CPU is connected to the PCIe bus switching unit and other CPUs in the computing node;

[0012] The computing communication unit is connected to the PCIe bus switching unit.

[0013] Furthermore, the enhanced data processing unit comprises:

[0014] CPU subsystem, RDMA engine, load balancing module and hard forwarding engine; among them,

[0015] The CPU subsystem is configured to: plan and issue routing strategies;

[0016] The RDMA engine is connected to the GPU; the RDMA engine is configured to: implement multi-hop interconnection of GPU node forwarding based on the RoCEV2 protocol; and implement priority flow control (PFC) and quantized congestion control (QCN) based on the RoCEV2 protocol;

[0017] The load balancing module is configured to: quantify the degree of congestion of the communication path based on the priority flow control (PFC) and the quantified congestion control (QCN), and realize load balancing of multi-path routing traffic based on the quantified degree of congestion of the communication path;

[0018] The hard forwarding engine is provided with the first switch port and the second switch port.

[0019] Furthermore, in the Scale-Up network, the RDMA physical links corresponding to the GPU nodes are interconnected through optical path switches, and the total number of links of the GPU nodes is M=d×r×s, where d represents the number of link dimensions; r represents the number of link directions in each dimension; and s represents the number of links in each direction.

[0020] Furthermore, the Scale-Out network includes several Scale-Up aggregation blocks; wherein,

[0021] Each aggregation block acts as a BGP alliance;

[0022] Each BGP alliance has a unique ASN, and each enhanced data processing unit in the BGP alliance has a unique sub-ASN that is invisible to other BGP alliances;

[0023] Sub-ASNs in different BGP alliances can be reused.

[0024] Furthermore, the load balancing module includes: a balancing decision maker and a flow slicing unit; wherein,

[0025] The flow slicing unit is configured to: perform flow slicing detection and slicing at the data packet transmission interval; and detect whether the incoming data packet starts a new flow slice, and if so, notify the balancing decision maker to execute the load balancing decision;

[0026] The load balancing decision maker is configured to implement load balancing decision by minimizing the congestion metric factor of each channel of the uplink port.

[0027] Furthermore, the calculation formula of the congestion measurement factor includes:

[0028] Q=β×q+(1-β)×p

[0029] Among them, Q represents the congestion measurement factor; q represents the first congestion measurement factor calculated based on priority flow control (PFC); p represents the second congestion measurement factor calculated based on quantized congestion control (QCN); β represents the allocation coefficient, which is a set value.

[0030] Furthermore, the calculation formula of the first congestion metric factor p includes:

[0031]

[0032] Among them, E(n) and Time(n) represent the values ​​of the network card register when the RDMA engine parses the PFC Pause frame; E(n) takes the value of 1 or 0, 1 indicates congestion occurs, and 0 indicates no congestion occurs; Time(n) represents the time when the priority flow control controls the network card to stop sending data packets; n represents one of the virtual channels divided by the priority flow control.

[0033] Furthermore, the calculation formula of the second congestion metric factor q includes:

[0034] q=α(t)=(1-g)×α t-Δt +g×CNP_arrived

[0035] Among them, g is a constant that depends on the network card firmware; Δt represents the rate adjustment time interval in quantized congestion control; CNP_arrived takes the value of 1 or 0, 1 means that CNP has arrived, and 0 means that CNP has not arrived.

[0036] The present application also proposes an enhanced data processing unit applicable to the above-mentioned intelligent optical switching networking system, including:

[0037] CPU subsystem, RDMA engine, load balancing module and hard forwarding engine; among them,

[0038] The CPU subsystem is configured to: plan and issue routing strategies;

[0039] The RDMA engine is connected to the GPU; the RDMA engine is configured to: implement multi-hop interconnection of GPU node forwarding based on the RoCEV2 protocol; and implement priority flow control (PFC) and quantized congestion control (QCN) based on the RoCEV2 protocol;

[0040] The load balancing module is configured to: quantify the degree of congestion of the communication path based on the priority flow control (PFC) and the quantified congestion control (QCN), and realize load balancing of multi-path routing traffic based on the quantified degree of congestion of the communication path;

[0041] The hard forwarding engine is provided with a first switching port and a second switching port;

[0042] The first switching port and the second switching port are respectively connected to an optical path switch to construct a Scale-Up network and a Scale-Out network.

[0043] Compared with the prior art, the present invention has the following beneficial effects:

[0044] This application proposes a programmable reconfigurable optical interconnection network architecture based on optical path switching, which has a larger node scale than the traditional mode and supports scalability. In addition, the solution proposed in this application adopts optical path switch (OCS) networking, which has lower power consumption and latency than the electrical switching solution, and can adjust the networking topology according to the parallelization strategy requirements of the application end, which has a significant effect on improving the networking performance of the intelligent computing center and accelerating parallel computing.

[0045] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description and the accompanying drawings. The technical scheme of the present invention is further described below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0047] Figure 1 The architecture diagram of the computing node of the intelligent optical switching network provided in the embodiment;

[0048] Figure 2 The architecture diagram of the enhanced data processing unit provided in the embodiment;

[0049] Figure 3 A schematic diagram of GPU node interconnection in a Scale-Up network provided in an embodiment;

[0050] Figure 4 A schematic diagram of a GPU node physical link configuration provided in an embodiment;

[0051] Figure 5 Schematic diagrams of four Scale-Up networking structures provided in the embodiments;

[0052] Figure 6 A schematic diagram of a Scale-Out networking structure provided in an embodiment;

[0053] Figure 7 A schematic diagram of a Scale-Out networking structure provided in another embodiment;

[0054] Figure 8 A schematic diagram of intelligent optical switching network routing planning provided in an embodiment;

[0055] Fig. 9 A schematic diagram of an SDN control system provided in an embodiment;

[0056] Fig.10 A diagram of the congestion-aware multipath load balancing implementation architecture provided in an embodiment;

[0057] Fig.11 A schematic diagram of a collective communication algorithm and topology mapping provided in an embodiment;

[0058] Fig.12 This is a flowchart of the optical path switch OCS topology configuration provided in the embodiment. DETAILED DESCRIPTION

[0059] The present invention is described below in conjunction with the accompanying drawings. The preferred embodiments described herein are only used to illustrate and explain the present invention and are not used to limit the present invention.

[0060] This application proposes an intelligent optical switching networking system, including:

[0061] Computing nodes and optical path switches; wherein,

[0062] The computing node comprises: an enhanced data processing unit;

[0063] The enhanced data processing unit is provided with an RDMA network interface, and implements priority flow control (PFC) and quantized congestion control (QCN) based on the RoCEV2 protocol;

[0064] The enhanced data processing unit is further provided with a first switching port and a second switching port, and the first switching port and the second switching port are respectively connected to the optical path switch to construct a Scale-Up network and a Scale-Out network.

[0065] According to some embodiments of the present application, the architecture of the enhanced data processing unit (eDPU) has an RDMA interface as its external network interface. Packet processing and memory access are offloaded to the eDPU, and the host cannot access individual packets. If the IP destination address of the packet does not match the IP address of the eDPU, the RDMA engine will silently discard the packet. Therefore, the eDPU needs to support multi-hop interconnection of the GPUx node forwarding of the computing card, enable RoCEv2 forwarding of RDMA on all eDPUs, and each RoCEv2 packet can be routed by its source and destination IP addresses.

[0066] In addition, the enhanced data processing unit (eDPU) has N ports, where the value of N matches the computing power of the GPU. Among the N ports, one part is used for Scale-Up networking and the other part is used for Scale-Out networking.

[0067] In summary, the enhanced data processing unit (eDPU) in this embodiment has the following additional functions compared to the traditional network card:

[0068] 1. RDMA-RoCEV2 function and lossless function offloading:

[0069] (a) End-to-end flow control support: PFC mechanism

[0070] (b) End-to-end DC-QCN: QCN mechanism based on ECN marking

[0071] 2. Linear forwarding engine:

[0072] (a) Simplified Layer 3 direct forwarding

[0073] (b) Implementing congestion-aware load balancing

[0074] 3. Support eBGP protocol:

[0075] The CPU subsystem is responsible for BGP route planning and delivery.

[0076] Furthermore, the computing node includes:

[0077] CPU, PCIe bus switching unit and computing communication unit; wherein,

[0078] A computing and communication unit, including: a GPU and an enhanced data processing unit;

[0079] The CPU is connected to the PCIe bus switch unit and other CPUs in the computing node;

[0080] The computing communication unit is connected to the PCIe bus switching unit.

[0081] According to some embodiments of the present application, Figure 1 As shown, the computing node given in the present application includes: a CPU, a PCIe bus switching unit and a computing communication unit, wherein an improved enhanced data processing unit (eDPU) is added to the computing communication unit, and the node has dual attributes of computing and forwarding under optical switching interconnection, and GPU+eDPU constructs a parallel and callable basic unit of computing and communication.

[0082] Furthermore, the enhanced data processing unit comprises:

[0083] CPU subsystem, RDMA engine, load balancing module and hard forwarding engine; wherein the CPU subsystem is configured to: plan and issue routing strategies;

[0084] The RDMA engine is connected to the GPU; the RDMA engine is configured to: implement multi-hop interconnection of GPU node forwarding based on the RoCEV2 protocol; and implement priority flow control (PFC) and quantized congestion control (QCN) based on the RoCEV2 protocol;

[0085] The load balancing module is configured to: quantify the congestion of the communication path based on priority flow control (PFC) and quantified congestion control (QCN), and implement load balancing of multi-path routing traffic based on the quantification of the congestion degree of the communication path;

[0086] The hard forwarding engine is provided with a first switching port and a second switching port.

[0087] According to some embodiments of the present application, Figure 2 As shown, the enhanced data processing unit includes: a CPU subsystem, an RDMA engine, a load balancing module and a hard forwarding engine; wherein the CPU subsystem carries out BGP route planning and delivery; the RDMA engine adopts a priority-based flow control mechanism and a quantitative congestion control mechanism based on RoCEV2's lossless network technology; the eDPU supports multi-hop interconnection of GPUx nodes forwarding of computing cards based on RoCEV2; the load balancing module performs a quantitative evaluation of communication path congestion based on making full use of RDMA's flow control and congestion control mechanisms, thereby realizing load balancing of multi-path routing traffic.

[0088] Furthermore, in the Scale-Up network, the RDMA physical links corresponding to the GPU nodes are interconnected through optical path switches, and the total number of links of the GPU nodes is M = d × r × s, where d represents the number of link dimensions; r represents the number of link directions in each dimension; and s represents the number of links in each direction.

[0089] According to some embodiments of the present application, the optical path switch is a large-scale cross matrix with full optical domain switching, pure optical signal input, pure optical signal exchange, pure optical signal output, and can achieve optical path level switching, no clock jitter, no delay, no data reading, no leakage risk, and the connection or disconnection of any two ports inside the switch can be controlled by programming through Ethernet or RS232 interfaces. The network card side can be interconnected with the optical path switch through an optical module and an optical fiber.

[0090] As the scale of large models continues to increase, the computing power and memory of a single computing node are difficult to bear. The industry has decomposed large models into two parts. One part is the part with high-frequency data interaction, such as tensor parallelism and expert parallelism. These parts require high-speed, low-latency interconnection networks to process to reduce communication costs. This is the scale-up network, which pursues extreme performance. The other part is relatively independent parallel data, such as pipeline parallelism and data parallelism, which can be achieved in a more economical and flexible way, namely the scale-out network.

[0091] In this embodiment, this solution builds an enhanced data processing unit in the computing node, in which N-2 RDMA physical links are used as the internal interconnection of the Scale-Up network. The interconnection architecture is as follows: Figure 3 As shown, the number of interconnected GPU nodes is a×b×c. Figure 3 Take a=b=c=8 as an example. According to the networking requirements, the values ​​of a, b, and c can be arbitrary. The number of optical circuit switches (OCS) can be expanded with the number of GPU nodes, thus realizing the multi-dimensional expansion of the Scale-Up network. Because each port of the optical circuit switch (OCS) is programmable, the N-2 RDMA physical links of any GPU node can be freely interconnected through the OCS. The networking method is as follows: Figure 4 As shown in the figure, different network topologies and link numbers or bandwidth plans are constructed based on dimension d, direction r, and number of paths s, where the total number of node links = d×r×s, dimension d represents the three dimensions of X / Y / Z or decreasing; direction r represents the interconnection direction of multiple fan-outs in each dimension; and number s represents the number of links allocated in each direction. Figure 5 Four Scale-Up networking modes are shown. The difference between these four architectures lies in the values ​​of d, r, and s.

[0092] Furthermore, the Scale-Out network includes several Scale-Up aggregation blocks; among them,

[0093] Each aggregation block acts as a BGP alliance;

[0094] Each BGP alliance has a unique ASN, and each enhanced data processing unit in the BGP alliance has a unique sub-ASN that is invisible to other BGP alliances;

[0095] Sub-ASNs in different BGP alliances can be reused.

[0096] According to some embodiments of the present application, there are two RDMA physical links in the eDPU for interconnection within the Scale-Out network. The interconnection architecture is as follows: Figure 3 As shown in the figure, an optical switch is used to interconnect the aggregation blocks of each Scale-Up network. Also, because each port of the optical switch (OCS) is programmable and controllable, the two-way RDMA physical links of any GPU node can be freely interconnected through the OCS. The number of optical switches (OCS) can be expanded as the Scale-Up aggregation blocks are added, thereby realizing the multi-dimensional expansion of the Scale-Out network scale. Figure 6 and Figure 7 Two Scale-Out networking structures are provided for the embodiments.

[0097] With the network topology, the next step is to solve the network routing problem. The main purpose is to calculate and update the route and avoid loops that cause network storms. eBGP has become the first choice for large data centers. The eBGP protocol characteristics are more compatible with the optical-electrical hybrid networking architecture. A single routing protocol is preferred to reduce complexity and interdependence. iBGP deployment is more complex, while eBGP deployment is simple and easy to understand.

[0098] ASN deployment of BGP protocol: Use BGP alliance and reusable ASN to divide the Scale-Up aggregation block in the Scale-Out network into multiple alliances. The sub-AS and internal paths in the alliance are not visible to BGP peers outside the alliance. Figure 8 As shown, each Scale-Up aggregation block in the Scale-Out network is regarded as a BGP alliance. Each aggregation block is assigned a unique private alliance identity ASN. Within the alliance of the aggregation block, each eDPU is assigned a unique internal alliance member ASN. The ASNs of alliance areas in different aggregation blocks can be reused and peered between these devices in a manner similar to eBGP. This ASN numbering method can be reused in each Scale-Out network.

[0099] In this embodiment, users can configure the BGP program, port binding, IP address settings, etc. on each eDPU through the SDN software system routing configuration module. The BGP program will work according to the alliance and policy in the protocol. The as-path attribute setting can avoid the loopback path of the alliance area of ​​the aggregation block; the attributes that need to be compared in the 1st to 8th rules in the attribute list are set to be exactly the same, which can achieve point-to-point equal-cost multi-path routing.

[0100] Furthermore, the intelligent optical switching networking system further includes: an SDN control module;

[0101] The SDN control module includes: a main control module, and a northbound interface, an information collection unit, a routing configuration unit, a topology calculation unit and an optical drive engine respectively connected to the main control module; the topology calculation unit is also connected to the optical drive engine; wherein,

[0102] The main control module is configured to: receive, process and send function instructions to the corresponding module;

[0103] The northbound interface is configured to: receive and forward function instructions from the AI ​​model;

[0104] The information collection unit is configured to: collect computing node information; the computing node information includes: CPU information, GPU information and eDPU information;

[0105] The routing configuration unit is configured to: configure a routing policy of a computing node;

[0106] A topology calculation unit is configured to: generate an intelligent optical switching networking topology command;

[0107] The optical drive engine is configured to: convert the intelligent optical switching networking topology command into a protocol command and send it to the optical switch; and collect and report the optical switch information.

[0108] According to some embodiments of the present application, the optical path switch is a programmable large-scale cross-optical matrix that does not have networking capabilities by itself and must be programmed and controlled by the SDN control system to realize the networking function; at the same time, the software system also needs to connect to the north and respond to AI models and applications, as well as collect and report information on networking components to realize the routing configuration of the enhanced data processing unit and the topology calculation and configuration of the OCS. Fig. 9 As shown in the figure, the relationship and function definitions of each module of the SDN software system are as follows:

[0109] Northbound interface: It is used for AI model standardization, accepting and responding to functional instructions, packaging or unpacking information transmitted between upper and lower layers, and storing or forwarding it as needed;

[0110] Main control module: completes user layer command and information analysis and response, such as inter-operator / intra-operator configuration information, and is responsible for coordinating the optical topology and circuit routing;

[0111] Information collection module: collects and reports information such as CPU / GPU / eDPU on computing nodes;

[0112] Routing configuration module: The main control module transmits user-set configurations and configures the BGP program and port binding, IP address settings, etc. on the eDPU through automated scripts according to the user input configurations;

[0113] Topology calculation module: completes topology calculation processing and generates commands;

[0114] Optical drive engine: converts optical switching topology control commands into protocol commands and downloads them, as well as queries and reports optical switch information.

[0115] Furthermore, the load balancing module includes:

[0116] Balance decision maker and stream slicing unit; wherein,

[0117] The flow slicing unit is configured to: perform flow slice detection and slicing at the data packet transmission interval; and detect whether the incoming data packet starts a new flow slice, and if so, notify the balancing decision maker to execute the load balancing decision;

[0118] The load balancing decision maker is configured to achieve load balancing decision by minimizing the congestion metric factor of each channel of the uplink port.

[0119] According to some embodiments of the present application, through the above topology and routing settings, the source of end-to-end multi-link interconnection mainly comes from multiple link interconnections in each direction; at the same time, the implementation of multi-path routing strategy will also form different numbers of equivalent multi-path routes, thus generating the problem of traffic load balancing of multi-path routing. Flow-based multi-path routing has a hash polarization problem: In the Al scenario, the number of flows between GPU computing units is very small, and a single flow is very large, requiring a very large network bandwidth. For flow-based transmission, traditional hash algorithms are prone to load imbalance and congestion, while load balancing based on cells and packets has a disorder problem.

[0120] For this reason, Fig.10 As shown, the present application adds an equalization decision maker and a stream slicing unit to the enhanced data processing unit (eDPU), wherein:

[0121] The flow slicing unit works as follows: there is enough interval between packet bursts to detect and segment flow slices, and at the same time, a flow slice table is updated and maintained; each entry in the table includes a port number, a valid bit, and an age bit. The flow slice entry uses the age bit for timeout management: each incoming packet resets the age bit. A timer periodically (every T fl seconds) to check the age bit and then set it. If the age bit is already set when the timer checks, then flIf no packets are received for that entry within seconds, the entry expires and the valid bit is set to zero. When a packet arrives, an entry is looked up based on the hash value of its 5-tuple. If the entry is valid (valid_bit == 1), the flow slice is active and the packet is sent to the port indicated in the entry. If the entry is invalid, the incoming packet starts a new flow slice. In this case, a load balancing decision is made and the result is cached in the table for subsequent packets to use, and the valid bit is set synchronously.

[0122] The working principle of the balancing decision maker is as follows: for a new flow slice, the uplink port is selected to minimize the congestion metric factor of each channel; if there are multiple uplinks that are equally suitable, a hash algorithm is used to randomly select one, while giving priority to the ports with (invalid bit) entries in the flow slice table.

[0123] Furthermore, the calculation formula of the congestion metric factor includes:

[0124] Q=β×q+(1-β)×p

[0125] Among them, Q represents the congestion measurement factor; q represents the first congestion measurement factor calculated based on priority flow control (PFC); p represents the second congestion measurement factor calculated based on quantized congestion control (QCN); β represents the allocation coefficient, which is a set value.

[0126] According to some embodiments of the present application, the present application performs load balancing based on a load balancing module that integrates a PFC congestion measurement factor and a QCN congestion measurement factor.

[0127] The expression of the congestion metric factor Q is as follows:

[0128] Q=β×q+(1-β)×p

[0129] Among them, β is the proportional allocation coefficient of the QCN mechanism, i.e., congestion control's ability to influence Q; correspondingly, 1-β is the proportional allocation coefficient of the PFC mechanism, i.e., the ability to influence network flow control; the assignment of β is guided by the fact that the factor Q can accurately and linearly reflect the degree of network congestion; the waterline setting of the QCN mechanism and the PFC waterline setting need to be determined based on specific application scenarios, traffic characteristics, and network configurations such as the number of ports, convergence ratio, and the performance of the switch itself. The general approach is that if there is still packet loss when the QCN mechanism is fully processing, PFC is started. The β value refers to the trade-off of this process and is assigned by experimental testing.

[0130] Furthermore, the calculation formula of the first congestion metric factor p includes:

[0131]

[0132] Among them, E(n) and Time(n) represent the values ​​of the network card register when the RDMA engine parses the PFC Pause frame; E(n) takes the value of 1 or 0, 1 indicates congestion occurs, and 0 indicates no congestion occurs; Time(n) represents the time when the priority flow control controls the network card to stop sending data packets; n represents one of the virtual channels divided by the priority flow control.

[0133] According to some embodiments of the present application, the congestion measurement unit of the eDPU can collect data from the relevant registers of the PFC mechanism through the RDMA engine. Here, a normalized variable factor p is defined as the measurement factor of the network congestion under PFC:

[0134]

[0135] E(n) and Time(n) are the values ​​of the PFC Pause frame stored in the NIC register when the eDPU's RDMA engine parses it. n represents one of the eight virtual channels divided by the PFC mechanism. E(n) is a bit value, 1 represents congestion, and 0 represents no congestion. Time(n) is a two-byte backpressure timer, which is the time when the PFC controls the NIC to stop sending data packets. The longer the time, the higher the congestion level.

[0136] In this embodiment, the principle of the PFC mechanism is used to quantify and normalize the congestion of the computing node port under the PFC mechanism, and the P value is between [0, 1].

[0137] Furthermore, the calculation formula of the second congestion metric factor q includes:

[0138] q=α(t)=(1-g)×α t-Δt +g×CNP_arrived

[0139] Among them, g is a constant that depends on the network card firmware; Δt represents the rate adjustment time interval in quantized congestion control; CNP_arrived takes the value of 1 or 0, 1 means that CNP has arrived, and 0 means that CNP has not arrived.

[0140] According to some embodiments of the present application, the RDMA engine of the computing power node can also collect data from relevant registers of the QCN mechanism and define a normalized variable factor q as a measure of network congestion under ECN.

[0141] q=α(t)=(1-g)×α t-Δt +g×CNP_arrived

[0142] Among them, the α parameter is a constantly changing average value on the network card side of the computing node. It is the ratio of the time slots of CNP arrival (if more than one CNP arrives in the same time slot, the effect is the same as if only one CNP arrives). At the end of each time slot, α is updated by the following formula. The α parameter can represent the congestion level of the network path corresponding to the computing node port under the QCN mechanism. g is a constant parameter between 0 and 1, which is determined by the network card firmware; Δt is the rate adjustment time interval, and CNP_arrived is a bit field, which is 1 if a CNP arrives, otherwise it is 0.

[0143] It should be noted here that the congestion measurement unit, flow slicing unit, balancing decision maker and forwarding engine functional entities can be implemented through FPGA programming development, can also be implemented through ASIC circuit construction, or a combination of the two.

[0144] According to other embodiments of the present application, the number N of RDMA links of the eDPU can be set to match the GPU computing power. Here, N=14: 12 400G + 2 200G is taken as an example, where the 12 400G optical links are used for Scale-Up networking, and the 2 200G optical links are used for Scale-Out networking.

[0145] In this embodiment, d=3, r=2, s=2 can be constructed as follows: Figure 4 The three-dimensional bidirectional two-way Scale-Up network shown in FIG. 1 is constructed by using d=1, r=4, and s=3. Figure 4 The one-dimensional four-way three-way Scale-Up network shown in FIG. 1 is constructed by using d=2, r=2, and s=3. Figure 4 The two-dimensional bidirectional three-way Scale-Up network shown in FIG. 1 is constructed by using d=1, r=2, and s=6. Figure 4 The one-dimensional bidirectional six-way Scale-Up network is shown.

[0146] In other words, through different combinations of dimensions, directions, and numbers of paths, different Scale-Up network topologies can be built on demand through OCS programming.

[0147] Use optical path switches to interconnect the aggregation blocks of each Scale-Up network, and reconstruct the optical interconnection architecture Scale-Out network link allocation method: Taking 2 200G optical links for Scale-Out networking and a×b×c=4×4×4 GPU nodes in each aggregation block as an example, each aggregation block is divided into 2 groups, namely 2×4×4 GPU nodes, each GPU node has 2 200G optical links, so one aggregation block group has 64 optical links.

[0148] In this embodiment, the link allocation is shown in the following table 1:

[0149] Table 1

[0150] A B C D E F A 14 10 10 10 10 10 B 10 14 10 10 10 10 C 10 10 14 10 10 10 D 10 10 10 14 10 10 E 10 10 10 10 14 10 F 10 10 10 10 10 14

[0151] Using the network construction and link allocation methods shown in the table above, the interconnection architecture of Scale-Out networking is as follows: Figure 6 The SDN software in this embodiment is deployed and runs in the server. The server communicates with the Scale-Out network and the Scale-Up network through the control plane network. The collective communication algorithm and topology mapping are shown in Fig.11 shown.

[0152] Based on the collective communication algorithm and topology mapping, the complete process from the interface configuration data of the upper-layer model application to the OCS topology configuration is as follows: Fig.12 As shown, it includes: based on the interface configuration data, the inter-operator (pipeline) topology and the intra-operator (tensor) topology are calculated respectively, and then the optical topology deployment plan is determined. After that, the topology and physical instructions are processed through SDN and sent to OCS. The logical design of the model and the physical topology mapping rules are as follows:

[0153] 1. Traffic-aware topology engineering is used between model layers: predicted traffic matrix + eBGP-based multi-path routing, with priority given to interconnecting GPU cards with the same number.

[0154] 2. In principle, all physical links are allocated within the same model layer, and the traffic bandwidth or links between nodes are evenly distributed, and each dimension is processed the same way.

[0155] In addition, the present application proposes an enhanced data processing unit, including: a CPU subsystem, an RDMA engine, a load balancing module and a hard forwarding engine; wherein the CPU subsystem is configured to: plan and issue routing strategies; the RDMA engine is connected to the GPU; the RDMA engine is configured to: implement multi-hop interconnection of GPU node forwarding based on the RoCEV2 protocol; and implement priority flow control (PFC) and quantified congestion control (QCN) based on the RoCEV2 protocol; the load balancing module is configured to: quantify the degree of congestion of the communication path based on priority flow control (PFC) and quantified congestion control (QCN), and implement load balancing of multi-path routing traffic based on the quantification of the degree of congestion of the communication path; the hard forwarding engine is provided with a first switching port and a second switching port; the first switching port and the second switching port are respectively connected to the optical path switch to construct a Scale-Up network and a Scale-Out network.

[0156] It is obvious that a person skilled in the art may make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. An intelligent optical switching networking system, characterized in that: include: Computing nodes and optical path switches; wherein, The computing node comprises: an enhanced data processing unit; The enhanced data processing unit is provided with an RDMA network interface, and implements priority flow control (PFC) and quantized congestion control (QCN) based on the RoCEV2 protocol; The enhanced data processing unit is further provided with a first switching port and a second switching port, and the first switching port and the second switching port are respectively connected to the optical path switch to construct a Scale-Up network and a Scale-Out network.

2. The system according to claim 1, characterized in that The computing node comprises: CPU, PCIe bus switching unit and computing communication unit; wherein, The computing and communication unit comprises: a GPU and the enhanced data processing unit; The CPU is connected to the PCIe bus switching unit and other CPUs in the computing node; The computing communication unit is connected to the PCIe bus switching unit.

3. The system according to claim 2, characterized in that The enhanced data processing unit comprises: CPU subsystem, RDMA engine, load balancing module and hard forwarding engine; among them, The CPU subsystem is configured to: plan and issue routing strategies; The RDMA engine is connected to the GPU; the RDMA engine is configured to: implement multi-hop interconnection of GPU node forwarding based on the RoCEV2 protocol; and implement priority flow control (PFC) and quantized congestion control (QCN) based on the RoCEV2 protocol; The load balancing module is configured to: quantify the degree of congestion of a communication path based on the priority flow control (PFC) and quantified congestion control (QCN), and implement load balancing of multi-path routing traffic based on the quantified degree of congestion of the communication path; The hard forwarding engine is provided with the first switch port and the second switch port.

4. The system according to claim 3, characterized in that In the Scale-Up network, the RDMA physical links corresponding to the GPU nodes are interconnected through optical path switches, and the total number of links of the GPU nodes is M=d×r×s, where d represents the number of link dimensions; r represents the number of link directions in each dimension; and s represents the number of links in each direction.

5. The system according to claim 3, characterized in that The Scale-Out network includes several Scale-Up aggregation blocks; wherein, Each aggregation block acts as a BGP alliance; Each BGP alliance has a unique ASN, and each enhanced data processing unit in the BGP alliance has a unique sub-ASN that is invisible to other BGP alliances; Sub-ASNs in different BGP alliances can be reused.

6. The system according to claim 3, characterized in that The load balancing module includes: a balancing decision maker and a flow slicing unit; wherein, The flow slicing unit is configured to: perform flow slicing detection and slicing at the data packet transmission interval; and detect whether the incoming data packet starts a new flow slice, and if so, notify the balancing decision maker to perform load balancing decision; The load balancing decision maker is configured to implement load balancing decision by minimizing the congestion metric factor of each channel of the uplink port.

7. The system according to claim 6, characterized in that The calculation formula of the congestion measurement factor includes: Q=β×q+(1-β)×p Among them, Q represents the congestion measurement factor; q represents the first congestion measurement factor calculated based on priority flow control (PFC); p represents the second congestion measurement factor calculated based on quantized congestion control (QCN); β represents the allocation coefficient, which is a set value.

8. The system according to claim 7, characterized in that The calculation formula of the first congestion measurement factor p includes: Among them, E(n) and Time(n) represent the values ​​of the network card register when the RDMA engine parses the PFC Pause frame; E(n) takes the value of 1 or 0, 1 indicates congestion occurs, and 0 indicates no congestion occurs; Time(n) represents the time when the priority flow control controls the network card to stop sending data packets; n represents one of the virtual channels divided by the priority flow control.

9. The system according to claim 7, characterized in that The calculation formula of the second congestion metric factor q includes: q=α(t)=(1-g)×α t - Δt +g×CNP_arrived Among them, g is a constant that depends on the network card firmware; Δt represents the rate adjustment time interval in quantized congestion control; CNP_arrived takes the value of 1 or 0, 1 means that CNP has arrived, and 0 means that CNP has not arrived.

10. An enhanced data processing unit applicable to the intelligent optical switching networking system according to any one of claims 1 to 9, characterized in that: include: CPU subsystem, RDMA engine, load balancing module and hard forwarding engine; among them, The CPU subsystem is configured to: plan and issue routing strategies; The RDMA engine is connected to the GPU; the RDMA engine is configured to: implement multi-hop interconnection of GPU node forwarding based on the RoCEV2 protocol; and implement priority flow control (PFC) and quantized congestion control (QCN) based on the RoCEV2 protocol; The load balancing module is configured to: quantify the degree of congestion of the communication path based on the priority flow control (PFC) and the quantified congestion control (QCN), and realize load balancing of multi-path routing traffic based on the quantified degree of congestion of the communication path; The hard forwarding engine is provided with a first switching port and a second switching port; The first switching port and the second switching port are respectively connected to an optical path switch to construct a Scale-Up network and a Scale-Out network.

Images