MSC downlink frame data configuration device, method, equipment, medium and program

Abstract

The embodiment of the invention discloses an MSC (Mobile Switching Center) downlink frame data configuration device, method, equipment, medium and program, the device comprises four data configuration register groups, and each data configuration register group is used for correspondingly configuring one data segment in MSC downlink frame data; and the data configuration register group is used for performing bit-by-bit on-demand configuration on each bit data of a target data segment in the MSC downlink frame data to obtain target MSC downlink frame data. According to the technical scheme of the embodiment of the invention, the flexibility of downlink frame data configuration of the MSC can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of communication technology, and in particular to an MSC downlink frame data configuration device, method, electronic device, storage medium and program. Background Art

[0002] MSC (Micro Second Channel) is a high-speed serial interface protocol. It supports high-speed serial data transmission and can effectively reduce the number of pins of external power devices, so it has great advantages in power control. Devices supporting the MSC protocol are widely used in many scenarios, including: multi-cylinder engine control (such as the control of injectors and igniters of multiple cylinders), brake systems, fountain systems, and lighting control (such as running water light effects).

[0003] The microcontroller integrated with the MSC communication module usually supports two types of communication frames, namely command frames and data frames, for controlling the downlink frames of the external power devices. The command frame is usually used to control the functions of the MSC slave, and the data frame is usually used to control the output of the MSC slave (usually pin output control). The downlink frame data sent by the MSC master device usually includes at most four stages, namely SRL (Shift Register Low), SRLE (Shift Register Low Extend) (optional data segment), SRH (Shift Register High) and SRHE (Shift Register High Extend) (optional data segment). The downlink frame data sent by the existing MSC master device to the outside needs to be controlled by the internal shift register, and the downlink frame data length is adjusted by configuring the number of shift bits. After configuring the specified shift number, the internal shift register of the MSC master device shifts from low to high according to the bit position to generate downlink frame data.

[0004] In the process of implementing the present invention, the inventors found that the prior art has the following defects: in the application scenario of MSC downlink frame data, the data bits in the MSC downlink frame data are bound to the corresponding data bits in the data source, and the shift order cannot be changed, and the function of omitting or repeating specific data bits cannot be realized. In many application scenarios such as multi-cylinder engine control, brake system, fountain system and lighting control, it is often necessary to flexibly configure the downlink frame data of the MSC master device. Summary of the invention

[0005] The embodiment of the present invention provides a MSC downlink frame data configuration device, method, electronic device, storage medium and program, which can improve the flexibility of MSC downlink frame data configuration.

[0006] According to one aspect of the present invention, there is provided an MSC downlink frame data configuration device, comprising four data configuration register groups, each of which is used to configure a data segment in the MSC downlink frame data;

[0007] The data configuration register group is used to configure each bit of the target data segment in the MSC downlink frame data bit by bit as required to obtain the target MSC downlink frame data.

[0008] According to another aspect of the present invention, a method for configuring MSC downlink frame data is provided, characterized in that the MSC downlink frame data configuration device applied to any embodiment of the present invention comprises four data configuration register groups, each of which is used to configure a data segment in the MSC downlink frame data; the method comprises:

[0009] The MSC downlink frame data configuration device determines the bit positions of the original data to be sent;

[0010] Configure the data configuration register corresponding to the data segment and select the corresponding SEL bit data;

[0011] Configure the data configuration register of the corresponding data segment, and configure the corresponding SELEN bit data to enable the corresponding SEL bit data;

[0012] According to the current corresponding enable SEL bit data, the hardware triggers the MSC to send the downlink frame data, and sends the original data of the corresponding bit to form the target MSC downlink frame data.

[0013] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising the MSC downlink frame data configuration device according to any embodiment of the present invention, and the electronic device further comprising:

[0014] at least one processor; and

[0015] a memory communicatively connected to the at least one processor; wherein,

[0016] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the MSC downlink frame data configuration method described in any embodiment of the present invention.

[0017] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the MSC downlink frame data configuration method described in any embodiment of the present invention when executed.

[0018] According to another aspect of the present invention, a computer program product is provided, including a computer program. When the computer program is executed by a processor, the MSC downlink frame data configuration method according to any embodiment of the present invention is implemented.

[0019] The embodiment of the present invention forms a MSC downlink frame data configuration device through four data configuration register groups, and each data configuration register group in the MSC downlink frame data configuration device is used to configure a data segment in the MSC downlink frame data. Specifically, the data configuration register group can configure each bit of the target data segment in the MSC downlink frame data bit by bit as needed to obtain the target MSC downlink frame data. It can be seen that the above-mentioned MSC downlink frame data configuration device can solve the problem of poor flexibility in the existing method of generating MSC downlink frame data according to the number of shifts from low to high, and can improve the flexibility of MSC downlink frame data configuration.

[0020] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 It is a schematic diagram of a process in which an MSC host generates downlink frame data through a shift module in the prior art;

[0023] Figure 2 It is a structural diagram of a MSC downlink frame data configuration device provided in Embodiment 1 of the present invention;

[0024] Figure 3 It is a structural diagram of another MSC downlink frame data configuration device provided in Embodiment 2 of the present invention;

[0025] Figure 4 It is a structural diagram of another MSC downlink frame data configuration device provided in Embodiment 2 of the present invention;

[0026] Figure 5 It is a schematic diagram of the internal structure of the first data configuration register in the SRL segment data configuration register group provided by the second embodiment of the present invention;

[0027] Figure 6 It is a schematic diagram of the internal structure of a second data configuration register in an SRL segment data configuration register group provided by Embodiment 2 of the present invention;

[0028] Figure 7 It is a schematic diagram of the internal structure of a third data configuration register in an SRL segment data configuration register group provided by Embodiment 2 of the present invention;

[0029] Figure 8 It is a schematic diagram of the internal structure of a fourth data configuration register in an SRL segment data configuration register group provided by Embodiment 2 of the present invention;

[0030] Fig. 9 It is a schematic diagram of a flow chart of data configuration based on a MSC downlink frame data configuration device in an MSC host device provided by a second embodiment of the present invention;

[0031] Fig.10 is a flow chart of a data configuration method provided by Embodiment 3 of the present invention;

[0032] Fig.11 A schematic diagram of the structure of an electronic device provided in Embodiment 4 of the present invention. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0034] It should be noted that the terms "first", "second", "third", "fourth" and "target" in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0035] Figure 1 FIG. 1 is a flow chart of the MSC host generating downlink frame data through the shift module in the prior art. Figure 1 As shown, the downlink frame data of the MSC host includes at most four data segments: SRL, SRLE, SRH and SRHE, and each data segment includes at most 16 bits of data. The downlink frame data control of the existing MSC host is realized by the internal shift register, and the adjustment of the downlink frame length is configured by the number of shift bits. After configuring the specified shift number, the internal shift register of the MSC host shifts from low to high according to the bit position to generate the downlink frame data. Therefore, the data bits in the downlink frame data are bound to the corresponding data bits in the data source, and the shift order of the bit positions cannot be changed, nor can the specific data bit omission or duplication function be realized. That is, it is impossible to realize that the user-configurable specified bit position data constitutes the downlink frame data. In many application scenarios such as multi-cylinder engine control (control of injectors and igniters of multiple cylinders), brake systems, fountain systems, and lighting control (such as running water light effects), it is necessary to flexibly configure the data of each bit position of the downlink frame data of the MSC host.

[0036] Embodiment 1

[0037] Figure 2 Schematic diagram of a structure of a MSC downlink frame data configuration device provided in Embodiment 1 of the present invention. Figure 2 As shown, the structure of the MSC downlink frame data configuration device 100 includes 4 data configuration register groups 110, each of which is used to configure a data segment in the MSC downlink frame data; the data configuration register group 110 is used to: configure each bit of the target data segment in the MSC downlink frame data bit by bit as needed to obtain the target MSC downlink frame data.

[0038] Among them, a data configuration register group 110 may include multiple registers, and each data configuration register group 110 is used to configure the data corresponding to a data segment in the MSC downlink frame data. The target data segment may be a data segment that the data configuration register group can configure accordingly. Exemplarily, the target data segment corresponding to the first data configuration register group may be an SRL data segment, the target data segment corresponding to the second data configuration register group may be an SRLE data segment, the target data segment corresponding to the third data configuration register group may be an SRH data segment, and the target data segment corresponding to the fourth data configuration register group may be an SRHE data segment. The target MSC downlink frame data may be MSC downlink frame data flexibly configured by the MSC downlink frame data configuration device 100. It can be understood that the target MSC downlink frame data may be downlink frame data sent externally by the MSC master device.

[0039] Specifically, in the MSC communication scenario, the maximum number of bits of MSC downlink frame data is 64 bits, and the MSC downlink frame data includes a total of 4 data segments, so 4 data configuration register groups can be configured in the MSC downlink frame data configuration device 100. The first data configuration register group 110 is used to configure the data of the SRL data segment, the second data configuration register group 110 is used to configure the data of the SRLE data segment, the third data configuration register group 110 is used to configure the data of the SRH data segment, and the fourth data configuration register group 110 is used to configure the data of the SRHE data segment.

[0040] Since the maximum number of bits of MSC downlink frame data is 64 bits, the number of bits that can be configured in each data configuration register group 110 can be 16 bits. When the MSC downlink frame data configuration device 100 receives the frame data configuration instruction, it can parse it to determine the data length (maximum not exceeding 64 bits) and specific data content of the target MSC downlink frame data to be configured and generated, and select one or more data configuration register groups 110 from each data configuration register group 110 as the target data configuration register group based on the frame data configuration instruction, and instruct the target data configuration register group to configure each bit of data in the corresponding target data segment bit by bit as needed to obtain the final target MSC downlink frame data. Optionally, the target data configuration register group can be part or all of the data configuration register group 110, and the embodiment of the present invention does not limit this.

[0041] The so-called bit-by-bit on-demand configuration of each bit of the frame data to be transmitted can be understood as configuring each bit of the corresponding target data segment on-demand through the data configuration register group 110, and the configuration operations between the bit data are independent of each other and do not affect each other.

[0042] In a specific example, assuming that the 5th and 10th bits of data in the data source need to be sent through the SRL data segment, and the 6th and 11th bits of data in the data source need to be sent through the SRH data segment, then the first data configuration register group 110 corresponding to the SRL data segment and the third data configuration register group 110 corresponding to the SRH data segment can be used as the target data configuration register group. Further, one bit can be arbitrarily selected from the 16 bits that can be configured by the first data configuration register group 110 to transmit the 5th bit of data in the data source, and another bit can be arbitrarily selected from the 16 bits that can be configured by the first data configuration register group 110 to transmit the 10th bit of data in the data source. At the same time, one bit can be arbitrarily selected from the 16 bits that can be configured by the third data configuration register group 110 to transmit the 6th bit of data in the data source, and another bit can be arbitrarily selected from the 16 bits that can be configured by the first data configuration register group 110 to transmit the 11th bit of data in the data source.

[0043] The embodiment of the present invention forms a MSC downlink frame data configuration device through four data configuration register groups, and each data configuration register group in the MSC downlink frame data configuration device is used to configure a data segment in the MSC downlink frame data. Specifically, the data configuration register group can configure each bit of the target data segment in the MSC downlink frame data bit by bit as needed to obtain the target MSC downlink frame data. It can be seen that the above-mentioned MSC downlink frame data configuration device can solve the problem of poor flexibility in the existing method of generating MSC downlink frame data according to the number of shifts from low to high, and can improve the flexibility of MSC downlink frame data configuration.

[0044] Embodiment 2

[0045] This embodiment is specific based on the above embodiment and provides a specific composition structure of each data configuration register group.

[0046] Optionally, each data configuration register group may include 4 data configuration registers; wherein: each data configuration register group is used to configure 16 downlink frame data bits of the data segment; each data configuration register includes 32 bits, which respectively correspond to the 4 downlink frame data bits of the data segment.

[0047] Figure 3 FIG. 1 is a schematic diagram of another MSC downlink frame data configuration device provided in Embodiment 2 of the present invention. In a specific example, Figure 3As shown, in the embodiment of the present invention, the MSC downlink frame data configuration device may include a first data configuration register group, a second data configuration register group, a third data configuration register group and a fourth data configuration register group. Among them, the first data configuration register group can be used to configure the data of the SRL data segment in the MSC downlink frame data, the second data configuration register group can be used to configure the data of the SRLE data segment in the MSC downlink frame data, the third data configuration register group can be used to configure the data of the SRH data segment in the MSC downlink frame data, and the fourth data configuration register group can be used to configure the data of the SRHE data segment in the MSC downlink frame data. Since each data segment of the MSC downlink frame data includes at most 16 bits of data, each data configuration register group can be used to configure the up to 16 downlink frame data bits of the corresponding configuration data segment. That is, the first data configuration register group can be used to configure the data of up to 16 bits of the SRL data segment, the second data configuration register group can be used to configure the data of up to 16 bits of the SRLE data segment, the third data configuration register group can be used to configure the data of up to 16 bits of the SRH data segment, and the fourth data configuration register group can be used to configure the data of up to 16 bits of the SRHE data segment.

[0048] In the embodiment of the present invention, each data configuration register group may include four data configuration registers, namely, a first data configuration register, a second data configuration register, a third data configuration register and a fourth data configuration register. One data configuration register group is used to configure a maximum of 16 bits of data, so one data configuration register can configure a maximum of 4 bits of data, which is used to configure a maximum of 4 downlink frame data bits of the corresponding data segment.

[0049] It should be noted that different data configuration registers can configure corresponding downlink frame data bits as needed. Exemplarily, the first data configuration register in the first data configuration register group can be used to configure the downlink frame data bits of the 1st to 4th bits of the SRL data segment; or, the first data configuration register in the first data configuration register group can be used to configure the downlink frame data bits of the 2nd to 5th bits of the SRL data segment; or, the first data configuration register in the first data configuration register group can also be used to configure the downlink frame data bits of the 1st, 2nd, 5th and 8th bits of the SRL data segment, etc. Similarly, the second data configuration register in the third data configuration register group can be used to configure the downlink frame data bits of the 1st to 4th bits of the SRH data segment; or, the second data configuration register in the third data configuration register group can also be used to configure the downlink frame data bits of the 7th, 8th, 10th and 15th bits of the SRH data segment, etc. That is, as long as one data configuration register in a data configuration register group can correspond to 4 of the downlink frame data bits of the configuration data segment, the embodiment of the present invention does not limit the specific bit positions in the corresponding data segment that each data configuration register can configure.

[0050] In an optional embodiment of the present invention, each downlink frame data bit is configured with 8 bits, of which: 6 bits are used to control the downlink frame data bit; and 2 bits are used to enable configuration of the downlink frame data bit.

[0051] Since the maximum number of bits of MSC downlink frame data is 64 bits, 6 =64, so each downlink frame data bit requires at least 6 bits to meet the transmission requirements of any one bit of the 64-bit data in the data source. Each data configuration register includes 32 bits, and each data configuration register configures 4 bits of downlink frame data bits. Therefore, each downlink frame data bit can be configured with 8 bits. Among them, every 6 bits in every 8 bits can be used to control the configuration of the downlink frame data bit, and the 6 bits can control a certain downlink frame data bit to select any one bit of data in the 64-bit data source for transmission. The remaining 2 bits in every 8 bits can be used to enable the configuration of the downlink frame data bit.

[0052] In an optional embodiment of the present invention, since two bits are used to enable the configuration of the downlink frame data bit, the downlink frame data bit enable configuration can adopt a redundant mechanism. That is, the enable configuration bit value can be set to 0x3 to represent enablement, and other values ​​to represent disablement. The advantage of such a setting is that the reliability and accuracy of the MSC downlink frame data configuration can be improved.

[0053] In an optional embodiment of the present invention, the MSC downlink frame data configuration device can be used to: determine a target data configuration register group for configuring the target data segment from each of the data configuration register groups; determine a target data configuration register from the target data configuration register group; configure the target data configuration register and select corresponding SEL bit data; configure the target data configuration register and configure corresponding SELEN bit data to enable corresponding SEL bit data.

[0054] Wherein, the target data configuration register group may be a data configuration register group for configuring the target data segment. It is understandable that the number of the target data segment may be one or more, and therefore, the number of the target data configuration register group may also be one or more. The target data configuration register may be a data configuration register for configuring the downlink frame data bit of the target data segment. The SEL bit may be a bit data group in the data configuration register for correspondingly configuring the downlink frame data bit. The SELEN bit may be a bit data group in the data configuration register for enabling the configuration of the downlink frame data bit.

[0055] Specifically, each data configuration register may include 4 groups of SEL bits and 4 groups of SELEN bits. Each group of SEL bits may include 6 bits for controlling the downlink frame data bits. Each group of SEL bits is correspondingly configured with a group of SELEN bits for controlling the enabling of the SEL bits. In the process of configuring the MSC downlink frame data by the MSC downlink frame data configuration device, any one of the data configuration register groups may be selected as the target data configuration register group from each data configuration register group as needed, and any one of the data configuration registers may be selected as the target data configuration register from the target data configuration register group. After determining the target data configuration register, the target data configuration register may be configured, and the corresponding SEL bit data may be selected to further configure the selected SEL bit with the data of the target bit in the corresponding transmitted data source. After selecting the corresponding SEL bit data, the SELEN bit data corresponding to the selected SEL bit in the target data configuration register may be further configured to enable the corresponding selected SEL bit data.

[0056] It can be seen that since the target data configuration register group, the target data configuration register and the SEL bit in the target data configuration register can all be configured as needed, it is possible to send data of a certain bit in the data source through any SEL bit in any data configuration register in any data configuration register group, thereby realizing on-demand configuration of the MSC downlink frame data.

[0057] In an optional embodiment of the present invention, the MSC downlink frame data configuration device can be used to: hardware trigger MSC downlink frame data transmission according to the current corresponding enable SEL bit data, and send the original data of the corresponding bit to form the target MSC downlink frame data.

[0058] The original data is data generated by a data source in the MSC host device. Optionally, the original data may include up to 64 bits of data.

[0059] Correspondingly, after selecting the SEL bit configuration in each target data configuration register in turn and enabling the SEL bit data, the hardware can trigger the sending process of the downlink frame data. Specifically, the hardware can splice the enabled SEL bit data in turn according to the order of the target data configuration register group in each data configuration register group and the order of the target data configuration register in the target data configuration register group to generate the target MSC downlink frame data.

[0060] Figure 4 FIG. 1 is a schematic diagram of another MSC downlink frame data configuration device provided in Embodiment 2 of the present invention. Figure 4As shown, the MSC downlink frame data configuration device configured in the MSC host may include 4 groups of data configuration register groups, namely, an SRL segment data configuration register group, an SRLE segment data configuration register group, an SRH segment data configuration register group, and an SRHE segment data configuration register group. Among them, the SRL segment data configuration register group can be used to configure the SRL data segment, the SRLE segment data configuration register group can be used to configure the SRLE data segment, the SRH segment data configuration register group can be used to configure the SRH data segment, and the SRHE segment data configuration register group can be used to configure the SRHE data segment. Each group of data configuration registers may include 4 data configuration registers, such as the SRL segment data configuration register group includes 4 data configuration registers, namely SRLMUX0, SRLMUX1, SRLMUX2 and SRLMUX3; the SRLE segment data configuration register group includes 4 data configuration registers, namely SRLEMUX0, SRLEMUX1, SRLEMUX2 and SRLEMUX3; the SRH segment data configuration register group includes 4 data configuration registers, namely SRHMUX0, SRHMUX1, SRHMUX2 and SRHMUX3; the SRHE segment data configuration register group includes 4 data configuration registers, namely SRHEMUX0, SRHEMUX1, SRHEMUX2 and SRHEMUX3. Each data configuration register may configure 4 corresponding MSC downlink frame data bits, for example, SRLMUX0 in the SRL segment data configuration register group may configure 4 bits in the MSC downlink frame data. In this way, the data configuration device can respectively configure the data content of each bit of the SRL segment, SRLE segment, SRH segment and SRHE segment (each segment is 16 bits at most) of the MSC downlink frame data with a maximum width of 64 bits.

[0061] Exemplarily, assume that the data of the third bit in the data source (i.e., the original data) needs to be sent through the first bit of the SRL segment, and the data of the sixth bit in the data source needs to be sent through the fifth bit of the SRH segment. The MSC downlink frame data configuration device can then specify that the SRL segment data configuration register group and the SRH segment data configuration register group are determined as the target data configuration register group. Since the data of the data source needs to be sent through the first bit of the SRL segment, SRLMUX0 in the SRL segment data configuration register group needs to be used as the target data configuration register. At the same time, since the data of the data source needs to be sent through the fifth bit of the SRH segment, SRHMUX1 in the SRH segment data configuration register group needs to be used as the target data configuration register.

[0062] Figure 5 Schematic diagram of the internal structure of the first data configuration register in the SRL segment data configuration register group provided by the second embodiment of the present invention. Figure 4 and Figure 5 As shown, taking the SRL segment data configuration register group as the target data configuration register group as an example, the first data configuration register SRLMUX0 in the SRL segment data configuration register group can include a total of 32 bits, and the 32 bits included in SRLMUX0 are divided, wherein 8k+7:8k+6 (k=0-3) are enable configuration bits, such as Figure 5 The corresponding SELkEN (k = 0-3) bit field names are shown, namely, four enable configuration bits, namely SEL0EN, SEL1EN, SEL2EN and SEL3EN. The enable configuration bit can be readable and writable (RW), and can be used to define whether the original data of the corresponding data bit SEL of the corresponding downlink frame in SRLMUX0 is enabled. Optionally, if the enable configuration bit adopts a redundant mechanism for enabling configuration, the enable configuration bit value can be set to 0x3 to represent enabling, and other values ​​to represent disabling. The bit position occupied by the SEL bit in SRLMUX0 is: 8k+5:8k (k = 0-3), such as Figure 5 The corresponding SELk (k=0-3) bit field names are shown, namely SEL0, SEL1, SEL2 and SEL3. Each group of SEL bits can be configured with one bit of data. The SEL bits can also be readable and writable (RW). Since each group of SEL bits includes 6 bits, each group of SEL bits can be configured with a maximum of 64 bits of data, and the 64 bits of data can be arbitrarily selected from the data source to meet the flexible configuration requirements of each bit.

[0063] Figure 6 is a schematic diagram of the internal structure of a second data configuration register in an SRL segment data configuration register group provided by Embodiment 2 of the present invention, Figure 7 is a schematic diagram of the internal structure of the third data configuration register in the SRL segment data configuration register group provided by the second embodiment of the present invention, Figure 8 1 is a schematic diagram of the internal structure of the fourth data configuration register in the SRL segment data configuration register group provided by the second embodiment of the present invention. Figure 5-Figure 8As shown, the internal structure of each data configuration register is the same, and the configuration method of its SEL bit and enable configuration bit can also be the same. Correspondingly, the configuration method of each data configuration register for data can also be the same. The internal structure of the SRL segment data configuration register group, the SRLE segment data configuration register group, the SRH segment data configuration register group and the SRHE segment data configuration register group is the same. Taking the SRL segment data configuration register group as an example, optionally, SEL0 can be used to configure the 0th bit in the SEL data segment, SEL1 can be used to configure the 1st bit in the SEL data segment, SEL2 can be used to configure the 2nd bit in the SEL data segment, SEL3 can be used to configure the 3rd bit in the SEL data segment, and so on, SEL15 can be used to configure the 15th bit in the SEL data segment. That is, SEL0-SEL15 can configure a total of up to 16 bits of the SEL data segment. Similarly, in the SRLE segment data configuration register group, SEL0-SEL15 can configure a total of up to 16 bits of the SELE data segment; in the SRH segment data configuration register group, SEL0-SEL15 can configure a total of up to 16 bits of the SEH data segment, and in the SRHE segment data configuration register group, SEL0-SEL15 can configure a total of up to 16 bits of the SRHE data segment.

[0064] Exemplarily, if the data of the third bit in the data source needs to be sent through the first bit of the SRL segment, SRLMUX0 in the SRL segment data configuration register group can be used as the target data configuration register, and the first SEL bit of SRLMUX0 can be used as the enabled SEL bit. Therefore, the enable configuration bit SEL0EN corresponding to SEL0 in SRLMUX0 can be configured, for example, the value is 0x3, so that SEL0 is enabled. Further, each bit of SEL0 is configured according to the third bit of the original data, so that the value of SEL0 in SRLMUX0 is 0x3, indicating that the data of the third bit in the original data is sent through the first bit of the SRL segment. Similarly, if it is necessary to configure the data of other bits of the SRL segment through the SRL data configuration register, the same principle as above can also be used for configuration. Accordingly, the data obtained by configuring the corresponding SEL bits of each SRL data configuration register included in the SRL segment data configuration register group is spliced ​​to obtain the complete SEL segment configuration data. Furthermore, by splicing at least one of the SEL segment configuration data, SELE segment configuration data, SEH segment configuration data and SEHE segment configuration data configured by the data configuration register group, complete target MSC downlink frame data can be obtained.

[0065] In the embodiment of the present invention, for the target MSC downlink frame data, each bit of data can flexibly specify which bit of data in the original data it comes from. Figure 5-Figure 8 In the SEL bit of each data configuration register, the corresponding relationship between each bit in the target MSC downlink frame data and the bit in the original data can be defined. Specifically, when the SEL bit of the data configuration register takes the value of 0x0, it means that the value of the SEL bit can come from the 0th bit of the original data; when the SEL bit of the data configuration register takes the value of 0x1, it means that the value of the SEL bit can come from the 1st bit of the original data; when the SEL bit of the data configuration register takes the value of 0x2, it means that the value of the SEL bit can come from the 2nd bit of the original data, and so on. When the SEL bit of the data configuration register takes the value of 0x3F, it means that the value of the SEL bit can come from the 63rd bit of the original data. It can be seen that each SEL bit can select any one bit of data from the 64-bit original data as needed to send, which greatly meets the flexible configuration requirements of the MSC downlink frame data.

[0066] It should be noted that the target MSC downlink frame data can include a maximum of 64 bits of data. That is, each data segment in the target MSC downlink frame data can correspond to the data on the bit in the original data to be sent, or it can be empty. Exemplarily, the target MSC downlink frame data can be: data less than 64 bits consisting of part of the bit data in the SRL data segment and part of the bit data in the SRH data segment, or it can be data consisting of 64 bits for all data segments.

[0067] Fig. 9 FIG. 1 is a flow chart of data configuration based on a MSC downlink frame data configuration device in an MSC host device according to a second embodiment of the present invention. In a specific example, Figure 4-Figure 9 As shown, the process of performing data configuration based on the MSC downlink frame data configuration device in the MSC host device may include the following operations:

[0068] (1) Multiple bits of original data constitute an original data stream. Determine the bit position of the original data to be sent in the original data stream to be sent, and determine the position of the bit position of the original data to be sent in the original data stream as the target sending position. For example, the data at the 0th bit position in the original data stream can be selected, and the bit position of the original data to be sent is at position 0 in the original data stream, and the target sending position is 0. The data at the 3rd bit position in the original data stream can be selected, and the bit position of the original data to be sent is at position 3 in the original data stream, and the target sending position is 3.

[0069] (2) Select the corresponding data configuration register group and the data configuration register in the data configuration register group as needed, and select the target SEL bit from the selected data configuration register, and configure the value of the target SEL bit as the target sending position. For example, SEL0 of SRHMUX0 in the SRH segment data configuration register group can be selected as the target SEL bit, and the data of SEL0 of SRHMUX0 in the SRH segment data configuration register group can be configured to 0x3, indicating that the data at the 3rd bit in the original data stream is sent through the data at the 0th bit in the SRH data segment.

[0070] (3) Configure the enable configuration bit corresponding to the target SEL bit to enable the corresponding target SEL bit.

[0071] (4) The hardware triggers the generation of the target MSC downlink frame data according to the configuration of each data configuration register in the MSC downlink frame data configuration device.

[0072] It can be seen that each group of bit configuration bits in the data configuration register can be configured to obtain data from which bit in the original data stream. For example, when the data value of the 6 bits of SEL12 of the SRH data configuration register 3 in the SRH segment data configuration register group is configured to 0x3, it means that the data of the 11th bit of the SRH segment in the MSC downlink frame data is the data on the 3rd bit in the original data stream; assuming that the SEL2EN bit in the SRLMUX0 is configured to 0, it means that the 2nd bit data of the SRL segment of the MSC downlink frame data is not enabled, and the hardware can automatically splice the enabled bits into the target MSC downlink frame data to be sent.

[0073] The so-called hardware automatically splicing the enabled bits into the target MSC downlink frame data to be sent can be understood as the hardware will detect whether the SEL bit is enabled bit by bit from low to high in the data segment. If it is enabled, it will be used as the data bit of the data segment of the downlink frame. If it is not enabled, the SEL bit will be skipped until the next enabled SEL bit is found, and then the enabled SEL bit data will be spliced ​​to the higher data bit of the data segment of the downlink frame.

[0074] In an optional embodiment of the present invention, the original data stream may be initiated by a data source. In the MSC communication scenario, the data source may include, but is not limited to, at least one of a data register, a data extension register, a command register, a command extension register, a GTM (Generic Timer Module) signal generator inside the chip, and an external pin.

[0075] It should be noted that, considering the update requirements of subsequent MSC data communication scenarios, and / or the update evolution of single register structures and functions, the data configuration device 100 in the embodiment of the present invention can adapt to the internal composition structure of the dynamic adjuster. That is, the number of data configuration register groups and the number of registers included in each data configuration register group can be dynamically changed according to the requirements of specific application scenarios. For example, when the number of data segments of MSC downlink frame data is updated to 5, the number of data configuration register groups can be configured to 5. When the number of bits included in a data configuration register is updated, such as 64 bits, the number of data configuration registers configured in each data configuration register group can also be updated adaptively. When the number of bits of the data source in the MSC data communication scenario changes, the composition structure of the data configuration register group can also be updated adaptively.

[0076] It can be seen that the above technical solution can break away from the restrictions of the bit height, shift number and shift direction of the MSC downlink frame data, and can configure each bit of the MSC downlink frame data on demand, which greatly improves the flexibility of the MSC downlink frame data configuration, thereby enhancing the flexibility advantage of the product, that is, the performance advantage.

[0077] Embodiment 3

[0078] Fig.10 1 is a flow chart of a data configuration method provided in Embodiment 3 of the present invention. This embodiment is applicable to the case where a data configuration device provided in any embodiment of the present invention performs a data configuration method. The MSC downlink frame data configuration device includes 4 data configuration register groups, each of which is used to configure a data segment in the MSC downlink frame data.

[0079] Correspondingly, such as Fig.10 As shown, the method includes the following operations:

[0080] S110. The MSC downlink frame data configuration device determines the bits of the original data to be sent.

[0081] The original data stream is composed of multiple bits of original data. The bit position of the original data to be sent in the original data stream to be sent is determined, and the position of the bit position of the original data to be sent in the original data stream is determined as the target sending position. For example, the data at the 0th bit position in the original data stream can be selected, and the bit position of the original data to be sent is at position 0 in the original data stream, and the target sending position is 0. The data at the 3rd bit position in the original data stream can be selected, and the bit position of the original data to be sent is at position 3 in the original data stream, and the target sending position is 3.

[0082] S120, configure the data configuration register corresponding to the data segment, and select the corresponding SEL bit number.

[0083] Select the corresponding data configuration register group and the data configuration register in the data configuration register group as needed, and filter the target SEL bit from the selected data configuration register, and configure the value of the target SEL bit as the target sending position. For example, you can select SEL0 of SRHMUX0 in the SRH segment data configuration register group as the target SEL bit, and configure the data of SEL0 of SRHMUX0 in the SRH segment data configuration register group to 0x3, which means that the data on the 3rd bit in the original data stream is sent through the data of the 0th bit in the SRH data segment.

[0084] S130, configure the data configuration register of the corresponding data segment, and configure the corresponding SELEN bit data to enable the corresponding SEL bit data.

[0085] S140. According to the current corresponding enable SEL bit data, hardware triggers the MSC to send downlink frame data, and sends the original data of the corresponding bit to form the target MSC downlink frame data.

[0086] Each group of bit configuration bits in the data configuration register can be configured to obtain data from which bit in the original data stream. For example, when the data value of the 6 bits of SEL12 of the SRH data configuration register 3 in the SRH segment data configuration register group is configured to 0x3, it means that the data of the 11th bit of the SRH segment in the MSC downlink frame data is the data on the 3rd bit in the original data stream; assuming that the SEL2EN bit in the SRLMUX0 is configured to 0, it means that the 2nd bit data of the SRL segment of the MSC downlink frame data is not enabled, and the hardware can automatically splice the enabled bits into the target MSC downlink frame data to be sent.

[0087] The so-called hardware automatically splicing the enabled bits into the target MSC downlink frame data to be sent can be understood as the hardware will detect whether the SEL bit is enabled bit by bit from low to high in the data segment. If it is enabled, it will be used as the data bit of the data segment of the downlink frame. If it is not enabled, the SEL bit will be skipped until the next enabled SEL bit is found, and then the enabled SEL bit data will be spliced ​​to the higher data bit of the data segment of the downlink frame.

[0088] Optionally, each of the data configuration register groups includes 4 data configuration registers; wherein:

[0089] Each of the data configuration register groups is used to configure 16 downlink frame data bits of the data segment accordingly;

[0090] Each of the data configuration registers includes 32 bits, which respectively correspond to the 4 downlink frame data bits of the data segment.

[0091] Optionally, each downlink frame data bit is configured with 8 bits, where:

[0092] 6 bits, used to control the downlink frame data bits;

[0093] 2 bits, used to enable configuration of the downlink frame data bits.

[0094] Optionally, the downlink frame data bit enable configuration adopts a redundancy mechanism.

[0095] The embodiment of the present invention determines the bit positions of the original data to be sent through an MSC downlink frame data configuration device, configures the data configuration register of the corresponding data segment, selects the corresponding SEL bit data, configures the corresponding SELEN bit data, enables the corresponding SEL bit data, thereby hardware triggers the MSC downlink frame data transmission according to the current corresponding enabled SEL bit data, and transmits the original data of the corresponding bit position to form the target MSC downlink frame data, solves the problem of poor flexibility in the existing MSC downlink frame data configuration method for generating MSC downlink frame data according to the bit shift number configuration from low to high, and can improve the flexibility of MSC downlink frame data configuration.

[0096] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information are in compliance with the relevant laws and regulations and do not violate public order and good morals.

[0097] It should be noted that any arrangement and combination of the technical features in the above embodiments also falls within the protection scope of the present invention.

[0098] Embodiment 4

[0099] Fig.11 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0100] The electronic device 10 includes a data configuration device (not shown in the figure) according to any embodiment of the present invention, such as Fig.11As shown, the electronic device 10 also includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0101] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0102] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the MSC downlink frame data configuration method.

[0103] Optionally, the MSC downlink frame data configuration method is applied to the MSC downlink frame data configuration device described in any embodiment of the present invention, the MSC downlink frame data configuration device includes 4 data configuration register groups, each of the data configuration register groups is used to configure a data segment in the MSC downlink frame data; the method includes:

[0104] The MSC downlink frame data configuration device determines the bit positions of the original data to be sent;

[0105] Configure the data configuration register corresponding to the data segment and select the corresponding SEL bit data;

[0106] Configure the data configuration register of the corresponding data segment, and configure the corresponding SELEN bit data to enable the corresponding SEL bit data;

[0107] According to the current corresponding enable SEL bit data, the hardware triggers the MSC to send the downlink frame data, and sends the original data of the corresponding bit to form the target MSC downlink frame data.

[0108] In some embodiments, the MSC downlink frame data configuration method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the MSC downlink frame data configuration method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to execute the MSC downlink frame data configuration method in any other appropriate manner (e.g., by means of firmware).

[0109] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0110] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0111] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0112] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0113] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0114] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0115] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0116] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A MSC downlink frame data configuration device, characterized in that: It includes 4 data configuration register groups, each of which is used to configure a data segment in the MSC downlink frame data; The data configuration register group is used to configure each bit of the target data segment in the MSC downlink frame data bit by bit as required to obtain the target MSC downlink frame data.

2. The device according to claim 1, characterized in that Each of the data configuration register groups includes 4 data configuration registers; wherein: Each of the data configuration register groups is used to configure 16 downlink frame data bits of the data segment accordingly; Each of the data configuration registers includes 32 bits, which respectively correspond to the 4 downlink frame data bits of the data segment.

3. The device according to claim 2, characterized in that Each downlink frame data bit is configured with 8 bits, where: 6 bits, used to control the downlink frame data bits; 2 bits, used to enable configuration of the downlink frame data bits.

4. The device according to claim 3, characterized in that The device is used for: Determining a target data configuration register group for configuring the target data segment from each of the data configuration register groups; Determining a target data configuration register from the target data configuration register group; Configure the target data configuration register and select the corresponding SEL bit data; The target data configuration register is configured, the corresponding SELEN bit data is configured, and the corresponding SEL bit data is enabled.

5. The device according to claim 4, characterized in that The device is used for: According to the current corresponding enable SEL bit data, the hardware triggers the MSC to send the downlink frame data, and sends the original data of the corresponding bit to form the target MSC downlink frame data.

6. The device according to any one of claims 3 to 5, characterized in that: The downlink frame data bit enable configuration adopts a redundancy mechanism.

7. A method for configuring MSC downlink frame data, characterized in that: Applicable to the MSC downlink frame data configuration device of any one of claims 1-6, the MSC downlink frame data configuration device comprises 4 data configuration register groups, each of the data configuration register groups is used to configure a data segment in the MSC downlink frame data; the method comprises: The MSC downlink frame data configuration device determines the bit position of the original data to be sent; Configure the data configuration register corresponding to the data segment and select the corresponding SEL bit data; Configure the data configuration register of the corresponding data segment, and configure the corresponding SELEN bit data to enable the corresponding SEL bit data; According to the current corresponding enable SEL bit data, the hardware triggers the MSC to send the downlink frame data, and sends the original data of the corresponding bit position to form the target MSC downlink frame data.

8. An electronic device, characterized in that: The electronic device comprises the MSC downlink frame data configuration device according to any one of claims 1 to 6, and the electronic device further comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the MSC downlink frame data configuration method according to claim 7.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the MSC downlink frame data configuration method according to claim 7 when executed.

10. A computer program product comprising a computer program / instructions, wherein: The computer program / instructions, when executed by a processor, implement the MSC downlink frame data configuration method of claim 7.

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