PCIe switching node INT interrupt processing method and system

Abstract

The invention relates to the technical field of computer networks, in particular to a PCIe switching node INT interrupt processing method and system, interrupt signals from all port controllers in a PCIe switching node are monitored, partition division is carried out through environment configuration, port INT interrupt message vectors are determined according to an INT interrupt message vector mapping rule, and the INT interrupt message vectors are sent to the PCIe switching node. The INT interrupt message vector mapping rule is used for determining a second port INT interrupt message type according to a port device number and a first port INT interrupt message type; redirecting the port INT interrupt message vector to a corresponding port to obtain the port INT interrupt message vector representation of each environment configuration partition; and combining the port INT interrupt message vector representations of the environment configuration partitions, obtaining target equipment according to the combined port INT interrupt message vector representations, and sending an INT information message to the target equipment, so that the target equipment executes an interrupt program. According to the invention, the PCIe switching node has the capability of processing the INT interrupt message.

Description

Technical Field

[0001] The present invention relates to the technical field of computer networks, and in particular to a PCIe switch node INT interrupt processing method and system. Background Art

[0002] With the rapid development of computer technology, the number of servers and storage devices in data centers and cloud computing environments is increasing, and PCIe switches are widely used in these environments. PCIe switches can achieve high-speed, high-density internal interconnection to meet the growing performance requirements. Interrupt processing is an important aspect of PCIe device performance optimization. Efficient interrupt processing can significantly reduce CPU overhead, improve data processing speed and system response. The prior art provides some PCIe endpoint device interrupt processing methods. However, these methods cannot be applied to switching nodes. PCIe switching nodes need to aggregate INT interrupts reported by downstream devices and make corresponding conversions. At present, there is no public information to explain the processing flow of INT interrupts in PCIe switching node devices, and the interrupt processing scheme of endpoint devices cannot meet the interrupt processing requirements of node devices. Summary of the invention

[0003] To this end, the present invention provides a PCIe switch node INT interrupt processing method and system to solve the problem that the existing PCIe endpoint device interrupt processing solution cannot meet the node device interrupt processing requirements, so that the PCIe switch node has the ability to process INT interrupt messages.

[0004] According to the design scheme provided by the present invention, on the one hand, a PCIe switch node INT interrupt processing method is provided, comprising:

[0005] Monitor interrupt signals from all port controllers in the PCIe switch node, wherein the interrupt signals include an INT interrupt message vector sent by the port controller of the first port, a partition flag indicating an environment configuration partition to which the first port belongs, and a second port flag indicating that the second port belongs to the same environment configuration partition as the first port, wherein the INT interrupt message vector includes multiple types;

[0006] Divide the environment configuration partition to which the first port controller belongs according to the INT interrupt message vector and the partition flag, and determine the second port INT interrupt message vector according to the INT interrupt message vector mapping rule, wherein the INT interrupt message vector mapping rule is used to determine the second port INT interrupt message type according to the port device number and the first port INT interrupt message type;

[0007] Redirecting the second port INT interrupt message vector to the corresponding second port through a logic operation between the second port INT interrupt message vector and the second port flag, and obtaining the second port INT interrupt message vector representation of each environment configuration partition;

[0008] The second port INT interrupt message vector representations of each environment configuration partition are merged, and the target device is obtained according to the merged second port INT interrupt message vector representation, and an INT message message is sent to the target device to enable the target device to execute an interrupt program.

[0009] As the PCIe switch node INT interrupt processing method of the present invention, further, the port controller configuration type of the first port is an upstream port or a downstream port, the port controller configuration type of the second port is an upstream port or a downstream port, and the number of both the first port and the second port is n, where n is a positive integer.

[0010] As the PCIe switch node INT interrupt processing method of the present invention, further, the INT interrupt message vector includes four INT interrupt message vector types: INTA, INTB, INTC, and INTD.

[0011] As the PCIe switch node INT interrupt processing method of the present invention, further, the partition flag and the second port flag are composed of register signals or other storage device signals, and the partition flag and the second port flag are represented by a one-dimensional array, and the number of elements in the one-dimensional array is consistent with the number of partitions.

[0012] As the PCIe switch node INT interrupt processing method of the present invention, further, the environment configuration partition to which the first port controller belongs is divided according to the INT interrupt message vector and the partition flag, including:

[0013] The INT interrupt message vector and the partition flag are subjected to AND logic processing, and the environment configuration partition to which the first port controller belongs is determined according to the AND logic processing result.

[0014] As a PCIe switch node INT interrupt processing method of the present invention, further, redirecting the second port INT interrupt message vector to the corresponding second port through a logical operation between the second port INT interrupt message vector and the second port flag includes:

[0015] An AND logic operation is performed on the second port INT interrupt message vector and the second port flag to determine the second port number corresponding to the second port INT interrupt message vector according to the result of the AND logic operation.

[0016] As the PCIe switch node INT interrupt processing method of the present invention, further, the second port INT interrupt message vector representation of each environment configuration partition is merged and processed, including:

[0017] The second port INT interrupt message vector representations of each environment configuration partition are merged by performing bitwise AND logic operation, and the second port INT interrupt message vector representations of each INT interrupt message vector type are obtained according to the merged processing result.

[0018] On the other hand, the present invention also provides a PCIe switch node INT interrupt processing system, comprising: a signal monitoring module, a partition division module, a redirection module and a partition merging module, wherein:

[0019] A signal monitoring module, used to monitor interrupt signals from all port controllers in the PCIe switch node, wherein the interrupt signal includes an INT interrupt message vector sent by the port controller of the first port, a partition flag indicating an environment configuration partition to which the first port belongs, and a second port flag indicating that the second port belongs to the same environment configuration partition as the first port, wherein the INT interrupt message vector includes multiple types;

[0020] A partition division module, used for dividing the environment configuration partition to which the first port controller belongs according to the INT interrupt message vector and the partition flag, and determining the second port INT interrupt message vector according to the INT interrupt message vector mapping rule, wherein the INT interrupt message vector mapping rule is used for determining the second port INT interrupt message type according to the port device number and the first port INT interrupt message type;

[0021] A redirection module, used for redirecting the second port INT interrupt message vector to the corresponding second port through a logic operation between the second port INT interrupt message vector and the second port flag, and obtaining the second port INT interrupt message vector representation of each environment configuration partition;

[0022] The partition merging module is used to merge the second port INT interrupt message vector representations of each environment configuration partition, obtain the target device according to the merged second port INT interrupt message vector representation, and send an INT message to the target device so that the target device executes the interrupt program.

[0023] Beneficial effects of the present invention:

[0024] The present invention uses operations such as partition isolation and vector mapping. When a PCIe switch node receives an INT interrupt message through a downstream port, it can aggregate and map according to the requirements of the PCIe protocol, and control the corresponding upstream port to send an appropriate INT message, which complies with the provisions on INT interrupt processing in the PCIe protocol. Through combinational logic, efficient interrupt communication between devices is realized, with extremely low interrupt processing delay, improving system performance, and without limiting the port role, supporting flexible configuration of the port as DSP or USP, and supporting multi-partition operation, with strong flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 The figure is a schematic diagram of the PCIe switch node INT interrupt processing flow in the embodiment. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the present invention clearer and more understandable, the present invention is further described in detail below in conjunction with the accompanying drawings and technical solutions.

[0027] PCIE is compatible with most of the characteristics of the PCI bus, the difference is that it uses a serial differential bus instead of a parallel bus and implements protocol layering. The PCIE bus topology is mainly composed of three types of nodes: RC (Root Complex), SW (Switch) and EP (Endpoint). Each PCIE device is uniquely identified by the bus number and device number. In response to the INT interrupt processing requirements in the PCIe switch node device, an embodiment of the present invention provides a PCIe switch node INT interrupt processing method, comprising:

[0028] Monitor interrupt signals from all port controllers in the PCIe switch node, wherein the interrupt signals include an INT interrupt message vector sent by the port controller of the first port, a partition flag indicating an environment configuration partition to which the first port belongs, and a second port flag indicating that the second port belongs to the same environment configuration partition as the first port, wherein the INT interrupt message vector includes multiple types;

[0029] Divide the environment configuration partition to which the first port controller belongs according to the INT interrupt message vector and the partition flag, and determine the second port INT interrupt message vector according to the INT interrupt message vector mapping rule, wherein the INT interrupt message vector mapping rule is used to determine the second port INT interrupt message type according to the port device number and the first port INT interrupt message type;

[0030] Redirecting the second port INT interrupt message vector to the corresponding second port through a logic operation between the second port INT interrupt message vector and the second port flag, and obtaining the second port INT interrupt message vector representation of each environment configuration partition;

[0031] The second port INT interrupt message vector representations of each environment configuration partition are merged, and the target device is obtained according to the merged second port INT interrupt message vector representation, and an INT message message is sent to the target device to enable the target device to execute an interrupt program.

[0032] The port controller configuration type of the first port is an upstream port or a downstream port, the port controller configuration type of the second port is an upstream port or a downstream port, and the number of the first port and the second port is n, wherein n is a positive integer. The INT interrupt message vector includes four INT interrupt message vector types, namely, INTA, INTB, INTC, and INTD. The partition flag and the second port flag are composed of register signals or other storage device signals, and the partition flag and the second port flag are represented by a one-dimensional array, and the number of elements in the one-dimensional array is consistent with the number of partitions.

[0033] like Figure 1 As shown, the solid line is the INT interrupt processing module, and the dotted line part is the port controller. The dotted line part does not belong to the content of the present invention, but is only used to assist in describing the complete data flow. The input signal of the NT interrupt processing module includes three parts, interrupt receiving signals intA_input, intB_input, intC_input, intD_input, partition mark partition_mark and USP mark usp_mark, where the number of controllers is n and the number of partitions is m.

[0034] The interrupt reception signal comes from all port controllers in the switching node. Each controller can issue four types of interrupts, corresponding to the four vectors A, B, C, and D of the INT interrupt message. The width of each type of signal is 1 bit. There are n port controllers in total, so the bit width of intA_input is n, and the bit widths of intB_input, intC_input, and intD_input are also n. When the port controller is configured as DSP (DownSteam Port) and receives an INT interrupt message from a downstream device, it issues a corresponding INT interrupt message reception signal, which is transmitted to the INT interrupt processing module through int_input.

[0035] The partition mark partition_mark and the USP mark usp_mark come from registers or other storage devices, and both are one-dimensional arrays of m elements, where m is the number of partitions. The elements in the array are variables with a bit width of n, where n is the number of controllers.

[0036] The int_output on the right is the output signal of the INT interrupt message processing module, which is sent to all port controllers. When the port controller is configured as USP (UpSteam Port) and receives the INT interrupt message sending signal int_output, it sends an INT message to the upstream device.

[0037] The INT interrupt message has a vector attribute, and the vector may be one of A / B / C / D. The interrupt vector output by the interrupt processing module is not exactly the same as the input interrupt vector, but the vector of the INT interrupt message sent by the USP is determined based on the DSP sequence number that receives the INT interrupt message, the received INT interrupt message vector, and the mapping rules specified by the protocol. The specific mapping rules can be shown in Table 1:

[0038] Table 1 Interrupt vector mapping table

[0039]

[0040]

[0041] For example, if the DSP with sequence number 1 receives the interrupt message INTA, the corresponding USP should send the interrupt message INTB.

[0042] USP or DSP is not fixed to a specific port controller, and any port controller can be configured as USP or DSP. Therefore, any port controller may send an INT interrupt message receiving signal to the interrupt processing module, and the interrupt processing module needs to select an appropriate port controller to send an INT interrupt message sending signal.

[0043] The port controllers in different partitions are isolated from each other, and the interrupt signals are not interoperable. The INT interrupt message reception signal received by the DSP is only sent through the USP of this partition, and will not affect the port controllers of other partitions.

[0044] Depend on Figure 1 The interrupt processing flow shown in the figure mainly includes four steps: partition isolation, vector mapping, USP redirection, and partition merging. Among them, the first three steps of partition isolation, vector mapping, and USP redirection are performed within the partition, and the processing results of each partition are output after merging in the fourth step.

[0045] Partition isolation is accomplished by performing an AND operation on the interrupt message receiving signal intX_input[Y] and the partition flag. The partition flag identifies whether the port belongs to the current partition. If the message belongs to the partition, the partition flag is 1'b1, otherwise it is 1'b0.

[0046] For example, there are 12 ports in a node, partition 0 includes ports 0, 1, and 2, and partition 1 includes the remaining ports. Then the partition 0 mark of ports 0, 1, and 2 is 1'b1, and the partition 0 mark of other ports is 1'b0. The partition 1 mark of ports 0, 1, and 2 is 1'b0, and the partition 1 mark of other ports is 1'b1.

[0047] The code example is:

[0048] partition_mark[0]=12'b000000000111;

[0049] partition_mark[1]=12'b111111111000;

[0050] The partition flag is given by a two-dimensional binary sequence partition[n][m], where n is the number of controllers and m is the number of partitions. partition[X][Y] indicates whether controller X belongs to partition Y. If so, the value is 1'b1; if not, the value is 1'b0.

[0051] Among them, the vector mapping is the mapping of different vectors of different ports according to Table 1, and the four vectors A, B, C, and D correspond to the interrupt sources of the USP respectively.

[0052] For example, the A vector interrupt of USP may only come from INTA of ports 0, 4, 8..., INTD of ports 1, 5, 9..., INTC of ports 2, 6, 10..., and INTB of ports 3, 7, 11... By performing logical OR processing on the above interrupt sources, the INTA interrupt sending signal of USP is obtained.

[0053] Code example:

[0054] intA_remap={intA_info[0]|intA_info[4]|intD_info[1]|intD_info[5]|intC_info[2]|

[0055] intC_info[6]|intB_info[3]|intB_info[7]|…}

[0056] Among them, when redirecting USP, the USP interrupt sending signal obtained according to the above-mentioned vector mapping needs to be redirected to the USP port. The redirection operation is completed by performing an AND operation with the USP flag. The USP flag identifies whether the port is the USP of the current partition. If the port is the USP of the partition, the partition flag is 1'b1, otherwise it is 1'b0.

[0057] For example, there are 12 ports in the node, and partition 0 includes ports 0, 1, and 2, of which the USP is port 0; partition 1 includes the remaining ports, and the USP of partition 1 is port 5. Then the partition 0 USP flag of port 0 is 1'b1, the partition 1 USP flag of port 5 is 1'b1, and the partition 0 USP flags and partition 1 USP flags of other ports are both 1'b0.

[0058] Code example:

[0059] usp_mark[0]=12'b000_0000_0001;

[0060] usp_mark[1]=12'b000_0010_0000

[0061] Partition merging is done by performing a bitwise AND operation on the processing results of all partitions in the first three steps and then outputting them.

[0062] Code example:

[0063] intA_output=intA_sd[0]&intA_sd[1];

[0064] intB_output=intB_sd[0]&intB_sd[1]

[0065] Further, based on the above method, an embodiment of the present invention also provides a PCIe switch node INT interrupt processing system, comprising: a signal monitoring module, a partition division module, a redirection module and a partition merging module, wherein:

[0066] A signal monitoring module, used to monitor interrupt signals from all port controllers in the PCIe switch node, wherein the interrupt signal includes an INT interrupt message vector sent by the port controller of the first port, a partition flag indicating an environment configuration partition to which the first port belongs, and a second port flag indicating that the second port belongs to the same environment configuration partition as the first port, wherein the INT interrupt message vector includes multiple types;

[0067] A partition division module, used for dividing the environment configuration partition to which the first port controller belongs according to the INT interrupt message vector and the partition flag, and determining the second port INT interrupt message vector according to the INT interrupt message vector mapping rule, wherein the INT interrupt message vector mapping rule is used for determining the second port INT interrupt message type according to the port device number and the first port INT interrupt message type;

[0068] A redirection module, used for redirecting the second port INT interrupt message vector to the corresponding second port through a logic operation between the second port INT interrupt message vector and the second port flag, and obtaining the second port INT interrupt message vector representation of each environment configuration partition;

[0069] The partition merging module is used to merge the second port INT interrupt message vector representations of each environment configuration partition, obtain the target device according to the merged second port INT interrupt message vector representation, and send an INT message to the target device so that the target device executes the interrupt program.

[0070] To verify the effectiveness of this solution, the following is a further explanation based on a specific case:

[0071] 1. Environment configuration: The node contains 12 ports, numbered 0-11. It is divided into two partitions, partition 0 and partition 1. Partition 0 contains ports 0, 1, and 2, port 0 is USP, and the rest are DSPs; partition 1 contains ports 3, 4, ... 11, port 5 is USP, and the rest are DSPs.

[0072] The interrupt receiving signals input from 12 ports of the INT interrupt processing module are defined as four binary variables intA_input, intB_input, intC_input, intD_input with a bit width of 12, corresponding to four vectors A, B, C, and D. The 12 bits of each variable correspond to 12 ports.

[0073] According to the partition information in the environment configuration, the partition flags of partitions 0 and 1 are:

[0074] partition_mark[0]=12'b000000000111;

[0075] partition_mark[1]=12'b111111111000;

[0076] The interrupt signal after partition isolation is intX_info[Y], where X is the interrupt vector and Y is the partition number. There are a total of 8 signal variables corresponding to the four vectors of the two partitions, and each variable has a bit width of 12:

[0077] intA_info[0]=intA_input&partition_mark[0];

[0078] intB_info[0]=intB_input&partition_mark[0];

[0079] intC_info[0]=intC_input&partition_mark[0];

[0080] intD_info[0]=intD_input&partition_mark[0];

[0081] intA_info[1]=intA_input&partition_mark[1];

[0082] intB_info[1]=intB_input&partition_mark[1];

[0083] intC_info[1]=intC_input&partition_mark[1];

[0084] intD_info[1]=intD_input&partition_mark[1];

[0085] The signal after vector mapping is intX_remap[Y], where X is the interrupt vector and Y is the partition number. Corresponding to the four vectors of the two partitions, there are a total of 8 signal variables, each of which is a single bit:

[0086] intA_remap[0]={intA_info[0][0]|intA_info[0][4]|intA_info[0][8]|intD_info[0][1]|intD_info[0][5]|intD_info[ 0][9]|intC_info[0][2]|intC_info[0][6]|intC_info[0]

[10] |intB_info[0][3]|intB_info[0][7]|intB_info[0]

[11] };

[0087] intB_remap[0]={intB_info[0][0]|intB_info[0][4]|intB_info[0][8]|intA_info[0][1]|intA_info[0][5]|intA_info[ 0][9]|intD_info[0][2]|intD_info[0][6]|intD_info[0]

[10] |intC_info[0][3]|intC_info[0][7]|intC_info[0]

[11] };

[0088] intC_remap[0]={intC_info[0][0]|intC_info[0][4]|intC_info[0][8]|intB_info[0][1]|intB_info[0][5]|intB_info[0][9]|intA_info[0][2]|intA_info[0][6]|intA_info[0]

[10] |intD_info[0][3]|intD_info[0][7]|intD_info[0]

[11] };

[0089] intD_remap[0]={intD_info[0][0]|intD_info[0][4]|intD_info[0][8]|intC_info[0][1]|intC_info[0][5]|intC_info[0][9]|intB_info[0][2]|intB_info[0][6]|intB_info[0]

[10] |intA_info[0][3]|intA_info[0][7]|intA_info[0]

[11] };

[0090] intA_remap[1]={intA_info[1][0]|intA_info[1][4]|intA_info[1][8]|intD_info[1][1]|intD_info[1][5]|intD_info[1][9]|intC_info[1][2]|intC_info[1][6]|intC_info[1]

[10] |intB_info[1][3]|intB_info[1][7]|intB_info[1]

[11] };

[0091] intB_remap[1]={intB_info[1][0]|intB_info[1][4]|intB_info[1][8]|intA_info[1][1]|intA_info[1][5]|intA_info[1][9]|intD_info[1][2]|intD_info[1][6]|intD_info[1]

[10] |intC_info[1][3]|intC_info[1][7]|intC_info[1]

[11] };

[0092] intC_remap[1]={intC_info[1][0]|intC_info[1][4]|intC_info[1][8]|intB_info[1][1]|intB_info[1][5]|intB_info[ 1][9]|intA_info[1][2]|intA_info[1][6]|intA_info[1]

[10] |intD_info[1][3]|intD_info[1][7]|intD_info[1]

[11] };

[0093] intD_remap[1]={intD_info[1][0]|intD_info[1][4]|intD_info[1][8]|intC_info[1][1]|intC_info[1][5]|intC_info[ 1][9]|intB_info[1][2]|intB_info[1][6]|intB_info[1]

[10] |intA_info[1][3]|intA_info[1][7]|intA_info[1]

[11] };

[0094] Among them, intA_info[0][4] represents the 4th bit of the intA_info[0] variable (intA_info[0] is a variable with a bit width of 12).

[0095] According to the environment configuration, port 0 and port 5 are the USPs of partition 0 and partition 1 respectively, that is, the USP flags are:

[0096] usp_mark[0]=12'b00000000001;

[0097] usp_mark[1]=12'b00000100000;

[0098] The signal after USP redirection is defined as intX_sd[Y], where X is the interrupt vector and Y is the partition number. There are a total of 8 signal variables corresponding to the four vectors of the two partitions, and each variable has a bit width of 12:

[0099] intA_sd[0]={12{intA_remap[0]}}&usp_mark[0];

[0100] intB_sd[0]={12{intB_remap[0]}}&usp_mark[0];

[0101] intC_sd[0]={12{intC_remap[0]}}&usp_mark[0];

[0102] intD_sd[0]={12{intD_remap[0]}}&usp_mark[0];

[0103] intA_sd[1]={12{intA_remap[1]}}&usp_mark[1];

[0104] intB_sd[1]={12{intB_remap[1]}}&usp_mark[1];

[0105] intC_sd[1]={12{intC_remap[1]}}&usp_mark[1];

[0106] intD_sd[1]={12{intD_remap[1]}}&usp_mark[1];

[0107] Here, {12{intA_remap[0]}} indicates that the single-bit signal intA_remap[0] is expanded to a 12-bit signal. For example, when intA_remap[0] is 1'b1, {12{intA_remap[0]}} is 12'b1111111111111.

[0108] The signal output by the INT interrupt processing module is defined as intX_sd, where X is the interrupt vector, corresponding to four vectors. Each variable has a bit width of 12:

[0109] intA_output=intA_sd[0]&intA_sd[1];

[0110] intB_output=intB_sd[0]&intB_sd[1];

[0111] intC_output=intC_sd[0]&intC_sd[1];

[0112] intD_output=intD_sd[0]&intD_sd[1];

[0113] 2. Environment configuration: The node contains 12 ports, numbered 0-11. It is divided into 4 partitions, partitions 0, 1, 2, and 3. Partition 0 contains ports 0, 1, and 2, port 0 is USP, and the rest are DSPs; partition 1 contains ports 3, 4, and 5, port 3 is USP, and the rest are DSPs; partition 2 contains ports 6, 7, and 8, port 6 is USP, and the rest are DSPs; partition 3 contains ports 9, 10, and 11, port 9 is USP, and the rest are DSPs.

[0114] The interrupt receiving signals input from the 12 ports of the INT interrupt processing module are four binary variables with a bit width of 12, intA_input, intB_input, intC_input, and intD_input.

[0115] According to the partition information in the environment configuration, the partition flags of each partition are:

[0116] partition_mark[0]=12'b000000000111;

[0117] partition_mark[1]=12'b000000111000;

[0118] partition_mark[2]=12'b000111000000;

[0119] partition_mark[3]=12'b111000000000;

[0120] The interrupt signal after partition isolation is intX_info[Y], where X is the interrupt vector and Y is the partition number. Corresponding to the 4 vectors of the 4 partitions, there are a total of 16 signal variables, each with a bit width of 12:

[0121] intA_info[0]=intA_input&partition_mark[0];

[0122] intB_info[0]=intB_input&partition_mark[0];

[0123] intC_info[0]=intC_input&partition_mark[0];

[0124] intD_info[0]=intD_input&partition_mark[0];

[0125] intA_info[1]=intA_input&partition_mark[1];

[0126] intB_info[1]=intB_input&partition_mark[1];

[0127] intC_info[1]=intC_input&partition_mark[1];

[0128] intD_info[1]=intD_input&partition_mark[1];

[0129] intA_info[2]=intA_input&partition_mark[2];

[0130] intB_info[2]=intB_input&partition_mark[2];

[0131] intC_info[2]=intC_input&partition_mark[2];

[0132] intD_info[2]=intD_input&partition_mark[2];

[0133] intA_info[3]=intA_input&partition_mark[3];

[0134] intB_info[3]=intB_input&partition_mark[3];

[0135] intC_info[3]=intC_input&partition_mark[3];

[0136] intD_info[3]=intD_input&partition_mark[3];

[0137] The signal after vector mapping is intX_remap[Y], where X is the interrupt vector and Y is the partition number. Corresponding to the four vectors of the two partitions, there are a total of 8 signal variables, each of which is a single bit:

[0138] intA_remap[0]={intA_info[0][0]|intA_info[0][4]|intA_info[0][8]|intD_info[0][1]|intD_info[0][5]|intD_info[0][9]|intC_info[0][2]|intC_info[0][6]|intC_info[0]

[10] |intB_info[0][3]|intB_info[0][7]|intB_info[0]

[11] };

[0139] intB_remap[0]={intB_info[0][0]|intB_info[0][4]|intB_info[0][8]|intA_info[0][1]|intA_info[0][5]|intA_info[0][9]|intD_info[0][2]|intD_info[0][6]|intD_info[0]

[10] |intC_info[0][3]|intC_info[0][7]|intC_info[0]

[11] };

[0140] intC_remap[0]={intC_info[0][0]|intC_info[0][4]|intC_info[0][8]|intB_info[0][1]|intB_info[0][5]|intB_info[0][9]|intA_info[0][2]|intA_info[0][6]|intA_info[0]

[10] |intD_info[0][3]|intD_info[0][7]|intD_info[0]

[11] };

[0141] intD_remap[0]={intD_info[0][0]|intD_info[0][4]|intD_info[0][8]|intC_info[0][1]|intC_info[0][5]|intC_info[0][9]|intB_info[0][2]|intB_info[0][6]|intB_info[0]

[10] |intA_info[0][3]|intA_info[0][7]|intA_info[0]

[11] };

[0142] intA_remap[1]={intA_info[1][0]|intA_info[1][4]|intA_info[1][8]|intD_info[1][1]|intD_info[1][5]|intD_info[1][9]|intC_info[1][2]|intC_info[1][6]|intC_info[1]

[10] |intB_info[1][3]|intB_info[1][7]|intB_info[1]

[11] };

[0143] intB_remap[1]={intB_info[1][0]|intB_info[1][4]|intB_info[1][8]|intA_info[1][1]|intA_info[1][5]|intA_info[1][9]|intD_info[1][2]|intD_info[1][6]|intD_info[1]

[10] |intC_info[1][3]|intC_info[1][7]|intC_info[1]

[11] };

[0144] intC_remap[1]={intC_info[1][0]|intC_info[1][4]|intC_info[1][8]|intB_info[1][1]|intB_info[1][5]|intB_info[1][9]|intA_info[1][2]|intA_info[1][6]|intA_info[1]

[10] |intD_info[1][3]|intD_info[1][7]|intD_info[1]

[11] };

[0145] intD_remap[1]={intD_info[1][0]|intD_info[1][4]|intD_info[1][8]|intC_info[1][1]|intC_info[1][5]|intC_info[1][9]|intB_info[1][2]|intB_info[1][6]|intB_info[1]

[10] |intA_info[1][3]|intA_info[1][7]|intA_info[1]

[11] };

[0146] intA_remap[2]={intA_info[2][0]|intA_info[2][4]|intA_info[2][8]|intD_info[2][1]|intD_info[2][5]|intD_info[2][9]|intC_info[2][2]|intC_info[2][6]|intC_info[2]

[10] |intB_info[2][3]|intB_info[2][7]|intB_info[2]

[11] };

[0147] intB_remap[2]={intB_info[2][0]|intB_info[2][4]|intB_info[2][8]|intA_info[2][1]|intA_info[2][5]|intA_info[2][9]|intD_info[2][2]|intD_info[2][6]|intD_info[2]

[10] |intC_info[2][3]|intC_info[2][7]|intC_info[2]

[11] };

[0148] intC_remap[2]={intC_info[2][0]|intC_info[2][4]|intC_info[2][8]|intB_info[2][1]|intB_info[2][5]|intB_info[2][9]|intA_info[2][2]|intA_info[2][6]|intA_info[2]

[10] |intD_info[2][3]|intD_info[2][7]|intD_info[2]

[11] };

[0149] intD_remap[2]={intD_info[2][0]|intD_info[2][4]|intD_info[2][8]|intC_info[2][1]|intC_info[2][5]|intC_info[2][9]|intB_info[2][2]|intB_info[2][6]|intB_info[2]

[10] |intA_info[2][3]|intA_info[2][7]|intA_info[2]

[11] };

[0150] intA_remap[3]={intA_info[3][0]|intA_info[3][4]|intA_info[3][8]|intD_info[3][1]|intD_info[3][5]|intD_info[3][9]|intC_info[3][2]|intC_info[3][6]|intC_info[3]

[10] |intB_info[3][3]|intB_info[3][7]|intB_info[3]

[11] };

[0151] intB_remap[3]={intB_info[3][0]|intB_info[3][4]|intB_info[3][8]|intA_info[3][1]|intA_info[3][5]|intA_info[3][9]|intD_info[3][2]|intD_info[3][6]|intD_info[3]

[10] |intC_info[3][3]|intC_info[3][7]|intC_info[3]

[11] };

[0152] intC_remap[3]={intC_info[3][0]|intC_info[3][4]|intC_info[3][8]|intB_info[3][1]|intB_info[3][5]|intB_info[3][9]|intA_info[3][2]|intA_info[3][6]|intA_info[3]

[10] |intD_info[3][3]|intD_info[3][7]|intD_info[3]

[11] };

[0153] intD_remap[3]={intD_info[3][0]|intD_info[3][4]|intD_info[3][8]|intC_info[3][1]|intC_info[3][5]|intC_info[3][9]|intB_info[3][2]|intB_info[3][6]|intB_info[3]

[10] |intA_info[3][3]|intA_info[3][7]|intA_info[3]

[11] };

[0154] Among them, intA_info[0][4] represents the 4th bit of the intA_info[0] variable (intA_info[0] is a variable with a bit width of 12).

[0155] According to the environment configuration, ports 0, 3, 6, and 9 are the USPs of partitions 0, 1, 2, and 3 respectively, that is, the USP flags are:

[0156] usp_mark[0]=12'b00000000001;

[0157] usp_mark[1]=12'b00000001000;

[0158] usp_mark[2]=12'b00001000000;

[0159] usp_mark[3]=12'b00100000000;

[0160] The signal after USP redirection is defined as intX_sd[Y], where X is the interrupt vector and Y is the partition number. Corresponding to the 4 vectors of the 4 partitions, there are a total of 16 signal variables, each with a bit width of 12:

[0161] intA_sd[0]={12{intA_remap[0]}}&usp_mark[0];

[0162] intB_sd[0]={12{intB_remap[0]}}&usp_mark[0];

[0163] intC_sd[0]={12{intC_remap[0]}}&usp_mark[0];

[0164] intD_sd[0]={12{intD_remap[0]}}&usp_mark[0];

[0165] intA_sd[1]={12{intA_remap[1]}}&usp_mark[1];

[0166] intB_sd[1]={12{intB_remap[1]}}&usp_mark[1];

[0167] intC_sd[1]={12{intC_remap[1]}}&usp_mark[1];

[0168] intD_sd[1]={12{intD_remap[1]}}&usp_mark[1];

[0169] intA_sd[2]={12{intA_remap[2]}}&usp_mark[2];

[0170] intB_sd[2]={12{intB_remap[2]}}&usp_mark[2];

[0171] intC_sd[2]={12{intC_remap[2]}}&usp_mark[2];

[0172] intD_sd[2]={12{intD_remap[2]}}&usp_mark[2];

[0173] intA_sd[3]={12{intA_remap[3]}}&usp_mark[3];

[0174] intB_sd[3]={12{intB_remap[3]}}&usp_mark[3];

[0175] intC_sd[3]={12{intC_remap[3]}}&usp_mark[3];

[0176] intD_sd[3]={12{intD_remap[3]}}&usp_mark[3];

[0177] Here, {12{intA_remap[0]}} indicates that the single-bit signal intA_remap[0] is expanded to a 12-bit signal. For example, when intA_remap[0] is 1'b1, {12{intA_remap[0]}} is 12'b1111111111111.

[0178] The signal output by the INT interrupt processing module is defined as intX_sd, where X is the interrupt vector, corresponding to four vectors. Each variable has a bit width of 12:

[0179] intA_output=intA_sd[0]&intA_sd[1]&intA_sd[2]&intA_sd[3];

[0180] intB_output=intB_sd[0]&intB_sd[1]&intB_sd[2]&intB_sd[3];

[0181] intC_output=intC_sd[0]&intC_sd[1]&intC_sd[2]&intC_sd[3];

[0182] intD_output=intD_sd[0]&intD_sd[1]&intD_sd[2]&intD_sd[3];

[0183] The above case shows that when the PCIe switch node receives an INT interrupt message through the downstream port, the solution in this case can aggregate and map according to the PCIe protocol requirements, and control the corresponding upstream port to send an appropriate INT message, enabling the PCIe switch node to process INT interrupt messages, thereby speeding up data processing and system response.

[0184] Unless otherwise specifically stated, the relative steps, numerical expressions and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present invention.

[0185] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0186] The units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. A person of ordinary skill in the art may use different methods to implement the described functions for each specific application, but such implementation is not considered to be beyond the scope of the present invention.

[0187] Those skilled in the art will appreciate that all or part of the steps in the above method can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a disk or an optical disk. Optionally, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits, and accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or in the form of software function modules. The present invention is not limited to any specific form of combination of hardware and software.

[0188] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A PCIe switch node INT interrupt processing method, characterized in that: Include: Monitor interrupt signals from all port controllers in the PCIe switch node, wherein the interrupt signals include an INT interrupt message vector sent by the port controller of the first port, a partition flag indicating an environment configuration partition to which the first port belongs, and a second port flag indicating that the second port belongs to the same environment configuration partition as the first port, wherein the INT interrupt message vector includes multiple types; Divide the environment configuration partition to which the first port controller belongs according to the INT interrupt message vector and the partition flag, and determine the second port INT interrupt message vector according to the INT interrupt message vector mapping rule, wherein the INT interrupt message vector mapping rule is used to determine the second port INT interrupt message type according to the port device number and the first port INT interrupt message type; Redirecting the second port INT interrupt message vector to the corresponding second port through a logic operation between the second port INT interrupt message vector and the second port flag, and obtaining the second port INT interrupt message vector representation of each environment configuration partition; The second port INT interrupt message vector representations of each environment configuration partition are merged, and the target device is obtained according to the merged second port INT interrupt message vector representation, and an INT message message is sent to the target device to enable the target device to execute an interrupt program.

2. The PCIe switch node INT interrupt processing method according to claim 1, characterized in that: The port controller configuration type of the first port is an upstream port or a downstream port, the port controller configuration type of the second port is an upstream port or a downstream port, and the number of both the first port and the second port is n, where n is a positive integer.

3. The PCIe switch node INT interrupt processing method according to claim 1, characterized in that: The INT interrupt message vectors include four INT interrupt message vector types: INTA, INTB, INTC, and INTD.

4. The PCIe switch node INT interrupt processing method according to claim 1, characterized in that: The partition flag and the second port flag are composed of register signals or other storage device signals, and the partition flag and the second port flag are represented by a one-dimensional array, and the number of elements in the one-dimensional array is consistent with the number of partitions.

5. The PCIe switch node INT interrupt processing method according to claim 1, characterized in that: The environment configuration partition to which the first port controller belongs is divided according to the INT interrupt message vector and the partition flag, including: The INT interrupt message vector and the partition flag are subjected to AND logic processing, and the environment configuration partition to which the first port controller belongs is determined according to the AND logic processing result.

6. The PCIe switch node INT interrupt processing method according to claim 1, characterized in that: Redirecting the second port INT interrupt message vector to the corresponding second port through a logic operation between the second port INT interrupt message vector and the second port flag includes: An AND logic operation is performed on the second port INT interrupt message vector and the second port flag to determine the second port number corresponding to the second port INT interrupt message vector according to the result of the AND logic operation.

7. The PCIe switch node INT interrupt processing method according to claim 1, characterized in that: The second port INT interrupt message vector representation of each environment configuration partition is merged and processed, including: The second port INT interrupt message vector representations of each environment configuration partition are merged by performing bitwise AND logic operation, and the second port INT interrupt message vector representations of each INT interrupt message vector type are obtained according to the merged processing result.

8. A PCIe switch node INT interrupt processing system, characterized in that: It includes: signal monitoring module, partition division module, redirection module and partition merging module, among which, A signal monitoring module, used to monitor interrupt signals from all port controllers in the PCIe switch node, wherein the interrupt signal includes an INT interrupt message vector sent by the port controller of the first port, a partition flag indicating an environment configuration partition to which the first port belongs, and a second port flag indicating that the second port belongs to the same environment configuration partition as the first port, wherein the INT interrupt message vector includes multiple types; A partition division module, used for dividing the environment configuration partition to which the first port controller belongs according to the INT interrupt message vector and the partition flag, and determining the second port INT interrupt message vector according to the INT interrupt message vector mapping rule, wherein the INT interrupt message vector mapping rule is used for determining the second port INT interrupt message type according to the port device number and the first port INT interrupt message type; A redirection module, used for redirecting the second port INT interrupt message vector to the corresponding second port through a logic operation between the second port INT interrupt message vector and the second port flag, and obtaining the second port INT interrupt message vector representation of each environment configuration partition; The partition merging module is used to merge the second port INT interrupt message vector representations of each environment configuration partition, obtain the target device according to the merged second port INT interrupt message vector representation, and send an INT message to the target device so that the target device executes the interrupt program.

9. An electronic device, characterized in that: include: at least one processor, and a memory coupled to the at least one processor; The memory stores a computer program, and the computer program can be executed by the at least one processor to implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed, the method according to any one of claims 1 to 7 can be implemented.

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