Preparation method of PD-SOI device and PD-SOI device

Abstract

The invention provides a preparation method of a PD-SOI device and the PD-SOI device, and the method comprises the steps: bonding a prepared device wafer and a support wafer, thinning a silicon substrate on the bottom surface of the device wafer, forming a groove with a preset depth in the thinned silicon substrate, enabling the groove to penetrate through the silicon substrate and a part of a buried oxide layer, and enabling the buried oxide layer to penetrate through the silicon substrate and a part of the buried oxide layer; and finally, the buried oxide layer at the bottom of the groove and the surface layer of the top silicon layer are doped and thermally annealed, so that the doped surface layer of the top silicon layer is changed into a polycrystalline silicon structure, and the kink effect of the PD-SOI device is effectively inhibited. And the buried oxide layer is not etched through, and the distance between the surface layer of the top silicon layer and the gate polysilicon is greater than the first distance, so that the performance of the PD-SOI device is not influenced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing, and in particular to a preparation method of a PD-SOI device and a PD-SOI device. Background Art

[0002] PD-SOI (Partially Depleted Silicon-On-Insulator) devices are semiconductor devices made on SOI (Silicon-On-Insulator) wafers, and have the following characteristics: the thickness of the device depletion layer is less than the thickness of the top silicon layer. Since PD-SOI devices have excellent performance such as good device isolation, no latch-up effect, and small coupling effect, PD-SOI devices are widely used in RF, MEMS (Micro-Electro-Mechanical Systems) and other fields.

[0003] However, when PD-SOI devices are used in analog circuits, the kink effect of the PD-SOI devices will cause the drain-source current of the device to suddenly increase, which will affect the performance of the analog circuit. For example, in RF applications, the kink effect of PD-SOI devices will cause problems such as time delay, waveform distortion, and signal distortion in signal propagation. Therefore, in analog circuit application scenarios, how to suppress the kink effect while ensuring device performance has become a difficult problem.

[0004] Therefore, providing a method to effectively suppress the kink effect without affecting the performance of PD-SOI devices has become a technical problem that the industry urgently needs to solve. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for preparing a PD-SOI device and a PD-SOI device, which solves the problem of effectively suppressing the kink effect without affecting the performance of the PD-SOI device.

[0006] In order to solve the above technical problems, an embodiment of the present invention provides a method for preparing a PD-SOI device, the method comprising:

[0007] Providing an SOI wafer, the SOI wafer comprising a silicon substrate, a buried oxide layer and a top silicon layer stacked in sequence;

[0008] forming a device layer in the top silicon layer, wherein gate polysilicon is formed in the device layer;

[0009] providing a support wafer;

[0010] Bonding the surface of the device layer to the first surface of the support wafer;

[0011] After the bonding is completed, the thickness of the silicon substrate is reduced from the bottom surface of the silicon substrate to a first thickness;

[0012] Etching a groove of a preset depth on the bottom surface of the silicon substrate, wherein the groove penetrates the silicon substrate and a portion of the buried oxide layer, and the groove corresponds to the gate polysilicon;

[0013] doping the buried oxide layer at the bottom of the groove and the surface layer of the top silicon layer, wherein the surface layer of the top silicon layer is used to characterize the area where the top silicon layer contacts the buried oxide layer at the bottom of the groove, wherein the distance between the surface layer of the top silicon layer and the gate polysilicon is greater than a first distance;

[0014] Annealing the buried oxide layer at the bottom of the groove and the surface layer of the top silicon layer so that the doped surface layer of the top silicon layer becomes a polysilicon structure;

[0015] A metal interconnection layer is formed on the bottom surface of the silicon substrate.

[0016] Optionally, etching a groove of a preset depth on the bottom surface of the silicon substrate specifically includes:

[0017] Applying a photoresist on the bottom surface of the thinned silicon substrate, wherein the thickness of the photoresist is a second thickness;

[0018] Forming a patterned first mask layer on the photoresist, wherein the patterned first mask layer includes a window pattern of the groove and a barrier layer;

[0019] Using the patterned first mask layer as a mask, the silicon substrate and the buried oxide layer are etched in sequence until a groove of a preset depth is formed in the buried oxide layer in the groove area, wherein the second thickness is greater than or equal to the sum of the first thickness and the preset depth.

[0020] Optionally, the size of the groove is smaller than or equal to the corresponding size of the gate polysilicon.

[0021] Optionally, doping the buried oxide layer at the bottom of the groove and the surface layer of the top silicon layer specifically includes:

[0022] Using the patterned first mask layer as a mask, ion implantation is performed on the buried oxide layer in the groove and the surface layer of the top silicon layer, wherein the implantation depth of the ions into the buried oxide layer in the groove is greater than the remaining thickness of the etched buried oxide layer;

[0023] The first mask layer is removed.

[0024] Optionally, the implanted ions include at least any one or any combination of carbon ions, silicon ions, germanium ions, and tin ions.

[0025] Optionally, forming a device layer on the surface of the top silicon layer specifically includes:

[0026] forming a shallow trench isolation structure in the top silicon layer, wherein a bottom of the shallow trench isolation structure contacts the buried oxide layer;

[0027] forming the gate polysilicon on the surface of the top silicon layer;

[0028] forming a source region and a drain region in the top silicon layer between the shallow trench isolation structures, wherein the source region and the drain region are located on both sides of the gate polysilicon;

[0029] A first dielectric layer is deposited on the top silicon layer, and first contact holes are formed on the source region, the drain region and the surface of the gate polysilicon. A first end of the first contact hole is connected to a first metal layer.

[0030] Optionally, in addition to forming the first contact hole in the source region, the drain region and the gate polysilicon surface, an external connection contact hole is also formed in the shallow trench isolation structure, and the external connection contact hole is formed in the shallow trench isolation structure, and one end is connected to any one of the first metal layers, and the other end passes through the buried oxide layer and is connected to the silicon substrate.

[0031] Optionally, forming the metal interconnect layer on the bottom surface of the silicon substrate specifically further includes:

[0032] Depositing a second dielectric layer in the groove, wherein the second dielectric layer covers the silicon substrate, and forming a second metal layer connected to the external connection contact hole in the second dielectric layer;

[0033] Dielectric layers are stacked in sequence on the second dielectric layer, metal through holes and metal layers are formed in the dielectric layers, and the metal layers are connected to the second metal layer through the metal through holes.

[0034] Optionally, the materials of the first dielectric layer, the second dielectric layer and the dielectric layer are any one of Low-K material / High-K material / TEOS / PEOX / SIN or a combination thereof.

[0035] The embodiment of the present invention further provides a PD-SOI device, which is manufactured by the manufacturing method of the PD-SOI device, and the device comprises:

[0036] Supporting wafers;

[0037] A device layer, the device layer includes a gate, a source / drain region and a first contact hole, and is located on the first surface of the supporting wafer, and the first surface of the device layer is bonded to the first surface of the supporting wafer;

[0038] A top silicon layer, wherein the top silicon layer is located on the second surface of the device layer, the first surface of the top silicon layer and the second surface of the device layer are in contact with each other, and a surface layer of the second surface of the top silicon layer corresponding to the gate in the device layer is a polysilicon structure;

[0039] A buried oxide layer, wherein the buried oxide layer is located on the second surface of the top silicon layer, the first surface of the buried oxide layer and the second surface of the top silicon layer are in contact with each other, the second surface of the buried oxide layer has a groove, the groove is filled with a dielectric layer, and the dielectric layer covers the silicon substrate, and the groove corresponds to the surface layer of the top silicon layer of the polysilicon structure from top to bottom;

[0040] The metal interconnection layer is arranged in a direction away from the surface of the dielectric layer.

[0041] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0042] In the preparation method of the PD-SOI device of the technical solution of the present invention, the prepared device wafer and the support wafer are first bonded, and then the silicon substrate at the bottom of the device wafer is thinned and a groove of a preset depth is formed on the thinned silicon substrate, the groove penetrates the silicon substrate and part of the buried oxide layer, and finally the buried oxide layer at the bottom of the groove and the surface layer of the top silicon layer are doped and thermally annealed, so that the surface layer of the doped top silicon layer becomes a polysilicon structure, reducing the carrier lifetime to suppress the floating body effect, thereby suppressing the kink effect of the PD-SOI device. Because the distance between the surface layer of the doped top silicon layer and the gate polysilicon is greater than the first distance, the polysilicon structure of the surface layer does not affect the top silicon layer close to the device layer, and thus does not affect the performance of the device layer; and because a certain thickness of the buried oxide layer is retained, the RF performance of the overall device is not affected. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 The process of the method for preparing the PD-SOI device provided by the embodiment of the present invention is Figure 1 ;

[0044] Figures 2 to 4 The following are simplified cross-sectional diagrams corresponding to different preparation stages of the preparation method of the PD-SOI device provided in the embodiment of the present invention. Figure 1 ;

[0045] Figure 5 The process of the method for preparing the PD-SOI device provided by the embodiment of the present invention is Figure 2 ;

[0046] Figures 6 to 15 The simplified cross-sectional structures of the PD-SOI device preparation method provided by the embodiment of the present invention at different preparation stages are shown in FIG. Figure 2 ;

[0047] Fig.16 The process of the method for preparing the PD-SOI device provided by the embodiment of the present invention is Figure 3 ;

[0048] Figures 17 to 22 The simplified cross-sectional structures of the PD-SOI device preparation method provided by the embodiment of the present invention at different preparation stages are shown in FIG. Figure 3 . DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the embodiments in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present invention. The terms "first", "second", "third", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0050] As described in the background art, when suppressing the kink effect of PD-SOI devices, the prior art either has a limited degree of suppressing the kink effect or affects the performance of the PD-SOI devices. The problems existing in the prior art will be described in detail below.

[0051] The existing solution is to suppress the kink effect of the PD-SOI device by adjusting the ion doping concentration of the source doping region and the drain doping region. However, the problem with this solution is that the effect of suppressing the kink effect is limited by the performance of the device, so the effect of suppressing the kink effect is limited.

[0052] In view of this, an embodiment of the present invention proposes a new method for preparing a PD-SOI device, so as to effectively suppress the kink effect of the PD-SOI device without affecting the performance of the PD-SOI device.

[0053] The method for preparing a PD-SOI device provided in an embodiment of the present invention comprises the following steps:

[0054] Providing an SOI wafer, the SOI wafer comprising a silicon substrate, a buried oxide layer and a top silicon layer stacked in sequence;

[0055] forming a device layer in the top silicon layer, wherein gate polysilicon is formed in the device layer;

[0056] providing a support wafer;

[0057] Bonding the surface of the device layer to the first surface of the support wafer;

[0058] After the bonding is completed, the thickness of the silicon substrate is reduced from the bottom surface of the silicon substrate to a first thickness;

[0059] Etching a groove of a preset depth on the bottom surface of the silicon substrate, wherein the groove penetrates the silicon substrate and a portion of the buried oxide layer, and the groove corresponds to the gate polysilicon;

[0060] doping the buried oxide layer at the bottom of the groove and the surface layer of the top silicon layer, wherein the surface layer of the top silicon layer is used to characterize the area where the top silicon layer contacts the buried oxide layer at the bottom of the groove, wherein the distance between the surface layer of the top silicon layer and the gate polysilicon is greater than a first distance;

[0061] Annealing the buried oxide layer at the bottom of the groove and the surface layer of the top silicon layer so that the doped surface layer of the top silicon layer becomes a polysilicon structure;

[0062] A metal interconnection layer is formed on the bottom surface of the silicon substrate.

[0063] Through the above technical means, the embodiment of the present invention can effectively suppress the kink effect of the PD-SOI device without affecting the performance of the PD-SOI device. The specific principle is as follows:

[0064] The present invention first bonds the prepared device wafer and the support wafer, then thins the silicon substrate at the bottom of the device wafer and forms a groove of a preset depth on the thinned silicon substrate, wherein the groove penetrates the silicon substrate and part of the buried oxide layer, and finally the buried oxide layer at the bottom of the groove and the surface of the top silicon layer are doped and thermally annealed to change the doped surface of the top silicon layer into a polysilicon structure, thereby greatly reducing the carrier lifetime in the contact surface layer. It can be seen from the above-mentioned prior art that the kink effect of the PD-SOI device is positively correlated with the carrier concentration in the contact surface layer, thereby effectively suppressing the kink effect of the PD-SOI device.

[0065] Furthermore, because the distance between the surface layer of the top silicon layer and the gate polysilicon is greater than the first distance, the first distance is used to ensure that the doped surface layer of the top silicon layer does not affect the channel of the gate polysilicon, thereby not affecting the performance of the PD-SOI device. At the same time, because the buried oxide layer is not etched through, it does not affect the RF performance of the PD-SOI device.

[0066] Therefore, the embodiment of the present invention performs small thickness and small range doping on the top silicon layer in contact with the buried oxide layer from the back side of the device wafer, thereby effectively suppressing the kink effect of the PD-SOI device without affecting the performance of the PD-SOI device.

[0067] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0068] Figure 1 The process of the method for preparing the PD-SOI device provided by the embodiment of the present invention is Figure 1 .Apart from Figure 5 and Fig.16 outside, Figures 2 to 21 They are simplified cross-sectional schematic diagrams corresponding to different preparation stages of the preparation method of the PD-SOI device provided in the embodiments of the present invention.

[0069] Please refer to Figures 1 to 21 The specific steps of the method for preparing the PD-SOI device provided in the embodiment of the present invention include the following:

[0070] S1: providing an SOI substrate; the SOI substrate comprises a silicon substrate, a buried oxide layer and a top silicon layer stacked in sequence.

[0071] The SOI substrate can directly use an existing SOI wafer, or can be prepared from a silicon substrate. The preparation of the SOI substrate from a silicon substrate specifically includes the following steps:

[0072] S11: Provide a silicon substrate, such as Figure 2 shown.

[0073] S12: Depositing the buried oxide layer 102 on the first surface of the silicon substrate 101, such as Figure 3 The material of the buried oxide layer 102 may include silicon dioxide, or other materials with insulating properties, which are not limited here.

[0074] S13: Depositing the top silicon layer 103 on the surface of the buried oxide layer 102, such as Figure 4 shown.

[0075] S2: forming a device layer in the top silicon layer to complete the preparation of the device wafer, wherein the device layer includes gate polysilicon.

[0076] The specific preparation process in step S2 is described in detail below:

[0077] in, Figure 5 This is a flow chart of a method for preparing a PD-SOI device provided in an embodiment of the present invention - 1.

[0078] Please refer to Figure 5 The specific steps of forming a device layer on the surface of the top silicon layer in S2 include the following:

[0079] S21: forming a shallow trench isolation structure in the top silicon layer at the same time, wherein the shallow trench isolation structure is in contact with the buried oxide layer, such as Figure 6 shown.

[0080] S22: forming the gate polysilicon 106 on the surface of the top silicon layer 103, such as Figure 7 Specifically, before forming the gate polysilicon 106, ion implantation is also performed in the top silicon layer between the shallow trench isolation structures to form a well region (not shown in the figure).

[0081] S23: forming a source region and a drain region in the top silicon layer 103, wherein the source region and the drain region are located on both sides of the gate polysilicon. Figure 8 shown.

[0082] S24: Depositing the first dielectric layer 109, such as Fig. 9 The material of the first dielectric layer 109 includes any one or any combination of Low-K material, High-K material, oxide, borophosphosilicate glass, and tetraethoxysilane, which is not limited here.

[0083] Before performing step S24, the method further includes: forming a conductive contact layer on the source region, the drain region and the gate, wherein the conductive contact layer is a metal silicide. Specifically, the metal silicide may be cobalt silicide or titanium silicide.

[0084] S25: forming a first contact hole 111 on the surfaces of the source region 107, the gate polysilicon 106 and the drain region 108 at the same time. Fig.10As shown, the first contact hole 111 is connected to the source region 107, the drain region 108 and the conductive contact layer of the gate polysilicon 106. It should be supplemented that, in addition to forming the first contact hole 111 in step S27, an external connection contact hole 112 may also be formed, and the external connection contact hole 112 passes through the buried oxide layer 102 through the first shallow trench isolation structure 104 or the second shallow trench isolation structure 105 and is connected to the silicon substrate 101.

[0085] S26: forming a first metal layer 114 on each of the first contact holes 111, such as Fig.11 As shown. The first contact holes 111 on the surfaces of the source region 107, the gate polysilicon 106 and the drain region 108 are physically connected through the first metal layer 114 and the external connection contact hole 112, so that the source region 107, the gate polysilicon 106 and the drain region 108 are externally connected. The first metal layer 114 includes copper metal.

[0086] It should be noted that since the first contact hole 111 on the surface of each of the gate polysilicon 106 and the drain region 108 is physically connected to the external connection contact hole 112 through the first metal layer 114 , it is inconvenient to show it in the cross-sectional schematic diagram.

[0087] S27: Depositing a third dielectric layer 115 to complete the preparation of the device wafer, such as Fig.12 The material of the third dielectric layer 115 may be the same as that of the first dielectric layer 109, which will not be described in detail herein.

[0088] The specific steps of etching the first region of the top silicon layer to form a first shallow trench isolation structure and etching the second region of the top silicon layer to form a second shallow trench isolation structure in step S21 include the following:

[0089] S211: forming a patterned first mask layer on the surface of the top silicon layer, the patterned first mask layer comprising a second window area, a third window area and a blocking area; the second window area corresponds to the first area, and the third window area corresponds to the second area.

[0090] S212: Using the patterned first mask layer as a mask, the top silicon layer in the second window area and the third window area is etched simultaneously to form a first shallow trench and a second shallow trench. The specific etching method may include wet etching or dry etching. Both wet etching and dry etching are conventional technical means in the art and will not be described in detail here.

[0091] S213: depositing a silicon dioxide layer, wherein the silicon dioxide fills the first shallow trench and the second shallow trench and covers the surface of the top silicon layer.

[0092] S214: performing chemical mechanical polishing on the silicon dioxide layer to eliminate the silicon dioxide layer on the surface of the top silicon layer and make the silicon dioxide layer slightly higher than the first shallow trench and the second shallow trench.

[0093] The specific steps of forming the gate polysilicon on the surface of the top silicon layer in step S22 include the following:

[0094] S221: depositing a polysilicon layer on the surface of the top silicon layer.

[0095] S222: forming a patterned second mask layer on the surface of the polysilicon layer, wherein the second mask layer comprises a blocking region and a fourth window region; the blocking region corresponds to a region of the gate polysilicon.

[0096] S223: Using the patterned second mask layer as a mask, the polysilicon layer in the fourth window region is etched to form the gate polysilicon. The specific etching method may include wet etching or dry etching. Both wet etching and dry etching are conventional techniques in the art and will not be described in detail herein.

[0097] Wherein, forming the source region and the drain region in the top silicon layer in step S23 specifically includes:

[0098] S231: forming a patterned fourth mask layer on the surface of the top silicon layer, wherein the mask plate is provided with a seventh window region corresponding to the source region and an eighth window region corresponding to the drain region.

[0099] S232: Using the patterned fourth mask layer as a mask, ion implantation is performed on the top silicon layer corresponding to the seventh window region and the eighth window region to form the source region and the drain region. According to different implanted ions, the source region may include a P-type doping region or an N-type doping region, and the drain region may also include a P-type doping region or an N-type doping region.

[0100] S233: performing thermal annealing on the surface of the top silicon layer.

[0101] The above is a detailed description of step S2. The remaining steps of the method for preparing a PD-SOI device provided in an embodiment of the present invention will be described in detail below:

[0102] S3: Provide a support wafer 116, such as Fig.13The support wafer 116 is used to bond with the device wafer prepared in step S2, and the resistance of the support wafer 116 is greater than 100 ohm.cm.

[0103] S4: Bonding the surface of the device layer to the first surface of the support wafer 116, such as Fig.14 shown.

[0104] It should be added that after step S4, the bonded whole needs to be turned over so that the second surface of the silicon substrate 101 faces upward, that is, the bottom surface of the silicon substrate 101 faces upward.

[0105] S5: After the bonding is completed, the thickness of the silicon substrate 101 is reduced from the bottom surface of the silicon substrate 101 to a first thickness, such as Fig.15 shown.

[0106] Among them, the purpose of thinning the silicon substrate 101 is to facilitate the subsequent etching of the buried oxide layer 102. Therefore, the thickness of the silicon substrate 101 can be thinned to a very small thickness. For example, the original 770μm silicon substrate 101 can be thinned to more than ten microns, or even close to 0μm. Of course, the specific value of the first thickness can be set according to needs and is not limited here. However, it should be noted that the buried oxide layer 102 should not be damaged.

[0107] S6: etching a groove of a preset depth on the bottom surface of the silicon substrate, wherein the groove penetrates the silicon substrate and a portion of the buried oxide layer, and the groove corresponds to the gate polysilicon.

[0108] in, Fig.16 The process of the method for preparing the PD-SOI device provided by the embodiment of the present invention is Figure 2 .

[0109] Please refer to Fig.16 In step S6, a groove of a preset depth is etched on the bottom surface of the silicon substrate, wherein the groove penetrates the silicon substrate and part of the buried oxide layer. The specific steps include:

[0110] S61: Coating a photoresist 117 on the bottom surface of the thinned silicon substrate 101, such as Fig.17 shown.

[0111] Among them, the coating thickness of the photoresist 117 needs to be greater than or equal to the second thickness, and the second thickness needs to be greater than the sum of the remaining first thickness of the silicon substrate 101 and the preset depth of etching of the buried oxide layer 102 in the subsequently formed groove, so as to avoid the photoresist 117 being unable to serve as a mask for subsequent ion implantation due to the etching depth of the subsequently formed groove being too large.

[0112] S62: Expose and develop the photoresist 117 through a mask plate to form a first mask layer on the photoresist 117, wherein the first mask layer is provided with a window pattern and a barrier layer, wherein the window pattern corresponds to the groove area i1, such as Fig.18 shown.

[0113] S63: Using the first mask layer 117 as a mask, sequentially etching the silicon substrate 101 and the buried oxide layer 102 in the groove region i1 until a groove of a preset depth is formed in the buried oxide layer 102 in the groove region i1. Fig.19 shown.

[0114] Since the buried oxide layer 102 is not etched through, the high frequency performance of the PD-SOI device is not affected.

[0115] S7: Using the first mask layer 117 as a mask, doping the buried oxide layer 102 and the corresponding surface layer 118 of the top silicon layer in the groove region i1, and removing the first mask layer 117 after the doping is completed. Fig. 20 shown.

[0116] The specific means of doping the buried oxide layer 102 and the corresponding surface layer 118 of the top silicon layer in the groove region i1 is ion implantation. The implanted ion elements include at least: C + , Si + ,Ge + , Sn + , Pn + wait.

[0117] Wherein, on the basis of ensuring that the buried oxide layer 102 is not etched through, the thickness of the buried oxide layer 102 remaining in the groove area i1 is specifically determined by the implantation depth of the ion energy and the thickness of the surface layer 118 of the top silicon layer to be doped, so the preset depth of the groove is equal to the thickness of the buried oxide layer minus the thickness of the remaining buried oxide layer. For example, the thickness of the surface layer 118 of the top silicon layer to be doped is only 0.005 μm, and the energy of the ion implantation is 3 KeV. Since the depth of the oxide layer implanted by the ion with an energy of 3 KeV is 0.1 μm, the thickness of the buried oxide layer 102 remaining in the groove area i1 is approximately 0.095 μm, and the preset depth of the groove is the thickness of the buried oxide layer in the SOI wafer used-0.095 μμm. Of course, this is just a specific example, and the actual value of the thickness of the remaining buried oxide layer 102 can vary according to the thickness of the surface layer 118 of the top silicon layer to be doped and the change of the ion implantation energy.

[0118] S8: Annealing the buried oxide layer 102 remaining in the groove region i1 and the corresponding surface layer 118 of the top silicon layer to change the doped surface layer 118 of the top silicon layer into a polysilicon structure, such as Fig.21 shown.

[0119] Since the surface layer 118 of the top silicon layer in contact with the buried oxide layer 102 is transformed into polysilicon, the carrier lifetime is reduced, thereby effectively suppressing the kink effect of the PD-SOI device. Also, since there is a safe distance between the doped surface layer 118 of the top silicon layer and the gate polysilicon 106, the performance of the PD-SOI device will not be affected.

[0120] Among them, the process parameters of the above-mentioned thermal annealing include: the process gas for thermal annealing can be selected from nitrogen, hydrogen or a mixture of nitrogen and hydrogen, which is not limited here. The process temperature of thermal annealing is specifically between 900 and 1110 degrees Celsius. The time of millisecond annealing in thermal annealing is between 5 milliseconds and 1 second. The time of rapid thermal treatment in thermal annealing is between 5 seconds and 20 seconds. Of course, the specific time of the millisecond annealing and the specific time of the rapid thermal treatment can vary according to the actual process environment, which is not limited here.

[0121] S9: forming a metal interconnection layer 118 in sequence on the second surface of the silicon substrate 101 in a direction away from the second surface of the silicon substrate 101, such as Fig. 22 shown.

[0122] In step S9, a metal interconnection layer 118 is formed on the second surface of the silicon substrate 101 along a direction away from the second surface of the silicon substrate 101, which specifically includes the following steps:

[0123] S91 : depositing a second dielectric layer 1180 in the groove, wherein the second dielectric layer covers the silicon substrate, and forming a second metal layer 1181 in the second dielectric layer 1180 connected to the external connection contact hole 112 .

[0124] S92: stacking dielectric layers in sequence on the second dielectric layer 1180, forming metal through holes and metal layers in the dielectric layers, and connecting the metal layers and the second metal layers through the metal through holes.

[0125] Specifically, a fourth dielectric layer 1182 is formed on the second dielectric layer, a first metal through hole 1183 is formed in the fourth dielectric layer 1182, the first metal through hole 1183 is connected to the second metal layer 1181, a fifth dielectric layer 1184 is formed on the fourth dielectric layer 1182, a third metal layer 1185 is formed in the fifth dielectric layer 1184, the third metal layer 1185 is connected to the first metal through hole 1183, a sixth dielectric layer 1186 is formed on the fifth dielectric layer 1184, and a second metal through hole 1187 is formed in the sixth dielectric layer 1186, the second metal through hole 1187 is connected to the third metal layer 1185. Since the preparation of the metal interconnection layer 118 is a conventional technical means in the art, it will not be described in detail here.

[0126] It should be noted that if the external connection contact hole 112 is not prepared in step S27, it can also be prepared in step S9. The preparation process and specific structure are the same and will not be repeated here.

[0127] The specific number of metal layers in the metal interconnect layer can be prepared according to demand and is not limited here.

[0128] In summary, the method for preparing the PD-SOI device provided in the embodiment of the present invention first bonds the prepared device wafer and the support wafer, then thins the silicon substrate at the bottom of the device wafer and forms a groove of a preset depth on the thinned silicon substrate, wherein the groove penetrates the silicon substrate and a portion of the buried oxide layer, and finally the buried oxide layer at the bottom of the groove and the surface layer of the top silicon layer are doped and thermally annealed to change the surface layer of the doped top silicon layer into a polysilicon structure, thereby greatly reducing the carrier lifetime in the contact surface layer. In addition, because the kink effect of the PD-SOI device is positively correlated with the carrier concentration in the contact surface layer, the kink effect of the PD-SOI device is effectively suppressed.

[0129] Moreover, since there is a safe distance between the doped top silicon layer and the gate polysilicon, the performance of the PD-SOI device will not be affected. At the same time, since the buried oxide layer is not etched through, the radio frequency performance of the PD-SOI device will not be affected.

[0130] Please refer to Fig. 22 The embodiment of the present invention further provides a PD-SOI device, which is manufactured by the manufacturing method provided by the above embodiment, and the device comprises:

[0131] supporting wafer 116;

[0132] A device layer, wherein the device layer is located on the first surface of the support wafer 116, and the first surface of the device layer is bonded to the first surface of the support wafer 116;

[0133] A top silicon layer 103, wherein the top silicon layer 103 is located on the second surface of the device layer, the first surface of the top silicon layer 103 and the second surface of the device layer are in contact with each other, and the surface layer of the second surface of the top silicon layer 103 is a polysilicon structure;

[0134] A buried oxide layer 102, wherein the buried oxide layer 102 is located on the second surface of the top silicon layer 103, the first surface of the buried oxide layer 102 and the second surface of the top silicon layer 103 are in contact with each other, the second surface of the buried oxide layer 102 has a groove, the groove is filled with a dielectric layer, and the dielectric layer covers the silicon substrate, and the groove corresponds to the surface layer 118 of the top silicon layer of the polysilicon structure;

[0135] The metal interconnection layers 118 are stacked in sequence along a direction away from the second surface of the buried oxide layer 102 .

[0136] The device layer, the top silicon layer 103, the buried oxide layer 102 and the metal interconnection layer 118 are all described in the previous embodiment and will not be described again here.

[0137] Among them, the PD-SOI device structure provided by the present invention has a polysilicon structure on the surface of the top silicon layer close to the buried oxide layer corresponding to the gate, which reduces the carrier lifetime and thus suppresses the kink effect of the PD-SOI device, thereby solving the problem in the prior art that the kink effect cannot be effectively suppressed while ensuring device performance.

[0138] The materials, formation process, working principle, specific implementation method and beneficial effects involved in the PD-SOI device structure in the embodiment of the present invention can all be found in the method for manufacturing the PD-SOI device in the embodiment of the present invention, and will not be repeated here.

[0139] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for preparing a PD-SOI device, characterized in that: The method includes: Providing an SOI wafer, the SOI wafer comprising a silicon substrate, a buried oxide layer and a top silicon layer stacked in sequence; forming a device layer in the top silicon layer, wherein gate polysilicon is formed in the device layer; providing a support wafer; Bonding the surface of the device layer to the first surface of the support wafer; After the bonding is completed, the thickness of the silicon substrate is reduced from the bottom surface of the silicon substrate to a first thickness; Etching a groove of a preset depth on the bottom surface of the silicon substrate, wherein the groove penetrates the silicon substrate and a portion of the buried oxide layer, and the groove corresponds to the gate polysilicon; doping the buried oxide layer at the bottom of the groove and the surface layer of the top silicon layer, wherein the surface layer of the top silicon layer is used to characterize the area where the top silicon layer contacts the buried oxide layer at the bottom of the groove, wherein the distance between the surface layer of the top silicon layer and the gate polysilicon is greater than a first distance; Annealing the buried oxide layer at the bottom of the groove and the surface layer of the top silicon layer so that the doped surface layer of the top silicon layer becomes a polysilicon structure; A metal interconnection layer is formed on the bottom surface of the silicon substrate.

2. The method for preparing a PD-SOI device according to claim 1, characterized in that: Etching a groove of a preset depth on the bottom surface of the silicon substrate specifically includes: Applying a photoresist on the bottom surface of the thinned silicon substrate, wherein the thickness of the photoresist is a second thickness; Forming a patterned first mask layer on the photoresist, wherein the patterned first mask layer includes a window pattern of the groove and a barrier layer; Using the patterned first mask layer as a mask, the silicon substrate and the buried oxide layer are etched in sequence until a groove of a preset depth is formed in the buried oxide layer in the groove area, wherein the second thickness is greater than or equal to the sum of the first thickness and the preset depth.

3. The method for preparing a PD-SOI device according to claim 2, characterized in that: The size of the groove is smaller than or equal to the corresponding size of the gate polysilicon.

4. The method for preparing a PD-SOI device according to claim 2, characterized in that: Doping the buried oxide layer at the bottom of the groove and the surface layer of the top silicon layer specifically includes: Using the patterned first mask layer as a mask, ion implantation is performed on the buried oxide layer in the groove and the surface layer of the top silicon layer, wherein the implantation depth of the ions into the buried oxide layer in the groove is greater than the remaining thickness of the etched buried oxide layer; The first mask layer is removed.

5. The method for preparing a PD-SOI device according to claim 2, characterized in that: The implanted ions include at least one or more of carbon ions, silicon ions, germanium ions, and tin ions.

6. The method for preparing a PD-SOI device according to claim 1, characterized in that: A device layer is formed on the surface of the top silicon layer, specifically comprising: forming a shallow trench isolation structure in the top silicon layer, wherein a bottom of the shallow trench isolation structure contacts the buried oxide layer; forming the gate polysilicon on the surface of the top silicon layer; forming a source region and a drain region in the top silicon layer between the shallow trench isolation structures, wherein the source region and the drain region are located on both sides of the gate polysilicon; A first dielectric layer is deposited on the top silicon layer, and first contact holes are formed on the source region, the drain region and the surface of the gate polysilicon. A first end of the first contact hole is connected to a first metal layer.

7. The method for preparing a PD-SOI device according to claim 6, characterized in that: In addition to forming the first contact hole on the source region, the drain region and the gate polysilicon surface, an external connection contact hole is also formed in the shallow trench isolation structure. The external connection contact hole is formed in the shallow trench isolation structure, and one end is connected to any one of the first metal layers, and the other end passes through the buried oxide layer and is connected to the silicon substrate.

8. The method for preparing a PD-SOI device according to claim 7, characterized in that: Forming the metal interconnection layer on the bottom surface of the silicon substrate specifically includes: Depositing a second dielectric layer in the groove, wherein the second dielectric layer covers the silicon substrate, and forming a second metal layer connected to the external connection contact hole in the second dielectric layer; Dielectric layers are stacked in sequence on the second dielectric layer, metal through holes and metal layers are formed in the dielectric layers, and the metal layers are connected to the second metal layer through the metal through holes.

9. The method for preparing a PD-SOI device according to claim 7, characterized in that: The materials of the first dielectric layer, the second dielectric layer and the dielectric layer are all any one of Low-K material / High-K material / TEOS / PEOX / SIN or a combination thereof.

10. A PD-SOI device, manufactured by the method for manufacturing a PD-SOI device according to claim 1, characterized in that: The device includes: Supporting wafer; A device layer, the device layer includes a gate, a source / drain region and a first contact hole, and is located on the first surface of the supporting wafer, the first surface of the device layer and the first surface of the supporting wafer being bonded; A top silicon layer, wherein the top silicon layer is located on the second surface of the device layer, the first surface of the top silicon layer and the second surface of the device layer are in contact with each other, and a surface layer of the second surface of the top silicon layer corresponding to the gate in the device layer is a polysilicon structure; A buried oxide layer, wherein the buried oxide layer is located on the second surface of the top silicon layer, the first surface of the buried oxide layer and the second surface of the top silicon layer are in contact with each other, the second surface of the buried oxide layer has a groove, the groove is filled with a dielectric layer, and the dielectric layer covers the silicon substrate, and the groove corresponds to the surface layer of the top silicon layer of the polysilicon structure from top to bottom; The metal interconnection layer is arranged in a direction away from the surface of the dielectric layer.

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