Enhanced gallium nitride high-mobility transistor and preparation method thereof

Abstract

The invention relates to an enhanced gallium nitride high-mobility transistor and a preparation method thereof. The transistor sequentially comprises a substrate, a buffer layer, an i-GaN channel layer, an AlGaN barrier layer, a p-GaN layer and a gate dielectric layer from bottom to top, the source electrode and the drain electrode are respectively in ohmic contact with the two-dimensional electron gas, and the grid electrode and the p-GaN layer are in Schottky contact, so that the two-dimensional electron gas below the grid electrode is exhausted to realize normal closing; an electrode is arranged in a region between the grid electrode and the drain electrode, a thin-layer medium is arranged below the electrode, and the thin-layer medium and the electrode form an equivalent MIS grid structure; and the electrode is electrically connected with the source electrode. The switching time of the device is determined by the switching speed of the p-GaN HEMT composed of S-G1-D. Compared with a traditional Si MOS cascade structure, the device has the advantages of being fast in switching and free of reverse recovery charges. And meanwhile, the withstand voltage of the device is determined by a depletion mode MIS GaN HEMT consisting of S-G2-D, and the p-GaN grid does not bear high voltage, so that the device has the advantage of high reliability.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to an enhanced gallium nitride high-mobility transistor and a preparation method thereof. Background Art

[0002] GaN-based high electron mobility transistor (HEMT) combines the advantages of wide bandgap semiconductors and two-dimensional electron gas channels, and has the advantages of high breakdown electric field and high electron saturation drift velocity, making it an ideal choice for high-frequency and high-efficiency power switches. As a power switching device, the device is required to be normally off, that is, an enhancement-mode device to improve system safety, reduce device losses and simplify circuit design. Currently, the commonly used enhancement-mode GaN HEMT implementation methods include p-GaN and cascode cascade. p-GaN HEMT is an internal enhancement type, does not require cascaded Si MOS devices, and can work at a higher frequency, but p-GaN HEMT faces gate reliability issues under high voltage. The parasitic effects and matching problems caused by the cascaded Si devices in the cascode cascade structure have a negative impact on the switching advantages of the GaN device itself. Therefore, it is necessary to develop a new enhancement-mode GaN power device that takes into account both reliability and switching speed. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide an enhanced gallium nitride high mobility transistor and a preparation method thereof. The switching time of the device is determined by the switching speed of the p-GaN HEMT. Compared with the traditional SiMOS cascade structure, it has the advantages of fast switching and no reverse recovery charge. At the same time, the withstand voltage of the device is determined by the depletion-type MIS GaN HEMT composed of S-G2-D. The p-GaN gate does not withstand high voltage, so the device has the advantage of high reliability.

[0004] The present invention provides an enhanced gallium nitride high-mobility transistor, which comprises a substrate, a buffer layer, an i-GaN channel layer, an AlGaN barrier layer, a p-GaN layer and a gate dielectric layer from bottom to top; a source and a drain respectively form an ohmic contact with a two-dimensional electron gas, a gate forms a Schottky contact with the p-GaN layer, so that the two-dimensional electron gas below the gate is depleted to achieve normally-off; an electrode is provided in a region between the gate and the drain, a thin layer of dielectric is provided below the electrode, and an equivalent MIS gate structure is formed with the electrode; the electrode is electrically connected to the source.

[0005] The present invention also provides a method for preparing an enhanced gallium nitride high mobility transistor, comprising the following steps:

[0006] (1) preparing a silicon-based epitaxial wafer, which includes, from bottom to top, a substrate, a buffer layer, an i-GaN channel layer, an AlGaN barrier layer, and a p-GaN layer;

[0007] (2) depositing a TiN metal film and etching the p-GaN layer using a self-aligned method to form a p-GaN gate structure;

[0008] (3) depositing source and drain metals on the AlGaN barrier layer to form source and drain electrodes, forming ohmic contacts with the two-dimensional electron gas below;

[0009] (4) depositing a gate dielectric to form a gate dielectric layer;

[0010] (5) etching the gate dielectric layer to form a gate window;

[0011] (6) depositing gate metal, forming a gate in the gate window, and forming an electrode on the gate dielectric layer;

[0012] (7) Deposition of isolation dielectric and planarization;

[0013] (8) Opening holes above the source, drain, and electrode;

[0014] (9) Depositing interconnect metal to obtain an enhanced-mode gallium nitride high-mobility transistor.

[0015] Preferably, the source / drain metal in step (3) is Ti / Al / Ni / Au or Ti / Al / W.

[0016] Preferably, the gate dielectric in step (4) is one or more of SiNx and Al2O3.

[0017] Preferably, the thickness of the gate dielectric layer in step (4) is 10-20 nm.

[0018] Preferably, the gate metal in step (6) is Ni or Pd.

[0019] Preferably, the isolation medium in step (7) is SiO2.

[0020] Preferably, the interconnection metal in step (9) is Al.

[0021] Beneficial Effects

[0022] The switching time of the device of the present invention is determined by the switching speed of the p-GaN HEMT. Compared with the traditional SiMOS cascade structure, it has the advantages of fast switching and no reverse recovery charge. The withstand voltage range of the device under high voltage is concentrated in the depletion-type MISHEMT part, and the p-GaN HEMT only withstands a low voltage of tens of volts. The reliability of the device is determined by the MIS HEMT, so it has better reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1Schematic diagram of the structure of the transistor of the present invention; wherein S is the source, D is the drain, G1 is the gate, and G2 is the electrode.

[0024] Figure 2 Schematic diagram of an equivalent circuit of the transistor of the present invention.

[0025] Figure 3 Schematic diagram of the structure of recessed gate enhancement mode GaN HEMT and fluorine ion implantation enhancement mode GaN HEMT.

[0026] Figure 4a -i is a schematic diagram of the structure of the transistor preparation process of the present invention. DETAILED DESCRIPTION

[0027] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.

[0028] Example 1

[0029] like Figure 1 As shown, this embodiment provides an enhanced gallium nitride high-mobility transistor, which includes a substrate, a buffer layer, an i-GaN channel layer, an AlGaN barrier layer, a p-GaN layer and a gate dielectric layer from bottom to top; the source and the drain form ohmic contacts with the two-dimensional electron gas respectively, and the gate forms a Schottky contact with the p-GaN layer, so that the two-dimensional electron gas under the gate is depleted to achieve normally-off; an electrode is provided in the area between the gate and the drain, and a thin layer of dielectric is provided under the electrode to form an equivalent MIS gate structure with the electrode; the electrode is electrically connected to the source.

[0030] The equivalent circuit diagram of the device is shown in Figure 2 As shown in the figure, a low-voltage enhancement-mode p-GaN HEMT and a high-voltage depletion-mode MIS HEMT are cascaded. When no signal is applied to the gate, the device remains in the off state because the equivalent p-GaN HEMT is normally off. In the off state, as the drain voltage increases, the voltage across the equivalent p-GaN HEMT increases, causing the depletion-mode MIS HEMT to turn off, and the off-state voltage is then borne by the depletion-mode MIS HEMT. When the p-GaN HEMT is turned on, the device is turned on, and the on-resistance is determined by the two equivalent HEMTs in series.

[0031] In addition, the gate of the enhancement mode device can be realized by recessed gate, fluorine ion implantation and other structures besides p-GaN. Figure 3 shown.

[0032] Taking the p-GaN gate as an example, this embodiment also provides a method for preparing an enhancement-mode gallium nitride high-mobility transistor, comprising the following steps:

[0033] (1) Figure 4a As shown, a silicon-based epitaxial wafer is prepared, which includes a substrate, a buffer layer, an i-GaN channel layer, an AlGaN barrier layer and a p-GaN layer from bottom to top;

[0034] (2) Figure 4b As shown, a TiN metal film is deposited, and the p-GaN layer is etched using a self-alignment method to form a p-GaN gate structure;

[0035] (3) Figure 4c As shown, source and drain metals Ti / Al / Ni / Au or Ti / Al / W are deposited on the AlGaN barrier layer to form source and drain electrodes, forming ohmic contacts with the two-dimensional electron gas below;

[0036] (4) Figure 4d As shown, a gate dielectric is deposited to form a gate dielectric layer; wherein the gate dielectric is one or more of SiNx and Al2O3; and the thickness of the gate dielectric layer is 10 to 20 nm;

[0037] (5) Figure 4e As shown, the gate dielectric layer is etched to form a gate window;

[0038] (6) Figure 4f As shown, a gate metal is deposited to form a gate in a gate window, and an electrode is formed on the gate dielectric layer; wherein the gate metal is Ni or Pd;

[0039] (7) Figure 4g As shown, deposit isolation dielectric SiO2 and planarize;

[0040] (8) Figure 4h As shown, through holes are opened above the source, drain and electrode;

[0041] (9) Figure 4i As shown, interconnect metal Al is deposited to obtain an enhanced gallium nitride high mobility transistor.

Claims

1. An enhancement-mode gallium nitride high-mobility transistor, characterized in that: The transistor includes, from bottom to top, a substrate, a buffer layer, an i-GaN channel layer, an AlGaN barrier layer, a p-GaN layer and a gate dielectric layer; the source and the drain form ohmic contacts with the two-dimensional electron gas respectively, and the gate forms a Schottky contact with the p-GaN layer, so that the two-dimensional electron gas under the gate is depleted to achieve normally-off; an electrode is provided in the area between the gate and the drain, and a thin layer of dielectric is provided under the electrode to form an equivalent MIS gate structure with the electrode; the electrode is electrically connected to the source.

2. A method for preparing an enhancement-mode gallium nitride high-mobility transistor, comprising the following steps: (1) preparing a silicon-based epitaxial wafer, which includes, from bottom to top, a substrate, a buffer layer, an i-GaN channel layer, an AlGaN barrier layer, and a p-GaN layer; (2) depositing a TiN metal film and etching the p-GaN layer using a self-aligned method to form a p-GaN gate structure; (3) depositing source and drain metals on the AlGaN barrier layer to form source and drain electrodes, forming ohmic contacts with the two-dimensional electron gas below; (4) depositing a gate dielectric to form a gate dielectric layer; (5) etching the gate dielectric layer to form a gate window; (6) depositing gate metal, forming a gate in the gate window, and forming an electrode on the gate dielectric layer; (7) Deposition of isolation dielectric and planarization; (8) Opening holes above the source, drain, and electrode; (9) Depositing interconnect metal to obtain an enhanced-mode gallium nitride high-mobility transistor.

3. The preparation method according to claim 2, characterized in that: The source / drain metal in step (3) is Ti / Al / Ni / Au or Ti / Al / W.

4. The preparation method according to claim 2, characterized in that: The gate dielectric in step (4) is one or more of SiNx and Al2O3.

5. The preparation method according to claim 2, characterized in that: The thickness of the gate dielectric layer in step (4) is 10-20 nm.

6. The preparation method according to claim 2, characterized in that: The gate metal in step (6) is Ni or Pd.

7. The preparation method according to claim 2, characterized in that: The isolation medium in step (7) is SiO2.

8. The preparation method according to claim 2, characterized in that: The interconnection metal in step (9) is Al.

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