Normally-closed field effect transistor

Abstract

The invention provides a normally-off field effect transistor. The normally-off field effect transistor comprises a semiconductor layer of a first conductivity type; a drain electrode located on the second main surface side of the semiconductor layer of the first conductivity type; a gate trench extending downward from the first main surface of the semiconductor layer of the first conductivity type; a gate electrode in the gate trench and including a conductive material having a higher work function than the first conductivity type semiconductor layer; a source contact trench extending downward from the first main surface of the semiconductor layer of the first conductivity type and located between adjacent gate trenches; the source electrode comprises a first part and a second part, the first part is in contact with the semiconductor layer of the first conductivity type along the side wall and the bottom of the source electrode contact groove and forms Schottky contact with the semiconductor layer of the first conductivity type, and the second part is located on the first part and is in contact with the semiconductor layer of the first conductivity type to form ohmic contact; and the gate dielectric layer is arranged between the gate electrode and the semiconductor layer of the first conductivity type and comprises a dielectric material of which the dielectric constant is greater than that of SiO2. According to the invention, the off-state leakage current of the field effect transistor can be reduced.

Description

Technical Field

[0001] The invention belongs to the field of field effect transistor devices, and in particular relates to a normally-off field effect transistor. Background Art

[0002] The Schottky source-drain MOSFET structure was proposed in the 1960s. It uses metal source-drain to replace the semiconductor-doped source-drain of the traditional pn junction MOSFET, and a Schottky contact barrier is formed between the metal source-drain and the semiconductor. For Schottky source-drain MOSFET, when a positive voltage is applied between the drain and the source, the Schottky barrier formed between the source and the semiconductor material is reverse biased, causing the depletion layer to widen to achieve shutdown. Based on this, the Schottky source-drain MOSFET is a normally-off device; the conduction of the Schottky source-drain MOSFET is achieved by forming a conductive channel under the action of a positive gate bias, and the carriers at the source end directly tunnel through the barrier into the channel.

[0003] Since the birth of Schottky source-drain MOSFET, there have been two significant disadvantages: First, the on-state current is small. When the drain-source voltage V DS When >0, the Schottky contact barrier formed by the Schottky source electrode and the semiconductor is reverse biased to widen the depletion region, so that even if a positive gate-source voltage V is applied between the gate electrode and the Schottky source electrode GS When the current density is J = σE (where E represents the electric field strength), the lower the conductivity σ, the lower the current density J. This is why the on-state current of the Schottky source-drain MOSFET is smaller than that of the pn junction MOSFET under the same conditions. The on-state current of the conventional pn junction MOSFET can reach tens of amperes to hundreds of amperes, while the on-state current of the Schottky source-drain MOSFET under the same conditions can only reach milliamperes or even lower. Second, the off-state leakage is large, and the leakage current includes the thermal electron emission current transmitted from the source junction through the substrate and the tunneling current from the source junction. Summary of the invention

[0004] In view of this, the technical problem to be solved by the present invention is to provide a normally-off field effect transistor, which at least solves one of the technical problems existing in the prior art to a certain extent.

[0005] In the patent application with application number 202310325051.0, the applicant of the present invention adjusted the pure Schottky source in the Schottky source-drain MOSFET to a combination of an ohmic source and a Schottky source, wherein the ohmic source is between the gate insulating film and the Schottky source. Through the design improvement of this structural detail, the problem of small on-state current of the Schottky source-drain MOSFET is completely solved, so that its on-state current carrying capacity can be comparable to that of the pn junction MOSFET under the same conditions. At the same time, in the equilibrium state (when V DS =0&V GS =0), the normally-off function can be realized by utilizing the local depletion effect of electron carriers on the Schottky junction formed by the Schottky source and the n-type semiconductor layer.

[0006] Furthermore, in the patent application with application number 202310844747.4, the applicant of the present invention not only utilizes the Schottky junction formed by the source electrode and the n-type semiconductor layer to produce depletion effect on the electron carriers in the n-type semiconductor layer from one side, but also introduces the Schottky gate or the p-type gate to produce depletion effect on the electron carriers in the n-type semiconductor layer from the other side, thereby achieving the effect of double-side depletion. In this way, from the perspective of electrical performance, the on-state current capacity is maintained and the off-state leakage current is further reduced.

[0007] However, the inventors of this application conducted a product quantitative simulation study on the field effect transistor with double-sided depletion function in the above-mentioned patent application with application number 202310844747.4 with the help of Sentaurus-TCAD simulation software and found that: the off-state leakage current of the Schottky field effect transistor based on this scheme is significantly reduced compared with the off-state leakage current of the single-sided depletion scheme, but it is still relatively high compared with the pn junction field effect transistor, which will lead to an increase in the off-state power consumption of the field effect transistor.

[0008] Therefore, the inventors of the present application have found through further research that the gate dielectric layer is introduced with a dielectric constant greater than SiO 2 Dielectric materials with a low dielectric constant can store charges better and have better field effect characteristics, which can enhance the gate electrode's ability to control carriers in the semiconductor layer, thereby reducing off-state leakage current.

[0009] Based on the above research findings, the inventors of this application proposed an embodiment of a normally-off field effect transistor as follows: A normally-off field effect transistor, comprising: A semiconductor layer of a first conductivity type having a first main surface on one side and a second main surface on the other side opposite thereto; a gate trench extending downward from the first main surface of the first conductive type semiconductor layer into the first conductive type semiconductor layer; a gate electrode located in the gate trench, the gate electrode comprising a conductive material having a work function higher than that of the semiconductor layer of the first conductive type; a source contact groove, the source contact groove extending downward from the first main surface of the first conductive type semiconductor layer into the first conductive type semiconductor layer, the source contact groove being located between adjacent gate trenches; A source electrode, the source electrode comprising a first portion of the source electrode and a second portion of the source electrode, the first portion of the source electrode contacts the first conductive type semiconductor layer along the sidewall and the bottom of the source contact groove and forms a Schottky contact therewith, and the second portion of the source electrode is located on the first portion of the source electrode and contacts the first conductive type semiconductor layer to form an ohmic contact; A gate dielectric layer is disposed between the gate electrode and the semiconductor layer of the first conductivity type, wherein the gate dielectric layer includes a dielectric constant greater than SiO 2 The dielectric constant of a dielectric material.

[0010] Preferably, the dielectric constant is greater than SiO 2 The dielectric materials with the highest dielectric constant are silicon oxynitride (SiNO), silicon nitride (Si 3 N 4 )、Alumina(Al 2 O 3 )、HfO 2 )

[0011] Preferably, the gate dielectric layer further comprises SiO 2 layer, the SiO 2 The dielectric constant of the layer is greater than that of SiO 2 The dielectric constant is between the dielectric material and the first conductivity type semiconductor layer.

[0012] Preferably, the first conductivity type semiconductor layer is an n-type semiconductor layer.

[0013] Furthermore, the first conductive type semiconductor layer includes, from bottom to top, a heavily doped n-type semiconductor substrate layer, a lightly doped n-type semiconductor drift layer, and a heavily doped n-type semiconductor source region.

[0014] Preferably, each gate trench comprises: a shielding electrode at the bottom of the gate trench, the shielding electrode being insulated from the first conductive type semiconductor layer by a field dielectric layer; and a recessed gate, above the shielding electrode, with an isolation dielectric layer between the recessed gate and the shielding electrode.

[0015] Preferably, each gate trench comprises: a shielding electrode, which is insulated from the first conductive type semiconductor layer by a field dielectric layer in the middle area of ​​the gate trench; and a recessed gate, which has an isolation dielectric layer between the recessed gate and the shielding electrode on both sides of the shielding electrode.

[0016] Preferably, the first portion of the source electrode and the second portion of the source electrode correspond to different metals or alloys, respectively.

[0017] Preferably, the material of the semiconductor layer is one of silicon, silicon carbide, gallium nitride, gallium oxide and tin oxide.

[0018] Preferably, the distance between the gate trench and the source contact trench is in the range of 20 nm to 150 nm.

[0019] The beneficial effects of the present invention are as follows: (1) The field effect transistor of the embodiment of the present invention has no inversion channel and is an accumulation channel field effect transistor, so it has a lower channel resistance, thereby improving the power handling capability and efficiency of the transistor; (2) The field effect transistor of the embodiment of the present invention is a technical innovation based on Schottky source-drain MOSFET, and the body diode is a Schottky type body diode, which can significantly shorten the reverse recovery time of the body diode, thereby reducing the loss caused by the body diode in the synchronous rectification circuit; (3) The field effect transistor of the embodiment of the present invention introduces a dielectric constant greater than SiO in the gate dielectric 2 Dielectric materials with high dielectric constants can store charges better and have better field effect characteristics, which can enhance the gate electrode's ability to control carriers in the semiconductor layer. When the field effect transistor is in the off state, the carriers in the semiconductor layer can be more fully depleted, thereby further reducing the off-state leakage current of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a vertical cross-sectional view of an embodiment of a conventional Schottky junction trench gate MOSFET; Figure 2 is a vertical cross-sectional view of an embodiment of a shielded gate MOSFET in patent application number 202310844747.4; Figure 3 is a vertical cross-sectional view of a first example of a MOSFET according to an embodiment of the present invention; Figure 4 is a vertical cross-sectional view of a second example of a MOSFET according to an embodiment of the present invention; Figure 5is a vertical cross-sectional view of a third example of a MOSFET according to an embodiment of the present invention; Figure 6 SiO 2 Gate dielectric and Si 3 N 4 The off-state leakage current I of the field effect transistor with gate dielectric DSS and drain-source voltage V DS Graph of the curve.

[0021] The technical features corresponding to the marks in the accompanying drawings are: 11 Drain electrode 12 Source electrode 121 The first part of the source electrode 122 The second part of the source electrode 131 control gate electrode 132 shielding gate electrode 211n+ substrate layer 212n-type drift layer 213n+ source region 41 gate dielectric layer 411 first gate dielectric layer 412 second gate dielectric layer 42 field dielectric layer 43 Gate top dielectric layer DETAILED DESCRIPTION In order to enable those skilled in the art to better understand the technical solution of the invention, the technical solution of the invention will be described in detail below with reference to the accompanying drawings and specific implementation methods, but the implementation methods of the invention are not limited thereto.

[0022] It should be noted that the terms "including" and "having" and any variations thereof described in the specification and claims of the present application are intended to cover non-exclusive inclusions. For example, a series of layers, regions or process steps are not necessarily limited to those layers, regions or process steps explicitly listed, but may include layers, regions or process steps that are not explicitly listed or inherent to these structures.

[0023] In addition, the embodiments and features of the embodiments in this application may be combined with each other if there is no conflict.

[0024] It should be understood that, in the specification and the claims, when a layer / region is described as being “disposed / stacked” on another layer / region, the layer / region may be “directly disposed / stacked” on the other layer / region, or be “disposed / stacked” on the other layer / region through a third layer / region; when a process step is described as being connected to another process step, the process step may be directly connected to the other process step, or be connected to the other process step through a third process step.

[0025] Figure 1 1 is a vertical cross-sectional view of an embodiment of an existing Schottky junction trench gate MOSFET. The Schottky junction trench gate MOSFET comprises: a drain electrode 11, an n+ type substrate layer 211, an n- type drift layer 212, a gate trench located in the n- type drift layer 212, a control gate electrode 131 located in the gate trench and wrapped by a gate dielectric layer 41, a gate top dielectric layer 43 covering the top of the control gate electrode 131, and a source electrode 12 located on the n- type drift layer 212 and forming a Schottky contact therewith.

[0026] Figure 1 The Schottky junction trench gate MOSFET shown in the figure has a Schottky junction formed between the source electrode 12 and the n-type drift layer 212. When a voltage V is applied between the drain electrode 11 and the source electrode 12, DS When >0, the reverse bias of the Schottky junction widens the depletion region, so that a complete electronic conductive channel is not formed between the drain electrode 11 and the source electrode 12, and no current flows between the drain and the source. Based on this principle, the attached Figure 1 The Schottky junction trench gate MOSFET shown is a normally-off device; when a voltage V is applied between the drain electrode 11 and the source electrode 12 DS >0 and the voltage V applied between the control gate electrode 131 and the source electrode 12 GS When >0, due to the presence of the Schottky barrier between the source electrode 12 and the n-type drift layer 212, the transport of electron carriers is suppressed, so that a complete and high-concentration electron conductive channel is still not formed between the drain electrode 11 and the source electrode 12. Only a small part of the electron carriers form a tunneling current through the tunneling effect, which leads to a very poor on-state current carrying capacity of the existing Schottky trench gate MOSFET, and its on-state current is much smaller than the on-state current of the pn junction MOSFET under the same conditions, so that the Schottky junction trench gate MOSFET has not been commercialized so far.

[0027] Figure 2It is a vertical cross-sectional view of an embodiment of a shielded gate MOSFET in a patent application with application number 202310844747.4. The shielded gate MOSFET comprises: a drain electrode 11, an n+ type substrate layer 211, an n- type drift layer 212, an n+ type source region 213, and a gate trench extending from the upper surface of the n+ type source region 213 downward into the n- type drift layer 212, a shielded gate electrode 132 located at the bottom of the gate trench and a field dielectric layer 42 surrounding the shielded gate electrode 132, a control gate electrode 131 located at the top of the gate trench and a gate dielectric layer 41 and a gate top dielectric layer 43 around the control gate electrode 131, wherein the control gate electrode 131 and the shielded gate electrode 132 are separated by a dielectric; a source trench, a first portion 121 of the source electrode located in the source trench, which forms a Schottky contact with the n- type drift layer 212, a second portion 122 of the source electrode located above the first portion 121 of the source electrode, which forms an ohmic contact with the n+ type source region 213, and the first portion 121 of the source electrode and the second portion 122 of the source electrode are in direct electrical contact.

[0028] Figure 2 The MOSFET shown is a normally-off device. Figure 2 In the embodiment, the source electrode is divided into two parts, including a first part 121 of the source electrode forming a Schottky contact with the n-type drift layer 212, and a second part 122 of the source electrode forming an ohmic contact with the n+ type source region. When a voltage V is applied between the control gate electrode 131 and the second part 122 of the source electrode GS When V > 0, a high-concentration electron accumulation layer is formed in the n-type drift layer 212 on one side of the gate dielectric layer 41, so that a complete and high-concentration electron conductive channel is formed between the drain electrode 11 and the second portion 122 of the source electrode. At this time, the voltage V applied between the drain electrode 11 and the second portion 122 of the source electrode is DS When >0, a larger current will flow between the two. Since no inversion channel is formed, the channel resistance is eliminated and the power handling capacity of the transistor is increased. This completely solves the problem of low on-state current capacity of Schottky junction MOSFET. Moreover, Figure 2 Since the MOSFET shown has no pn junction diode, the reverse recovery time can be shortened, thereby reducing the loss caused by the pn junction diode in the synchronous rectification circuit.

[0029] exist Figure 2In the embodiment, the first part 121 of the source electrode forms a Schottky contact with the n-type drift layer 212, and the work function of the control gate electrode 131 is greater than the work function of the n-type drift layer 212. With such a design, the Schottky junction formed by the first part 121 of the source electrode and the n-type drift layer 212 has a depletion effect on the electron carriers in the n-type drift layer 212 from one side, and the control gate electrode 131 with a larger work function has a depletion effect on the electron carriers in the n-type drift layer 212 from the other side, thereby achieving a double-side depletion effect on the electron carriers in the n-type drift layer 212 located between the gate trench and the source trench. In this way, from the perspective of electrical performance, a larger on-state current capacity is achieved and the off-state leakage current is further reduced.

[0030] However, the inventors used Sentaurus-TCAD simulation software to Figure 2 When the MOSFET shown in the figure is subjected to quantitative simulation research for product design, when the material of the n-type drift layer 212 and the n+ type source region 213 is Si, and the material of the gate dielectric layer 41 is SiO 2 When it was found that Figure 2 Although the field effect transistor of the scheme shown can be normally off, its off-state leakage current is still relatively high compared with the traditional pn junction field effect transistor, which will lead to Figure 2 The off-state power consumption of the field effect transistor of the illustrated scheme increases.

[0031] Figure 3 It is a vertical cross-sectional view of a first example of a MOSFET according to an embodiment of the present invention. Figure 3 The MOSFET shown is a shielded gate MOSFET, which has: a drain electrode 11, an n+ type substrate layer 211, an n- type drift layer 212, an n+ type source region 213, and a gate trench extending from the upper surface of the n+ type source region 213 downward into the n- type drift layer 212, a shielded gate electrode 132 located at the bottom of the gate trench and a field dielectric layer 42 surrounding the shielded gate electrode 132, a control gate electrode 131 located at the top of the gate trench and a gate dielectric layer 41 and a gate top dielectric layer 43 surrounding the control gate electrode 131, wherein the material of the gate dielectric layer 41 is a dielectric constant greater than SiO 2 A dielectric material with a dielectric constant of 1.140 W, a source trench, a first portion 121 of the source electrode located in the source trench, which forms a Schottky contact with the n-type drift layer 212, a second portion 122 of the source electrode located above the first portion 121 of the source electrode, which forms an ohmic contact with the n+ type source region 213, and the first portion 121 of the source electrode and the second portion 122 of the source electrode are in direct electrical contact.

[0032] Figure 3 The MOSFET shown is in the attached Figure 2Based on the MOSFET shown in FIG. 1 , the gate dielectric layer 41 around the control gate electrode 131 is replaced with a dielectric constant greater than SiO 2 The dielectric material with a dielectric constant, for example, the material of the gate dielectric layer 41 is SiO 2 Replaced with hafnium oxide (HfO 2 ) or silicon oxynitride (SiNO), such a design can further enhance the control ability of the control gate electrode 131 on the electron carriers in the n-type drift layer 212. For example, in the off state, the depletion effect of the control gate electrode 131 on the electron carriers in the n-type drift layer 212 can be enhanced, thereby further reducing the off-state leakage current and reducing the off-state power consumption.

[0033] Figure 4 It is a vertical cross-sectional view of a second example of a MOSFET according to an embodiment of the present invention. Figure 4 The MOSFET shown is in Figure 3 Based on the MOSFET shown in the figure, the gate dielectric layer 41 is divided into two, and the gate dielectric layer 41 includes a first gate dielectric layer 411 and a second gate dielectric layer 412. The first gate dielectric layer 411 is between the n-type drift layer 212 and the second gate dielectric layer 412. Figure 4 In the embodiment shown, the material of the n-type drift layer 212 is silicon (Si), and the material of the first gate dielectric layer 411 is SiO 2 The material of the second gate dielectric layer 412 is, for example, silicon nitride (Si 3 N 4 ), whose dielectric constant is higher than that of SiO 2 . Figure 4 The structural design adopts a gate dielectric structure composed of two dielectric materials. 2 The dielectric layer is placed on silicon nitride (Si 3 N 4 ) between the dielectric layer and the n-type drift layer 212, SiO 2 The dielectric layer can be made by thermal oxidation process, which can alleviate the silicon nitride (Si 3 N 4 ) The interface stress between the dielectric layer and the n-type drift layer 212 can improve reliability while reducing the off-state leakage current.

[0034] Figure 5 2 is a vertical cross-sectional view of a second example of a MOSFET according to an embodiment of the present invention. Figure 5In the figure, it is a shielded gate MOSFET with a left-right split gate structure, the shielded gate electrode 132 is in the center area of ​​the gate trench, and the control gate electrode 131 is distributed on the left and right sides of the shielded gate electrode 132. The shielded gate electrode 132 is insulated from the n-type drift layer 212 by the field dielectric layer 42, and is insulated from the control gate electrode 131 by the gate dielectric layer 41. Figure 5 In the structure shown, the control gate electrode 131 is made of a metal material having a work function greater than the work function of the n-type drift layer 212, such as metal nickel (Ni) or metal (Pt); the gate dielectric layer 41 is made of a material having a dielectric constant greater than SiO 2 Dielectric materials with a dielectric constant such as hafnium oxide (HfO 2 ) or silicon oxynitride (SiNO). Such a design helps to enhance the depletion effect of the control gate electrode 131 on the electron carriers in the n-type drift layer 212, thereby further reducing the off-state leakage current and reducing the off-state power consumption.

[0035] Figure 6 yes Figure 2 The field effect transistor shown (using SiO 2 gate dielectric layer) and Figure 3 The field effect transistor shown (using Si 3 N 4 gate dielectric layer), respectively, at the gate-source voltage V GS =0 when the off-state leakage current I DS and drain-source voltage V DS The curve comparison chart. Figure 6 It can be seen from the curve shown that Figure 3 The field effect transistor shown (using Si 3 N 4 The off-state leakage current ratio of the gate dielectric layer Figure 2 The field effect transistor shown (using SiO 2 The off-state leakage current of the gate dielectric layer is lower and is about one order of magnitude lower, which can significantly reduce the off-state power consumption of the field effect transistor.

[0036] In the embodiment of the present invention, an n-channel normally-off MOSFET is taken as an example. On the control gate electrode side, a dielectric material with a higher dielectric constant is introduced on the basis of using a metal or alloy with a higher work function for the control gate electrode to enhance the depletion effect of the control gate electrode on the electron carriers of the semiconductor layer. When the MOSFET is in the off state, the control gate electrode can more fully deplete the electron carriers of the semiconductor layer, thereby further reducing the off-state leakage current of the MOSFET.

[0037] It should be noted that the MOSFETs shown in the various embodiments of the present invention are all n-channel MOSFETs based on the participation of electron carriers in conduction. The essence of the technical solution of the present invention is also applicable to p-channel MOSFETs based on the participation of hole carriers in conduction.

[0038] It should also be noted that the MOSFET shown in each embodiment of the present invention is based on the structural innovation of Schottky junction MOSFET, does not need to use p-type diffusion or injection, and is not only applicable to silicon (Si)-based semiconductor materials, but is particularly suitable for using other types of semiconductor materials, such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga 2 O 3 ) and tin oxide (SnO 2 ), etc. In these materials, the p-type diffusion, implantation and activation processes are difficult to complete and control.

[0039] In addition, for example, in a traditional pn junction SiC-based normally-off MOSFET, since the channel carrier mobility is very low, the contribution of the inversion channel to the on-resistance is particularly large. However, when the scheme of the present invention is adopted, the inversion channel is converted into an accumulation channel, which can greatly improve the channel carrier mobility, thereby reducing the on-resistance.

[0040] It should be understood that the embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the essence and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A normally-off field effect transistor, comprising: A semiconductor layer of a first conductivity type having a first main surface on one side and a second main surface on the other side opposite thereto; a drain electrode, the drain electrode being located on a side of the second main surface of the first conductive type semiconductor layer; a gate trench extending downward from the first main surface of the first conductive type semiconductor layer into the first conductive type semiconductor layer; a gate electrode located in the gate trench, the gate electrode comprising a conductive material having a work function higher than that of the first conductive type semiconductor layer; a source contact groove, the source contact groove extending downward from the first main surface of the first conductive type semiconductor layer into the first conductive type semiconductor layer, the source contact groove being located between adjacent gate trenches; A source electrode, the source electrode comprising a first portion of the source electrode and a second portion of the source electrode, the first portion of the source electrode contacts the first conductive type semiconductor layer along the sidewall and the bottom of the source contact groove and forms a Schottky contact therewith, and the second portion of the source electrode is located on the first portion of the source electrode and contacts the first conductive type semiconductor layer to form an ohmic contact; A gate dielectric layer is disposed between the gate electrode and the semiconductor layer of the first conductivity type, and the gate dielectric layer comprises a dielectric material having a dielectric constant greater than that of SiO2.

2. The normally-off field effect transistor according to claim 1, characterized in that: The dielectric material is one of silicon oxynitride (SiNO), silicon nitride (Si3N4), aluminum oxide (Al2O3), and hafnium oxide (HfO2).

3. The normally-off field effect transistor according to claim 1, characterized in that: The gate dielectric layer further includes a SiO2 layer, and the SiO2 layer is located between the dielectric material having a dielectric constant greater than that of SiO2 and the semiconductor layer of the first conductivity type.

4. The normally-off field effect transistor according to claim 1, characterized in that: The first conductivity type semiconductor layer is an n-type semiconductor layer.

5. The normally-off field effect transistor according to claim 4, characterized in that: The first conductive type semiconductor layer includes, from bottom to top, a heavily doped n-type semiconductor substrate layer, a lightly doped n-type semiconductor drift layer, and a heavily doped n-type semiconductor source region.

6. The normally-off field effect transistor according to claim 1, characterized in that: Each gate trench comprises: a shielding electrode at the bottom of the gate trench, the shielding electrode being insulated from the first conductive type semiconductor layer by a field dielectric layer; and a recessed gate above the shielding electrode, with an isolation dielectric layer between the recessed gate and the shielding electrode.

7. The normally-off field effect transistor according to claim 1, characterized in that: Each gate trench comprises: a shielding electrode in the middle region of the gate trench, the shielding electrode being insulated from the first conductive type semiconductor layer by a field dielectric layer; and a recessed gate having an isolation dielectric layer between the recessed gate and the shielding electrode on both sides of the shielding electrode.

8. The normally-off field effect transistor according to claim 1, characterized in that: The first portion of the source electrode and the second portion of the source electrode correspond to different metals or alloys, respectively.

9. The normally-off field effect transistor according to claim 1, characterized in that: The material of the semiconductor layer is one of silicon, silicon carbide, gallium nitride, gallium oxide, and tin oxide.

10. The normally-off field effect transistor according to claim 1, characterized in that: The distance between the gate trench and the source contact trench is in the range of 20nm to 150nm.

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