Super-junction vertical double-diffused metal oxide semiconductor device and preparation method thereof

Abstract

The invention relates to a super-junction vertical double-diffused metal oxide semiconductor device and a preparation method thereof. The super-junction vertical double-diffused metal oxide semiconductor device comprises a substrate structure; the super junction structure is arranged in the substrate structure; the super junction structure comprises first doped regions and second doped regions which are sequentially and alternately arranged along a first direction; the second doped region comprises a first sub-region and two second sub-regions which are arranged along the first direction, and the first sub-region is located between the two second sub-regions; the body region is arranged in the substrate structure; the body region is located on the side, close to the front face of the substrate structure, of the first doping region and connected with the first doping region. The source region is arranged in the body region; the grid electrode is arranged on the substrate structure; wherein the substrate structure, the first sub-region, the second sub-region and the source region are of a first conductive type, the doping concentration of the first sub-region is greater than that of the second sub-region, and the first doped region and the body region are of a second conductive type. The performance of the device can be improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a superjunction vertical double diffused metal oxide semiconductor device and a preparation method thereof. Background Art

[0002] Due to its special functions, the power metal-oxide-semiconductor long-effect transistor structure has a wide range of applications in a very broad field, such as disk drives, automotive electronics, and power devices. Taking power devices as an example, VDMOS (Vertical double-diffused metal oxide semiconductor) is used in ultra-large-scale integrated circuit devices for power devices. It has the advantages of low switching loss, high input impedance, low driving power, and good frequency characteristics, and is widely used.

[0003] In VDMOS devices, increasing the breakdown voltage of the device and reducing the on-resistance of the device are a contradiction. Superjunction VDMOS devices use a new voltage-resistant layer structure, using a series of alternating P-type and N-type semiconductor thin layers to deplete the P-type and N-type regions at a lower reverse voltage, achieving charge compensation, so that the N-type region can achieve a high breakdown voltage at a high doping concentration, thereby simultaneously obtaining low on-resistance and high breakdown voltage, breaking the theoretical limit of on-resistance of traditional VDMOS devices. However, the performance of current VDMOS devices needs to be further improved. Summary of the invention

[0004] Based on this, it is necessary to provide a super junction vertical double diffused metal oxide semiconductor device and a method for preparing the same in order to address at least one of the above problems.

[0005] In order to achieve the above objectives, in a first aspect, the present application provides a super junction vertical double diffused metal oxide semiconductor device, comprising:

[0006] Substrate structure;

[0007] A super junction structure is provided in the substrate structure; the super junction structure comprises first doped regions and second doped regions arranged alternately in sequence along a first direction; the first direction is perpendicular to the thickness direction of the substrate structure; the second doped region comprises a first sub-region and two second sub-regions arranged along the first direction, and the first sub-region is located between the two second sub-regions;

[0008] A body region, disposed in the substrate structure; the body region is located on a side of the first doping region close to the front side of the substrate structure and is connected to the first doping region;

[0009] a source region, disposed in the body region;

[0010] A gate, disposed on the substrate structure, wherein an orthographic projection of the gate on the substrate structure covers the second doped region and a portion of the body region;

[0011] The substrate structure, the first sub-region, the second sub-region and the source region are of the first conductivity type, the doping concentration of the first sub-region is greater than the doping concentration of the second sub-region, and the first doping region and the body region are of the second conductivity type.

[0012] In one embodiment, the size of the first sub-area along the first direction is A, the sum of the sizes of the two second sub-areas along the first direction is B, and A and B satisfy the following relationship:

[0013] .

[0014] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0015] In one of the embodiments, the substrate structure includes a stacked base and an epitaxial layer, the super junction structure and the body region are both arranged in the epitaxial layer, and the gate is arranged on a side of the epitaxial layer away from the base.

[0016] In a second aspect, an embodiment of the present application provides a method for preparing a super junction vertical double diffused metal oxide semiconductor device, comprising:

[0017] A super junction structure is formed in the substrate structure; the super junction structure comprises first doped regions and second doped regions arranged alternately in sequence along a first direction; the first direction is perpendicular to the thickness direction of the substrate structure; the second doped region comprises a first sub-region and two second sub-regions arranged along the first direction, the first sub-region is located between the two second sub-regions, and the doping concentration of the first sub-region is greater than the doping concentration of the second sub-region;

[0018] A body region, a source region and a gate are formed; the body region is arranged in the substrate structure, the body region is located on the side of the first doped region close to the front side of the substrate structure, and is connected to the first doped region; the source region is arranged in the body region; the gate is arranged on the substrate structure, and the orthographic projection of the gate on the substrate structure covers the second doped region and part of the body region; wherein the substrate structure, the first sub-region, the second sub-region and the source region are of the first conductivity type, and the first doped region and the body region are of the second conductivity type.

[0019] In one embodiment, the step of forming a super junction structure in the substrate structure includes:

[0020] providing a substrate structure;

[0021] Etching a groove on the substrate structure;

[0022] Implanting a first conductive type doping element on one side wall of the trench along the first direction, and implanting a second conductive type doping element on the other side wall of the trench along the first direction;

[0023] Filling the trench with an epitaxial material of a first conductivity type to form an intermediate structure;

[0024] The intermediate structure is thermally treated to form the super junction structure.

[0025] In one embodiment, the step of providing a substrate structure comprises:

[0026] providing a substrate of a first conductivity type;

[0027] An epitaxial layer of a first conductivity type is formed on the substrate.

[0028] In one embodiment, the step of forming a super junction structure in the substrate structure includes:

[0029] providing a substrate of a first conductivity type;

[0030] forming a first sub-epitaxial layer of a first conductivity type on the substrate;

[0031] Etching a first sub-trench on the first sub-epitaxial layer;

[0032] Implanting a first conductive type doping element into a sidewall of the first sub-trench along the first direction, and implanting a second conductive type doping element into a sidewall of the first sub-trench along the first direction;

[0033] Filling the first sub-trench with an epitaxial material of a first conductivity type;

[0034] forming a second sub-epitaxial layer of a first conductivity type on the first sub-epitaxial layer;

[0035] Etching a second sub-groove on the second sub-epitaxial layer; an orthographic projection of the second sub-groove on the substrate overlaps with at least a portion of an orthographic projection of the first sub-groove on the substrate;

[0036] Implanting a first conductive type doping element into a sidewall of the second sub-trench along the first direction, and implanting a second conductive type doping element into a sidewall of the second sub-trench along the first direction;

[0037] Filling the second sub-trench with an epitaxial material of the first conductivity type to form an intermediate structure;

[0038] The intermediate structure is thermally treated to form the super junction structure.

[0039] In one embodiment, the step of forming the body region, the source region and the gate comprises:

[0040] forming a gate on the substrate structure;

[0041] forming a body region in the substrate structure;

[0042] A source region is formed in the body region.

[0043] In one embodiment, the step of forming a gate on the substrate structure includes:

[0044] forming a gate dielectric layer on the substrate structure;

[0045] A gate conductive layer is formed on the gate dielectric layer.

[0046] The superjunction vertical double diffused metal oxide semiconductor device and the preparation method thereof provided in the embodiment of the present application are configured by setting the second doping region of the superjunction structure to a first sub-region and two second sub-regions, wherein the first sub-region is located between the two second sub-regions, and the doping concentration of the first sub-region is greater than the doping concentration of the second sub-region. In this way, the conductive resistance of the first sub-region is less than the conductive resistance of the second sub-region, which is equivalent to forming a higher concentration of electron channels in the middle region of the second doping region, so that the breakdown voltage will not be greatly affected, and the on-state resistance of the device can be optimized, thereby improving the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of the present application, the drawings required for use in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0048] Figure 1 A schematic diagram of the cross-sectional structure of a superjunction vertical double diffused metal oxide semiconductor device provided in one embodiment of the present application.

[0049] Figure 2 A schematic flow chart of a method for preparing a superjunction vertical double diffused metal oxide semiconductor device provided in one embodiment of the present application.

[0050] Figure 3 for Figure 2 A detailed schematic diagram of S100 in the flowchart shown.

[0051] Figure 4for Figure 2 Another detailed schematic diagram of S100 in the flowchart shown.

[0052] Figure 5-Figure 11 for Figure 2 Schematic diagram of the cross-sectional structure of the device during the preparation method shown.

[0053] Description of reference numerals:

[0054] 1. Super junction vertical double diffused metal oxide semiconductor device; 11. Substrate structure; 111. Base; 112. Epitaxial layer; 112a. First sub-epitaxial layer; 112b. Second sub-epitaxial layer; 1131. First sub-groove; 1132. Second sub-groove; 12. Super junction structure; 121. First doped region; 122. Second doped region; 1221. First sub-region; 1222. Second sub-region; 13. Body region; 14. Source region; 15. Gate; 151. Gate dielectric layer; 152. Gate conductive layer; 21. First conductive type doping element; 22. Second conductive type doping element. DETAILED DESCRIPTION

[0055] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0057] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0058] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0059] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0060] Embodiments of the application are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the application, so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the application should not be limited to the specific shapes of the zones shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the application.

[0061] In the first aspect, the embodiment of the present application provides a superjunction vertical double diffused metal oxide semiconductor device 1, which specifically includes a substrate structure 11, a superjunction structure 12, a body region 13, a source region 14 and a gate 15. The superjunction structure 12 is arranged in the substrate structure 11; the superjunction structure 12 includes a first doping region 121 and a second doping region 122 arranged alternately in sequence along a first direction X; the first direction X is perpendicular to the thickness direction of the substrate structure 11; the second doping region 122 includes a first sub-region 1221 and two second sub-regions 1222 arranged along the first direction X, and the first sub-region 1221 is located between the two second sub-regions 1222. The body region 13 is arranged in the substrate structure 11; the body region 13 is located on the side of the first doping region 121 close to the front of the substrate structure 11, and is connected to the first doping region 121. The source region 14 is arranged in the body region 13. The gate 15 is arranged on the substrate structure 11, and the orthographic projection of the gate 15 on the substrate structure 11 covers the second doping region 122 and part of the body region 13.

[0062] The substrate structure 11, the first sub-region 1221, the second sub-region 1222 and the source region 14 are of the first conductivity type, the doping concentration of the first sub-region 1221 is greater than the doping concentration of the second sub-region 1222, and the first doping region 121 and the body region 13 are of the second conductivity type. It can be understood that one of the first conductivity type and the second conductivity type is N-type, and the other is P-type.

[0063] Here, it should be noted that the super junction structure 12 may include a first doping region 121 and a second doping region 122, or may include multiple first doping regions 121 and multiple second doping regions 122. When the number of the first doping regions 121 and the second doping regions 122 are both multiple, the first doping regions 121 and the second doping regions 122 are arranged alternately in sequence along the first direction X.

[0064] The superjunction vertical double diffused metal oxide semiconductor device 1 provided in the embodiment of the present application sets the second doping region 122 of the superjunction structure 12 as a first sub-region 1221 and two second sub-regions 1222, wherein the first sub-region 1221 is located between the two second sub-regions 1222, and the doping concentration of the first sub-region 1221 is greater than the doping concentration of the second sub-region 1222. In this way, the conductive resistance of the first sub-region 1221 is less than the conductive resistance of the second sub-region 1222, which is equivalent to forming an electron channel with a higher concentration in the middle area of ​​the second doping region 122, so that the breakdown voltage will not be greatly affected, and the on-state resistance of the device can be optimized, thereby improving the performance of the device.

[0065] In one embodiment, the size of the first sub-area 1221 along the first direction X is A, the sum of the sizes of the two second sub-areas 1222 along the first direction X is B, and A and B satisfy the following relationship:

[0066] .

[0067] Specifically, Figure 1 As shown, the size of the first sub-region 1221 along the first direction X is equivalent to the width of the first sub-region 1221, and the size of the second sub-region 1222 along the first direction X is equivalent to the width of the second sub-region 1222. In other words, the ratio of the width of the first sub-region 1221 to the sum of the widths of the two second sub-regions 1222 is between one eighth and one third. In this way, the width of the first sub-region 1221 can be made narrower and not too wide, which is beneficial to reduce the on-resistance while ensuring the breakdown voltage.

[0068] In one embodiment, the first conductivity type is N type, and the second conductivity type is P type. Thus, the first doping region 121 is equivalent to a P column, and the second doping region 122 is equivalent to an N column.

[0069] In one embodiment, the material of the substrate structure 11 can be single crystal silicon, polycrystalline silicon, amorphous silicon, germanium silicon compound, silicon-on-insulator (SOI) or low temperature polysilicon (LTPS), or other materials known to those skilled in the art.

[0070] In one embodiment, the substrate structure 11 includes a stacked base 111 and an epitaxial layer 112 , the super junction structure 12 and the body region 13 are both disposed in the epitaxial layer 112 , and the gate 15 is disposed on a side of the epitaxial layer 112 away from the base 111 .

[0071] Second, as Figure 2As shown, the embodiment of the present application provides a method for preparing a super junction vertical double diffused metal oxide semiconductor device 1, which specifically includes the following steps:

[0072] S100: forming a super junction structure 12 in the substrate structure 11. The super junction structure 12 includes a first doping region 121 and a second doping region 122 arranged alternately in sequence along a first direction X; the first direction X is perpendicular to the thickness direction of the substrate structure 11; the second doping region 122 includes a first sub-region 1221 and two second sub-regions 1222 arranged along the first direction X, the first sub-region 1221 is located between the two second sub-regions 1222, and the doping concentration of the first sub-region 1221 is greater than the doping concentration of the second sub-region 1222.

[0073] S200: forming a body region 13, a source region 14 and a gate 15. The body region 13 is provided in the substrate structure 11, and the body region 13 is located on the side of the first doping region 121 close to the front surface of the substrate structure 11, and is connected to the first doping region 121; the source region 14 is provided in the body region 13; the gate 15 is provided on the substrate structure 11, and the positive projection of the gate 15 on the substrate structure 11 covers the second doping region 122 and part of the body region 13; wherein the substrate structure 11, the first sub-region 1221, the second sub-region 1222 and the source region 14 are of the first conductivity type, and the first doping region 121 and the body region 13 are of the second conductivity type. Exemplarily, the first conductivity type is N-type, and the second conductivity type is P-type.

[0074] The method for preparing the superjunction vertical double diffused metal oxide semiconductor device 1 provided in the embodiment of the present application is to set the second doping region 122 of the superjunction structure 12 as a first sub-region 1221 and two second sub-regions 1222, wherein the first sub-region 1221 is located between the two second sub-regions 1222, and the doping concentration of the first sub-region 1221 is greater than the doping concentration of the second sub-region 1222. In this way, the conductive resistance of the first sub-region 1221 is less than the conductive resistance of the second sub-region 1222, which is equivalent to forming a higher concentration of electron channels in the middle area of ​​the second doping region 122, so that the breakdown voltage will not be greatly affected, and the on-state resistance of the device can be optimized, thereby improving the performance of the device.

[0075] In one embodiment, referring to Figure 3 As shown, S100: forming a super junction structure 12 in a substrate structure 11, specifically comprising the following steps:

[0076] S110A: Provide a substrate structure 11.

[0077] S120A: etching a trench on the substrate structure 11 .

[0078] S130A: injecting a first conductive type doping element 21 on one side wall of the groove along the first direction X, and injecting a second conductive type doping element 22 on the other side wall of the groove along the first direction X. It should be noted here that the implantation depth can be made deeper by adopting the method of etching the groove + ion implantation, which is conducive to reducing the difficulty of ion implantation. In addition, by respectively injecting two different types of doping elements on both sides of the groove, it is conducive to suppressing the lateral diffusion of the doping elements, thereby facilitating improving the performance of the device.

[0079] S140A: Fill the trench with an epitaxial material of the first conductivity type to form an intermediate structure. It is understood that the doping concentration of the epitaxial material is less than the concentration of the doping element implanted into the trench sidewall, so that a second doping region 122 with a gradient doping concentration can be formed.

[0080] S150A: heat-treating the intermediate structure to form a super junction structure 12. In this way, the doping elements can be diffused to form a first doping region 121 and a second doping region 122.

[0081] It should be noted that the manufacturing process provided in this embodiment is suitable for devices that do not have high requirements on withstand voltage thickness.

[0082] In one embodiment, S110A: providing a substrate structure 11, specifically comprising the following steps:

[0083] S111A: providing a substrate 111 of a first conductivity type.

[0084] S112A: forming an epitaxial layer 112 of a first conductivity type on the substrate 111 .

[0085] In one embodiment, referring to Figure 4 , and combined with Figure 5-Figure 11 As shown, S100: forming a super junction structure 12 in a substrate structure 11, specifically comprising the following steps:

[0086] S110B: providing a substrate 111 of a first conductivity type.

[0087] S120B: forming a first sub-epitaxial layer 112a of the first conductivity type on the substrate 111. The structure of the first sub-epitaxial layer 112a after formation is as follows Figure 5 shown.

[0088] S130B: etching a first sub-trench 1131 on the first sub-epitaxial layer 112 a .

[0089] S140B: implanting the first conductive type doping element 21 on one side wall of the first sub-trench 1131 along the first direction X, and implanting the second conductive type doping element 22 on the other side wall of the first sub-trench 1131 along the first direction X. The structure after the first conductive type doping element 21 and the second conductive type doping element 22 are implanted is as follows: Figure 6 shown.

[0090] S150B: Fill the first sub-trench 1131 with an epitaxial material of the first conductivity type. The structure after the epitaxial material is filled is as follows: Figure 7 shown.

[0091] S160B: forming a second sub-epitaxial layer 112b of the first conductivity type on the first sub-epitaxial layer 112a. The structure of the second sub-epitaxial layer 112b after formation is as follows Figure 8 shown.

[0092] S170B: etching a second sub-trench 1132 on the second sub-epitaxial layer 112 b . The orthographic projection of the second sub-trench 1132 on the substrate 111 overlaps at least part of the orthographic projection of the first sub-trench 1131 on the substrate 111 . In other words, the second sub-trench 1132 is connected to the first sub-trench 1131 .

[0093] S180B: implanting the first conductive type doping element 21 on one side wall of the second sub-trench 1132 along the first direction X, and implanting the second conductive type doping element 22 on the other side wall of the second sub-trench 1132 along the first direction X. The structure after the first conductive type doping element 21 and the second conductive type doping element 22 are implanted is as follows: Fig. 9 shown.

[0094] S190B: Fill the second sub-trench 1132 with an epitaxial material of the first conductivity type to form an intermediate structure. The structure after the epitaxial material is formed is as follows: Fig.10 shown.

[0095] S1100B: Heat-treating the intermediate structure to form a super junction structure 12. In this way, the doping elements can be diffused to form a first doping region 121 and a second doping region 122. The structure after heat treatment is as follows: Fig.11 shown.

[0096] It should be noted that the traditional super junction VDMOS device uses epitaxy and ion implantation processes to make the super junction structure 12. In order to control the lateral diffusion of impurities, it can only be achieved through more epitaxy and ion implantation. However, to achieve the designed withstand voltage thickness, multiple epitaxy implantations are required, which is a huge challenge in terms of cost and process. Therefore, how to control the lateral diffusion of impurities at a lower cost has become the research focus of designers.

[0097] The embodiment of the present application adopts the method of 2 epitaxy + 2 trench etching + sidewall injection, which can not only suppress the lateral diffusion of impurities, but also reduce the number of epitaxy times, thereby reducing the process cost.

[0098] Taking the 7.5μm cell pitch super junction VDMOS device as an example, due to the need to suppress the lateral diffusion of impurities, the 45μm N column thickness requires 13 epitaxy + implantation to achieve. However, the 7.5μm cell pitch super junction device formed by epitaxy + trench + sidewall implantation can be completed with only 2 epitaxy + 2 trench etching + sidewall implantation using a 5° ion implantation angle.

[0099] In one embodiment, S200: forming the body region 13, the source region 14 and the gate 15, specifically includes the following steps:

[0100] S210 : forming a gate 15 on the substrate structure 11 .

[0101] S220: forming a body region 13 in the substrate structure 11. Exemplarily, the body region 13 may be formed by an ion implantation process.

[0102] S230: forming a source region 14 in the body region 13. Exemplarily, the source region 14 may be formed by an ion implantation process.

[0103] In one embodiment, S210: forming a gate 15 on the substrate structure 11, specifically comprising the following steps:

[0104] S211: forming a gate dielectric layer 151 on the substrate structure 11. Exemplarily, the gate dielectric layer 151 may be made of silicon dioxide.

[0105] S212: forming a gate conductive layer 152 on the dielectric layer of the gate 15. Exemplarily, the gate conductive layer 152 may be made of polysilicon.

[0106] It should be understood that, in the embodiments of the present application, although the various steps in the flowchart of the accompanying drawings are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the accompanying drawings may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the steps or stages in other steps.

[0107] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0108] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0109] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A superjunction vertical double diffused metal oxide semiconductor device, characterized in that: include: Substrate structure; A super junction structure is provided in the substrate structure; the super junction structure comprises first doped regions and second doped regions arranged alternately in sequence along a first direction; the first direction is perpendicular to the thickness direction of the substrate structure; the second doped region comprises a first sub-region and two second sub-regions arranged along the first direction, the first sub-region is located between the two second sub-regions; A body region, disposed in the substrate structure; the body region is located on a side of the first doping region close to the front side of the substrate structure and is connected to the first doping region; a source region, disposed in the body region; A gate, disposed on the substrate structure, wherein an orthographic projection of the gate on the substrate structure covers the second doped region and a portion of the body region; The substrate structure, the first sub-region, the second sub-region and the source region are of the first conductivity type, the doping concentration of the first sub-region is greater than the doping concentration of the second sub-region, and the first doping region and the body region are of the second conductivity type.

2. The superjunction vertical double diffused metal oxide semiconductor device according to claim 1, characterized in that: The size of the first sub-area along the first direction is A, the sum of the sizes of the two second sub-areas along the first direction is B, and A and B satisfy the following relationship: 。 3. The superjunction vertical double diffused metal oxide semiconductor device according to claim 1, characterized in that: The first conductivity type is N type, and the second conductivity type is P type.

4. The superjunction vertical double diffused metal oxide semiconductor device according to claim 1, characterized in that: The substrate structure comprises a stacked base and an epitaxial layer, the super junction structure and the body region are both arranged in the epitaxial layer, and the gate is arranged on a side of the epitaxial layer away from the base.

5. A method for preparing a superjunction vertical double diffused metal oxide semiconductor device, characterized in that: include: A super junction structure is formed in the substrate structure; the super junction structure includes first doped regions and second doped regions alternately arranged in sequence along a first direction; The first direction is perpendicular to the thickness direction of the substrate structure; the second doping region includes a first sub-region and two second sub-regions arranged along the first direction, the first sub-region is located between the two second sub-regions, and the doping concentration of the first sub-region is greater than the doping concentration of the second sub-region; forming a body region, a source region and a gate; The body region is disposed in the substrate structure, the body region is located on a side of the first doping region close to the front side of the substrate structure, and is connected to the first doping region; The source region is arranged in the body region; the gate is arranged on the substrate structure, and the orthographic projection of the gate on the substrate structure covers the second doped region and a portion of the body region; wherein the substrate structure, the first sub-region, the second sub-region and the source region are of the first conductivity type, and the first doped region and the body region are of the second conductivity type.

6. The method for preparing a superjunction vertical double diffused metal oxide semiconductor device according to claim 5, characterized in that: The step of forming a super junction structure in the substrate structure includes: providing a substrate structure; Etching a groove on the substrate structure; Implanting a first conductive type doping element on one side wall of the trench along the first direction, and implanting a second conductive type doping element on the other side wall of the trench along the first direction; Filling the trench with an epitaxial material of a first conductivity type to form an intermediate structure; The intermediate structure is thermally treated to form the super junction structure.

7. The method for preparing a superjunction vertical double diffused metal oxide semiconductor device according to claim 6, characterized in that: The step of providing a substrate structure comprises: providing a substrate of a first conductivity type; An epitaxial layer of a first conductivity type is formed on the substrate.

8. The method for preparing a superjunction vertical double diffused metal oxide semiconductor device according to claim 5, characterized in that: The step of forming a super junction structure in the substrate structure includes: providing a substrate of a first conductivity type; forming a first sub-epitaxial layer of a first conductivity type on the substrate; Etching a first sub-trench on the first sub-epitaxial layer; Implanting a first conductive type doping element into a sidewall of the first sub-trench along the first direction, and implanting a second conductive type doping element into a sidewall of the first sub-trench along the first direction; Filling the first sub-trench with an epitaxial material of a first conductivity type; forming a second sub-epitaxial layer of a first conductivity type on the first sub-epitaxial layer; Etching a second sub-groove on the second sub-epitaxial layer; an orthographic projection of the second sub-groove on the substrate overlaps with at least a portion of an orthographic projection of the first sub-groove on the substrate; Implanting a first conductive type doping element into a sidewall of the second sub-trench along the first direction, and implanting a second conductive type doping element into a sidewall of the second sub-trench along the first direction; Filling the second sub-trench with an epitaxial material of the first conductivity type to form an intermediate structure; The intermediate structure is thermally treated to form the super junction structure.

9. The method for preparing a superjunction vertical double diffused metal oxide semiconductor device according to claim 5, characterized in that: The step of forming the body region, the source region and the gate comprises: forming a gate on the substrate structure; forming a body region in the substrate structure; A source region is formed in the body region.

10. The method for preparing a superjunction vertical double diffused metal oxide semiconductor device according to claim 9, characterized in that: The step of forming a gate on the substrate structure includes: forming a gate dielectric layer on the substrate structure; A gate conductive layer is formed on the gate dielectric layer.

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