SOI wafer processing method and SOI wafer
By performing thermal oxidation and thinning and rapid heat treatment on the SOI wafer, the processing parameters are controlled, and the slip line problem caused by thermal stress is solved, and SOI wafer processing without slip line is achieved.
Patent Information
- Application Number
- CN202411684546.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-11-19
- Filing Date
- 2024-11-21
- Publication Date
- 2025-03-07
AI Technical Summary
During the non-contact planarization process, the SOI wafer is prone to slip lines caused by thermal stress, which affects the uniformity and roughness of the wafer.
By performing thermal oxidation thinning treatment and rapid heat treatment on the SOI wafer, the removal amount of the top silicon layer and the temperature and time of the rapid heat treatment are controlled to ensure that (X-Y)/(T×t×0.2) is between 0.05 and 0.1.
It effectively avoids the generation of slip lines after rapid heat treatment, and obtains SOI wafers without slip lines, improving the uniformity and roughness of the wafer.
Smart Images
Figure CN119584638A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a processing method of an SOI wafer and an SOI wafer. Background Art
[0002] Silicon on insulator (SOI) technology has now become one of the mainstream products in most electronic materials fields. With the rapid development of smart phones and new energy vehicles, the integration of automotive-grade SOI material on-board chips has gradually increased. Therefore, the market demand for high-uniformity and low-roughness SOI is getting higher and higher.
[0003] In order to replace traditional mechanical chemical polishing, non-contact planarization treatment is now often performed on silicon wafers in heat treatment machines. The temperature during the non-contact planarization process is relatively high. In the heat treatment machine, the position in contact with the wafer usually has thermal stress due to the high temperature process. This thermal stress can easily cause lattice slip during the release process, thereby causing slip lines on the wafer surface, and also causing the slip lines to extend in the subsequent heat treatment, and even cause fragmentation in severe cases. Summary of the invention
[0004] The object of the present invention is to provide a method for processing an SOI wafer and an SOI wafer to solve one or more problems in the prior art.
[0005] In order to solve the above problems, the present invention provides a method for processing an SOI wafer, comprising:
[0006] Providing an SOI wafer, wherein the SOI wafer comprises a substrate silicon layer and a top silicon layer, wherein the top silicon layer and the substrate silicon layer are bonded together, and the thickness of the top silicon layer is X (nm);
[0007] Performing thermal oxidation thinning treatment on the SOI wafer so that the removal amount of the top silicon layer is Y (nm); and,
[0008] Performing a rapid thermal treatment on the SOI wafer, wherein the temperature of the rapid thermal treatment is T (° C.) and the time is t (s);
[0009] Among them, X, Y, T, and t satisfy: 0.05<(XY) / (T×t×0.2)<0.1.
[0010] Optionally, in the processing method of the SOI wafer, the thickness of the top silicon layer is 300nm to 500nm, and the thickness range of the top silicon layer is 1.5nm to 6nm.
[0011] Optionally, in the processing method of the SOI wafer, the SOI wafer also includes a buried oxide layer located between the substrate silicon layer and the top silicon layer, and before the substrate silicon layer and the top silicon layer are bonded to form the SOI wafer, an oxide layer is formed on the surface of the substrate silicon layer, and after the substrate silicon layer and the top silicon layer are bonded, the oxide layer is used as the buried oxide layer, and the thickness of the oxide layer is greater than 20nm and less than 300nm.
[0012] Optionally, in the processing method of the SOI wafer, the SOI wafer is prepared by using a layer transfer technology based on ion implantation.
[0013] Optionally, in the SOI wafer processing method, the step of preparing the SOI wafer using the ion implantation-based layer transfer technology includes:
[0014] implanting ions into the top silicon layer on a side of the top silicon layer where the oxide layer is formed, so as to form an embrittled layer, and,
[0015] peeling off the top silicon layer along the embrittled layer;
[0016] Wherein, when ions are injected into the top silicon layer, the current is 10 mA to 20 mA, the energy is 45 keV to 65 keV, and the dosage is 1 to 6E16.
[0017] Optionally, in the SOI wafer processing method, before performing thermal oxidation thinning treatment on the SOI wafer, the processing method further includes:
[0018] The SOI wafer obtained by peeling is washed on both sides by using a wafer brushing machine.
[0019] Optionally, in the processing method of the SOI wafer, the ions implanted into the top silicon layer are hydrogen ions, or the ions implanted into the top silicon layer are hydrogen ions and helium ions.
[0020] Optionally, in the processing method of the SOI wafer, the step of stripping the top silicon layer is performed in a low-temperature stripping furnace tube.
[0021] Optionally, in the processing method of the SOI wafer, the thickness of the substrate silicon layer is 773um to 775um.
[0022] The present invention also provides an SOI wafer, wherein the SOI wafer is obtained by using the processing method as described in any of the preceding items.
[0023] In summary, the present invention provides a method for processing an SOI wafer and an SOI wafer, comprising: providing an SOI wafer, the SOI wafer comprising a substrate silicon layer and a top silicon layer, the top silicon layer and the substrate silicon layer being bonded together, the thickness of the top silicon layer being X (nm); performing thermal oxidation thinning treatment on the SOI wafer so that the amount of the top silicon layer removed is Y (nm); and performing rapid thermal treatment on the SOI wafer, the temperature of the rapid thermal treatment being T (°C) and the time being t (s); wherein X, Y, T, and t satisfy: 0.05<(XY) / (T×t×0.2)<0.1. The method for processing an SOI wafer provided by the present invention optimizes the overall SOI wafer processing process flow, and by satisfying a set relationship between the thickness of the substrate silicon layer, the thickness of the top silicon layer removed by the thermal oxidation thinning treatment, the temperature of the rapid thermal treatment, and the time of the rapid thermal treatment, the generation of slip lines after the rapid thermal treatment can be avoided, and finally a slip line-free SOI wafer is obtained. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 A flowchart of a method for processing an SOI wafer provided by an embodiment of the present invention;
[0025] Figure 2 to Figure 4 A schematic diagram of the structure corresponding to each step in preparing an SOI wafer using a layer transfer technology based on ion implantation;
[0026] Figure 5 Schematic diagram of surface inspection results after three SOI wafers are processed respectively in an embodiment of the present invention;
[0027] The descriptions of the reference numerals are as follows:
[0028] 10-top silicon layer; 20-oxide layer; 30-embrittlement layer; 40-substrate silicon layer;
[0029] 100 - first silicon wafer; 200 - second silicon wafer; 300 - third silicon wafer. DETAILED DESCRIPTION
[0030] The following is a further detailed description of the SOI wafer processing method and SOI wafer proposed in the present invention in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are all in non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis required to be shown in each drawing is different, and sometimes different proportions are used. It should be recognized that relative terms such as "above", "below", "top", "bottom", "above" and "below" shown in the drawings can be used to describe the relationship between various elements. These relative terms are intended to cover different orientations of elements other than the orientations depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, for example, an element described as "above" another element will now be below the element. It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third" and the like in the specification are only used to distinguish between the various components, elements, steps, etc. in the specification, rather than to represent the logical relationship or sequential relationship between the various components, elements, steps, etc.
[0031] like Figure 1 As shown, an embodiment of the present invention provides a method for processing an SOI wafer, comprising the following steps:
[0032] S1, providing an SOI wafer, wherein the SOI wafer comprises a substrate silicon layer and a top silicon layer, wherein the top silicon layer and the substrate silicon layer are bonded together, and the thickness of the top silicon layer is X (nm);
[0033] S2, performing thermal oxidation thinning treatment on the SOI wafer, wherein the amount of the top silicon layer removed by the thermal oxidation thinning treatment is Y (nm); and
[0034] S3, performing a rapid thermal treatment on the SOI wafer, wherein the temperature of the rapid thermal treatment is T (°C), the time is t (s), and T×t represents the overall thermal budget during the wafer thermal treatment process;
[0035] Among them, X, Y, T, and t satisfy: 0.05<(XY) / (T×t×0.2)<0.1.
[0036] The processing method provided in the embodiment of the present invention optimizes the overall SOI wafer processing process flow. By ensuring that the thickness of the substrate silicon layer, the thickness of the top silicon layer removed by the thermal oxidation thinning treatment, the temperature of the rapid thermal treatment, and the time of the rapid thermal treatment satisfy a set relationship, the generation of slip lines after the rapid thermal treatment can be avoided, and ultimately a slip-line-free SOI wafer can be obtained.
[0037] The above steps are described in further detail below.
[0038] First, step S1 is performed to provide an SOI wafer, wherein the SOI wafer includes a substrate silicon layer and a top silicon layer, and the two are bonded together. Optionally, the thickness of the substrate silicon layer is 773um to 775um.
[0039] A buried oxide layer is formed between the substrate silicon layer and the top silicon layer, and the buried oxide layer is used as an insulating layer between the substrate silicon layer and the top silicon layer.
[0040] The SOI wafer provided in this step mainly refers to the SOI wafer obtained by the layer transfer technology based on ion implantation. After the SOI wafer is obtained by the layer transfer technology based on ion implantation, it is often necessary to perform an oxidation thinning process and a non-contact planarization process on the SOI wafer. The surface of the top silicon layer obtained after peeling is rough and there is a damaged layer. The damaged layer can be removed by the oxidation thinning process, and the surface roughness can be improved by the non-contact planarization process. However, the method provided in this embodiment is also applicable to SOI wafers obtained by other methods, for example, it is also applicable to SOI wafers obtained by oxygen injection separation technology and bonding etch-back technology.
[0041] When preparing SOI wafers using layer transfer technology based on ion implantation, an oxide layer is formed on the surface of the substrate silicon layer, and the oxide layer is used as the buried oxide layer after the substrate silicon layer and the top silicon layer are bonded. Preferably, the thickness of the oxide layer is greater than 10nm and less than 3000nm. If the thickness of the oxide layer is too low, it will affect the bonding and insulation effects. If the thickness of the oxide layer is too high, the wafer will be warped due to the long oxidation process, affecting its flatness. If the oxide layer is within this range, the bonding and insulation effects can be ensured while improving the wafer flatness.
[0042] When SOI wafers are prepared using other technologies, an oxide layer may also be formed on the surface of the substrate silicon layer, or oxide layers may be formed on the surfaces of both the substrate silicon layer and the top silicon layer, and the oxide layers formed on the surfaces of both together constitute the buried oxide layer.
[0043] See also Figure 2 to Figure 4 The steps of preparing the SOI wafer using the ion implantation-based layer transfer technology include: injecting ions into the top silicon layer 10 on the side of the top silicon layer 10 where the oxide layer 20 is formed to form a brittle layer 30; bonding the top silicon layer 10 to the substrate silicon layer 40; and peeling off the top silicon layer 10 along the brittle layer 30.
[0044] Optionally, the ions injected into the top silicon layer 10 are hydrogen ions, or the ions injected into the top silicon layer 10 are hydrogen ions and helium ions. Optionally, the current when injecting ions into the top silicon layer 10 is 10mA to 20mA, the energy is 45keV to 65keV, and the dose is 1 to 6E16. Optionally, the step of stripping the top silicon layer 10 is performed in a low-temperature stripping furnace tube.
[0045] It can be understood that the embrittled layer 30 has an upper surface and a lower surface relative to each other, and the upper surface is closer to the oxide layer 20 than the lower surface. When the top silicon layer 10 is peeled off by thermal reaction, the top silicon layer 10 is divided into two along the lower surface of the embrittled layer 30, so that the thickness of the top silicon layer 10 bonded to the substrate silicon layer 40 is reduced.
[0046] Preferably, in the SOI wafer provided in step S1, the thickness of the top silicon layer 10 is 300nm-500nm, and the thickness range of the top silicon layer 10 is 1.5nm-6nm.
[0047] Next, step S2 is performed to perform thermal oxidation thinning treatment on the SOI wafer. After the thermal oxidation thinning treatment, the surface defects of the top silicon layer 10 are removed.
[0048] Preferably, before performing thermal oxidation thinning treatment on the SOI wafer, the treatment method further comprises: washing the stripped SOI wafer on both sides by using a wafer brushing machine.
[0049] Finally, the SOI wafer is subjected to rapid thermal processing, wherein the temperature of the rapid thermal processing is T (° C.) and the time is t (s).
[0050] It can be understood that the temperature of the rapid thermal treatment described here refers to the highest point temperature of the rapid thermal treatment, that is, the Soak temperature. When the SOI wafer is subjected to rapid thermal treatment, the SOI wafer is loaded into an annealing furnace chamber with a standby temperature. Step-by-step temperature increase oxidation begins, and the temperature in the annealing furnace chamber begins to increase at a certain heating rate. After the temperature in the annealing furnace chamber reaches the Soak temperature, the temperature is kept constant for a certain period of time, and then the temperature in the annealing furnace chamber begins to decrease at a certain cooling rate. When the temperature in the annealing furnace chamber decreases to a certain degree, the SOI wafer is moved out of the annealing furnace chamber.
[0051] In the SOI wafer provided in step S1, the thickness of the top silicon layer 10 is X (nm). In step S2, the removal amount of the top silicon layer 10 is Y (nm), and X, Y, T, and t should satisfy: 0.05<(XY) / (T×t×0.2)<0.1.
[0052] The embodiment of the present invention further provides an SOI wafer, and the SOI wafer is obtained by using the processing method described in this embodiment. Therefore, the surface of the SOI wafer provided by the embodiment of the present invention has no slip line.
[0053] The following further describes the SOI wafer processing method and SOI wafer provided by the embodiment of the present invention by taking examples.
[0054] Provide three device wafers with an oxide layer thickness of 200nm, and perform hydrogen ion implantation on the three device wafers respectively, with an injection current of 10mA, an injection energy of 45keV, and an implantation dose of 3.6E16. Bond the three device wafers after hydrogen ion implantation to a support wafer with a thickness of 773um to 775um to obtain three SOI wafers. The three SOI wafers are subjected to low-temperature stripping furnace tube treatment and stripped to obtain three SOI wafers with a top silicon layer thickness of 360nm. It can be understood that the device wafer is stripped and thinned to obtain the top silicon layer, and the substrate silicon layer is composed of the support wafer. The stripped SOI wafer is double-sided rinsed by a wafer brushing machine, and then the three SOI wafers (the first SOI wafer, the second SOI wafer, and the third SOI wafer) are subjected to the following thermal oxidation treatment and rapid high-temperature thermal annealing treatment respectively:
[0055] (1) The first SOI wafer
[0056] First, thermal oxidation treatment was performed with an oxidation temperature of 950°C, a heating rate of 5°C / min, a cooling rate of 5°C / min, a volume ratio of H2 and O2 of 1:2, and a thickness of 100 nm of the top silicon layer removed by thermal oxidation.
[0057] Then, a rapid heat treatment is performed, during which the highest point temperature (Soak temperature) is 1200°C, the time is 10S, the heating rate and the cooling rate are both 30°C / S, the gas flow rate is 50slm, and the gas atmosphere is argon.
[0058] (2) Second SOI Wafer
[0059] First, thermal oxidation treatment was performed with an oxidation temperature of 950°C, a heating rate of 5°C / min, a cooling rate of 5°C / min, a volume ratio of H2 and O2 of 1:2, and a thickness of 150nm of the top silicon layer removed by thermal oxidation.
[0060] Then, a rapid heat treatment is performed, during which the highest point temperature (Soak temperature) is 1200°C, the time is 10S, the heating rate and the cooling rate are both 30°C / S, the gas flow rate is 50slm, and the gas atmosphere is argon.
[0061] (3) Third SOI Wafer
[0062] First, thermal oxidation treatment was performed with an oxidation temperature of 950°C, a heating rate of 5°C / min, a cooling rate of 5°C / min, a volume ratio of H2 and O2 of 1:2, and a thickness of 250nm of the top silicon layer removed by thermal oxidation.
[0063] Then, a rapid heat treatment is performed, during which the highest point temperature (Soak temperature) is 1200°C, the time is 10S, the heating rate and the cooling rate are both 30°C / S, the gas flow rate is 50slm, and the gas atmosphere is argon.
[0064] By comparison, it can be seen that when the above-mentioned thermal oxidation treatment and rapid thermal treatment are respectively performed on the first SOI wafer, the second SOI wafer and the third SOI wafer, wherein, for the treatment of the first SOI wafer, (XY) / (T×t×0.2)>0.1, for the treatment of the second SOI wafer, 0.05<(XY) / (T×t×0.2)<0.1, and for the treatment of the third SOI wafer, (XY) / (T×t×0.2)<0.05.
[0065] After the first SOI wafer, the second SOI wafer and the third SOI wafer are subjected to the above-mentioned thermal oxidation treatment and rapid thermal treatment respectively, the detection results of the three SOI wafers are shown in Table 1:
[0066] Table 1
[0067] Number of defects Number of sliding lines Curvature(μm) The first SOI wafer 80 0 31.56 Second SOI Wafer 10 0 33.31 The third SOI wafer 11 5 44.1
[0068] It can be seen from Table 1 that when the third SOI wafer 300 is processed, (XY) / (T×t×0.2)<0.05. Since the thickness of the top silicon layer removed by the thermal oxidation treatment is large, the reaction time of the rapid thermal treatment is too long and / or the temperature is too high, resulting in severe deformation of the wafer and more slip lines on the surface. When the second SOI wafer 200 is processed, 0.05<(XY) / (T×t×0.2)<0.1 is satisfied, so its surface defects are well removed, and after the processing is completed, there are no slip lines on its surface. In addition, combined with Figure 5 It can be seen that when the first SOI wafer 100 is processed, (XY) / (T×t×0.2)>0.1. Since the thickness of the top silicon layer removed by the thermal oxidation treatment is small, the reaction time and / or temperature of the rapid thermal treatment is insufficient, resulting in insufficient repair, so that there are many surface defects after the treatment is completed. In Table 1, the number of defects is observed under the 120nm light scattering channel. It can be seen that by adopting the processing method provided by the embodiment of the present invention, by optimizing the overall SOI wafer processing process flow, slip lines can be generated after rapid thermal treatment, and finally a slip-line-free SOI wafer can be obtained.
[0069] In summary, the embodiment of the present invention provides a method for processing an SOI wafer and an SOI wafer, comprising: providing an SOI wafer, the SOI wafer comprising a substrate silicon layer and a top silicon layer, the top silicon layer and the substrate silicon layer being bonded together, the thickness of the top silicon layer being X (nm); performing thermal oxidation thinning treatment on the SOI wafer so that the amount of the top silicon layer removed is Y (nm); and performing rapid thermal treatment on the SOI wafer, the temperature of the rapid thermal treatment being T (℃), and the time being t (s); wherein X, Y, T, and t satisfy: 0.05<(XY) / (T×t×0.2)<0.1. The method for processing an SOI wafer provided in the embodiment of the present invention optimizes the overall SOI wafer processing process flow, and by satisfying the set relationship between the thickness of the substrate silicon layer, the thickness of the top silicon layer removed by the thermal oxidation thinning treatment, the temperature of the rapid thermal treatment, and the time of the rapid thermal treatment, the generation of slip lines after the rapid thermal treatment can be avoided, and finally a slip line-free SOI wafer is obtained.
[0070] It should be noted that, although the present invention has been disclosed as a preferred embodiment, any person skilled in the art can make many possible changes and modifications to the technical solution of the present invention by using the technical content disclosed above without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.
Claims
1. A method for processing an SOI wafer, characterized in that: include: Providing an SOI wafer, wherein the SOI wafer comprises a substrate silicon layer and a top silicon layer, wherein the top silicon layer and the substrate silicon layer are bonded together, and the thickness of the top silicon layer is X (nm); Performing thermal oxidation thinning treatment on the SOI wafer, wherein the amount of the top silicon layer removed by the thermal oxidation thinning treatment is Y (nm); and, Performing a rapid thermal treatment on the SOI wafer, wherein the temperature of the rapid thermal treatment is T (° C.) and the time is t (s); Among them, X, Y, T, and t satisfy: 0.05<(XY) / (T×t×0.2)<0.
1.
2. The method for processing an SOI wafer according to claim 1, wherein: The thickness of the top silicon layer is 300nm-500nm, and the thickness range of the top silicon layer is 1.5nm-6nm.
3. The method for processing an SOI wafer according to claim 2, wherein: The SOI wafer also includes a buried oxide layer located between the substrate silicon layer and the top silicon layer. Before the substrate silicon layer and the top silicon layer are bonded to form the SOI wafer, an oxide layer is formed on the surface of the substrate silicon layer. After the substrate silicon layer and the top silicon layer are bonded, the oxide layer is used as the buried oxide layer. The thickness of the oxide layer is greater than 20nm and less than 300nm.
4. The method for processing an SOI wafer according to claim 3, characterized in that: The SOI wafer is prepared by using a layer transfer technology based on ion implantation.
5. The method for processing an SOI wafer according to claim 4, wherein: The steps of preparing the SOI wafer by using the layer transfer technology based on ion implantation include: implanting ions into the top silicon layer on a side of the top silicon layer where the oxide layer is formed, so as to form an embrittled layer, and, peeling off the top silicon layer along the embrittled layer; Wherein, when ions are injected into the top silicon layer, the current is 10 mA to 20 mA, the energy is 45 keV to 65 keV, and the dosage is 1 to 6E16.
6. The method for processing an SOI wafer according to claim 5, wherein: Before performing thermal oxidation thinning treatment on the SOI wafer, the treatment method further includes: The SOI wafer obtained by peeling is washed on both sides by using a wafer brushing machine.
7. The method for preparing an SOI wafer according to claim 5, wherein: The ions implanted into the top silicon layer are hydrogen ions, or the ions implanted into the top silicon layer are hydrogen ions and helium ions.
8. The method for processing an SOI wafer according to claim 5, wherein: The step of stripping the top silicon layer is performed in a low temperature stripping furnace tube.
9. The method for processing an SOI wafer according to claim 3, characterized in that: The thickness of the substrate silicon layer is 773um-775um.
10. An SOI wafer, characterized in that: The SOI wafer is obtained by using the processing method according to any one of claims 1 to 9.