Micro LED chip and manufacturing method thereof

Abstract

The invention discloses a Micro LED (Light Emitting Diode) chip and a manufacturing method thereof. The Micro LED chip comprises a driving back plate, a plurality of LED chips and a plurality of LED chips, wherein the driving back plate is provided with a pixel driving circuit; the first reflecting layer is arranged on one side of the driving back plate; a plurality of first conductive film layers arranged at intervals; the LED light-emitting units are arranged on the side, away from the driving backboard, of the first conductive film layer; the passivation layer at least covers the side wall of the LED light-emitting unit; the second reflecting layer at least covers the side wall of the passivation layer; a first insulating layer; the second conductive film layer is in contact with the LED light-emitting unit; the concave reflecting layers are arranged on the side, away from the driving back plate, of the first insulating layer, and each concave reflecting layer is arranged around one LED light-emitting unit. The concave reflecting layer can at least reduce light crosstalk between the LED light-emitting units to a certain extent and converge a light divergence angle, so that the light extraction efficiency of the chip is improved.

Description

Technical Field

[0001] The present invention relates to the field of display, and in particular, to a Micro LED chip and a method for manufacturing the same. Background Art

[0002] In the process of manufacturing high PPI (pixel density) InGaN-based RGB full-color MicroLED chips, as the average In component increases, the defect density of the InGaN quantum well structure will increase; in addition, the micro-nano processing process is prone to damage the surface and sidewalls of the MicroLED chip, forming surface / interface states or defect states (non-radiative recombination centers). As the chip size further decreases, the proportion of surface state density increases, resulting in a more significant decrease in the brightness and efficiency of MicroLEDs working under low current injection conditions.

[0003] According to the electro-optical conversion efficiency formula of MicroLED chip η WPE =η IQE ×η extra ×η electr , where η WPE is the electro-optical conversion efficiency of the LED device, η IQE is the internal quantum efficiency of the LED device, η extra is the light extraction efficiency of the LED device, η electr is the electrical injection efficiency of the LED device, η IQE Usually, the improvement is achieved by reducing the material defect density and optimizing the quantum well structure. In addition, the light extraction efficiency (η extra ) and electrical injection efficiency (η electr ) is also to improve the electro-optical conversion efficiency (η WPE ) is the key.

[0004] Therefore, the current Micro LED chips and their manufacturing methods still need to be improved. Summary of the invention

[0005] The present invention aims to alleviate or solve at least one of the above-mentioned problems to at least some extent.

[0006] In one aspect of the present invention, the present invention proposes a Micro LED chip. According to an embodiment of the present invention, the Micro LED chip includes: a driving backplane, the driving backplane has a pixel driving circuit; a first reflective layer, the first reflective layer is arranged on one side of the driving backplane; a plurality of first conductive film layers arranged at intervals, the first conductive film layer is arranged on the side of the first reflective layer away from the driving backplane; a plurality of LED light-emitting units, the plurality of LED light-emitting units are arranged on the side of the first conductive film layer away from the driving backplane; a passivation layer, the passivation layer at least covers the sidewalls of the LED light-emitting units; a second reflective layer, the second reflective layer at least covers the sidewalls of the passivation layer; a first insulating layer, the first insulating layer covers part of the surface of the second reflective layer and part of the surface of the first reflective layer; a second conductive film layer, the second conductive film layer is in contact with the LED light-emitting unit; and a plurality of concave reflective layers, the concave reflective layers are arranged on the side of the first insulating layer away from the driving backplane, and each of the concave reflective layers is arranged around one of the LED light-emitting units. Therefore, the concave reflective layer of the Micro LED chip can at least to a certain extent reduce the light crosstalk between LED light-emitting units (pixels) and converge the light divergence angle. At the same time, it can improve the light extraction efficiency of the chip and thus improve the light-emitting performance of the chip.

[0007] According to an embodiment of the present invention, the Micro LED chip meets at least one of the following conditions: the thickness of the first conductive film layer is 40nm to 100nm; the material of the first conductive film layer includes ITO; the material of the first reflective layer includes at least one of metal silver and metal aluminum; the material of the passivation layer includes at least one of silicon nitride and silicon oxide; the thickness of the passivation layer is 20nm to 200nm; the second reflective layer is a Bragg reflector, and the material of the second reflective layer includes at least one of tantalum oxide, titanium oxide and silicon oxide; the material of the second conductive film layer includes ITO; the thickness of the second conductive film layer is 20nm to 100nm; the material of the concave reflective layer includes at least one of metal silver and metal aluminum; the material of the first insulating layer includes at least one of silicon nitride and silicon oxide. Thus, it is beneficial to further improve the luminous performance of the Micro LED chip and to extend the service life of the Micro LED chip.

[0008] In another aspect of the present invention, a method for making a Micro LED chip is proposed. According to an embodiment of the present invention, the method for making a Micro LED chip includes: providing a substrate; forming an LED light-emitting unit on a surface of one side of the substrate, wherein the formation of the LED light-emitting unit includes the step of forming a quantum well light-emitting layer; forming a first conductive material layer and a first reflective layer in sequence on a side of the LED light-emitting unit away from the substrate; binding a driving backplane on a side of the first reflective layer away from the substrate, wherein the driving backplane has a pixel driving circuit; peeling off the substrate; etching the LED light-emitting unit to form a plurality of spaced LED light-emitting units; forming a passivation layer on a side of the plurality of LED light-emitting units away from the driving backplane, wherein the passivation layer at least covers the sidewalls of the LED light-emitting unit; forming a second reflective layer; and The first conductive material layer is etched to form a plurality of first conductive film layers spaced apart from each other; a first insulating layer is formed, the first insulating layer covers a portion of the surface of the second reflective layer and a portion of the surface of the first reflective layer; the passivation layer and the second reflective layer are etched to expose a portion of the surface of the LED light-emitting unit away from the driving backplane; a second conductive film layer is formed, the second conductive film layer is in contact with the LED light-emitting unit; a plurality of concave reflective layers are formed on the side of the first insulating layer away from the driving backplane, each of the concave reflective layers is arranged around one of the LED light-emitting units. Thus, a Micro LED chip with good luminous performance can be obtained by using this method, and the concave reflective layer of the Micro LED chip can at least reduce the light crosstalk between the LED light-emitting units to a certain extent, converge the light divergence angle, and improve the light extraction efficiency of the chip, thereby improving the luminous performance of the chip.

[0009] According to an embodiment of the present invention, the substrate is a sapphire substrate, and forming the LED light-emitting unit includes: forming an aluminum nitride buffer layer on one side of the substrate; forming an undoped gallium nitride film layer and at least two inorganic insulating mask layers on a side of the aluminum nitride buffer layer away from the substrate, wherein the inorganic insulating mask layer is located in the undoped gallium nitride film layer, and each of the inorganic insulating mask layers includes a hollow region, and the hollow regions in different inorganic insulating mask layers overlap in their orthographic projections on the substrate; epitaxially growing a heavily doped n-type gallium nitride layer on a side of the undoped gallium nitride film layer away from the substrate, wherein the electron concentration of the heavily doped n-type gallium nitride layer is 2×10 18 cm -3 ~1×10 19 cm -3 Alternatively, a periodic n-Al layer is formed on the surface of the non-doped GaN film layer away from the substrate. x Ga 1-xN / n-GaN superlattice structure layer, 0.02≤x≤0.05, periodic n-Al x Ga 1-x The electron concentration of the N / n-GaN superlattice structure layer is 2×10 18 cm -3 ~1×10 19 cm -3 ; Wherein, forming the non-doped gallium nitride film layer and at least two of the inorganic insulating mask layers comprises: epitaxially growing the non-doped gallium nitride film layer, introducing ammonia and silane each time the non-doped gallium nitride with a thickness of 0.5 μm to 1 μm is grown, reacting at 1045° C. to 1065° C. for 10s to 60s to form a silicon nitride grid structure with a thickness of 10nm to 25nm, and subsequently the non-doped gallium nitride continues to nucleate at the openings of the silicon nitride grid structure and epitaxially forms a film on the silicon nitride grid structure until the non-doped gallium nitride is The thickness of the gallium film layer is 3μm to 5μm; or, the non-doped gallium nitride film layer is epitaxially grown, and when the non-doped gallium nitride with a thickness of 0.5μm to 1μm is grown, a silicon nitride film layer or a silicon oxide film layer with a thickness of 10nm to 25nm is formed on the surface of the non-doped gallium nitride away from the substrate, and the silicon nitride film layer or the silicon oxide film layer is etched to form a grid structure or a plurality of spaced strip structures, and the longitudinal section of the strip structure is rectangular or trapezoidal, until the thickness of the non-doped gallium nitride film layer is 3μm to 5μm. Therefore, by inserting multiple layers of inorganic insulating mask layers into the non-doped gallium nitride film layer, the defect density in the non-doped gallium nitride material can be reduced, which is beneficial to improve the internal quantum efficiency of the LED device, and further to improve the electro-optical conversion efficiency of the LED device.

[0010] According to an embodiment of the present invention, the substrate is peeled off by a laser peeling process, and optionally, the pulsed laser wavelength is 355nm, 266nm or 248nm. During the laser peeling process, the inorganic insulating mask layer can absorb part of the laser energy, thereby alleviating the damage of the interface high temperature to the quantum well structure, thereby improving the luminescence performance of the chip; laser peeling can effectively remove the sapphire substrate, and the sapphire substrate is peeled off by a laser with a pulsed laser wavelength of 355nm, 266nm or 248nm, and the peeling effect is better.

[0011] According to an embodiment of the present invention, the substrate is a silicon substrate or a silicon carbide substrate, and forming the LED light-emitting unit includes: forming an aluminum nitride buffer layer on one side of the substrate; forming a gradient Al2O3 on the surface of the aluminum nitride buffer layer away from the substrate; p Ga 1-p N layer, along the direction away from the aluminum nitride buffer layer, the value of p linearly changes from 20% to 30% to 0; in the gradient Al p Ga 1-pA non-doped gallium nitride film layer and at least two inorganic insulating mask layers are formed on a side of the N layer away from the substrate, wherein the inorganic insulating mask layer is located in the non-doped gallium nitride film layer, and each of the inorganic insulating mask layers includes a hollow region, and the hollow regions in different inorganic insulating mask layers overlap with the orthographic projections on the substrate; a heavily doped n-type gallium nitride layer is epitaxially grown on a side of the non-doped gallium nitride film layer away from the substrate, and the electron concentration of the heavily doped n-type gallium nitride layer is 2×10 18 cm -3 ~1×10 19 cm -3 Alternatively, a periodic n-Al layer is formed on the surface of the non-doped GaN film layer away from the substrate. x Ga 1-x N / n-GaN superlattice structure layer, 0.02≤x≤0.05, periodic n-Al x Ga 1-x The electron concentration of the N / n-GaN superlattice structure layer is 2×10 18 cm -3 ~1×10 19 cm -3 ; Wherein, forming the non-doped gallium nitride film layer and at least two of the inorganic insulating mask layers comprises: epitaxially growing the non-doped gallium nitride film layer, introducing ammonia and silane each time the non-doped gallium nitride with a thickness of 0.5 μm to 1 μm is grown, reacting at 1045° C. to 1065° C. for 10s to 60s to form a silicon nitride grid structure with a thickness of 10nm to 25nm, and subsequently the non-doped gallium nitride continues to nucleate at the openings of the silicon nitride grid structure and epitaxially forms a film on the silicon nitride grid structure until the non-doped gallium nitride is The thickness of the gallium film layer is 3μm to 5μm; or, the non-doped gallium nitride film layer is epitaxially grown, and when the non-doped gallium nitride film layer with a thickness of 0.5μm to 1μm is grown, a silicon nitride film layer or a silicon oxide film layer with a thickness of 10nm to 25nm is formed on the surface of the non-doped gallium nitride away from the substrate, and the silicon nitride film layer or the silicon oxide film layer is etched to form a grid structure or a plurality of spaced strip structures, and the longitudinal section of the strip structure is rectangular or trapezoidal, until the thickness of the non-doped gallium nitride film layer is 3μm to 5μm. Thus, the gradient Al p Ga 1-p The N layer is arranged on an aluminum nitride buffer layer and a heavily doped gallium nitride layer or a periodic n-Al x Ga 1- xIt can play a good transition role between N / n-GaN superlattice structures; inserting multiple layers of inorganic insulating mask layers into the non-doped gallium nitride film layer can at least reduce the defect density in the non-doped gallium nitride material to a certain extent, which is beneficial to improve the internal quantum efficiency of the LED device, and then help improve the electro-optical conversion efficiency of the LED device.

[0012] According to an embodiment of the present invention, the substrate is a silicon carbide substrate, and forming the LED light-emitting unit includes: forming an n-type doped AlGaN buffer layer on one side of the substrate; epitaxially growing a heavily doped n-type gallium nitride layer on a surface of the n-type doped AlGaN buffer layer away from the substrate, wherein the electron concentration of the heavily doped n-type gallium nitride layer is 2×10 18 cm -3 ~1×10 19 cm -3 Alternatively, a periodic n-Al2O3 layer is formed on the surface of the n-type doped AlGaN buffer layer away from the substrate. x Ga 1-x N / n-GaN superlattice structure layer, 0.02≤x≤0.05, periodic n-Al x Ga 1-x The electron concentration of the N / n-GaN superlattice structure layer is 2×10 18 cm -3 ~1×10 19 cm -3 Alternatively, a heavily doped n-type gallium nitride layer and at least two inorganic insulating mask layers are epitaxially grown on the side of the n-type doped AlGaN buffer layer away from the substrate, and the electron concentration of the heavily doped n-type gallium nitride layer is 2×10 18 cm -3 ~1×10 19 cm -3 , the inorganic insulating mask layer is located in the heavily doped n-type gallium nitride layer, and each of the inorganic insulating mask layers includes a hollow region, and the hollow regions in different inorganic insulating mask layers overlap with each other in orthographic projection on the substrate; or, a periodic n-Al is formed on the side of the n-type doped AlGaN buffer layer away from the substrate x Ga 1-x N / n-GaN superlattice structure layer and at least two inorganic insulating mask layers, 0.02≤x≤0.05, periodic n-Al x Ga 1-x The electron concentration of the N / n-GaN superlattice structure layer is 2×10 18 cm -3 ~1×10 19 cm -3 The inorganic insulating mask layer is located on the periodic n-Al x Ga1-x In the N / n-GaN superlattice structure layer, each of the inorganic insulating mask layers includes a hollow region, and the orthographic projections of the hollow regions in different inorganic insulating mask layers on the substrate overlap. This is beneficial to reducing the defect density in the material, thereby facilitating the improvement of the internal quantum efficiency of the LED device, and further facilitating the improvement of the electro-optical conversion efficiency of the LED device.

[0013] According to an embodiment of the present invention, the substrate is a gallium nitride substrate, and forming the LED light-emitting unit comprises: epitaxially growing a heavily doped n-type gallium nitride layer on a surface of one side of the substrate, wherein the electron concentration of the heavily doped n-type gallium nitride layer is 2×10 18 cm -3 ~1×10 19 cm -3 Alternatively, a periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer, 0.02≤x≤0.05, periodic n-Al x Ga 1-x The electron concentration of the N / n-GaN superlattice structure layer is 2×10 18 cm -3 ~1×10 19 cm -3 Alternatively, a heavily doped n-type gallium nitride layer and at least two inorganic insulating mask layers are formed on one side of the substrate, wherein the electron concentration of the heavily doped n-type gallium nitride layer is 2×10 18 cm -3 ~1×10 19 cm -3 , the inorganic insulating mask layer is located in the heavily doped n-type gallium nitride layer, and each of the inorganic insulating mask layers includes a hollow region, and the hollow regions in different inorganic insulating mask layers overlap in their orthographic projections on the substrate; or, a periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer and at least two inorganic insulating mask layers, 0.02≤x≤0.05, periodic n-Al x Ga 1-x The electron concentration of the N / n-GaN superlattice structure layer is 2×10 18 cm -3 ~1×10 19 cm -3 The inorganic insulating mask layer is located on the periodic n-Al x Ga 1-xIn the N / n-GaN superlattice structure layer, each of the inorganic insulating mask layers includes a hollow region, and the orthographic projections of the hollow regions in different inorganic insulating mask layers on the substrate overlap. This is beneficial to reducing the defect density in the material, thereby improving the internal quantum efficiency of the LED device, and further improving the electro-optical conversion efficiency of the LED device.

[0014] According to an embodiment of the present invention, forming the LED light emitting unit further comprises: in the heavily doped n-type gallium nitride layer or the periodic n-Al x Ga 1-x A lightly doped n-type gallium nitride layer is formed on the side of the N / n-GaN superlattice structure layer away from the substrate, and the electron concentration of the lightly doped n-type gallium nitride layer is 1×10 17 cm -3 ~5×10 17 cm -3 ; forming a first barrier layer on the side of the lightly doped n-type gallium nitride layer away from the substrate; sequentially growing 3 to 5 periods of non-doped In on the side of the first barrier layer away from the substrate y Ga 1-y N / GaN quantum well structure and 3 to 5 periods of non-doped In z Ga 1-z N / GaN quantum well structure, wherein 0.01≤y≤0.03, 0.03≤z≤0.05; in the non-doped In z Ga 1-z A blue light quantum well light emitting layer, a green light quantum well light emitting layer and a red light quantum well light emitting layer are grown on the side of the N / GaN quantum well structure away from the substrate; and a non-doped gallium nitride protection layer, an electron blocking layer, a hole injection layer and an ohmic contact layer are sequentially formed on the side of the quantum well light emitting layer away from the substrate. This is conducive to further improving the light emitting performance of the LED device and providing a better user experience.

[0015] According to an embodiment of the present invention, forming the blue light quantum well light emitting layer comprises: in the non-doped In z Ga 1-z The side of the N / GaN quantum well structure away from the substrate sequentially forms a first non-doped GaN layer, an In a Ga 1-a N potential well layer, second undoped GaN layer, In b Ga 1-b N barrier layer, wherein 0.18≤a≤0.21, 0.01≤b≤0.05; forming the green light quantum well light-emitting layer comprises: in the non-doped In z Ga 1-z The N / GaN quantum well structure grows 1 to 2 periods of In on the side away from the substrate. cGa 1-c N / n-type GaN quantum well structure and 2 to 3 periods of In d Ga 1-d N / n-type GaN quantum well structure, growing In c Ga 1- c The N / n-type GaN quantum well structure includes a third non-doped GaN layer, an In c Ga 1-c N potential well layer, the fourth non-doped GaN layer and the first n-type GaN barrier layer, grow In d Ga 1-d The N / n-type GaN quantum well structure includes a fifth non-doped GaN layer, an In d Ga 1-d N potential well layer, a sixth non-doped GaN layer, a second n-type GaN barrier layer, wherein 0.24≤c≤0.25, 0.25≤d≤0.28; forming the red light quantum well light-emitting layer comprises: in the non-doped In z Ga 1-z The N / GaN quantum well structure forms a seventh undoped GaN layer, an In e Ga 1-e N potential well layer, eighth undoped GaN layer, In f Ga 1-f N barrier layer, ninth undoped GaN layer, In g Ga 1-g N potential well layer, tenth undoped GaN layer, p-type doped GaN barrier layer, Al h Ga 1-h N layers, wherein 0.18≤e≤0.21, 0.01≤f≤0.05, 0.35≤g≤0.38, 0.10≤h≤0.30. Thus, the blue light quantum well light emitting layer, the green light quantum well light emitting layer and the red light quantum well light emitting layer all have good light emitting performance and good stability, which is conducive to further improving the light emitting performance of the chip and further extending the service life of the chip.

[0016] According to an embodiment of the present invention, the method for making Micro LED satisfies at least one of the following conditions: the thickness of the aluminum nitride buffer layer is 10nm to 50nm; the temperature for forming the undoped gallium nitride film layer is 1045°C to 1065°C; the temperature for epitaxially growing the heavily doped n-type gallium nitride layer is 1040°C to 1060°C, and silane is an n-type dopant; the periodic n-Al x Ga 1-x In the N / n-GaN superlattice structure layer, in each period, n-Al x Ga 1-xThe thickness of N is 2nm to 3nm, and the thickness of n-GaN is 5nm to 10nm; the periodic n-Al x Ga 1-x The film forming temperature of the N / n-GaN superlattice structure layer is 1060°C to 1080°C; the temperature for forming the lightly doped n-type gallium nitride layer is 1040°C to 1060°C; the thickness of the lightly doped n-type gallium nitride layer is 0.3μm to 0.5μm; the thickness of the first barrier layer is 15nm to 30nm; the non-doped In y Ga 1-y In each period of the N / GaN quantum well structure, In y Ga 1-y The thickness of N is 2.5nm~3.5nm, the thickness of GaN is 5nm~15nm; the thickness of non-doped In z Ga 1-z In each period of the N / GaN quantum well structure, In z Ga 1-z The thickness of N is 2.5nm to 3.5nm, the thickness of GaN is 5nm to 15nm; the thickness of the first non-doped GaN layer and the thickness of the second non-doped GaN layer are independently 1nm to 5nm; the In a Ga 1-a The thickness of the N potential well layer is 2.5nm to 3.5nm; b Ga 1-b The thickness of the N barrier layer is 5nm to 15nm; the thickness of the third undoped GaN layer, the thickness of the fourth undoped GaN layer, the thickness of the fifth undoped GaN layer, the thickness of the sixth undoped GaN layer, the thickness of the seventh undoped GaN layer, the thickness of the eighth undoped GaN layer, the thickness of the ninth undoped GaN layer, and the thickness of the tenth undoped GaN layer are each independently 1nm to 3nm; the In c Ga 1-c The thickness of the N potential well layer, the In d Ga 1-d The thickness of the N barrier layer, the In e Ga 1-e The thickness of the N potential well layer, the In g Ga 1-g The thickness of the N potential well layer is independently 2.5nm to 3.5nm; the thickness of the first n-type GaN barrier layer, the thickness of the second n-type GaN barrier layer, the thickness of the In f Ga 1-f The thickness of the N barrier layer and the thickness of the p-type doped GaN barrier layer are independently 5nm to 15nm; h Ga 1-hThe thickness of the N layer is 1nm to 2nm; the thickness of the non-doped gallium nitride protective layer is 15nm to 30nm; the thickness of the electron blocking layer is 60nm to 70nm, and the material of the electron blocking layer is p-type doped Al q Ga 1-q N, in the direction away from the substrate, the value of q linearly changes from 20% to 30% to 0; the hole injection layer is 8 to 16 periods of p-Al i Ga 1-i N / p-GaN superlattice structure, the hole concentration of the hole injection layer is 1.5×10 18 cm -3 ~3.5×10 18 cm -3 In each cycle, p-Al i Ga 1-i The thickness of N is 2.5nm to 3.5nm, the thickness of p-GaN is 5nm to 8nm, 0.10≤i≤0.20; the material of the ohmic contact layer is heavily doped p-GaN, and the thickness of the ohmic contact layer is 20nm to 40nm. This is conducive to further improving the overall performance of the manufactured Micro LED chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0018] Figure 1 A schematic diagram showing the structure of a Micro LED chip according to an embodiment of the present invention is shown;

[0019] Figure 2 A schematic diagram showing the structure of a Micro LED chip according to another embodiment of the present invention is shown;

[0020] Figure 3 A schematic diagram showing a partial process of manufacturing a Micro LED chip according to an embodiment of the present invention;

[0021] Figure 4 A schematic structural diagram of an inorganic insulating mask layer according to an embodiment of the present invention is shown;

[0022] Figure 5 A schematic structural diagram of an inorganic insulating mask layer according to an embodiment of the present invention is shown;

[0023] Figure 6 A schematic diagram showing the structure of a substrate, an aluminum nitride buffer layer, a non-doped gallium nitride layer and an inorganic insulating mask layer according to an embodiment of the present invention is shown;

[0024] Figure 7A schematic diagram showing the structure of a substrate, an aluminum nitride buffer layer, a non-doped gallium nitride layer and an inorganic insulating mask layer according to another embodiment of the present invention is shown;

[0025] Figure 8 A schematic diagram showing a partial process of manufacturing a Micro LED chip according to an embodiment of the present invention;

[0026] Fig. 9 A schematic diagram showing a partial process of manufacturing a Micro LED chip according to an embodiment of the present invention;

[0027] Fig.10 A schematic diagram showing a partial process of manufacturing a Micro LED chip according to an embodiment of the present invention;

[0028] Fig.11 A schematic diagram showing a partial process of manufacturing a Micro LED chip according to an embodiment of the present invention;

[0029] Fig.12 A schematic diagram showing a partial process of manufacturing a Micro LED chip according to an embodiment of the present invention;

[0030] Fig.13 A schematic diagram showing a partial process of manufacturing a Micro LED chip according to an embodiment of the present invention;

[0031] Fig.14 A schematic diagram showing a partial process of manufacturing a Micro LED chip according to an embodiment of the present invention;

[0032] Fig.15 A schematic diagram of a part of the structure in the process of manufacturing a Micro LED chip according to an embodiment of the present invention is shown;

[0033] Fig.16 A schematic diagram of a part of the structure in the process of manufacturing a Micro LED chip according to an embodiment of the present invention is shown;

[0034] Fig.17 A schematic diagram of a part of the structure in the process of manufacturing a Micro LED chip according to an embodiment of the present invention is shown;

[0035] Fig.18 A partial schematic diagram of the process of manufacturing a Micro LED chip according to an embodiment of the present invention is shown.

[0036] Description of reference numerals:

[0037] 1: first insulating layer; 2: second insulating layer; 3 substrate; 4: aluminum nitride buffer layer; 4': n-type doped AlGaN buffer layer; 5: undoped gallium nitride layer; 6: inorganic insulating mask layer; 7: dislocation; 8: gradient Al p Ga 1-p N layer; 10: driving backplane; 20: first reflective layer; 30: first conductive material layer; 31: first conductive film layer; 40: LED light-emitting unit; 41: heavily doped n-type gallium nitride layer; 41': periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer; 42: lightly doped n-type gallium nitride layer; 43: first barrier layer; 44: quantum well light-emitting layer; 45: non-doped gallium nitride protection layer; 46: electron blocking layer; 47: hole injection layer; 48: ohmic contact layer; 50: passivation layer; 60: second reflection layer; 70: second conductive film layer; 80: n-type ohmic contact electrode; 90: concave reflection layer. DETAILED DESCRIPTION

[0038] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0039] In one aspect of the present invention, the present invention provides a Micro LED chip. According to an embodiment of the present invention, referring to Figure 1 and Figure 2The Micro LED chip may include: a driving backplane 10, the driving backplane 10 having a pixel driving circuit; a first reflective layer 20, the first reflective layer 20 is arranged on one side of the driving backplane 10; a plurality of first conductive film layers 31 arranged at intervals, the first conductive film layer 31 is arranged on a side of the first reflective layer 20 away from the driving backplane 10; a plurality of LED light-emitting units, the plurality of LED light-emitting units are arranged on a side of the first conductive film layer 31 away from the driving backplane 10; a passivation layer 50, the passivation layer 50 at least covers the side wall of the LED light-emitting unit; a second reflective layer 60, the second reflective layer 60 at least covers the side wall of the passivation layer 50; a first insulating layer 1, the first insulating layer 1 covers a portion of the surface of the second reflective layer 60 and a portion of the surface of the first reflective layer 20; a second conductive film layer 70, the second conductive film layer 70 is in contact with the LED light-emitting unit; and a plurality of concave reflective layers 90, the concave reflective layers 90 are arranged on a side of the first insulating layer 1 away from the driving backplane 10, and each concave reflective layer 90 is arranged around an LED light-emitting unit. Therefore, the concave reflective layer in the Micro LED chip has a good reflective effect, which can reduce the light crosstalk between LED light-emitting units (pixels) and converge the light divergence angle. At the same time, it can at least improve the light extraction efficiency of the chip to a certain extent, thereby improving the luminescence performance of the chip.

[0040] According to some specific embodiments of the present invention, the concave reflective layer 90 may be Figure 1 and Figure 2 In the three-dimensional bowl-shaped structure shown in FIG, the opening of the concave reflective layer 90 gradually increases in the direction away from the driving back plate 10 .

[0041] According to some embodiments of the present invention, reference Figure 1 and Figure 2 The passivation layer 50 is arranged on the side of the LED light-emitting unit 40 away from the driving backplane 10, and the passivation layer 50 can cover the side wall of the LED light-emitting unit, at least part of the surface of the first conductive film layer 31 away from the driving backplane 10, and part of the surface of the LED light-emitting unit 40 away from the driving backplane 10; the second reflective layer 60 is arranged on the side of the passivation layer 50 away from the driving backplane 10, and the second reflective layer 60 can cover at least part of the surface of the passivation layer 50 away from the driving backplane 10; the second conductive film layer 70 can cover at least part of the surface of the first insulating layer 1 away from the driving backplane 10 and at least part of the surface of the second reflective layer 60 away from the driving backplane 10.

[0042] According to some specific embodiments of the present invention, Figure 1 and Figure 2The Micro LED chip may further include a plurality of spaced-apart n-type ohmic contact electrodes 80 , the n-type ohmic contact electrodes 80 may be disposed on a side of the second conductive film layer 70 away from the driving backplane 10 , and each n-type ohmic contact electrode 80 may be disposed around an LED light-emitting unit 40 ; a concave reflective layer 90 may be disposed on a side of the n-type ohmic contact electrode 80 away from the driving backplane 10 , and the concave reflective layer 90 may be disposed in contact with the n-type ohmic contact electrode 80 .

[0043] According to some specific embodiments of the present invention, Figure 1 and Figure 2 The Micro LED chip may further include a second insulating layer 2, which may be disposed on a side of the second conductive film layer 60 away from the driving backplane 10, and the second insulating layer 2 covers at least a portion of the surface of the second conductive film layer 60, at least a portion of the surface of the n-type ohmic contact electrode 80, and at least a portion of the surface of the concave reflective layer 90. Thus, the second insulating layer may achieve electrical insulation between the LED light-emitting unit surfaces, thereby further extending the service life of the chip.

[0044] It should be noted that Figure 1 and Figure 2 Two LED light-emitting units 40, two n-type ohmic contact electrodes 80, and two concave reflective layers 90 are shown, which are not used to limit the present invention. Those skilled in the art can set the number of LED light-emitting units and the number of n-type ohmic contact electrodes and concave reflective layers accordingly according to actual needs.

[0045] According to some embodiments of the present invention, reference Figure 2 The Micro LED chip can be based on InGaN (indium gallium nitride) material, and the LED light emitting unit 40 can include a heavily doped n-type gallium nitride layer 41 or a periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer 41', lightly doped n-type gallium nitride layer 42, first barrier layer 43, quantum well light-emitting layer 44, undoped gallium nitride protection layer 45, electron blocking layer 46, hole injection layer 47 and ohmic contact layer 48, the quantum well light-emitting layer may include a red light quantum well light-emitting layer, a green light quantum well light-emitting layer and a blue light quantum well light-emitting layer.

[0046] According to some other embodiments of the present invention, the Micro LED chip may also be based on AlGaInP (aluminum gallium indium phosphide) material, wherein the quantum well light-emitting layer is a red light quantum well light-emitting layer.

[0047] According to some embodiments of the present invention, the thickness of the first conductive film layer 31 can be 40nm to 100nm. For example, the thickness of the first conductive film layer 31 can be 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, or 100nm. Thus, the first conductive film layer has a thinner thickness and better light transmittance (≥85%). In addition, the first conductive film has a smaller resistance and better conductivity.

[0048] According to some embodiments of the present invention, the material of the first conductive film layer 31 may include ITO (indium tin oxide). For example, the first conductive film layer may be composed of ITO. Thus, the first conductive film layer has good conductivity, and the LED light-emitting unit can emit light by applying voltage thereon.

[0049] According to some embodiments of the present invention, the material of the first reflective layer 20 may include at least one of metallic silver and metallic aluminum, whereby the first reflective layer has a good reflective effect, which can at least to a certain extent improve the light extraction efficiency of the chip, and is conducive to improving the luminous effect of the chip. According to some specific embodiments of the present invention, the material of the first reflective layer 20 may be metallic silver. According to other specific embodiments of the present invention, the material of the first reflective layer 20 may be metallic aluminum.

[0050] According to some embodiments of the present invention, the material of the passivation layer 50 may include at least one of silicon nitride and silicon oxide, so that the passivation layer has good insulation properties, which is beneficial to improving the overall performance of the chip.

[0051] According to some embodiments of the present invention, the thickness of the passivation layer 50 may be 20 nm to 200 nm. For example, the thickness of the passivation layer 50 may be 20 nm, 50 nm, 80 nm, 100 nm, 150 nm, 200 nm, etc.

[0052] According to some embodiments of the present invention, the second reflective layer 60 may be a Bragg reflector (DBR), and the material of the second reflective layer 60 may include at least one of tantalum oxide, titanium oxide and silicon oxide. Thus, the second reflective layer may further improve the light extraction efficiency of the chip, thereby improving the luminescence effect of the chip.

[0053] According to some embodiments of the present invention, the material of the second conductive film layer 70 may include ITO, so that the second conductive film layer has good conductivity, which is beneficial to improving the overall performance of the chip.

[0054] According to some embodiments of the present invention, the thickness of the second conductive film layer 70 can be 20nm to 100nm. For example, the thickness of the second conductive film layer 70 can be 20nm, 40nm, 50nm, 80nm, 100nm, etc. Therefore, the second conductive film layer has a higher transmittance and a lower resistance, which is beneficial to further improve the overall performance of the chip.

[0055] According to some embodiments of the present invention, the material of the n-type ohmic contact electrode 80 may include at least one of metal titanium, metal aluminum and metal gold, whereby the n-type ohmic contact electrode has excellent conductivity, which is beneficial to further improve the overall performance of the chip. According to some specific embodiments of the present invention, the n-type ohmic contact electrode may include multiple metal layers, for example, may include a titanium layer, an aluminum layer, a titanium layer and a gold layer stacked in sequence.

[0056] According to some embodiments of the present invention, the material of the concave reflective layer 90 may include at least one of metal silver and metal aluminum. Thus, the concave reflective layer formed by the above materials has a good reflective effect, can reduce the light crosstalk between the light-emitting units, converge the light divergence angle, and at the same time, can improve the light extraction efficiency of the chip.

[0057] According to some embodiments of the present invention, the material of the first insulating layer 1 and the material of the second insulating layer 2 independently include at least one of silicon nitride and silicon oxide, that is, the material of the first insulating layer 1 may include at least one of silicon nitride and silicon oxide, and the material of the second insulating layer 2 may include at least one of silicon nitride and silicon oxide. Thus, the first insulating layer and / or the second insulating layer has good insulation and can achieve good electrical insulation.

[0058] In another aspect of the present invention, the present invention provides a method for manufacturing a Micro LED chip. According to an embodiment of the present invention, the method for manufacturing a Micro LED chip may include the following steps:

[0059] S1: providing a substrate.

[0060] A substrate is provided. According to some embodiments of the present invention, the substrate may be a sapphire substrate, a silicon substrate, a silicon carbide substrate or a gallium nitride substrate.

[0061] S2: forming an LED light-emitting unit on one side surface of the substrate.

[0062] An LED light-emitting unit is formed on one side surface of the substrate, wherein forming the LED light-emitting unit may include a step of forming a quantum well light-emitting layer. The steps of forming the LED light-emitting unit are described in detail below in conjunction with a substrate of a specific material.

[0063] According to some embodiments of the present invention, reference Figure 3 , the substrate 3 is a sapphire substrate, and the formation of the LED light-emitting unit includes: forming an aluminum nitride buffer layer 4 on one side of the substrate 3; forming an undoped gallium nitride film layer 5 and at least two inorganic insulating mask layers 6 on the side of the aluminum nitride buffer layer 4 away from the substrate 3, the inorganic insulating mask layer 6 is located in the undoped gallium nitride film layer 5, and each inorganic insulating mask layer includes a hollow region (the hollow region can continue to grow undoped gallium nitride), and the orthographic projections of the hollow regions in different inorganic insulating mask layers 6 on the substrate overlap; epitaxially growing a heavily doped n-type gallium nitride layer 41 on the side of the undoped gallium nitride film layer 5 away from the substrate 3, and the electron concentration of the heavily doped n-type gallium nitride layer 41 can be 2×10 18 cm -3 ~1×10 19 cm -3 Alternatively, a periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer 41 ′, wherein 0.02≤x≤0.05, periodic n-Al x Ga 1-x The electron concentration of the N / n-GaN superlattice structure layer 41 ′ may be 2×10 18 cm -3 ~1×10 19 cm -3 The formation of at least two inorganic insulating mask layers can effectively block the dislocations from extending upward and reduce the density of penetrating dislocations, thereby facilitating the improvement of the internal quantum efficiency of the LED device; the orthographic projections of the hollowed-out areas in different inorganic insulating mask layers 6 on the substrate overlap, and in the process of manufacturing the inorganic insulating mask layers, different inorganic insulating mask layers can use the same mask plate, thereby saving the cost of the mask plate and reducing the manufacturing cost of the chip.

[0064] When substrate 3 is a sapphire substrate, the lattice mismatch between the aluminum nitride buffer layer and the sapphire substrate is small (the lattice mismatch is about 13%), which is beneficial to reducing the threading dislocation density of the subsequently grown non-doped gallium nitride film layer, thereby improving the overall performance of the chip.

[0065] According to an embodiment of the present invention, the number of the inorganic insulating mask layer 6 may be two layers (eg Figure 3 As shown), 3 layers, 4 layers, etc.

[0066] According to some embodiments of the present invention, the thickness of the aluminum nitride buffer layer 4 may be 10 nm to 50 nm. For example, the thickness of the aluminum nitride buffer layer 4 may be 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, etc.

[0067] According to some embodiments of the present invention, when the substrate 3 is a sapphire substrate, forming the non-doped gallium nitride film layer 5 and at least two inorganic insulating mask layers 6 may include: epitaxially growing the non-doped gallium nitride film layer, each time the non-doped gallium nitride with a thickness of 0.5 μm to 1 μm is grown, ammonia and silane are introduced, and reacted at 1045° C. to 1065° C. for 10s to 60s to form a silicon nitride grid structure with a thickness of 10nm to 25nm, and the inorganic insulating mask layer 6 with a grid structure is as follows: Figure 4 As shown, the subsequent non-doped gallium nitride can continue to nucleate at the openings (hollow structures 6') of the silicon nitride grid structure and epitaxially form a film on the silicon nitride grid structure until the thickness of the non-doped gallium nitride film layer 5 is 3μm to 5μm. The reaction time after the introduction of ammonia and silane is short, the silicon nitride will not be completely film-formed, and a silicon nitride grid structure can be formed. The subsequent non-doped gallium nitride can continue to nucleate at the openings and epitaxially form a film on the upper side of the grid structure film layer (ELOG growth mode, i.e., epitaxial lateral overgrowth mode); the mask layer can prevent dislocations from extending upward. According to some specific embodiments of the present invention, MOCVD (metal-organic chemical vapor deposition) equipment can be used to epitaxially grow a non-doped gallium nitride film layer, and a silicon nitride grid structure can be grown in situ in stages. The temperature for forming the non-doped gallium nitride film layer 5 can be 1045°C to 1065°C.

[0068] According to other embodiments of the present invention, when the substrate 3 is a sapphire substrate, forming the non-doped gallium nitride film layer 5 and at least two inorganic insulating mask layers 6 may include: epitaxially growing the non-doped gallium nitride film layer, each time the non-doped gallium nitride with a thickness of 0.5 μm to 1 μm is grown, a silicon nitride film layer or a silicon oxide film layer with a thickness of 10 nm to 25 nm is formed on the surface of the non-doped gallium nitride away from the substrate 3, the silicon nitride film layer or the silicon oxide film layer is a whole layer structure, and the silicon nitride film layer or the silicon oxide film layer is etched to form a grid structure (such as Figure 4 as shown) or multiple spaced strip structures (as shown Figures 5 to 7 As shown), the longitudinal section of the strip structure is a rectangle (as shown Figure 5 and Figure 7 as shown) or trapezoidal (as Figure 6As shown), until the thickness of the non-doped gallium nitride film layer 5 is 3μm to 5μm. In this process, a non-doped gallium nitride film layer can be epitaxially grown using MOCVD (metal-organic chemical vapor deposition) equipment, and an inorganic insulating mask layer can be epitaxially grown using PECVD (plasma enhanced chemical vapor deposition) equipment, epitaxially growing 0.5μm to 1μm non-doped gallium nitride, taking the sample out of the reaction chamber, growing a 10nm to 25nm thick silicon nitride film layer or a silicon oxide film layer by PECVD, and etching the silicon nitride film layer or the silicon oxide film layer into a grid structure or a plurality of spaced strip structures by photolithography and ICP-RIE (inductively coupled plasma etching) processes, and repeating the above steps until the thickness of the non-doped gallium nitride film layer reaches 3μm to 5μm. This method can effectively reduce the dislocation density in the non-doped GaN film layer, and the residual dislocation distribution pattern can be followed. In the subsequent pixel formation process, the pixels can be distributed in low-dislocation or dislocation-free areas, which is conducive to the setting of small-size pixels. Figure 6 and Figure 7 , where the strip structure is provided, the density of dislocations 7 of the non-doped gallium nitride film layer is low or even there is no dislocation 7, and pixels can be subsequently formed in the corresponding area, thereby improving the internal quantum efficiency and luminescence performance of the LED device.

[0069] According to some embodiments of the present invention, the substrate 3 may be a silicon substrate or a silicon carbide substrate. Figure 8 The formation of the LED light-emitting unit may include: forming an aluminum nitride buffer layer 4 on one side of the substrate 3; forming a gradient Al p Ga 1-p In the direction away from the aluminum nitride buffer layer 4, the value of p in the N layer 8 is linearly changed from 20% to 30% to 0; p GaN 1-p A non-doped gallium nitride film layer 5 and at least two inorganic insulating mask layers 6 are formed on the side of the layer 8 away from the substrate 3. The inorganic insulating mask layer 6 is located in the non-doped gallium nitride film layer 5, and each inorganic insulating mask layer 6 includes a hollow region. The hollow regions in different inorganic insulating mask layers 6 overlap in their orthographic projections on the substrate 3. A heavily doped n-type gallium nitride layer 41 is epitaxially grown on the side of the non-doped gallium nitride film layer 5 away from the substrate 3. The electron concentration of the heavily doped n-type gallium nitride layer 41 is 2×10 18 cm -3 ~1×10 19 cm -3 Alternatively, a periodic n-Al x Ga 1- x N / n-GaN superlattice structure layer 41 ′, 0.02≤x≤0.05, periodic n-Alx Ga 1-x The electron concentration of the N / n-GaN superlattice structure layer 41 ′ is 2×10 18 cm -3 ~1×10 19 cm -3 . Set the gradient Al p Ga 1-p The N layer can realize the transition from the aluminum nitride buffer layer to gallium nitride, which is beneficial to improving the performance of the chip; the inorganic insulating mask layer can effectively reduce the dislocation density and prevent dislocations from extending upward.

[0070] According to some specific embodiments of the present invention, when the substrate 3 can be a silicon substrate or a silicon carbide substrate, the formation of the undoped gallium nitride film layer 5 and at least two inorganic insulating mask layers 6 can include: epitaxially growing the undoped gallium nitride film layer, introducing ammonia and silane every time the undoped gallium nitride with a thickness of 0.5μm to 1μm is grown, and reacting at 1045℃ to 1065℃ for 10s to 60s to form a silicon nitride grid structure with a thickness of 10nm to 25nm, and subsequently the undoped gallium nitride continues to nucleate at the openings (hollow areas) of the silicon nitride grid structure and epitaxially forms a film on the silicon nitride grid structure until the thickness of the undoped gallium nitride film layer is 3μm to 5μm. In this process, MOCVD (metal-organic chemical vapor deposition) equipment can be used to epitaxially grow a non-doped gallium nitride film layer, and a silicon nitride grid structure can be grown in situ in stages. The temperature for forming the non-doped gallium nitride film layer 5 can be 1045°C to 1065°C, which is the same as the temperature for forming the silicon nitride grid structure.

[0071] According to some other specific embodiments of the present invention, when the substrate 3 may be a silicon substrate or a silicon carbide substrate, forming the non-doped gallium nitride film layer 5 and at least two inorganic insulating mask layers 6 may include: epitaxially growing the non-doped gallium nitride film layer, and when each non-doped gallium nitride with a thickness of 0.5 μm to 1 μm is grown, a silicon nitride film layer or a silicon oxide film layer with a thickness of 10 nm to 25 nm is formed on the surface of the non-doped gallium nitride away from the substrate, the silicon nitride film layer or the silicon oxide film layer is a whole layer structure, and the silicon nitride film layer or the silicon oxide film layer is etched to form a grid structure (such as Figure 4 as shown) or multiple spaced strip structures (as shown Figure 8 As shown), the longitudinal section of the strip structure is a rectangle (as shown Figure 8As shown) or trapezoidal, until the thickness of the non-doped gallium nitride film layer is 3μm to 5μm. In this process, a non-doped gallium nitride film layer can be epitaxially grown using MOCVD (metal-organic chemical vapor deposition) equipment, and an inorganic insulating mask layer can be epitaxially grown using PECVD (plasma enhanced chemical vapor deposition) equipment, epitaxially growing 0.5μm to 1μm non-doped gallium nitride, taking the sample out of the reaction chamber, growing a 10nm to 25nm thick silicon nitride film layer or a silicon oxide film layer by PECVD, etching the silicon nitride film layer or the silicon oxide film layer into a grid structure or a plurality of spaced strip structures by photolithography and ICP-RIE (inductively coupled plasma etching) processes, and repeating the above steps until the thickness of the non-doped gallium nitride film layer reaches 3μm to 5μm. This method can effectively reduce the dislocation density in the non-doped gallium nitride film layer, and the residual dislocation distribution pattern can be followed. In the subsequent pixel formation process, the pixels can be distributed in low-dislocation or dislocation-free areas.

[0072] According to some embodiments of the present invention, the substrate 3 may be a silicon carbide substrate. Fig. 9 The formation of the LED light-emitting unit may include: forming an n-type doped AlGaN buffer layer 4' on one side of the substrate 3; epitaxially growing a heavily doped n-type gallium nitride layer 41 on the surface of the n-type doped AlGaN buffer layer 4' away from the substrate 3, and the electron concentration of the heavily doped n-type gallium nitride layer 41 may be 2×10 18 cm -3 ~1×10 19 cm -3 Alternatively, a periodic n-Al is formed on the surface of the n-type doped AlGaN buffer layer 4' away from the substrate 3. x Ga 1-x N / n-GaN superlattice structure layer 41 ′, wherein 0.02≤x≤0.05, periodic n-Al x Ga 1-x The electron concentration of the N / n-GaN superlattice structure layer 41 ′ may be 2×10 18 cm -3 ~1×10 19 cm -3 The lattice mismatch between GaN and SiC substrate is smaller. With SiC as substrate, heavily doped n-type GaN layer or periodic n-Al x Ga 1-x The dislocation density of the N / n-GaN superlattice structure layer is relatively small.

[0073] According to some other embodiments of the present invention, the substrate 3 may be a silicon carbide substrate. Fig.10The formation of the LED light-emitting unit may include: forming an n-type doped AlGaN buffer layer 4' on one side of the substrate 3; epitaxially growing a heavily doped n-type gallium nitride layer 41 and at least two inorganic insulating mask layers 6 on the side of the n-type doped AlGaN buffer layer 4' away from the substrate 3, wherein the electron concentration of the heavily doped n-type gallium nitride layer 41 may be 2×10 18 cm -3 ~1×10 19 cm -3 , the inorganic insulating mask layer 6 is located in the heavily doped n-type gallium nitride layer 41, and each inorganic insulating mask layer 6 includes a hollow region, and the orthographic projections of the hollow regions in different inorganic insulating mask layers 6 on the substrate 3 overlap; according to some other embodiments of the present invention, the substrate 3 may be a silicon carbide substrate, referring to Fig.10 , forming an n-type doped AlGaN buffer layer 4' on one side of the substrate 3; forming a periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer 41 ′ and at least two inorganic insulating mask layers 6, wherein 0.02≤x≤0.05, periodic n-Al x Ga 1-x The electron concentration of the N / n-GaN superlattice structure layer can be 2×10 18 cm -3 ~1×10 19 cm -3 The inorganic insulating mask layer 6 is located in the periodic n-Al x Ga 1-x In the N / n-GaN superlattice structure layer 41', each inorganic insulating mask layer 6 includes a hollow region, and the orthographic projections of the hollow regions in different inorganic insulating mask layers 6 on the substrate overlap. x Ga 1-x The formation of an inorganic insulating mask layer during the process of forming the N / n-GaN superlattice structure layer can further reduce the dislocation density in the structure, thereby facilitating further improvement of the light-emitting performance of the chip.

[0074] According to some embodiments of the present invention, the substrate 3 may be a gallium nitride substrate. Fig.11 , forming an LED light-emitting unit may include: epitaxially growing a heavily doped n-type gallium nitride layer 41 on one side surface of the substrate 3, wherein the electron concentration of the heavily doped n-type gallium nitride layer 41 may be 2×10 18 cm -3 ~1×10 19 cm -3 Alternatively, a periodic n-Al x Ga 1-xN / n-GaN superlattice structure layer 41 ′, wherein 0.02≤x≤0.05, periodic n-Al x Ga 1-x The electron concentration of the N / n-GaN superlattice structure layer 41 ′ may be 2×10 18 cm -3 ~1×10 19 cm -3 As a homogeneous substrate of the heavily doped n-type GaN layer, the GaN substrate has a higher matching degree with the heavily doped n-type GaN layer, which is beneficial to reduce the dislocation density and improve the internal quantum efficiency of the LED device, thereby improving the luminescence performance of the chip.

[0075] According to some other embodiments of the present invention, the substrate 3 may be a gallium nitride substrate. Fig.12 The formation of the LED light-emitting unit may include: forming a heavily doped n-type gallium nitride layer 41 and at least two inorganic insulating mask layers 6 on one side of the substrate 3, wherein the electron concentration of the heavily doped n-type gallium nitride layer 41 may be 2×10 18 cm -3 ~1×10 19 cm -3 , the inorganic insulating mask layer 6 is located in the heavily doped n-type gallium nitride layer 41, and each inorganic insulating mask layer 6 includes a hollow region, and the orthographic projections of the hollow regions in different inorganic insulating mask layers 6 on the substrate 3 overlap; or, a periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer 41 ′ and at least two inorganic insulating mask layers 6, 0.02≤x≤0.05, periodic n-Al x Ga 1-x The electron concentration of the N / n-GaN superlattice structure layer 41 ′ may be 2×10 18 cm -3 ~1×10 19 cm -3 The inorganic insulating mask layer 6 is located in the periodic n-Al x Ga 1-x In the N / n-GaN superlattice structure layer 41', each inorganic insulating mask layer 6 includes a hollow region, and the orthographic projections of the hollow regions in different inorganic insulating mask layers 6 on the substrate 3 overlap. Thus, by forming at least two inorganic insulating mask layers in the heavily doped n-type gallium nitride layer, dislocations can be prevented from extending upward, thereby further reducing the dislocation density.

[0076] According to some embodiments of the present invention, the temperature for epitaxially growing the heavily doped n-type gallium nitride layer 41 may be 1040°C to 1060°C, for example, 1040°C, 1045°C, 1050°C, 1055°C, 1060°C, etc., and silane is an n-type dopant. Thus, n-type doping of gallium nitride can be achieved, and the gallium nitride layer grown at the above temperature has good stability, which is beneficial to improving the overall performance of the chip.

[0077] According to some embodiments of the present invention, the periodic n-Al x Ga 1-x In the N / n-GaN superlattice structure layer 41 ′, in each period, n-Al x Ga 1-x The thickness of N can be 2nm to 3nm, and the thickness of n-GaN can be 5nm to 10nm.

[0078] According to some embodiments of the present invention, the periodic n-Al x Ga 1-x The film forming temperature of the N / n-GaN superlattice structure layer 41 ′ may be 1060° C. to 1080° C., for example, 1060° C., 1065° C., 1070° C., 1075° C., 1080° C., etc. The superlattice structure layer formed at the above temperature has good stability.

[0079] According to some embodiments of the present invention, the thickness or periodicity of the heavily doped n-type gallium nitride layer 41 is x Ga 1-x The thickness of the N / n-GaN superlattice structure layer 41 ′ may be 2 μm to 2.5 μm.

[0080] According to an embodiment of the present invention, referring to Figures 9 to 14 The LED light emitting unit may further include: in the heavily doped n-type gallium nitride layer 41 or the periodic n-Al x Ga 1-x A lightly doped n-type gallium nitride layer 42 is formed on the side of the N / n-GaN superlattice structure layer 41' away from the substrate 3. The electron concentration of the lightly doped n-type gallium nitride layer 42 can be 1×10 17 cm -3 ~5×10 17 cm -3 ; Form a first barrier layer 43 on the side of the lightly doped n-type gallium nitride layer 42 away from the substrate 3; and sequentially grow 3 to 5 periods of non-doped In on the side of the first barrier layer 43 away from the substrate 3 y Ga 1-y N / GaN quantum well structure and 3 to 5 periods of non-doped In z Ga 1-zN / GaN quantum well structure (not shown in the figure), where 0.01≤y≤0.03, 0.03≤z≤0.05; in the non-doped In z Ga 1-z A quantum well light-emitting layer 44 is grown on the side of the N / GaN quantum well structure away from the substrate 3, wherein the quantum well light-emitting layer 44 may include a blue light quantum well light-emitting layer, a green light quantum well light-emitting layer and a red light quantum well light-emitting layer; an undoped gallium nitride protective layer 45, an electron blocking layer 46, a hole injection layer 47 and an ohmic contact layer 48 are sequentially formed on the side of the quantum well light-emitting layer 44 away from the substrate 3.

[0081] According to some embodiments of the present invention, the temperature for forming the lightly doped n-type gallium nitride layer 42 is 1040° C. to 1060° C., for example, 1040° C., 1045° C., 1050° C., 1055° C., 1060° C., etc.

[0082] According to some embodiments of the present invention, the thickness of the lightly doped n-type gallium nitride layer 42 may be 0.3 μm to 0.5 μm, for example, 0.3 μm, 0.35 μm, 0.4 μm, 0.45 μm, 0.5 μm, etc.

[0083] According to some embodiments of the present invention, the thickness of the first barrier layer 43 may be 15 nm to 30 nm, for example, 15 nm, 20 nm, 25 nm, 30 nm, etc.

[0084] According to some embodiments of the present invention, non-doped In y Ga 1-y In each period of the N / GaN quantum well structure, In y Ga 1-y The thickness of N can be 2.5nm to 3.5nm, for example, 2.5nm, 2.8nm, 3nm, 3.2nm, 3.5nm, etc., and the thickness of GaN can be 5nm to 15nm, for example, 5nm, 8nm, 10nm, 13nm, 15nm, etc.

[0085] According to some embodiments of the present invention, non-doped In z Ga 1-z In each period of the N / GaN quantum well structure, In z Ga 1-z The thickness of N is 2.5 nm to 3.5 nm, for example, 2.5 nm, 2.8 nm, 3 nm, 3.2 nm, 3.5 nm, etc., and the thickness of GaN is 5 nm to 15 nm, for example, 5 nm, 8 nm, 10 nm, 13 nm, 15 nm, etc.

[0086] According to some embodiments of the present invention, forming a blue light quantum well light emitting layer (blue light wavelength 455nm ~ 465nm) may include:z Ga 1-z The side of the N / GaN quantum well structure away from the substrate sequentially forms a first undoped GaN layer, an In a Ga 1-a N potential well layer, second undoped GaN layer, In b Ga 1-b N barrier layer, wherein 0.18≤a≤0.21, 0.01≤b≤0.05.

[0087] According to some embodiments of the present invention, forming a green light quantum well light emitting layer (green light wavelength 520nm ~ 535nm) may include: z Ga 1-z The N / GaN quantum well structure grows 1 to 2 cycles of In on the side away from the substrate. c Ga 1-c N / n-type GaN quantum well structure and 2 to 3 periods of In d Ga 1-d N / n-type GaN quantum well structure, growing In c Ga 1-c The N / n-type GaN quantum well structure includes a third non-doped GaN layer, an In c Ga 1-c N potential well layer, the fourth non-doped GaN layer and the first n-type GaN barrier layer, grow In d Ga 1-d The N / n-type GaN quantum well structure includes a fifth non-doped GaN layer, an In d Ga 1-d N potential well layer, a sixth undoped GaN layer, and a second n-type GaN barrier layer, wherein 0.24≤c≤0.25, 0.25≤d≤0.28.

[0088] According to some embodiments of the present invention, forming a red light quantum well light emitting layer (red light wavelength 620nm ~ 635nm) may include: z Ga 1-z The side of the N / GaN quantum well structure away from the substrate successively forms the seventh undoped GaN layer, In e Ga 1-e N potential well layer, eighth undoped GaN layer, In f Ga 1-f N barrier layer, ninth undoped GaN layer, In g Ga 1-g N potential well layer, tenth undoped GaN layer, p-type doped GaN barrier layer, Al h Ga 1-hN layers, wherein 0.18≤e≤0.21, 0.01≤f≤0.05, 0.35≤g≤0.38, and 0.10≤h≤0.30.

[0089] According to some embodiments of the present invention, the thickness of the first undoped GaN layer and the thickness of the second undoped GaN layer may be independently 1 nm to 5 nm, for example, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, etc.

[0090] According to an embodiment of the present invention, In a Ga 1-a The thickness of the N-well layer may be 2.5 nm to 3.5 nm, for example, 2.5 nm, 2.8 nm, 3 nm, 3.2 nm, 3.5 nm, etc.

[0091] According to an embodiment of the present invention, In b Ga 1-b The thickness of the N barrier layer may be 5 nm to 15 nm, for example, 5 nm, 8 nm, 10 nm, 13 nm, 15 nm, etc.

[0092] According to an embodiment of the present invention, the thickness of the third non-doped GaN layer, the thickness of the fourth non-doped GaN layer, the thickness of the fifth non-doped GaN layer, the thickness of the sixth non-doped GaN layer, the thickness of the seventh non-doped GaN layer, the thickness of the eighth non-doped GaN layer, the thickness of the ninth non-doped GaN layer, and the thickness of the tenth non-doped GaN layer can be independently 1nm to 3nm. Before growing the potential well layer and the barrier layer, the non-doped GaN layer is deposited at a low temperature, and the growth temperature of the non-doped GaN layer can be the same as the formation temperature of the potential well layer. The non-doped GaN layer can improve the surface flatness of the film layer before growing the quantum well structure, which is beneficial to the growth of the quantum well structure.

[0093] According to an embodiment of the present invention, In c Ga 1-c The thickness of the N-well layer, In d Ga 1-d The thickness of the N barrier layer, In e Ga 1-e The thickness of the N-well layer, In g Ga 1-g The thickness of the N-well layers can be independently 2.5 nm to 3.5 nm, for example, 2.5 nm, 2.8 nm, 3 nm, 3.2 nm, 3.5 nm, etc.

[0094] According to an embodiment of the present invention, the thickness of the first n-type GaN barrier layer, the thickness of the second n-type GaN barrier layer, and the In f Ga 1-fThe thickness of the N barrier layer and the thickness of the p-type doped GaN barrier layer may be independently 5 nm to 15 nm, for example, 5 nm, 8 nm, 10 nm, 13 nm, 15 nm, etc.

[0095] According to an embodiment of the present invention, Al h Ga 1-h The thickness of the N layer may be 1 nm to 2 nm, for example, 1 nm, 1.2 nm, 1.5 nm, 1.8 nm, 2 nm, etc.

[0096] According to an embodiment of the present invention, the thickness of the non-doped gallium nitride protective layer may be 15 nm to 30 nm, for example, 15 nm, 18 nm, 20 nm, 23 nm, 25 nm, 28 nm, 30 nm, etc. The quantum well structure is grown in a nitrogen atmosphere, which is converted to a hydrogen atmosphere during the subsequent growth of the electron blocking layer, which may cause etching to the quantum well structure, while the non-doped gallium nitride protective layer can protect the quantum well structure, reducing or even preventing the quantum well structure from being etched in a hydrogen atmosphere.

[0097] According to an embodiment of the present invention, the thickness of the electron blocking layer may be 60 nm to 70 nm, and the material of the electron blocking layer may be polarization-induced p-type doped Al q Ga 1-q N, in the direction away from the substrate, the value of q linearly changes from 20% to 30% to 0.

[0098] According to an embodiment of the present invention, the hole injection layer may be 8 to 16 periods of p-Al i Ga 1-i N / p-GaN superlattice structure, the hole concentration of the hole injection layer is 1.5×10 18 cm -3 ~3.5×10 18 cm -3 In each cycle, p-Al i Ga 1-i The thickness of N can be 2.5 nm to 3.5 nm, the thickness of p-GaN can be 5 nm to 8 nm, and 0.10≤i≤0.20.

[0099] According to an embodiment of the present invention, the material of the ohmic contact layer may be heavily doped p-GaN, and the thickness of the ohmic contact layer may be 20 nm to 40 nm, for example, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, etc.

[0100] S3: forming a first conductive material layer and a first reflective layer in sequence on a side of the LED light-emitting unit away from the substrate.

[0101] It should be noted that the steps after forming the LED light-emitting unit using a sapphire substrate, a silicon substrate, a silicon carbide substrate or a gallium nitride substrate are the same. Therefore, the drawings corresponding to steps S3 to S15 are all described using the case where the substrate is a sapphire substrate as an example.

[0102] According to an embodiment of the present invention, after the LED light-emitting unit is formed, a first conductive material layer 30 and a first reflective layer 20 are sequentially formed on a side of the LED light-emitting unit away from the substrate 3, so as to obtain Fig.15 The structure shown.

[0103] According to some embodiments of the present invention, the material of the first conductive material layer 30 can be ITO, and an ITO film layer with a thickness of 40nm to 100nm can be deposited by electron beam evaporation, combined with a rapid thermal annealing process to improve the transmittance of the ITO film layer (transmittance ≥ 85%) and reduce the resistance of the material.

[0104] According to some embodiments of the present invention, the first reflective layer may be obtained by depositing a 100 nm to 400 nm thick Ag or Al film layer using electron beam evaporation.

[0105] S4: Bonding a driving backplane to a side of the first reflective layer away from the substrate.

[0106] According to some embodiments of the present invention, the driving backplane 10 is bonded to the side of the first reflective layer 20 away from the substrate 3, so as to obtain Fig.16 In the structure shown, the driving backplane 10 has a pixel driving circuit. According to some embodiments of the present invention, the driving backplane 10 may be a CMOS (complementary metal oxide semiconductor) driving backplane on a silicon substrate or a silicon-based CMOS driving backplane.

[0107] According to some specific embodiments of the present invention, a first binding metal may be deposited on the surface of the first reflective layer 20 away from the substrate 3 by electron beam evaporation deposition, and the first binding metal may include metal chromium, metal platinum, metal nickel, metal titanium, metal silver, etc. For example, the first binding metal may include a chromium layer, a platinum layer, a nickel layer, a titanium layer, a nickel layer, and a silver layer stacked in sequence; a second binding metal may be deposited on the driving backplane, and the second binding metal may include metal chromium, metal platinum, metal silver, metal indium, etc. For example, the second binding metal may include a chromium layer, a platinum layer, a silver layer, and an indium layer stacked in sequence; and then, the driving backplane 10 is bonded to the side of the first reflective layer 20 away from the substrate 3. Those skilled in the art should understand that the side of the driving backplane provided with the pixel driving circuit is bonded to the previously formed structure.

[0108] S5: Peeling off the substrate.

[0109] According to some embodiments of the present invention, when the substrate is a sapphire substrate, a laser stripping process can be used to strip the substrate. Optionally, the pulsed laser wavelength is 355nm, 266nm or 248nm, thereby effectively stripping the sapphire substrate. When the substrate is laser stripped, the inorganic insulating mask layer 6 can absorb part of the laser energy and alleviate the damage of the high interface temperature to the quantum well structure, thereby further improving the luminescence performance of the chip.

[0110] According to some other embodiments of the present invention, when the substrate is a silicon substrate, a wet etching method may be used to peel off the silicon substrate.

[0111] According to some other embodiments of the present invention, when the substrate is a silicon carbide substrate and the buffer layer is an n-type doped AlGaN buffer layer 4 ′, the silicon carbide substrate may be stripped by using a wet etching method and / or a grinding method.

[0112] According to some other embodiments of the present invention, when the substrate is a silicon carbide substrate, an aluminum nitride buffer layer 4 and a gradient Al p Ga 1-p When the N layer 8 is formed, the silicon carbide substrate can be stripped by using a wet etching method, a grinding method and / or an ICP-RIE etching method.

[0113] According to some other embodiments of the present invention, when the substrate is a gallium nitride substrate, a grinding method and / or an ICP-RIE etching method may be used to strip the gallium nitride substrate.

[0114] It should be noted that during the process of laser stripping of the sapphire substrate, a portion of the aluminum nitride buffer layer will also be etched away.

[0115] After the sapphire substrate is peeled off, the non-doped GaN film layer 5 is etched by ICP-RIE etching method until the heavily doped n-type GaN layer 41 or the periodic n-Al x Ga 1-x The N / n-GaN superlattice structure layer 41' is exposed, and the obtained structure is as follows Fig.17 As shown, the surface is then subjected to chemical mechanical polishing.

[0116] S6: Etching the LED light-emitting unit to form a plurality of LED light-emitting units arranged at intervals.

[0117] According to some embodiments of the present invention, reference Fig.18, the LED light-emitting unit is etched to form a plurality of LED light-emitting units 40 arranged at intervals. According to some embodiments of the present invention, photolithography and ICP-RIE processes can be used to etch InGaN-based RGB three-primary color pixels of different pixel sizes and different pixel spacings, and the LED light-emitting unit (pixel) can be set in a low dislocation area or a non-dislocation area, and then acetone, ethanol and deionized water are used in turn to remove the glue and clean the surface. According to some embodiments of the present invention, when a non-doped GaN film layer or a heavily doped n-type GaN layer is made in the front, if an inorganic insulating mask layer is formed, a non-dislocation or low-dislocation area alignment mark can be set to better set the pixel in the non-dislocation or low-dislocation area.

[0118] S7: forming a passivation layer on a side of the plurality of LED light-emitting units away from the driving backplane.

[0119] According to an embodiment of the present invention, referring to Fig.18 After forming a plurality of LED light-emitting units 40 , a passivation layer 50 is formed on a side of the LED light-emitting unit away from the driving backplane 10 , and the passivation layer 50 at least covers the side wall of the LED light-emitting unit 40 .

[0120] According to some embodiments of the present invention, wet etching (25wt% TMAH solution, TMAH refers to tetramethylammonium hydroxide) can be used to repair the etching interface, and an ALD (atomic layer deposition) device can be used to deposit a 20nm to 40nm thick silicon oxide or silicon nitride passivation layer. According to other embodiments of the present invention, a 60nm to 200nm thick silicon oxide or silicon nitride passivation layer can be deposited using a PECVD device.

[0121] S8: forming a second reflective layer, wherein the second reflective layer at least covers a side wall of the passivation layer.

[0122] According to an embodiment of the present invention, referring to Fig.18 After the passivation layer 50 is formed, a second reflective layer 60 may be formed on a side of the passivation layer 50 away from the driving backplane 10 , thereby further enhancing the light extraction efficiency.

[0123] According to some embodiments of the present invention, PVD (physical vapor deposition) or ALD method can be used to deposit a tantalum oxide, titanium oxide and / or silicon oxide reflective film layer to form a Bragg reflector, i.e., the second reflective layer 60. Setting the second reflective layer can further enhance the light extraction efficiency.

[0124] S9: etching the first conductive material layer to form a plurality of first conductive film layers spaced apart from each other.

[0125] According to an embodiment of the present invention, referring to Fig.18After forming the passivation layer 50 and the second reflective layer 60, the first conductive material layer 30 is etched to form a plurality of first conductive film layers 31 spaced apart from each other. According to some embodiments of the present invention, the first conductive material layer 30 can be etched by photolithography and ICP-RIE processes to form isolation grooves, and acetone, ethanol and deionized water can be used for degumming and surface cleaning.

[0126] S10: forming a first insulating layer.

[0127] According to an embodiment of the present invention, referring to Fig.18 After etching the first conductive material layer, a first insulating layer 1 is formed, and the first insulating layer 1 covers a portion of the surface of the second reflective layer 60 and a portion of the surface of the first reflective layer 20. According to an embodiment of the present invention, a silicon oxide or silicon nitride film layer can be deposited by using a photolithography process and PECVD equipment to form the first insulating layer 1, and acetone, ethanol and deionized water are used for degumming and surface cleaning.

[0128] S11: etching the passivation layer and the second reflective layer to expose a portion of the surface of the LED light-emitting unit away from the driving backplane.

[0129] According to an embodiment of the present invention, referring to Fig.18 , the passivation layer 50 and the second reflective layer 60 are etched to expose the surface of the LED light emitting unit 40 away from the driving backplane 10. According to some embodiments of the present invention, the LED light emitting unit 40 (pixel) table top heavily doped with n-type gallium nitride layer 41 or periodic n-Al x Ga 1-x Part of the passivation layer 50 and the second reflective layer 60 on the N / n-GaN superlattice structure layer 41 ′ are removed, exposing a portion of the surface of the LED light-emitting unit away from the driving backplane.

[0130] S12: forming a second conductive film layer.

[0131] According to an embodiment of the present invention, referring to Fig.18 , forming a second conductive film layer 70, the second conductive film layer 70 is in contact with the LED light-emitting unit 40, and the second conductive film layer 70 can cover at least a portion of the surface of the first insulating layer 1 away from the driving backplane 10, and at least a portion of the surface of the second reflective layer 60 away from the driving backplane 10. According to some embodiments of the present invention, the material of the second conductive film layer 70 can be ITO, and a 20nm to 100nm thick ITO film layer can be deposited and combined with an RTA (rapid thermal annealing) process to improve the light transmittance of the ITO film layer and reduce the resistance of the material.

[0132] S13: forming a plurality of concave reflective layers on a side of the first insulating layer away from the driving back plate.

[0133] According to an embodiment of the present invention, referring to Fig.18 A plurality of concave reflective layers 90 are formed on the side of the first insulating layer 1 away from the driving backplane 10, and each concave reflective layer 90 is arranged around an LED light-emitting unit 40. According to an embodiment of the present invention, metal silver and / or metal aluminum can be deposited by nanoimprinting method, photolithography and electron beam deposition method to obtain a concave reflective layer, which can effectively reduce the light crosstalk between LED light-emitting units, converge the light divergence angle, and at the same time, improve the light extraction efficiency of the chip.

[0134] According to an embodiment of the present invention, referring to Fig.18 Before forming the concave reflective layer 90, the method for manufacturing a Micro LED chip may further include: forming a plurality of spaced n-type ohmic contact electrodes 80 on a side of the second conductive film layer 70 away from the driving backplane 10, each n-type ohmic contact electrode 80 being arranged around an LED light-emitting unit 40. According to an embodiment of the present invention, the n-type ohmic contact electrode may be formed by photolithography and electron beam evaporation, and then acetone, ethanol and deionized water may be used for degumming and surface cleaning, and the n-type ohmic contact electrode may include metal layers such as a titanium layer, an aluminum layer, a titanium layer and a gold layer stacked in sequence.

[0135] According to some specific embodiments of the present invention, Fig.18 The concave reflective layer 90 may be formed on a side of the n-type ohmic contact electrode 80 away from the driving backplane 10 , and the concave reflective layer 90 may be disposed in contact with the n-type ohmic contact electrode 80 .

[0136] According to some embodiments of the present invention, the method for manufacturing a Micro LED chip may further include: forming a second insulating layer on a side of the second conductive film layer away from the driving backplane.

[0137] According to an embodiment of the present invention, referring to Fig.18 A second insulating layer 2 is formed on the side of the second conductive film layer 70 away from the driving backplane 10, and the second insulating layer 2 can cover at least a portion of the surface of the second conductive film layer 70, at least a portion of the surface of the n-type ohmic contact electrode 80, and at least a portion of the surface of the concave reflective layer 90. According to an embodiment of the present invention, a silicon oxide and / or silicon nitride insulating layer can be deposited by using a photolithography process and PECVD equipment, thereby achieving electrical insulation between the LED light-emitting unit (pixel) mesas.

[0138] According to some embodiments of the present invention, the quantum well light-emitting layer can also be an AlGaInP (aluminum gallium indium phosphide) red light quantum well light-emitting layer. During the preparation process, a quantum well light-emitting layer and other structures are formed on a gallium arsenide substrate, and an ICP-RIE device is used to etch the quantum well light-emitting layer and other structures to form a plurality of LED light-emitting units. Afterwards, the side of the LED light-emitting unit away from the gallium arsenide substrate is bound to a transfer substrate (sapphire substrate or silicon substrate), the gallium arsenide substrate is peeled off, and a driving backplane is bound. The driving backplane has a pixel driving circuit, and the driving backplane is arranged on the side of the LED light-emitting unit away from the transfer substrate. Afterwards, the transfer substrate is peeled off, and then a concave reflective layer and other structures are formed. The final chip structure is similar to Figure 1 and Figure 2 The structures shown are roughly the same, the difference is that the materials of each layer in the LED light-emitting unit are different, all based on AlGaInP, wherein the concave reflective layer can also reduce the optical crosstalk between red light pixels (LED light-emitting units), converge the light divergence angle, and improve the light extraction efficiency and luminescence performance of the chip.

[0139] In the description of this specification, the description of reference terms "one embodiment", "another embodiment", "some embodiments", "other embodiments", "some specific embodiments", "other specific embodiments" and the like means that the specific features, structures, materials or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples, unless otherwise contradictory. In addition, it should be noted that in this specification, the terms "first", "second", "third", "fourth", "fifth", "sixth", "seventh", "eighth", "ninth" and "tenth" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0140] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A Micro LED chip, characterized in that: include: A driving backplane, wherein the driving backplane has a pixel driving circuit; A first reflective layer, wherein the first reflective layer is disposed on one side of the driving backplane; A plurality of first conductive film layers arranged at intervals, wherein the first conductive film layers are arranged on a side of the first reflective layer away from the driving backplane; A plurality of LED light-emitting units, wherein the plurality of LED light-emitting units are arranged on a side of the first conductive film layer away from the driving backplane; A passivation layer, wherein the passivation layer at least covers the side wall of the LED light-emitting unit; a second reflective layer, wherein the second reflective layer at least covers a side wall of the passivation layer; a first insulating layer, wherein the first insulating layer covers a portion of a surface of the second reflective layer and a portion of a surface of the first reflective layer; A second conductive film layer, wherein the second conductive film layer is in contact with the LED light-emitting unit; as well as A plurality of concave reflective layers are provided on a side of the first insulating layer away from the driving back plate, and each of the concave reflective layers is provided around one of the LED light-emitting units.

2. The Micro LED chip according to claim 1, characterized in that: At least one of the following conditions is met: The thickness of the first conductive film layer is 40nm to 100nm; The material of the first conductive film layer includes ITO; The material of the first reflective layer includes at least one of metal silver and metal aluminum; The material of the passivation layer includes at least one of silicon nitride and silicon oxide; The thickness of the passivation layer is 20nm to 200nm; The second reflective layer is a Bragg reflector, and a material of the second reflective layer includes at least one of tantalum oxide, titanium oxide and silicon oxide; The material of the second conductive film layer includes ITO; The thickness of the second conductive film layer is 20nm to 100nm; The material of the concave reflective layer includes at least one of metal silver and metal aluminum; A material of the first insulating layer includes at least one of silicon nitride and silicon oxide.

3. A method for manufacturing a Micro LED chip, characterized in that: include: providing a substrate; Forming an LED light-emitting unit on one side surface of the substrate, wherein forming the LED light-emitting unit includes the step of forming a quantum well light-emitting layer; Forming a first conductive material layer and a first reflective layer in sequence on a side of the LED light-emitting unit away from the substrate; A driving backplane is bound to a side of the first reflective layer away from the substrate, wherein the driving backplane has a pixel driving circuit; peeling off the substrate; Etching the LED light-emitting unit to form a plurality of LED light-emitting units arranged at intervals; Forming a passivation layer on a side of the plurality of LED light-emitting units away from the driving backplane, wherein the passivation layer at least covers the side walls of the LED light-emitting units; forming a second reflective layer, wherein the second reflective layer at least covers a side wall of the passivation layer; Etching the first conductive material layer to form a plurality of first conductive film layers spaced apart from each other; forming a first insulating layer, wherein the first insulating layer covers a portion of the surface of the second reflective layer and a portion of the surface of the first reflective layer; Etching the passivation layer and the second reflective layer to expose a portion of the surface of the LED light-emitting unit away from the driving backplane; forming a second conductive film layer, wherein the second conductive film layer is in contact with the LED light-emitting unit; A plurality of concave reflective layers are formed on a side of the first insulating layer away from the driving back plate, and each of the concave reflective layers is arranged around one of the LED light-emitting units.

4. The method according to claim 3, characterized in that The substrate is a sapphire substrate, and the LED light-emitting unit is formed by: forming an aluminum nitride buffer layer on one side of the substrate; A non-doped gallium nitride film layer and at least two inorganic insulating mask layers are formed on a side of the aluminum nitride buffer layer away from the substrate, wherein the inorganic insulating mask layer is located in the non-doped gallium nitride film layer, and each of the inorganic insulating mask layers includes a hollow region, and the orthographic projections of the hollow regions in different inorganic insulating mask layers on the substrate overlap; A heavily doped n-type gallium nitride layer is epitaxially grown on the side of the non-doped gallium nitride film layer away from the substrate, and the electron concentration of the heavily doped n-type gallium nitride layer is 2×10 18 cm -3 ~1×10 19 cm -3 Alternatively, a periodic n-Al layer is formed on the surface of the non-doped GaN film layer away from the substrate. x Ga 1-x N / n-GaN superlattice structure layer, 0.02≤x≤0.05, periodic n-Al x Ga 1-x The electron concentration of the N / n-GaN superlattice structure layer is 2×10 18 cm -3 ~1×10 19 cm -3 ; Wherein, forming the undoped gallium nitride film layer and at least two inorganic insulating mask layers comprises: Epitaxially grow the non-doped gallium nitride film layer, and when each non-doped gallium nitride with a thickness of 0.5 μm to 1 μm is grown, introduce ammonia and silane, react at 1045° C. to 1065° C. for 10 seconds to 60 seconds to form a silicon nitride grid structure with a thickness of 10 nm to 25 nm, and subsequently the non-doped gallium nitride continues to nucleate at the openings of the silicon nitride grid structure and epitaxially form a film on the silicon nitride grid structure until the thickness of the non-doped gallium nitride film layer is 3 μm to 5 μm; or, The non-doped gallium nitride film layer is epitaxially grown, and each time the non-doped gallium nitride with a thickness of 0.5 μm to 1 μm is grown, a silicon nitride film layer or a silicon oxide film layer with a thickness of 10 nm to 25 nm is formed on the surface of the non-doped gallium nitride away from the substrate, and the silicon nitride film layer or the silicon oxide film layer is etched to form a grid structure or a plurality of spaced-apart strip structures, wherein the longitudinal cross-section of the strip structure is a rectangle or a trapezoid, until the thickness of the non-doped gallium nitride film layer is 3 μm to 5 μm.

5. The method according to claim 4, characterized in that The substrate is peeled off by a laser lift-off process, and optionally, the pulse laser wavelength is 355 nm, 266 nm or 248 nm.

6. The method according to claim 3, characterized in that The substrate is a silicon substrate or a silicon carbide substrate, and forming the LED light-emitting unit includes: forming an aluminum nitride buffer layer on one side of the substrate; A gradient Al p Ga 1-p In the N layer, the value of p linearly changes from 20% to 30% to 0 in the direction away from the aluminum nitride buffer layer; In the gradient Al p Ga 1-p A non-doped gallium nitride film layer and at least two inorganic insulating mask layers are formed on a side of the N layer away from the substrate, wherein the inorganic insulating mask layer is located in the non-doped gallium nitride film layer, and each of the inorganic insulating mask layers includes a hollow region, and the orthographic projections of the hollow regions in different inorganic insulating mask layers on the substrate overlap; A heavily doped n-type gallium nitride layer is epitaxially grown on the side of the non-doped gallium nitride film layer away from the substrate, and the electron concentration of the heavily doped n-type gallium nitride layer is 2×10 18 cm -3 ~1×10 19 cm -3 Alternatively, a periodic n-Al layer is formed on the surface of the non-doped GaN film layer away from the substrate. x Ga 1-x N / n-GaN superlattice structure layer, 0.02≤x≤0.05, periodic n-Al x Ga 1-x The electron concentration of the N / n-GaN superlattice structure layer is 2×10 18 cm -3 ~1×10 19 cm -3 ; Wherein, forming the undoped gallium nitride film layer and at least two inorganic insulating mask layers comprises: Epitaxially grow the non-doped gallium nitride film layer, and when each non-doped gallium nitride with a thickness of 0.5 μm to 1 μm is grown, introduce ammonia and silane, react at 1045° C. to 1065° C. for 10 seconds to 60 seconds to form a silicon nitride grid structure with a thickness of 10 nm to 25 nm, and subsequently the non-doped gallium nitride continues to nucleate at the openings of the silicon nitride grid structure and epitaxially form a film on the silicon nitride grid structure until the thickness of the non-doped gallium nitride film layer is 3 μm to 5 μm; or, The non-doped gallium nitride film layer is epitaxially grown, and each time the non-doped gallium nitride with a thickness of 0.5 μm to 1 μm is grown, a silicon nitride film layer or a silicon oxide film layer with a thickness of 10 nm to 25 nm is formed on the surface of the non-doped gallium nitride away from the substrate, and the silicon nitride film layer or the silicon oxide film layer is etched to form a grid structure or a plurality of spaced-apart strip structures, wherein the longitudinal cross-section of the strip structure is a rectangle or a trapezoid, until the thickness of the non-doped gallium nitride film layer is 3 μm to 5 μm.

7. The method according to claim 3, characterized in that The substrate is a silicon carbide substrate, and forming the LED light-emitting unit includes: forming an n-type doped AlGaN buffer layer on one side of the substrate; A heavily doped n-type gallium nitride layer is epitaxially grown on the surface of the n-type doped AlGaN buffer layer away from the substrate, and the electron concentration of the heavily doped n-type gallium nitride layer is 2×10 18 cm -3 ~1×10 19 cm -3 Alternatively, a periodic n-Al2O3 layer is formed on the surface of the n-type doped AlGaN buffer layer away from the substrate. x Ga 1-x N / n-GaN superlattice structure layer, 0.02≤x≤0.05, periodic n-Al x Ga 1-x The electron concentration of the N / n-GaN superlattice structure layer is 2×10 18 cm -3 ~1×10 19 cm -3 ; Alternatively, a heavily doped n-type gallium nitride layer and at least two inorganic insulating mask layers are epitaxially grown on a side of the n-type doped AlGaN buffer layer away from the substrate, and the electron concentration of the heavily doped n-type gallium nitride layer is 2×10 18 cm -3 ~1×10 19 cm -3 , the inorganic insulating mask layer is located in the heavily doped n-type gallium nitride layer, and each of the inorganic insulating mask layers includes a hollow region, and the hollow regions in different inorganic insulating mask layers overlap with each other in orthographic projection on the substrate; or, a periodic n-Al is formed on the side of the n-type doped AlGaN buffer layer away from the substrate x Ga 1-x N / n-GaN superlattice structure layer and at least two inorganic insulating mask layers, 0.02≤x≤0.05, periodic n-Al x Ga 1-x The electron concentration of the N / n-GaN superlattice structure layer is 2×10 18 cm -3 ~1×10 19 cm -3 The inorganic insulating mask layer is located on the periodic n-Al x Ga 1-x In the N / n-GaN superlattice structure layer, each of the inorganic insulating mask layers includes a hollow region, and the orthographic projections of the hollow regions in different inorganic insulating mask layers on the substrate overlap.

8. The method according to claim 3, characterized in that The substrate is a gallium nitride substrate, and forming the LED light-emitting unit includes: A heavily doped n-type gallium nitride layer is epitaxially grown on one side surface of the substrate, and the electron concentration of the heavily doped n-type gallium nitride layer is 2×10 18 cm -3 ~1×10 19 cm -3 Alternatively, a periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer, 0.02≤x≤0.05, periodic n-Al x Ga 1-x The electron concentration of the N / n-GaN superlattice structure layer is 2×10 18 cm -3 ~1×10 19 cm -3 ; Alternatively, a heavily doped n-type gallium nitride layer and at least two inorganic insulating mask layers are formed on one side of the substrate, wherein the electron concentration of the heavily doped n-type gallium nitride layer is 2×10 18 cm -3 ~1×10 19 cm -3 , the inorganic insulating mask layer is located in the heavily doped n-type gallium nitride layer, and each of the inorganic insulating mask layers includes a hollow region, and the hollow regions in different inorganic insulating mask layers overlap in their orthographic projections on the substrate; or, a periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer and at least two inorganic insulating mask layers, 0.02≤x≤0.05, periodic n-Al x Ga 1-x The electron concentration of the N / n-GaN superlattice structure layer is 2×10 18 cm -3 ~1×10 19 cm -3 The inorganic insulating mask layer is located on the periodic n-Al x Ga 1-x In the N / n-GaN superlattice structure layer, each of the inorganic insulating mask layers includes a hollow region, and the orthographic projections of the hollow regions in different inorganic insulating mask layers on the substrate overlap.

9. The method according to any one of claims 4 to 8, characterized in that: Forming the LED light emitting unit further includes: In the heavily doped n-type gallium nitride layer or the periodic n-Al x Ga 1-x A lightly doped n-type gallium nitride layer is formed on the side of the N / n-GaN superlattice structure layer away from the substrate, and the electron concentration of the lightly doped n-type gallium nitride layer is 1×10 17 cm -3 ~5×10 17 cm -3 ; forming a first barrier layer on a side of the lightly doped n-type gallium nitride layer away from the substrate; On the side of the first barrier layer away from the substrate, 3 to 5 periods of non-doped In are sequentially grown. y Ga 1-y N / GaN quantum well structure and 3 to 5 periods of non-doped In z Ga 1-z N / GaN quantum well structure, wherein 0.01≤y≤0.03, 0.03≤z≤0.05; In the non-doped In z Ga 1-z A blue light quantum well light emitting layer, a green light quantum well light emitting layer and a red light quantum well light emitting layer are grown on a side of the N / GaN quantum well structure away from the substrate; A non-doped gallium nitride protection layer, an electron blocking layer, a hole injection layer and an ohmic contact layer are sequentially formed on a side of the quantum well light-emitting layer away from the substrate.

10. The method according to claim 9, characterized in that Forming the blue light quantum well light emitting layer comprises: z Ga 1-z The side of the N / GaN quantum well structure away from the substrate sequentially forms a first non-doped GaN layer, an In a Ga 1-a N potential well layer, second undoped GaN layer, In b Ga 1-b N barrier layer, wherein 0.18≤a≤0.21, 0.01≤b≤0.05; Forming the green light quantum well light emitting layer comprises: z Ga 1-z The N / GaN quantum well structure grows 1 to 2 periods of In on the side away from the substrate. c Ga 1-c N / n-type GaN quantum well structure and 2 to 3 periods of In d Ga 1-d N / n-type GaN quantum well structure, growing In c Ga 1-c The N / n-type GaN quantum well structure includes a third non-doped GaN layer, an In c Ga 1-c N potential well layer, the fourth non-doped GaN layer and the first n-type GaN barrier layer, grow In d Ga 1-d The N / n-type GaN quantum well structure includes a fifth non-doped GaN layer, an In d Ga 1-d N potential well layer, a sixth undoped GaN layer, and a second n-type GaN barrier layer, wherein 0.24≤c≤0.25, 0.25≤d≤0.28; Forming the red light quantum well emitting layer comprises: z Ga 1-z The N / GaN quantum well structure is formed on the side away from the substrate in sequence with a seventh undoped GaN layer, an In e Ga 1-e N potential well layer, eighth undoped GaN layer, In f Ga 1-f N barrier layer, ninth undoped GaN layer, In g Ga 1-g N potential well layer, tenth undoped GaN layer, p-type doped GaN barrier layer, Al h Ga 1-h N layers, wherein 0.18≤e≤0.21, 0.01≤f≤0.05, 0.35≤g≤0.38, and 0.10≤h≤0.

30.

11. The method according to claim 10, characterized in that At least one of the following conditions is met: The thickness of the aluminum nitride buffer layer is 10nm to 50nm; The temperature for forming the non-doped gallium nitride film layer is 1045° C. to 1065° C.; The temperature for epitaxially growing the heavily doped n-type gallium nitride layer is 1040° C. to 1060° C., and silane is an n-type dopant; Periodic n-Al x Ga 1-x In the N / n-GaN superlattice structure layer, in each period, n-Al x Ga 1-x The thickness of N is 2nm~3nm, and the thickness of n-GaN is 5nm~10nm; The periodic n-Al x Ga 1-x The film forming temperature of the N / n-GaN superlattice structure layer is 1060℃~1080℃; The temperature for forming the lightly doped n-type gallium nitride layer is 1040° C. to 1060° C.; The thickness of the lightly doped n-type gallium nitride layer is 0.3 μm to 0.5 μm; The thickness of the first barrier layer is 15nm to 30nm; Non-doped In y Ga 1-y In each period of the N / GaN quantum well structure, In y Ga 1-y The thickness of N is 2.5nm to 3.5nm, and the thickness of GaN is 5nm to 15nm; Non-doped In z Ga 1-z In each period of the N / GaN quantum well structure, In z Ga 1-z The thickness of N is 2.5nm to 3.5nm, and the thickness of GaN is 5nm to 15nm; The thickness of the first undoped GaN layer and the thickness of the second undoped GaN layer are independently 1 nm to 5 nm; In a Ga 1-a The thickness of the N potential well layer is 2.5nm to 3.5nm; In b Ga 1-b The thickness of the N barrier layer is 5nm to 15nm; The thickness of the third undoped GaN layer, the thickness of the fourth undoped GaN layer, the thickness of the fifth undoped GaN layer, the thickness of the sixth undoped GaN layer, the thickness of the seventh undoped GaN layer, the thickness of the eighth undoped GaN layer, the thickness of the ninth undoped GaN layer, and the thickness of the tenth undoped GaN layer are each independently 1 nm to 3 nm; In c Ga 1-c The thickness of the N potential well layer, the In d Ga 1-d The thickness of the N barrier layer, the In e Ga 1-e The thickness of the N potential well layer, the In g Ga 1-g The thickness of the N potential well layer is independently 2.5nm to 3.5nm; The thickness of the first n-type GaN barrier layer, the thickness of the second n-type GaN barrier layer, and the In f Ga 1-f The thickness of the N barrier layer and the thickness of the p-type doped GaN barrier layer are independently 5nm to 15nm; The Al h Ga 1-h The thickness of the N layer is 1nm to 2nm; The thickness of the non-doped gallium nitride protective layer is 15nm to 30nm; The thickness of the electron blocking layer is 60nm to 70nm, and the material of the electron blocking layer is p-type doped Al q Ga 1-q N, in the direction away from the substrate, the value of q linearly changes from 20% to 30% to 0; The hole injection layer is 8 to 16 periods of p-Al i Ga 1-i N / p-GaN superlattice structure, the hole concentration of the hole injection layer is 1.5×10 18 cm -3 ~3.5×10 18 cm -3 In each cycle, p-Al i Ga 1-i The thickness of N is 2.5nm to 3.5nm, the thickness of p-GaN is 5nm to 8nm, 0.10≤i≤0.20; The material of the ohmic contact layer is heavily doped p-GaN, and the thickness of the ohmic contact layer is 20nm-40nm.

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